MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/gpio_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2015, STMicroelectronics
sahilmgandhi 18:6a4db94011d3 4 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 7 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 10 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 12 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 13 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 15 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 16 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 28 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 31 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 32 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 33 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 34 #include "pin_device.h"
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 extern const uint32_t ll_pin_defines[16];
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 // Enable GPIO clock and return GPIO base address
sahilmgandhi 18:6a4db94011d3 39 GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) {
sahilmgandhi 18:6a4db94011d3 40 uint32_t gpio_add = 0;
sahilmgandhi 18:6a4db94011d3 41 switch (port_idx) {
sahilmgandhi 18:6a4db94011d3 42 case PortA:
sahilmgandhi 18:6a4db94011d3 43 gpio_add = GPIOA_BASE;
sahilmgandhi 18:6a4db94011d3 44 __GPIOA_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 45 break;
sahilmgandhi 18:6a4db94011d3 46 case PortB:
sahilmgandhi 18:6a4db94011d3 47 gpio_add = GPIOB_BASE;
sahilmgandhi 18:6a4db94011d3 48 __GPIOB_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 49 break;
sahilmgandhi 18:6a4db94011d3 50 #if defined(GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 51 case PortC:
sahilmgandhi 18:6a4db94011d3 52 gpio_add = GPIOC_BASE;
sahilmgandhi 18:6a4db94011d3 53 __GPIOC_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 54 break;
sahilmgandhi 18:6a4db94011d3 55 #endif
sahilmgandhi 18:6a4db94011d3 56 #if defined GPIOD_BASE
sahilmgandhi 18:6a4db94011d3 57 case PortD:
sahilmgandhi 18:6a4db94011d3 58 gpio_add = GPIOD_BASE;
sahilmgandhi 18:6a4db94011d3 59 __GPIOD_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 60 break;
sahilmgandhi 18:6a4db94011d3 61 #endif
sahilmgandhi 18:6a4db94011d3 62 #if defined GPIOE_BASE
sahilmgandhi 18:6a4db94011d3 63 case PortE:
sahilmgandhi 18:6a4db94011d3 64 gpio_add = GPIOE_BASE;
sahilmgandhi 18:6a4db94011d3 65 __GPIOE_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 66 break;
sahilmgandhi 18:6a4db94011d3 67 #endif
sahilmgandhi 18:6a4db94011d3 68 #if defined GPIOF_BASE
sahilmgandhi 18:6a4db94011d3 69 case PortF:
sahilmgandhi 18:6a4db94011d3 70 gpio_add = GPIOF_BASE;
sahilmgandhi 18:6a4db94011d3 71 __GPIOF_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 72 break;
sahilmgandhi 18:6a4db94011d3 73 #endif
sahilmgandhi 18:6a4db94011d3 74 #if defined GPIOG_BASE
sahilmgandhi 18:6a4db94011d3 75 case PortG:
sahilmgandhi 18:6a4db94011d3 76 #if defined TARGET_STM32L4
sahilmgandhi 18:6a4db94011d3 77 __HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 78 HAL_PWREx_EnableVddIO2();
sahilmgandhi 18:6a4db94011d3 79 #endif
sahilmgandhi 18:6a4db94011d3 80 gpio_add = GPIOG_BASE;
sahilmgandhi 18:6a4db94011d3 81 __GPIOG_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 82 break;
sahilmgandhi 18:6a4db94011d3 83 #endif
sahilmgandhi 18:6a4db94011d3 84 #if defined GPIOH_BASE
sahilmgandhi 18:6a4db94011d3 85 case PortH:
sahilmgandhi 18:6a4db94011d3 86 gpio_add = GPIOH_BASE;
sahilmgandhi 18:6a4db94011d3 87 __GPIOH_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 88 break;
sahilmgandhi 18:6a4db94011d3 89 #endif
sahilmgandhi 18:6a4db94011d3 90 #if defined GPIOI_BASE
sahilmgandhi 18:6a4db94011d3 91 case PortI:
sahilmgandhi 18:6a4db94011d3 92 gpio_add = GPIOI_BASE;
sahilmgandhi 18:6a4db94011d3 93 __GPIOI_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 94 break;
sahilmgandhi 18:6a4db94011d3 95 #endif
sahilmgandhi 18:6a4db94011d3 96 #if defined GPIOJ_BASE
sahilmgandhi 18:6a4db94011d3 97 case PortJ:
sahilmgandhi 18:6a4db94011d3 98 gpio_add = GPIOJ_BASE;
sahilmgandhi 18:6a4db94011d3 99 __GPIOJ_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 100 break;
sahilmgandhi 18:6a4db94011d3 101 #endif
sahilmgandhi 18:6a4db94011d3 102 #if defined GPIOK_BASE
sahilmgandhi 18:6a4db94011d3 103 case PortK:
sahilmgandhi 18:6a4db94011d3 104 gpio_add = GPIOK_BASE;
sahilmgandhi 18:6a4db94011d3 105 __GPIOK_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 106 break;
sahilmgandhi 18:6a4db94011d3 107 #endif
sahilmgandhi 18:6a4db94011d3 108 default:
sahilmgandhi 18:6a4db94011d3 109 error("Pinmap error: wrong port number.");
sahilmgandhi 18:6a4db94011d3 110 break;
sahilmgandhi 18:6a4db94011d3 111 }
sahilmgandhi 18:6a4db94011d3 112 return (GPIO_TypeDef *) gpio_add;
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 uint32_t gpio_set(PinName pin) {
sahilmgandhi 18:6a4db94011d3 116 MBED_ASSERT(pin != (PinName)NC);
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
sahilmgandhi 18:6a4db94011d3 121 }
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 void gpio_init(gpio_t *obj, PinName pin) {
sahilmgandhi 18:6a4db94011d3 125 obj->pin = pin;
sahilmgandhi 18:6a4db94011d3 126 if (pin == (PinName)NC) {
sahilmgandhi 18:6a4db94011d3 127 return;
sahilmgandhi 18:6a4db94011d3 128 }
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 uint32_t port_index = STM_PORT(pin);
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 // Enable GPIO clock
sahilmgandhi 18:6a4db94011d3 133 GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 // Fill GPIO object structure for future use
sahilmgandhi 18:6a4db94011d3 136 obj->mask = gpio_set(pin);
sahilmgandhi 18:6a4db94011d3 137 obj->gpio = gpio;
sahilmgandhi 18:6a4db94011d3 138 obj->ll_pin = ll_pin_defines[STM_PIN(obj->pin)];
sahilmgandhi 18:6a4db94011d3 139 obj->reg_in = &gpio->IDR;
sahilmgandhi 18:6a4db94011d3 140 obj->reg_set = &gpio->BSRR;
sahilmgandhi 18:6a4db94011d3 141 #ifdef GPIO_IP_WITHOUT_BRR
sahilmgandhi 18:6a4db94011d3 142 obj->reg_clr = &gpio->BSRR;
sahilmgandhi 18:6a4db94011d3 143 #else
sahilmgandhi 18:6a4db94011d3 144 obj->reg_clr = &gpio->BRR;
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146 }
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 void gpio_mode(gpio_t *obj, PinMode mode) {
sahilmgandhi 18:6a4db94011d3 149 pin_mode(obj->pin, mode);
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 inline void gpio_dir(gpio_t *obj, PinDirection direction) {
sahilmgandhi 18:6a4db94011d3 153 if (direction == PIN_INPUT) {
sahilmgandhi 18:6a4db94011d3 154 LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT);
sahilmgandhi 18:6a4db94011d3 155 } else {
sahilmgandhi 18:6a4db94011d3 156 LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159