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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dac.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l1xx_ll_dac.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.2.0
sahilmgandhi 18:6a4db94011d3 6 * @date 01-July-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of DAC LL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32L1xx_LL_DAC_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32L1xx_LL_DAC_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32l1xx.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32L1xx_LL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 #if defined (DAC1)
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /** @defgroup DAC_LL DAC
sahilmgandhi 18:6a4db94011d3 56 * @{
sahilmgandhi 18:6a4db94011d3 57 */
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 60 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 63 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
sahilmgandhi 18:6a4db94011d3 64 * @{
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 /* Internal masks for DAC channels definition */
sahilmgandhi 18:6a4db94011d3 68 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
sahilmgandhi 18:6a4db94011d3 69 /* - channel bits position into register CR */
sahilmgandhi 18:6a4db94011d3 70 /* - channel bits position into register SWTRIG */
sahilmgandhi 18:6a4db94011d3 71 /* - channel register offset of data holding register DHRx */
sahilmgandhi 18:6a4db94011d3 72 /* - channel register offset of data output register DORx */
sahilmgandhi 18:6a4db94011d3 73 #define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
sahilmgandhi 18:6a4db94011d3 74 #define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
sahilmgandhi 18:6a4db94011d3 75 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
sahilmgandhi 18:6a4db94011d3 78 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
sahilmgandhi 18:6a4db94011d3 79 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 #define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
sahilmgandhi 18:6a4db94011d3 82 #define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
sahilmgandhi 18:6a4db94011d3 83 #define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
sahilmgandhi 18:6a4db94011d3 84 #define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
sahilmgandhi 18:6a4db94011d3 85 #define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
sahilmgandhi 18:6a4db94011d3 86 #define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
sahilmgandhi 18:6a4db94011d3 87 #define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
sahilmgandhi 18:6a4db94011d3 88 #define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
sahilmgandhi 18:6a4db94011d3 89 #define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
sahilmgandhi 18:6a4db94011d3 90 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 #define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
sahilmgandhi 18:6a4db94011d3 93 #define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
sahilmgandhi 18:6a4db94011d3 94 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 /* DAC registers bits positions */
sahilmgandhi 18:6a4db94011d3 97 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
sahilmgandhi 18:6a4db94011d3 98 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
sahilmgandhi 18:6a4db94011d3 99 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /* Miscellaneous data */
sahilmgandhi 18:6a4db94011d3 102 #define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /**
sahilmgandhi 18:6a4db94011d3 105 * @}
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
sahilmgandhi 18:6a4db94011d3 111 * @{
sahilmgandhi 18:6a4db94011d3 112 */
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /**
sahilmgandhi 18:6a4db94011d3 115 * @brief Driver macro reserved for internal use: isolate bits with the
sahilmgandhi 18:6a4db94011d3 116 * selected mask and shift them to the register LSB
sahilmgandhi 18:6a4db94011d3 117 * (shift mask on register position bit 0).
sahilmgandhi 18:6a4db94011d3 118 * @param __BITS__ Bits in register 32 bits
sahilmgandhi 18:6a4db94011d3 119 * @param __MASK__ Mask in register 32 bits
sahilmgandhi 18:6a4db94011d3 120 * @retval Bits in register 32 bits
sahilmgandhi 18:6a4db94011d3 121 */
sahilmgandhi 18:6a4db94011d3 122 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
sahilmgandhi 18:6a4db94011d3 123 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /**
sahilmgandhi 18:6a4db94011d3 126 * @brief Driver macro reserved for internal use: set a pointer to
sahilmgandhi 18:6a4db94011d3 127 * a register from a register basis from which an offset
sahilmgandhi 18:6a4db94011d3 128 * is applied.
sahilmgandhi 18:6a4db94011d3 129 * @param __REG__ Register basis from which the offset is applied.
sahilmgandhi 18:6a4db94011d3 130 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
sahilmgandhi 18:6a4db94011d3 131 * @retval Pointer to register address
sahilmgandhi 18:6a4db94011d3 132 */
sahilmgandhi 18:6a4db94011d3 133 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
sahilmgandhi 18:6a4db94011d3 134 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /**
sahilmgandhi 18:6a4db94011d3 137 * @}
sahilmgandhi 18:6a4db94011d3 138 */
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 142 #if defined(USE_FULL_LL_DRIVER)
sahilmgandhi 18:6a4db94011d3 143 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
sahilmgandhi 18:6a4db94011d3 144 * @{
sahilmgandhi 18:6a4db94011d3 145 */
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /**
sahilmgandhi 18:6a4db94011d3 148 * @brief Structure definition of some features of DAC instance.
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150 typedef struct
sahilmgandhi 18:6a4db94011d3 151 {
sahilmgandhi 18:6a4db94011d3 152 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
sahilmgandhi 18:6a4db94011d3 153 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 158 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 163 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
sahilmgandhi 18:6a4db94011d3 164 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
sahilmgandhi 18:6a4db94011d3 165 @note If waveform automatic generation mode is disabled, this parameter is discarded.
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 170 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 } LL_DAC_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /**
sahilmgandhi 18:6a4db94011d3 177 * @}
sahilmgandhi 18:6a4db94011d3 178 */
sahilmgandhi 18:6a4db94011d3 179 #endif /* USE_FULL_LL_DRIVER */
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 182 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
sahilmgandhi 18:6a4db94011d3 183 * @{
sahilmgandhi 18:6a4db94011d3 184 */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
sahilmgandhi 18:6a4db94011d3 187 * @brief Flags defines which can be used with LL_DAC_ReadReg function
sahilmgandhi 18:6a4db94011d3 188 * @{
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 /* DAC channel 1 flags */
sahilmgandhi 18:6a4db94011d3 191 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /* DAC channel 2 flags */
sahilmgandhi 18:6a4db94011d3 194 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
sahilmgandhi 18:6a4db94011d3 195 /**
sahilmgandhi 18:6a4db94011d3 196 * @}
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /** @defgroup DAC_LL_EC_IT DAC interruptions
sahilmgandhi 18:6a4db94011d3 200 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
sahilmgandhi 18:6a4db94011d3 201 * @{
sahilmgandhi 18:6a4db94011d3 202 */
sahilmgandhi 18:6a4db94011d3 203 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
sahilmgandhi 18:6a4db94011d3 204 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
sahilmgandhi 18:6a4db94011d3 205 /**
sahilmgandhi 18:6a4db94011d3 206 * @}
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
sahilmgandhi 18:6a4db94011d3 210 * @{
sahilmgandhi 18:6a4db94011d3 211 */
sahilmgandhi 18:6a4db94011d3 212 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
sahilmgandhi 18:6a4db94011d3 213 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
sahilmgandhi 18:6a4db94011d3 214 /**
sahilmgandhi 18:6a4db94011d3 215 * @}
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
sahilmgandhi 18:6a4db94011d3 219 * @{
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
sahilmgandhi 18:6a4db94011d3 222 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
sahilmgandhi 18:6a4db94011d3 223 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
sahilmgandhi 18:6a4db94011d3 224 #define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
sahilmgandhi 18:6a4db94011d3 225 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
sahilmgandhi 18:6a4db94011d3 226 #define LL_DAC_TRIG_EXT_TIM9_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
sahilmgandhi 18:6a4db94011d3 227 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
sahilmgandhi 18:6a4db94011d3 228 /**
sahilmgandhi 18:6a4db94011d3 229 * @}
sahilmgandhi 18:6a4db94011d3 230 */
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
sahilmgandhi 18:6a4db94011d3 233 * @{
sahilmgandhi 18:6a4db94011d3 234 */
sahilmgandhi 18:6a4db94011d3 235 #define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
sahilmgandhi 18:6a4db94011d3 236 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
sahilmgandhi 18:6a4db94011d3 237 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
sahilmgandhi 18:6a4db94011d3 238 /**
sahilmgandhi 18:6a4db94011d3 239 * @}
sahilmgandhi 18:6a4db94011d3 240 */
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
sahilmgandhi 18:6a4db94011d3 243 * @{
sahilmgandhi 18:6a4db94011d3 244 */
sahilmgandhi 18:6a4db94011d3 245 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 253 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 254 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 255 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 256 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 257 /**
sahilmgandhi 18:6a4db94011d3 258 * @}
sahilmgandhi 18:6a4db94011d3 259 */
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
sahilmgandhi 18:6a4db94011d3 262 * @{
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264 #define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 265 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 266 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 267 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 268 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 269 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 270 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 271 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 272 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 273 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 274 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 275 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
sahilmgandhi 18:6a4db94011d3 276 /**
sahilmgandhi 18:6a4db94011d3 277 * @}
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
sahilmgandhi 18:6a4db94011d3 281 * @{
sahilmgandhi 18:6a4db94011d3 282 */
sahilmgandhi 18:6a4db94011d3 283 #define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
sahilmgandhi 18:6a4db94011d3 284 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
sahilmgandhi 18:6a4db94011d3 285 /**
sahilmgandhi 18:6a4db94011d3 286 * @}
sahilmgandhi 18:6a4db94011d3 287 */
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
sahilmgandhi 18:6a4db94011d3 291 * @{
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293 #define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
sahilmgandhi 18:6a4db94011d3 294 #define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
sahilmgandhi 18:6a4db94011d3 295 /**
sahilmgandhi 18:6a4db94011d3 296 * @}
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
sahilmgandhi 18:6a4db94011d3 300 * @{
sahilmgandhi 18:6a4db94011d3 301 */
sahilmgandhi 18:6a4db94011d3 302 /* List of DAC registers intended to be used (most commonly) with */
sahilmgandhi 18:6a4db94011d3 303 /* DMA transfer. */
sahilmgandhi 18:6a4db94011d3 304 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
sahilmgandhi 18:6a4db94011d3 305 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
sahilmgandhi 18:6a4db94011d3 306 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
sahilmgandhi 18:6a4db94011d3 307 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
sahilmgandhi 18:6a4db94011d3 308 /**
sahilmgandhi 18:6a4db94011d3 309 * @}
sahilmgandhi 18:6a4db94011d3 310 */
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
sahilmgandhi 18:6a4db94011d3 313 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
sahilmgandhi 18:6a4db94011d3 314 * not timeout values.
sahilmgandhi 18:6a4db94011d3 315 * For details on delays values, refer to descriptions in source code
sahilmgandhi 18:6a4db94011d3 316 * above each literal definition.
sahilmgandhi 18:6a4db94011d3 317 * @{
sahilmgandhi 18:6a4db94011d3 318 */
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /* Delay for DAC channel voltage settling time from DAC channel startup */
sahilmgandhi 18:6a4db94011d3 321 /* (transition from disable to enable). */
sahilmgandhi 18:6a4db94011d3 322 /* Note: DAC channel startup time depends on board application environment: */
sahilmgandhi 18:6a4db94011d3 323 /* impedance connected to DAC channel output. */
sahilmgandhi 18:6a4db94011d3 324 /* The delay below is specified under conditions: */
sahilmgandhi 18:6a4db94011d3 325 /* - voltage maximum transition (lowest to highest value) */
sahilmgandhi 18:6a4db94011d3 326 /* - until voltage reaches final value +-1LSB */
sahilmgandhi 18:6a4db94011d3 327 /* - DAC channel output buffer enabled */
sahilmgandhi 18:6a4db94011d3 328 /* - load impedance of 5kOhm (min), 50pF (max) */
sahilmgandhi 18:6a4db94011d3 329 /* Literal set to maximum value (refer to device datasheet, */
sahilmgandhi 18:6a4db94011d3 330 /* parameter "tWAKEUP"). */
sahilmgandhi 18:6a4db94011d3 331 /* Unit: us */
sahilmgandhi 18:6a4db94011d3 332 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 /* Delay for DAC channel voltage settling time. */
sahilmgandhi 18:6a4db94011d3 335 /* Note: DAC channel startup time depends on board application environment: */
sahilmgandhi 18:6a4db94011d3 336 /* impedance connected to DAC channel output. */
sahilmgandhi 18:6a4db94011d3 337 /* The delay below is specified under conditions: */
sahilmgandhi 18:6a4db94011d3 338 /* - voltage maximum transition (lowest to highest value) */
sahilmgandhi 18:6a4db94011d3 339 /* - until voltage reaches final value +-1LSB */
sahilmgandhi 18:6a4db94011d3 340 /* - DAC channel output buffer enabled */
sahilmgandhi 18:6a4db94011d3 341 /* - load impedance of 5kOhm min, 50pF max */
sahilmgandhi 18:6a4db94011d3 342 /* Literal set to maximum value (refer to device datasheet, */
sahilmgandhi 18:6a4db94011d3 343 /* parameter "tSETTLING"). */
sahilmgandhi 18:6a4db94011d3 344 /* Unit: us */
sahilmgandhi 18:6a4db94011d3 345 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /*!< Delay for DAC channel voltage settling time */
sahilmgandhi 18:6a4db94011d3 346 /**
sahilmgandhi 18:6a4db94011d3 347 * @}
sahilmgandhi 18:6a4db94011d3 348 */
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /**
sahilmgandhi 18:6a4db94011d3 351 * @}
sahilmgandhi 18:6a4db94011d3 352 */
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 355 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
sahilmgandhi 18:6a4db94011d3 356 * @{
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
sahilmgandhi 18:6a4db94011d3 360 * @{
sahilmgandhi 18:6a4db94011d3 361 */
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /**
sahilmgandhi 18:6a4db94011d3 364 * @brief Write a value in DAC register
sahilmgandhi 18:6a4db94011d3 365 * @param __INSTANCE__ DAC Instance
sahilmgandhi 18:6a4db94011d3 366 * @param __REG__ Register to be written
sahilmgandhi 18:6a4db94011d3 367 * @param __VALUE__ Value to be written in the register
sahilmgandhi 18:6a4db94011d3 368 * @retval None
sahilmgandhi 18:6a4db94011d3 369 */
sahilmgandhi 18:6a4db94011d3 370 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /**
sahilmgandhi 18:6a4db94011d3 373 * @brief Read a value in DAC register
sahilmgandhi 18:6a4db94011d3 374 * @param __INSTANCE__ DAC Instance
sahilmgandhi 18:6a4db94011d3 375 * @param __REG__ Register to be read
sahilmgandhi 18:6a4db94011d3 376 * @retval Register value
sahilmgandhi 18:6a4db94011d3 377 */
sahilmgandhi 18:6a4db94011d3 378 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 /**
sahilmgandhi 18:6a4db94011d3 381 * @}
sahilmgandhi 18:6a4db94011d3 382 */
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
sahilmgandhi 18:6a4db94011d3 385 * @{
sahilmgandhi 18:6a4db94011d3 386 */
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 /**
sahilmgandhi 18:6a4db94011d3 389 * @brief Helper macro to get DAC channel number in decimal format
sahilmgandhi 18:6a4db94011d3 390 * from literals LL_DAC_CHANNEL_x.
sahilmgandhi 18:6a4db94011d3 391 * Example:
sahilmgandhi 18:6a4db94011d3 392 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
sahilmgandhi 18:6a4db94011d3 393 * will return decimal number "1".
sahilmgandhi 18:6a4db94011d3 394 * @note The input can be a value from functions where a channel
sahilmgandhi 18:6a4db94011d3 395 * number is returned.
sahilmgandhi 18:6a4db94011d3 396 * @param __CHANNEL__ This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 397 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 398 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 399 * @retval 1...2
sahilmgandhi 18:6a4db94011d3 400 */
sahilmgandhi 18:6a4db94011d3 401 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
sahilmgandhi 18:6a4db94011d3 402 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 /**
sahilmgandhi 18:6a4db94011d3 405 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
sahilmgandhi 18:6a4db94011d3 406 * from number in decimal format.
sahilmgandhi 18:6a4db94011d3 407 * Example:
sahilmgandhi 18:6a4db94011d3 408 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
sahilmgandhi 18:6a4db94011d3 409 * will return a data equivalent to "LL_DAC_CHANNEL_1".
sahilmgandhi 18:6a4db94011d3 410 * @note If the input parameter does not correspond to a DAC channel,
sahilmgandhi 18:6a4db94011d3 411 * this macro returns value '0'.
sahilmgandhi 18:6a4db94011d3 412 * @param __DECIMAL_NB__ 1...2
sahilmgandhi 18:6a4db94011d3 413 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 414 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 415 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 416 */
sahilmgandhi 18:6a4db94011d3 417 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
sahilmgandhi 18:6a4db94011d3 418 (((__DECIMAL_NB__) == 1U) \
sahilmgandhi 18:6a4db94011d3 419 ? ( \
sahilmgandhi 18:6a4db94011d3 420 LL_DAC_CHANNEL_1 \
sahilmgandhi 18:6a4db94011d3 421 ) \
sahilmgandhi 18:6a4db94011d3 422 : \
sahilmgandhi 18:6a4db94011d3 423 (((__DECIMAL_NB__) == 2U) \
sahilmgandhi 18:6a4db94011d3 424 ? ( \
sahilmgandhi 18:6a4db94011d3 425 LL_DAC_CHANNEL_2 \
sahilmgandhi 18:6a4db94011d3 426 ) \
sahilmgandhi 18:6a4db94011d3 427 : \
sahilmgandhi 18:6a4db94011d3 428 ( \
sahilmgandhi 18:6a4db94011d3 429 0 \
sahilmgandhi 18:6a4db94011d3 430 ) \
sahilmgandhi 18:6a4db94011d3 431 ) \
sahilmgandhi 18:6a4db94011d3 432 )
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /**
sahilmgandhi 18:6a4db94011d3 435 * @brief Helper macro to define the DAC conversion data full-scale digital
sahilmgandhi 18:6a4db94011d3 436 * value corresponding to the selected DAC resolution.
sahilmgandhi 18:6a4db94011d3 437 * @note DAC conversion data full-scale corresponds to voltage range
sahilmgandhi 18:6a4db94011d3 438 * determined by analog voltage references Vref+ and Vref-
sahilmgandhi 18:6a4db94011d3 439 * (refer to reference manual).
sahilmgandhi 18:6a4db94011d3 440 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 441 * @arg @ref LL_DAC_RESOLUTION_12B
sahilmgandhi 18:6a4db94011d3 442 * @arg @ref LL_DAC_RESOLUTION_8B
sahilmgandhi 18:6a4db94011d3 443 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
sahilmgandhi 18:6a4db94011d3 444 */
sahilmgandhi 18:6a4db94011d3 445 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
sahilmgandhi 18:6a4db94011d3 446 (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /**
sahilmgandhi 18:6a4db94011d3 449 * @brief Helper macro to calculate the DAC conversion data (unit: digital
sahilmgandhi 18:6a4db94011d3 450 * value) corresponding to a voltage (unit: mVolt).
sahilmgandhi 18:6a4db94011d3 451 * @note This helper macro is intended to provide input data in voltage
sahilmgandhi 18:6a4db94011d3 452 * rather than digital value,
sahilmgandhi 18:6a4db94011d3 453 * to be used with LL DAC functions such as
sahilmgandhi 18:6a4db94011d3 454 * @ref LL_DAC_ConvertData12RightAligned().
sahilmgandhi 18:6a4db94011d3 455 * @note Analog reference voltage (Vref+) must be either known from
sahilmgandhi 18:6a4db94011d3 456 * user board environment or can be calculated using ADC measurement
sahilmgandhi 18:6a4db94011d3 457 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
sahilmgandhi 18:6a4db94011d3 458 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
sahilmgandhi 18:6a4db94011d3 459 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
sahilmgandhi 18:6a4db94011d3 460 * (unit: mVolt).
sahilmgandhi 18:6a4db94011d3 461 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 462 * @arg @ref LL_DAC_RESOLUTION_12B
sahilmgandhi 18:6a4db94011d3 463 * @arg @ref LL_DAC_RESOLUTION_8B
sahilmgandhi 18:6a4db94011d3 464 * @retval DAC conversion data (unit: digital value)
sahilmgandhi 18:6a4db94011d3 465 */
sahilmgandhi 18:6a4db94011d3 466 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
sahilmgandhi 18:6a4db94011d3 467 __DAC_VOLTAGE__,\
sahilmgandhi 18:6a4db94011d3 468 __DAC_RESOLUTION__) \
sahilmgandhi 18:6a4db94011d3 469 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
sahilmgandhi 18:6a4db94011d3 470 / (__VREFANALOG_VOLTAGE__) \
sahilmgandhi 18:6a4db94011d3 471 )
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 /**
sahilmgandhi 18:6a4db94011d3 474 * @}
sahilmgandhi 18:6a4db94011d3 475 */
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /**
sahilmgandhi 18:6a4db94011d3 478 * @}
sahilmgandhi 18:6a4db94011d3 479 */
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 483 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
sahilmgandhi 18:6a4db94011d3 484 * @{
sahilmgandhi 18:6a4db94011d3 485 */
sahilmgandhi 18:6a4db94011d3 486 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
sahilmgandhi 18:6a4db94011d3 487 * @{
sahilmgandhi 18:6a4db94011d3 488 */
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 /**
sahilmgandhi 18:6a4db94011d3 491 * @brief Set the conversion trigger source for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 492 * @note For conversion trigger source to be effective, DAC trigger
sahilmgandhi 18:6a4db94011d3 493 * must be enabled using function @ref LL_DAC_EnableTrigger().
sahilmgandhi 18:6a4db94011d3 494 * @note To set conversion trigger source, DAC channel must be disabled.
sahilmgandhi 18:6a4db94011d3 495 * Otherwise, the setting is discarded.
sahilmgandhi 18:6a4db94011d3 496 * @note Availability of parameters of trigger sources from timer
sahilmgandhi 18:6a4db94011d3 497 * depends on timers availability on the selected device.
sahilmgandhi 18:6a4db94011d3 498 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
sahilmgandhi 18:6a4db94011d3 499 * CR TSEL2 LL_DAC_SetTriggerSource
sahilmgandhi 18:6a4db94011d3 500 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 501 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 502 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 503 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 504 * @param TriggerSource This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 505 * @arg @ref LL_DAC_TRIG_SOFTWARE
sahilmgandhi 18:6a4db94011d3 506 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
sahilmgandhi 18:6a4db94011d3 507 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
sahilmgandhi 18:6a4db94011d3 508 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
sahilmgandhi 18:6a4db94011d3 509 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
sahilmgandhi 18:6a4db94011d3 510 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
sahilmgandhi 18:6a4db94011d3 511 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
sahilmgandhi 18:6a4db94011d3 512 * @retval None
sahilmgandhi 18:6a4db94011d3 513 */
sahilmgandhi 18:6a4db94011d3 514 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
sahilmgandhi 18:6a4db94011d3 515 {
sahilmgandhi 18:6a4db94011d3 516 MODIFY_REG(DACx->CR,
sahilmgandhi 18:6a4db94011d3 517 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
sahilmgandhi 18:6a4db94011d3 518 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 519 }
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 /**
sahilmgandhi 18:6a4db94011d3 522 * @brief Get the conversion trigger source for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 523 * @note For conversion trigger source to be effective, DAC trigger
sahilmgandhi 18:6a4db94011d3 524 * must be enabled using function @ref LL_DAC_EnableTrigger().
sahilmgandhi 18:6a4db94011d3 525 * @note Availability of parameters of trigger sources from timer
sahilmgandhi 18:6a4db94011d3 526 * depends on timers availability on the selected device.
sahilmgandhi 18:6a4db94011d3 527 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
sahilmgandhi 18:6a4db94011d3 528 * CR TSEL2 LL_DAC_GetTriggerSource
sahilmgandhi 18:6a4db94011d3 529 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 530 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 531 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 532 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 533 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 534 * @arg @ref LL_DAC_TRIG_SOFTWARE
sahilmgandhi 18:6a4db94011d3 535 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
sahilmgandhi 18:6a4db94011d3 536 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
sahilmgandhi 18:6a4db94011d3 537 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
sahilmgandhi 18:6a4db94011d3 538 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
sahilmgandhi 18:6a4db94011d3 539 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
sahilmgandhi 18:6a4db94011d3 540 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
sahilmgandhi 18:6a4db94011d3 541 */
sahilmgandhi 18:6a4db94011d3 542 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 543 {
sahilmgandhi 18:6a4db94011d3 544 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 545 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
sahilmgandhi 18:6a4db94011d3 546 );
sahilmgandhi 18:6a4db94011d3 547 }
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 /**
sahilmgandhi 18:6a4db94011d3 550 * @brief Set the waveform automatic generation mode
sahilmgandhi 18:6a4db94011d3 551 * for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 552 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
sahilmgandhi 18:6a4db94011d3 553 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
sahilmgandhi 18:6a4db94011d3 554 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 555 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 556 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 557 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 558 * @param WaveAutoGeneration This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 559 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
sahilmgandhi 18:6a4db94011d3 560 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
sahilmgandhi 18:6a4db94011d3 561 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
sahilmgandhi 18:6a4db94011d3 562 * @retval None
sahilmgandhi 18:6a4db94011d3 563 */
sahilmgandhi 18:6a4db94011d3 564 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
sahilmgandhi 18:6a4db94011d3 565 {
sahilmgandhi 18:6a4db94011d3 566 MODIFY_REG(DACx->CR,
sahilmgandhi 18:6a4db94011d3 567 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
sahilmgandhi 18:6a4db94011d3 568 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 569 }
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 /**
sahilmgandhi 18:6a4db94011d3 572 * @brief Get the waveform automatic generation mode
sahilmgandhi 18:6a4db94011d3 573 * for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 574 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
sahilmgandhi 18:6a4db94011d3 575 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
sahilmgandhi 18:6a4db94011d3 576 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 577 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 578 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 579 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 580 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 581 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
sahilmgandhi 18:6a4db94011d3 582 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
sahilmgandhi 18:6a4db94011d3 583 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
sahilmgandhi 18:6a4db94011d3 584 */
sahilmgandhi 18:6a4db94011d3 585 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 586 {
sahilmgandhi 18:6a4db94011d3 587 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 588 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
sahilmgandhi 18:6a4db94011d3 589 );
sahilmgandhi 18:6a4db94011d3 590 }
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 /**
sahilmgandhi 18:6a4db94011d3 593 * @brief Set the noise waveform generation for the selected DAC channel:
sahilmgandhi 18:6a4db94011d3 594 * Noise mode and parameters LFSR (linear feedback shift register).
sahilmgandhi 18:6a4db94011d3 595 * @note For wave generation to be effective, DAC channel
sahilmgandhi 18:6a4db94011d3 596 * wave generation mode must be enabled using
sahilmgandhi 18:6a4db94011d3 597 * function @ref LL_DAC_SetWaveAutoGeneration().
sahilmgandhi 18:6a4db94011d3 598 * @note This setting can be set when the selected DAC channel is disabled
sahilmgandhi 18:6a4db94011d3 599 * (otherwise, the setting operation is ignored).
sahilmgandhi 18:6a4db94011d3 600 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
sahilmgandhi 18:6a4db94011d3 601 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
sahilmgandhi 18:6a4db94011d3 602 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 603 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 604 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 605 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 606 * @param NoiseLFSRMask This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 607 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
sahilmgandhi 18:6a4db94011d3 608 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
sahilmgandhi 18:6a4db94011d3 609 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
sahilmgandhi 18:6a4db94011d3 610 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
sahilmgandhi 18:6a4db94011d3 611 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
sahilmgandhi 18:6a4db94011d3 612 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
sahilmgandhi 18:6a4db94011d3 613 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
sahilmgandhi 18:6a4db94011d3 614 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
sahilmgandhi 18:6a4db94011d3 615 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
sahilmgandhi 18:6a4db94011d3 616 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
sahilmgandhi 18:6a4db94011d3 617 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
sahilmgandhi 18:6a4db94011d3 618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
sahilmgandhi 18:6a4db94011d3 619 * @retval None
sahilmgandhi 18:6a4db94011d3 620 */
sahilmgandhi 18:6a4db94011d3 621 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
sahilmgandhi 18:6a4db94011d3 622 {
sahilmgandhi 18:6a4db94011d3 623 MODIFY_REG(DACx->CR,
sahilmgandhi 18:6a4db94011d3 624 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
sahilmgandhi 18:6a4db94011d3 625 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 626 }
sahilmgandhi 18:6a4db94011d3 627
sahilmgandhi 18:6a4db94011d3 628 /**
sahilmgandhi 18:6a4db94011d3 629 * @brief Set the noise waveform generation for the selected DAC channel:
sahilmgandhi 18:6a4db94011d3 630 * Noise mode and parameters LFSR (linear feedback shift register).
sahilmgandhi 18:6a4db94011d3 631 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
sahilmgandhi 18:6a4db94011d3 632 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
sahilmgandhi 18:6a4db94011d3 633 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 634 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 635 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 636 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 637 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 638 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
sahilmgandhi 18:6a4db94011d3 639 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
sahilmgandhi 18:6a4db94011d3 640 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
sahilmgandhi 18:6a4db94011d3 641 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
sahilmgandhi 18:6a4db94011d3 642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
sahilmgandhi 18:6a4db94011d3 643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
sahilmgandhi 18:6a4db94011d3 644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
sahilmgandhi 18:6a4db94011d3 645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
sahilmgandhi 18:6a4db94011d3 646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
sahilmgandhi 18:6a4db94011d3 647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
sahilmgandhi 18:6a4db94011d3 648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
sahilmgandhi 18:6a4db94011d3 649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
sahilmgandhi 18:6a4db94011d3 650 */
sahilmgandhi 18:6a4db94011d3 651 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 652 {
sahilmgandhi 18:6a4db94011d3 653 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 654 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
sahilmgandhi 18:6a4db94011d3 655 );
sahilmgandhi 18:6a4db94011d3 656 }
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /**
sahilmgandhi 18:6a4db94011d3 659 * @brief Set the triangle waveform generation for the selected DAC channel:
sahilmgandhi 18:6a4db94011d3 660 * triangle mode and amplitude.
sahilmgandhi 18:6a4db94011d3 661 * @note For wave generation to be effective, DAC channel
sahilmgandhi 18:6a4db94011d3 662 * wave generation mode must be enabled using
sahilmgandhi 18:6a4db94011d3 663 * function @ref LL_DAC_SetWaveAutoGeneration().
sahilmgandhi 18:6a4db94011d3 664 * @note This setting can be set when the selected DAC channel is disabled
sahilmgandhi 18:6a4db94011d3 665 * (otherwise, the setting operation is ignored).
sahilmgandhi 18:6a4db94011d3 666 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
sahilmgandhi 18:6a4db94011d3 667 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
sahilmgandhi 18:6a4db94011d3 668 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 669 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 670 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 671 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 672 * @param TriangleAmplitude This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 673 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
sahilmgandhi 18:6a4db94011d3 674 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
sahilmgandhi 18:6a4db94011d3 675 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
sahilmgandhi 18:6a4db94011d3 676 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
sahilmgandhi 18:6a4db94011d3 677 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
sahilmgandhi 18:6a4db94011d3 678 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
sahilmgandhi 18:6a4db94011d3 679 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
sahilmgandhi 18:6a4db94011d3 680 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
sahilmgandhi 18:6a4db94011d3 681 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
sahilmgandhi 18:6a4db94011d3 682 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
sahilmgandhi 18:6a4db94011d3 683 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
sahilmgandhi 18:6a4db94011d3 684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
sahilmgandhi 18:6a4db94011d3 685 * @retval None
sahilmgandhi 18:6a4db94011d3 686 */
sahilmgandhi 18:6a4db94011d3 687 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
sahilmgandhi 18:6a4db94011d3 688 {
sahilmgandhi 18:6a4db94011d3 689 MODIFY_REG(DACx->CR,
sahilmgandhi 18:6a4db94011d3 690 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
sahilmgandhi 18:6a4db94011d3 691 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 692 }
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 /**
sahilmgandhi 18:6a4db94011d3 695 * @brief Set the triangle waveform generation for the selected DAC channel:
sahilmgandhi 18:6a4db94011d3 696 * triangle mode and amplitude.
sahilmgandhi 18:6a4db94011d3 697 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
sahilmgandhi 18:6a4db94011d3 698 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
sahilmgandhi 18:6a4db94011d3 699 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 700 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 701 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 702 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 703 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 704 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
sahilmgandhi 18:6a4db94011d3 705 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
sahilmgandhi 18:6a4db94011d3 706 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
sahilmgandhi 18:6a4db94011d3 707 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
sahilmgandhi 18:6a4db94011d3 708 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
sahilmgandhi 18:6a4db94011d3 709 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
sahilmgandhi 18:6a4db94011d3 710 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
sahilmgandhi 18:6a4db94011d3 711 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
sahilmgandhi 18:6a4db94011d3 712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
sahilmgandhi 18:6a4db94011d3 713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
sahilmgandhi 18:6a4db94011d3 714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
sahilmgandhi 18:6a4db94011d3 715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
sahilmgandhi 18:6a4db94011d3 716 */
sahilmgandhi 18:6a4db94011d3 717 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 718 {
sahilmgandhi 18:6a4db94011d3 719 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 720 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
sahilmgandhi 18:6a4db94011d3 721 );
sahilmgandhi 18:6a4db94011d3 722 }
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 /**
sahilmgandhi 18:6a4db94011d3 725 * @brief Set the output buffer for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 726 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
sahilmgandhi 18:6a4db94011d3 727 * CR BOFF2 LL_DAC_SetOutputBuffer
sahilmgandhi 18:6a4db94011d3 728 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 729 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 730 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 731 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 732 * @param OutputBuffer This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 733 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
sahilmgandhi 18:6a4db94011d3 734 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
sahilmgandhi 18:6a4db94011d3 735 * @retval None
sahilmgandhi 18:6a4db94011d3 736 */
sahilmgandhi 18:6a4db94011d3 737 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
sahilmgandhi 18:6a4db94011d3 738 {
sahilmgandhi 18:6a4db94011d3 739 MODIFY_REG(DACx->CR,
sahilmgandhi 18:6a4db94011d3 740 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
sahilmgandhi 18:6a4db94011d3 741 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 742 }
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 /**
sahilmgandhi 18:6a4db94011d3 745 * @brief Get the output buffer state for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 746 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
sahilmgandhi 18:6a4db94011d3 747 * CR BOFF2 LL_DAC_GetOutputBuffer
sahilmgandhi 18:6a4db94011d3 748 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 749 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 750 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 751 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 752 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 753 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
sahilmgandhi 18:6a4db94011d3 754 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
sahilmgandhi 18:6a4db94011d3 755 */
sahilmgandhi 18:6a4db94011d3 756 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 757 {
sahilmgandhi 18:6a4db94011d3 758 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 759 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
sahilmgandhi 18:6a4db94011d3 760 );
sahilmgandhi 18:6a4db94011d3 761 }
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 /**
sahilmgandhi 18:6a4db94011d3 764 * @}
sahilmgandhi 18:6a4db94011d3 765 */
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
sahilmgandhi 18:6a4db94011d3 768 * @{
sahilmgandhi 18:6a4db94011d3 769 */
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 /**
sahilmgandhi 18:6a4db94011d3 772 * @brief Enable DAC DMA transfer request of the selected channel.
sahilmgandhi 18:6a4db94011d3 773 * @note To configure DMA source address (peripheral address),
sahilmgandhi 18:6a4db94011d3 774 * use function @ref LL_DAC_DMA_GetRegAddr().
sahilmgandhi 18:6a4db94011d3 775 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
sahilmgandhi 18:6a4db94011d3 776 * CR DMAEN2 LL_DAC_EnableDMAReq
sahilmgandhi 18:6a4db94011d3 777 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 778 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 779 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 780 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 781 * @retval None
sahilmgandhi 18:6a4db94011d3 782 */
sahilmgandhi 18:6a4db94011d3 783 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 784 {
sahilmgandhi 18:6a4db94011d3 785 SET_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 786 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 787 }
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 /**
sahilmgandhi 18:6a4db94011d3 790 * @brief Disable DAC DMA transfer request of the selected channel.
sahilmgandhi 18:6a4db94011d3 791 * @note To configure DMA source address (peripheral address),
sahilmgandhi 18:6a4db94011d3 792 * use function @ref LL_DAC_DMA_GetRegAddr().
sahilmgandhi 18:6a4db94011d3 793 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
sahilmgandhi 18:6a4db94011d3 794 * CR DMAEN2 LL_DAC_DisableDMAReq
sahilmgandhi 18:6a4db94011d3 795 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 796 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 797 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 798 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 799 * @retval None
sahilmgandhi 18:6a4db94011d3 800 */
sahilmgandhi 18:6a4db94011d3 801 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 802 {
sahilmgandhi 18:6a4db94011d3 803 CLEAR_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 804 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 805 }
sahilmgandhi 18:6a4db94011d3 806
sahilmgandhi 18:6a4db94011d3 807 /**
sahilmgandhi 18:6a4db94011d3 808 * @brief Get DAC DMA transfer request state of the selected channel.
sahilmgandhi 18:6a4db94011d3 809 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
sahilmgandhi 18:6a4db94011d3 810 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
sahilmgandhi 18:6a4db94011d3 811 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
sahilmgandhi 18:6a4db94011d3 812 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 813 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 814 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 815 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 816 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 817 */
sahilmgandhi 18:6a4db94011d3 818 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 819 {
sahilmgandhi 18:6a4db94011d3 820 return (READ_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 821 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 822 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
sahilmgandhi 18:6a4db94011d3 823 }
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 /**
sahilmgandhi 18:6a4db94011d3 826 * @brief Function to help to configure DMA transfer to DAC: retrieve the
sahilmgandhi 18:6a4db94011d3 827 * DAC register address from DAC instance and a list of DAC registers
sahilmgandhi 18:6a4db94011d3 828 * intended to be used (most commonly) with DMA transfer.
sahilmgandhi 18:6a4db94011d3 829 * @note These DAC registers are data holding registers:
sahilmgandhi 18:6a4db94011d3 830 * when DAC conversion is requested, DAC generates a DMA transfer
sahilmgandhi 18:6a4db94011d3 831 * request to have data available in DAC data holding registers.
sahilmgandhi 18:6a4db94011d3 832 * @note This macro is intended to be used with LL DMA driver, refer to
sahilmgandhi 18:6a4db94011d3 833 * function "LL_DMA_ConfigAddresses()".
sahilmgandhi 18:6a4db94011d3 834 * Example:
sahilmgandhi 18:6a4db94011d3 835 * LL_DMA_ConfigAddresses(DMA1,
sahilmgandhi 18:6a4db94011d3 836 * LL_DMA_CHANNEL_1,
sahilmgandhi 18:6a4db94011d3 837 * (uint32_t)&< array or variable >,
sahilmgandhi 18:6a4db94011d3 838 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
sahilmgandhi 18:6a4db94011d3 839 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
sahilmgandhi 18:6a4db94011d3 840 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
sahilmgandhi 18:6a4db94011d3 841 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
sahilmgandhi 18:6a4db94011d3 842 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
sahilmgandhi 18:6a4db94011d3 843 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
sahilmgandhi 18:6a4db94011d3 844 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
sahilmgandhi 18:6a4db94011d3 845 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
sahilmgandhi 18:6a4db94011d3 846 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 847 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 848 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 849 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 850 * @param Register This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 851 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
sahilmgandhi 18:6a4db94011d3 852 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
sahilmgandhi 18:6a4db94011d3 853 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
sahilmgandhi 18:6a4db94011d3 854 * @retval DAC register address
sahilmgandhi 18:6a4db94011d3 855 */
sahilmgandhi 18:6a4db94011d3 856 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
sahilmgandhi 18:6a4db94011d3 857 {
sahilmgandhi 18:6a4db94011d3 858 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
sahilmgandhi 18:6a4db94011d3 859 /* DAC channel selected. */
sahilmgandhi 18:6a4db94011d3 860 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
sahilmgandhi 18:6a4db94011d3 861 }
sahilmgandhi 18:6a4db94011d3 862 /**
sahilmgandhi 18:6a4db94011d3 863 * @}
sahilmgandhi 18:6a4db94011d3 864 */
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
sahilmgandhi 18:6a4db94011d3 867 * @{
sahilmgandhi 18:6a4db94011d3 868 */
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 /**
sahilmgandhi 18:6a4db94011d3 871 * @brief Enable DAC selected channel.
sahilmgandhi 18:6a4db94011d3 872 * @rmtoll CR EN1 LL_DAC_Enable\n
sahilmgandhi 18:6a4db94011d3 873 * CR EN2 LL_DAC_Enable
sahilmgandhi 18:6a4db94011d3 874 * @note After enable from off state, DAC channel requires a delay
sahilmgandhi 18:6a4db94011d3 875 * for output voltage to reach accuracy +/- 1 LSB.
sahilmgandhi 18:6a4db94011d3 876 * Refer to device datasheet, parameter "tWAKEUP".
sahilmgandhi 18:6a4db94011d3 877 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 878 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 879 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 880 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 881 * @retval None
sahilmgandhi 18:6a4db94011d3 882 */
sahilmgandhi 18:6a4db94011d3 883 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 884 {
sahilmgandhi 18:6a4db94011d3 885 SET_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 886 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 887 }
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 /**
sahilmgandhi 18:6a4db94011d3 890 * @brief Disable DAC selected channel.
sahilmgandhi 18:6a4db94011d3 891 * @rmtoll CR EN1 LL_DAC_Disable\n
sahilmgandhi 18:6a4db94011d3 892 * CR EN2 LL_DAC_Disable
sahilmgandhi 18:6a4db94011d3 893 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 894 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 895 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 896 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 897 * @retval None
sahilmgandhi 18:6a4db94011d3 898 */
sahilmgandhi 18:6a4db94011d3 899 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 CLEAR_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 902 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 903 }
sahilmgandhi 18:6a4db94011d3 904
sahilmgandhi 18:6a4db94011d3 905 /**
sahilmgandhi 18:6a4db94011d3 906 * @brief Get DAC enable state of the selected channel.
sahilmgandhi 18:6a4db94011d3 907 * (0: DAC channel is disabled, 1: DAC channel is enabled)
sahilmgandhi 18:6a4db94011d3 908 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
sahilmgandhi 18:6a4db94011d3 909 * CR EN2 LL_DAC_IsEnabled
sahilmgandhi 18:6a4db94011d3 910 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 911 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 912 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 913 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 914 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 915 */
sahilmgandhi 18:6a4db94011d3 916 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 917 {
sahilmgandhi 18:6a4db94011d3 918 return (READ_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 919 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 920 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
sahilmgandhi 18:6a4db94011d3 921 }
sahilmgandhi 18:6a4db94011d3 922
sahilmgandhi 18:6a4db94011d3 923 /**
sahilmgandhi 18:6a4db94011d3 924 * @brief Enable DAC trigger of the selected channel.
sahilmgandhi 18:6a4db94011d3 925 * @note - If DAC trigger is disabled, DAC conversion is performed
sahilmgandhi 18:6a4db94011d3 926 * automatically once the data holding register is updated,
sahilmgandhi 18:6a4db94011d3 927 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
sahilmgandhi 18:6a4db94011d3 928 * @ref LL_DAC_ConvertData12RightAligned(), ...
sahilmgandhi 18:6a4db94011d3 929 * - If DAC trigger is enabled, DAC conversion is performed
sahilmgandhi 18:6a4db94011d3 930 * only when a hardware of software trigger event is occurring.
sahilmgandhi 18:6a4db94011d3 931 * Select trigger source using
sahilmgandhi 18:6a4db94011d3 932 * function @ref LL_DAC_SetTriggerSource().
sahilmgandhi 18:6a4db94011d3 933 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
sahilmgandhi 18:6a4db94011d3 934 * CR TEN2 LL_DAC_EnableTrigger
sahilmgandhi 18:6a4db94011d3 935 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 936 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 937 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 938 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 939 * @retval None
sahilmgandhi 18:6a4db94011d3 940 */
sahilmgandhi 18:6a4db94011d3 941 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 942 {
sahilmgandhi 18:6a4db94011d3 943 SET_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 944 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 945 }
sahilmgandhi 18:6a4db94011d3 946
sahilmgandhi 18:6a4db94011d3 947 /**
sahilmgandhi 18:6a4db94011d3 948 * @brief Disable DAC trigger of the selected channel.
sahilmgandhi 18:6a4db94011d3 949 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
sahilmgandhi 18:6a4db94011d3 950 * CR TEN2 LL_DAC_DisableTrigger
sahilmgandhi 18:6a4db94011d3 951 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 952 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 953 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 954 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 955 * @retval None
sahilmgandhi 18:6a4db94011d3 956 */
sahilmgandhi 18:6a4db94011d3 957 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 CLEAR_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 960 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 961 }
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /**
sahilmgandhi 18:6a4db94011d3 964 * @brief Get DAC trigger state of the selected channel.
sahilmgandhi 18:6a4db94011d3 965 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
sahilmgandhi 18:6a4db94011d3 966 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
sahilmgandhi 18:6a4db94011d3 967 * CR TEN2 LL_DAC_IsTriggerEnabled
sahilmgandhi 18:6a4db94011d3 968 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 969 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 970 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 971 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 972 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 973 */
sahilmgandhi 18:6a4db94011d3 974 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 975 {
sahilmgandhi 18:6a4db94011d3 976 return (READ_BIT(DACx->CR,
sahilmgandhi 18:6a4db94011d3 977 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
sahilmgandhi 18:6a4db94011d3 978 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
sahilmgandhi 18:6a4db94011d3 979 }
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 /**
sahilmgandhi 18:6a4db94011d3 982 * @brief Trig DAC conversion by software for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 983 * @note Preliminarily, DAC trigger must be set to software trigger
sahilmgandhi 18:6a4db94011d3 984 * using function @ref LL_DAC_SetTriggerSource()
sahilmgandhi 18:6a4db94011d3 985 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
sahilmgandhi 18:6a4db94011d3 986 * and DAC trigger must be enabled using
sahilmgandhi 18:6a4db94011d3 987 * function @ref LL_DAC_EnableTrigger().
sahilmgandhi 18:6a4db94011d3 988 * @note For devices featuring DAC with 2 channels: this function
sahilmgandhi 18:6a4db94011d3 989 * can perform a SW start of both DAC channels simultaneously.
sahilmgandhi 18:6a4db94011d3 990 * Two channels can be selected as parameter.
sahilmgandhi 18:6a4db94011d3 991 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
sahilmgandhi 18:6a4db94011d3 992 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
sahilmgandhi 18:6a4db94011d3 993 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
sahilmgandhi 18:6a4db94011d3 994 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 995 * @param DAC_Channel This parameter can a combination of the following values:
sahilmgandhi 18:6a4db94011d3 996 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 997 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 998 * @retval None
sahilmgandhi 18:6a4db94011d3 999 */
sahilmgandhi 18:6a4db94011d3 1000 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 1001 {
sahilmgandhi 18:6a4db94011d3 1002 SET_BIT(DACx->SWTRIGR,
sahilmgandhi 18:6a4db94011d3 1003 (DAC_Channel & DAC_SWTR_CHX_MASK));
sahilmgandhi 18:6a4db94011d3 1004 }
sahilmgandhi 18:6a4db94011d3 1005
sahilmgandhi 18:6a4db94011d3 1006 /**
sahilmgandhi 18:6a4db94011d3 1007 * @brief Set the data to be loaded in the data holding register
sahilmgandhi 18:6a4db94011d3 1008 * in format 12 bits left alignment (LSB aligned on bit 0),
sahilmgandhi 18:6a4db94011d3 1009 * for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 1010 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
sahilmgandhi 18:6a4db94011d3 1011 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
sahilmgandhi 18:6a4db94011d3 1012 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1013 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1014 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 1015 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 1016 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1017 * @retval None
sahilmgandhi 18:6a4db94011d3 1018 */
sahilmgandhi 18:6a4db94011d3 1019 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
sahilmgandhi 18:6a4db94011d3 1020 {
sahilmgandhi 18:6a4db94011d3 1021 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 1022
sahilmgandhi 18:6a4db94011d3 1023 MODIFY_REG(*preg,
sahilmgandhi 18:6a4db94011d3 1024 DAC_DHR12R1_DACC1DHR,
sahilmgandhi 18:6a4db94011d3 1025 Data);
sahilmgandhi 18:6a4db94011d3 1026 }
sahilmgandhi 18:6a4db94011d3 1027
sahilmgandhi 18:6a4db94011d3 1028 /**
sahilmgandhi 18:6a4db94011d3 1029 * @brief Set the data to be loaded in the data holding register
sahilmgandhi 18:6a4db94011d3 1030 * in format 12 bits left alignment (MSB aligned on bit 15),
sahilmgandhi 18:6a4db94011d3 1031 * for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 1032 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
sahilmgandhi 18:6a4db94011d3 1033 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
sahilmgandhi 18:6a4db94011d3 1034 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1035 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1036 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 1037 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 1038 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1039 * @retval None
sahilmgandhi 18:6a4db94011d3 1040 */
sahilmgandhi 18:6a4db94011d3 1041 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
sahilmgandhi 18:6a4db94011d3 1042 {
sahilmgandhi 18:6a4db94011d3 1043 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 MODIFY_REG(*preg,
sahilmgandhi 18:6a4db94011d3 1046 DAC_DHR12L1_DACC1DHR,
sahilmgandhi 18:6a4db94011d3 1047 Data);
sahilmgandhi 18:6a4db94011d3 1048 }
sahilmgandhi 18:6a4db94011d3 1049
sahilmgandhi 18:6a4db94011d3 1050 /**
sahilmgandhi 18:6a4db94011d3 1051 * @brief Set the data to be loaded in the data holding register
sahilmgandhi 18:6a4db94011d3 1052 * in format 8 bits left alignment (LSB aligned on bit 0),
sahilmgandhi 18:6a4db94011d3 1053 * for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 1054 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
sahilmgandhi 18:6a4db94011d3 1055 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
sahilmgandhi 18:6a4db94011d3 1056 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1057 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1058 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 1059 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 1060 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
sahilmgandhi 18:6a4db94011d3 1061 * @retval None
sahilmgandhi 18:6a4db94011d3 1062 */
sahilmgandhi 18:6a4db94011d3 1063 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
sahilmgandhi 18:6a4db94011d3 1064 {
sahilmgandhi 18:6a4db94011d3 1065 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 1066
sahilmgandhi 18:6a4db94011d3 1067 MODIFY_REG(*preg,
sahilmgandhi 18:6a4db94011d3 1068 DAC_DHR8R1_DACC1DHR,
sahilmgandhi 18:6a4db94011d3 1069 Data);
sahilmgandhi 18:6a4db94011d3 1070 }
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /**
sahilmgandhi 18:6a4db94011d3 1073 * @brief Set the data to be loaded in the data holding register
sahilmgandhi 18:6a4db94011d3 1074 * in format 12 bits left alignment (LSB aligned on bit 0),
sahilmgandhi 18:6a4db94011d3 1075 * for both DAC channels.
sahilmgandhi 18:6a4db94011d3 1076 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
sahilmgandhi 18:6a4db94011d3 1077 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
sahilmgandhi 18:6a4db94011d3 1078 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1079 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1080 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1081 * @retval None
sahilmgandhi 18:6a4db94011d3 1082 */
sahilmgandhi 18:6a4db94011d3 1083 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
sahilmgandhi 18:6a4db94011d3 1084 {
sahilmgandhi 18:6a4db94011d3 1085 MODIFY_REG(DACx->DHR12RD,
sahilmgandhi 18:6a4db94011d3 1086 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
sahilmgandhi 18:6a4db94011d3 1087 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
sahilmgandhi 18:6a4db94011d3 1088 }
sahilmgandhi 18:6a4db94011d3 1089
sahilmgandhi 18:6a4db94011d3 1090 /**
sahilmgandhi 18:6a4db94011d3 1091 * @brief Set the data to be loaded in the data holding register
sahilmgandhi 18:6a4db94011d3 1092 * in format 12 bits left alignment (MSB aligned on bit 15),
sahilmgandhi 18:6a4db94011d3 1093 * for both DAC channels.
sahilmgandhi 18:6a4db94011d3 1094 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
sahilmgandhi 18:6a4db94011d3 1095 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
sahilmgandhi 18:6a4db94011d3 1096 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1097 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1098 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1099 * @retval None
sahilmgandhi 18:6a4db94011d3 1100 */
sahilmgandhi 18:6a4db94011d3 1101 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
sahilmgandhi 18:6a4db94011d3 1102 {
sahilmgandhi 18:6a4db94011d3 1103 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
sahilmgandhi 18:6a4db94011d3 1104 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
sahilmgandhi 18:6a4db94011d3 1105 /* the 4 LSB must be taken into account for the shift value. */
sahilmgandhi 18:6a4db94011d3 1106 MODIFY_REG(DACx->DHR12LD,
sahilmgandhi 18:6a4db94011d3 1107 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
sahilmgandhi 18:6a4db94011d3 1108 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110
sahilmgandhi 18:6a4db94011d3 1111 /**
sahilmgandhi 18:6a4db94011d3 1112 * @brief Set the data to be loaded in the data holding register
sahilmgandhi 18:6a4db94011d3 1113 * in format 8 bits left alignment (LSB aligned on bit 0),
sahilmgandhi 18:6a4db94011d3 1114 * for both DAC channels.
sahilmgandhi 18:6a4db94011d3 1115 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
sahilmgandhi 18:6a4db94011d3 1116 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
sahilmgandhi 18:6a4db94011d3 1117 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1118 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
sahilmgandhi 18:6a4db94011d3 1119 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
sahilmgandhi 18:6a4db94011d3 1120 * @retval None
sahilmgandhi 18:6a4db94011d3 1121 */
sahilmgandhi 18:6a4db94011d3 1122 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
sahilmgandhi 18:6a4db94011d3 1123 {
sahilmgandhi 18:6a4db94011d3 1124 MODIFY_REG(DACx->DHR8RD,
sahilmgandhi 18:6a4db94011d3 1125 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
sahilmgandhi 18:6a4db94011d3 1126 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
sahilmgandhi 18:6a4db94011d3 1127 }
sahilmgandhi 18:6a4db94011d3 1128
sahilmgandhi 18:6a4db94011d3 1129 /**
sahilmgandhi 18:6a4db94011d3 1130 * @brief Retrieve output data currently generated for the selected DAC channel.
sahilmgandhi 18:6a4db94011d3 1131 * @note Whatever alignment and resolution settings
sahilmgandhi 18:6a4db94011d3 1132 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
sahilmgandhi 18:6a4db94011d3 1133 * @ref LL_DAC_ConvertData12RightAligned(), ...),
sahilmgandhi 18:6a4db94011d3 1134 * output data format is 12 bits right aligned (LSB aligned on bit 0).
sahilmgandhi 18:6a4db94011d3 1135 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
sahilmgandhi 18:6a4db94011d3 1136 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
sahilmgandhi 18:6a4db94011d3 1137 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1138 * @param DAC_Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1139 * @arg @ref LL_DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 1140 * @arg @ref LL_DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 1141 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
sahilmgandhi 18:6a4db94011d3 1142 */
sahilmgandhi 18:6a4db94011d3 1143 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
sahilmgandhi 18:6a4db94011d3 1144 {
sahilmgandhi 18:6a4db94011d3 1145 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
sahilmgandhi 18:6a4db94011d3 1146
sahilmgandhi 18:6a4db94011d3 1147 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
sahilmgandhi 18:6a4db94011d3 1148 }
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 /**
sahilmgandhi 18:6a4db94011d3 1151 * @}
sahilmgandhi 18:6a4db94011d3 1152 */
sahilmgandhi 18:6a4db94011d3 1153
sahilmgandhi 18:6a4db94011d3 1154 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
sahilmgandhi 18:6a4db94011d3 1155 * @{
sahilmgandhi 18:6a4db94011d3 1156 */
sahilmgandhi 18:6a4db94011d3 1157 /**
sahilmgandhi 18:6a4db94011d3 1158 * @brief Get DAC underrun flag for DAC channel 1
sahilmgandhi 18:6a4db94011d3 1159 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
sahilmgandhi 18:6a4db94011d3 1160 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1161 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 1162 */
sahilmgandhi 18:6a4db94011d3 1163 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1164 {
sahilmgandhi 18:6a4db94011d3 1165 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
sahilmgandhi 18:6a4db94011d3 1166 }
sahilmgandhi 18:6a4db94011d3 1167
sahilmgandhi 18:6a4db94011d3 1168 /**
sahilmgandhi 18:6a4db94011d3 1169 * @brief Get DAC underrun flag for DAC channel 2
sahilmgandhi 18:6a4db94011d3 1170 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
sahilmgandhi 18:6a4db94011d3 1171 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1172 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 1173 */
sahilmgandhi 18:6a4db94011d3 1174 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1175 {
sahilmgandhi 18:6a4db94011d3 1176 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
sahilmgandhi 18:6a4db94011d3 1177 }
sahilmgandhi 18:6a4db94011d3 1178
sahilmgandhi 18:6a4db94011d3 1179 /**
sahilmgandhi 18:6a4db94011d3 1180 * @brief Clear DAC underrun flag for DAC channel 1
sahilmgandhi 18:6a4db94011d3 1181 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
sahilmgandhi 18:6a4db94011d3 1182 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1183 * @retval None
sahilmgandhi 18:6a4db94011d3 1184 */
sahilmgandhi 18:6a4db94011d3 1185 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1186 {
sahilmgandhi 18:6a4db94011d3 1187 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
sahilmgandhi 18:6a4db94011d3 1188 }
sahilmgandhi 18:6a4db94011d3 1189
sahilmgandhi 18:6a4db94011d3 1190 /**
sahilmgandhi 18:6a4db94011d3 1191 * @brief Clear DAC underrun flag for DAC channel 2
sahilmgandhi 18:6a4db94011d3 1192 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
sahilmgandhi 18:6a4db94011d3 1193 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1194 * @retval None
sahilmgandhi 18:6a4db94011d3 1195 */
sahilmgandhi 18:6a4db94011d3 1196 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1197 {
sahilmgandhi 18:6a4db94011d3 1198 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
sahilmgandhi 18:6a4db94011d3 1199 }
sahilmgandhi 18:6a4db94011d3 1200
sahilmgandhi 18:6a4db94011d3 1201 /**
sahilmgandhi 18:6a4db94011d3 1202 * @}
sahilmgandhi 18:6a4db94011d3 1203 */
sahilmgandhi 18:6a4db94011d3 1204
sahilmgandhi 18:6a4db94011d3 1205 /** @defgroup DAC_LL_EF_IT_Management IT management
sahilmgandhi 18:6a4db94011d3 1206 * @{
sahilmgandhi 18:6a4db94011d3 1207 */
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 /**
sahilmgandhi 18:6a4db94011d3 1210 * @brief Enable DMA underrun interrupt for DAC channel 1
sahilmgandhi 18:6a4db94011d3 1211 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
sahilmgandhi 18:6a4db94011d3 1212 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1213 * @retval None
sahilmgandhi 18:6a4db94011d3 1214 */
sahilmgandhi 18:6a4db94011d3 1215 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1216 {
sahilmgandhi 18:6a4db94011d3 1217 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
sahilmgandhi 18:6a4db94011d3 1218 }
sahilmgandhi 18:6a4db94011d3 1219
sahilmgandhi 18:6a4db94011d3 1220 /**
sahilmgandhi 18:6a4db94011d3 1221 * @brief Enable DMA underrun interrupt for DAC channel 2
sahilmgandhi 18:6a4db94011d3 1222 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
sahilmgandhi 18:6a4db94011d3 1223 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1224 * @retval None
sahilmgandhi 18:6a4db94011d3 1225 */
sahilmgandhi 18:6a4db94011d3 1226 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1227 {
sahilmgandhi 18:6a4db94011d3 1228 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
sahilmgandhi 18:6a4db94011d3 1229 }
sahilmgandhi 18:6a4db94011d3 1230
sahilmgandhi 18:6a4db94011d3 1231 /**
sahilmgandhi 18:6a4db94011d3 1232 * @brief Disable DMA underrun interrupt for DAC channel 1
sahilmgandhi 18:6a4db94011d3 1233 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
sahilmgandhi 18:6a4db94011d3 1234 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1235 * @retval None
sahilmgandhi 18:6a4db94011d3 1236 */
sahilmgandhi 18:6a4db94011d3 1237 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1238 {
sahilmgandhi 18:6a4db94011d3 1239 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
sahilmgandhi 18:6a4db94011d3 1240 }
sahilmgandhi 18:6a4db94011d3 1241
sahilmgandhi 18:6a4db94011d3 1242 /**
sahilmgandhi 18:6a4db94011d3 1243 * @brief Disable DMA underrun interrupt for DAC channel 2
sahilmgandhi 18:6a4db94011d3 1244 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
sahilmgandhi 18:6a4db94011d3 1245 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1246 * @retval None
sahilmgandhi 18:6a4db94011d3 1247 */
sahilmgandhi 18:6a4db94011d3 1248 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1249 {
sahilmgandhi 18:6a4db94011d3 1250 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
sahilmgandhi 18:6a4db94011d3 1251 }
sahilmgandhi 18:6a4db94011d3 1252
sahilmgandhi 18:6a4db94011d3 1253 /**
sahilmgandhi 18:6a4db94011d3 1254 * @brief Get DMA underrun interrupt for DAC channel 1
sahilmgandhi 18:6a4db94011d3 1255 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
sahilmgandhi 18:6a4db94011d3 1256 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1257 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 1258 */
sahilmgandhi 18:6a4db94011d3 1259 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1260 {
sahilmgandhi 18:6a4db94011d3 1261 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
sahilmgandhi 18:6a4db94011d3 1262 }
sahilmgandhi 18:6a4db94011d3 1263
sahilmgandhi 18:6a4db94011d3 1264 /**
sahilmgandhi 18:6a4db94011d3 1265 * @brief Get DMA underrun interrupt for DAC channel 2
sahilmgandhi 18:6a4db94011d3 1266 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
sahilmgandhi 18:6a4db94011d3 1267 * @param DACx DAC instance
sahilmgandhi 18:6a4db94011d3 1268 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 1269 */
sahilmgandhi 18:6a4db94011d3 1270 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
sahilmgandhi 18:6a4db94011d3 1271 {
sahilmgandhi 18:6a4db94011d3 1272 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
sahilmgandhi 18:6a4db94011d3 1273 }
sahilmgandhi 18:6a4db94011d3 1274
sahilmgandhi 18:6a4db94011d3 1275 /**
sahilmgandhi 18:6a4db94011d3 1276 * @}
sahilmgandhi 18:6a4db94011d3 1277 */
sahilmgandhi 18:6a4db94011d3 1278
sahilmgandhi 18:6a4db94011d3 1279 #if defined(USE_FULL_LL_DRIVER)
sahilmgandhi 18:6a4db94011d3 1280 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 1281 * @{
sahilmgandhi 18:6a4db94011d3 1282 */
sahilmgandhi 18:6a4db94011d3 1283
sahilmgandhi 18:6a4db94011d3 1284 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
sahilmgandhi 18:6a4db94011d3 1285 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
sahilmgandhi 18:6a4db94011d3 1286 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
sahilmgandhi 18:6a4db94011d3 1287
sahilmgandhi 18:6a4db94011d3 1288 /**
sahilmgandhi 18:6a4db94011d3 1289 * @}
sahilmgandhi 18:6a4db94011d3 1290 */
sahilmgandhi 18:6a4db94011d3 1291 #endif /* USE_FULL_LL_DRIVER */
sahilmgandhi 18:6a4db94011d3 1292
sahilmgandhi 18:6a4db94011d3 1293 /**
sahilmgandhi 18:6a4db94011d3 1294 * @}
sahilmgandhi 18:6a4db94011d3 1295 */
sahilmgandhi 18:6a4db94011d3 1296
sahilmgandhi 18:6a4db94011d3 1297 /**
sahilmgandhi 18:6a4db94011d3 1298 * @}
sahilmgandhi 18:6a4db94011d3 1299 */
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301 #endif /* DAC1 */
sahilmgandhi 18:6a4db94011d3 1302
sahilmgandhi 18:6a4db94011d3 1303 /**
sahilmgandhi 18:6a4db94011d3 1304 * @}
sahilmgandhi 18:6a4db94011d3 1305 */
sahilmgandhi 18:6a4db94011d3 1306
sahilmgandhi 18:6a4db94011d3 1307 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1308 }
sahilmgandhi 18:6a4db94011d3 1309 #endif
sahilmgandhi 18:6a4db94011d3 1310
sahilmgandhi 18:6a4db94011d3 1311 #endif /* __STM32L1xx_LL_DAC_H */
sahilmgandhi 18:6a4db94011d3 1312
sahilmgandhi 18:6a4db94011d3 1313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/