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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l1xx_hal_flash.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.2.0
sahilmgandhi 18:6a4db94011d3 6 * @date 01-July-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of Flash HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32L1xx_HAL_FLASH_EX_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32L1xx_HAL_FLASH_EX_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32l1xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32L1xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup FLASHEx
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /** @addtogroup FLASHEx_Private_Constants
sahilmgandhi 18:6a4db94011d3 58 * @{
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60 #if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
sahilmgandhi 18:6a4db94011d3 63 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
sahilmgandhi 18:6a4db94011d3 64 FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 #elif defined(FLASH_SR_RDERR)
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
sahilmgandhi 18:6a4db94011d3 69 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
sahilmgandhi 18:6a4db94011d3 70 FLASH_FLAG_RDERR)
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #elif defined(FLASH_SR_OPTVERRUSR)
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
sahilmgandhi 18:6a4db94011d3 75 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
sahilmgandhi 18:6a4db94011d3 76 FLASH_FLAG_OPTVERRUSR)
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 #else
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
sahilmgandhi 18:6a4db94011d3 81 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 #endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
sahilmgandhi 18:6a4db94011d3 86 || defined(STM32L151xBA) || defined(STM32L152xBA)
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /******* Devices with FLASH 128K *******/
sahilmgandhi 18:6a4db94011d3 89 #define FLASH_NBPAGES_MAX 512 /* 512 pages from page 0 to page 511 */
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 #elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
sahilmgandhi 18:6a4db94011d3 92 || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /******* Devices with FLASH 256K *******/
sahilmgandhi 18:6a4db94011d3 95 #define FLASH_NBPAGES_MAX 1025 /* 1025 pages from page 0 to page 1024 */
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 #elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
sahilmgandhi 18:6a4db94011d3 98 || defined(STM32L162xD) || defined(STM32L162xDX)
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /******* Devices with FLASH 384K *******/
sahilmgandhi 18:6a4db94011d3 101 #define FLASH_NBPAGES_MAX 1536 /* 1536 pages from page 0 to page 1535 */
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 #elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /******* Devices with FLASH 512K *******/
sahilmgandhi 18:6a4db94011d3 106 #define FLASH_NBPAGES_MAX 2048 /* 2048 pages from page 0 to page 2047 */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 #define WRP_MASK_LOW ((uint32_t)0x0000FFFFU)
sahilmgandhi 18:6a4db94011d3 111 #define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U)
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /**
sahilmgandhi 18:6a4db94011d3 114 * @}
sahilmgandhi 18:6a4db94011d3 115 */
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 /** @addtogroup FLASHEx_Private_Macros
sahilmgandhi 18:6a4db94011d3 118 * @{
sahilmgandhi 18:6a4db94011d3 119 */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 126 ((__VALUE__) == OB_WRPSTATE_ENABLE))
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 #define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
sahilmgandhi 18:6a4db94011d3 131 ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
sahilmgandhi 18:6a4db94011d3 132 ((__LEVEL__) == OB_RDP_LEVEL_2))
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
sahilmgandhi 18:6a4db94011d3 135 ((__LEVEL__) == OB_BOR_LEVEL1) || \
sahilmgandhi 18:6a4db94011d3 136 ((__LEVEL__) == OB_BOR_LEVEL2) || \
sahilmgandhi 18:6a4db94011d3 137 ((__LEVEL__) == OB_BOR_LEVEL3) || \
sahilmgandhi 18:6a4db94011d3 138 ((__LEVEL__) == OB_BOR_LEVEL4) || \
sahilmgandhi 18:6a4db94011d3 139 ((__LEVEL__) == OB_BOR_LEVEL5))
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 #if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 #define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 #elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 #endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 #if defined(FLASH_OBR_SPRMOD)
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 164 ((__VALUE__) == OB_PCROP_STATE_ENABLE))
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 #define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
sahilmgandhi 18:6a4db94011d3 167 #endif /* FLASH_OBR_SPRMOD */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 #if defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 #endif /* FLASH_OBR_nRST_BFB2 */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 #define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
sahilmgandhi 18:6a4db94011d3 176 ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
sahilmgandhi 18:6a4db94011d3 177 ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
sahilmgandhi 18:6a4db94011d3 180 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
sahilmgandhi 18:6a4db94011d3 181 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
sahilmgandhi 18:6a4db94011d3 182 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \
sahilmgandhi 18:6a4db94011d3 183 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
sahilmgandhi 18:6a4db94011d3 184 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /** @defgroup FLASHEx_Address FLASHEx Address
sahilmgandhi 18:6a4db94011d3 187 * @{
sahilmgandhi 18:6a4db94011d3 188 */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
sahilmgandhi 18:6a4db94011d3 193 || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \
sahilmgandhi 18:6a4db94011d3 194 || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \
sahilmgandhi 18:6a4db94011d3 195 || defined(STM32L162xCA)
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 #else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
sahilmgandhi 18:6a4db94011d3 202 #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))
sahilmgandhi 18:6a4db94011d3 203 #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 #define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /**
sahilmgandhi 18:6a4db94011d3 210 * @}
sahilmgandhi 18:6a4db94011d3 211 */
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 /**
sahilmgandhi 18:6a4db94011d3 214 * @}
sahilmgandhi 18:6a4db94011d3 215 */
sahilmgandhi 18:6a4db94011d3 216 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
sahilmgandhi 18:6a4db94011d3 219 * @{
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /**
sahilmgandhi 18:6a4db94011d3 223 * @brief FLASH Erase structure definition
sahilmgandhi 18:6a4db94011d3 224 */
sahilmgandhi 18:6a4db94011d3 225 typedef struct
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 uint32_t TypeErase; /*!< TypeErase: Page Erase only.
sahilmgandhi 18:6a4db94011d3 228 This parameter can be a value of @ref FLASHEx_Type_Erase */
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
sahilmgandhi 18:6a4db94011d3 231 This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
sahilmgandhi 18:6a4db94011d3 234 This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 } FLASH_EraseInitTypeDef;
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /**
sahilmgandhi 18:6a4db94011d3 239 * @brief FLASH Option Bytes PROGRAM structure definition
sahilmgandhi 18:6a4db94011d3 240 */
sahilmgandhi 18:6a4db94011d3 241 typedef struct
sahilmgandhi 18:6a4db94011d3 242 {
sahilmgandhi 18:6a4db94011d3 243 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
sahilmgandhi 18:6a4db94011d3 244 This parameter can be a value of @ref FLASHEx_Option_Type */
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
sahilmgandhi 18:6a4db94011d3 247 This parameter can be a value of @ref FLASHEx_WRP_State */
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
sahilmgandhi 18:6a4db94011d3 250 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
sahilmgandhi 18:6a4db94011d3 253 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
sahilmgandhi 18:6a4db94011d3 254 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
sahilmgandhi 18:6a4db94011d3 255 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 256 uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
sahilmgandhi 18:6a4db94011d3 257 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
sahilmgandhi 18:6a4db94011d3 258 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
sahilmgandhi 18:6a4db94011d3 261 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
sahilmgandhi 18:6a4db94011d3 262 || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 263 uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
sahilmgandhi 18:6a4db94011d3 264 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */
sahilmgandhi 18:6a4db94011d3 265 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
sahilmgandhi 18:6a4db94011d3 268 || defined(STM32L152xDX) || defined(STM32L162xDX)
sahilmgandhi 18:6a4db94011d3 269 uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or
sahilmgandhi 18:6a4db94011d3 270 Sectors 96 to 111 for STM32L1xxxDX devices.
sahilmgandhi 18:6a4db94011d3 271 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */
sahilmgandhi 18:6a4db94011d3 272 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
sahilmgandhi 18:6a4db94011d3 275 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
sahilmgandhi 18:6a4db94011d3 278 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
sahilmgandhi 18:6a4db94011d3 281 This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
sahilmgandhi 18:6a4db94011d3 282 @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
sahilmgandhi 18:6a4db94011d3 283 } FLASH_OBProgramInitTypeDef;
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 286 /**
sahilmgandhi 18:6a4db94011d3 287 * @brief FLASH Advanced Option Bytes Program structure definition
sahilmgandhi 18:6a4db94011d3 288 */
sahilmgandhi 18:6a4db94011d3 289 typedef struct
sahilmgandhi 18:6a4db94011d3 290 {
sahilmgandhi 18:6a4db94011d3 291 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
sahilmgandhi 18:6a4db94011d3 292 This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 #if defined(FLASH_OBR_SPRMOD)
sahilmgandhi 18:6a4db94011d3 295 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
sahilmgandhi 18:6a4db94011d3 296 This parameter can be a value of @ref FLASHEx_PCROP_State */
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
sahilmgandhi 18:6a4db94011d3 299 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
sahilmgandhi 18:6a4db94011d3 302 uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
sahilmgandhi 18:6a4db94011d3 303 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
sahilmgandhi 18:6a4db94011d3 304 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
sahilmgandhi 18:6a4db94011d3 305 #endif /* FLASH_OBR_SPRMOD */
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 #if defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 308 uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
sahilmgandhi 18:6a4db94011d3 309 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
sahilmgandhi 18:6a4db94011d3 310 #endif /* FLASH_OBR_nRST_BFB2*/
sahilmgandhi 18:6a4db94011d3 311 } FLASH_AdvOBProgramInitTypeDef;
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /**
sahilmgandhi 18:6a4db94011d3 314 * @}
sahilmgandhi 18:6a4db94011d3 315 */
sahilmgandhi 18:6a4db94011d3 316 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
sahilmgandhi 18:6a4db94011d3 322 * @{
sahilmgandhi 18:6a4db94011d3 323 */
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
sahilmgandhi 18:6a4db94011d3 326 * @{
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /**
sahilmgandhi 18:6a4db94011d3 331 * @}
sahilmgandhi 18:6a4db94011d3 332 */
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type
sahilmgandhi 18:6a4db94011d3 335 * @{
sahilmgandhi 18:6a4db94011d3 336 */
sahilmgandhi 18:6a4db94011d3 337 #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/
sahilmgandhi 18:6a4db94011d3 338 #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/
sahilmgandhi 18:6a4db94011d3 339 #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/
sahilmgandhi 18:6a4db94011d3 340 #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /**
sahilmgandhi 18:6a4db94011d3 343 * @}
sahilmgandhi 18:6a4db94011d3 344 */
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State
sahilmgandhi 18:6a4db94011d3 347 * @{
sahilmgandhi 18:6a4db94011d3 348 */
sahilmgandhi 18:6a4db94011d3 349 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/
sahilmgandhi 18:6a4db94011d3 350 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /**
sahilmgandhi 18:6a4db94011d3 353 * @}
sahilmgandhi 18:6a4db94011d3 354 */
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
sahilmgandhi 18:6a4db94011d3 357 * @{
sahilmgandhi 18:6a4db94011d3 358 */
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
sahilmgandhi 18:6a4db94011d3 361 #define OB_WRP1_PAGES0TO15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
sahilmgandhi 18:6a4db94011d3 362 #define OB_WRP1_PAGES16TO31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
sahilmgandhi 18:6a4db94011d3 363 #define OB_WRP1_PAGES32TO47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
sahilmgandhi 18:6a4db94011d3 364 #define OB_WRP1_PAGES48TO63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
sahilmgandhi 18:6a4db94011d3 365 #define OB_WRP1_PAGES64TO79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
sahilmgandhi 18:6a4db94011d3 366 #define OB_WRP1_PAGES80TO95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
sahilmgandhi 18:6a4db94011d3 367 #define OB_WRP1_PAGES96TO111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
sahilmgandhi 18:6a4db94011d3 368 #define OB_WRP1_PAGES112TO127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
sahilmgandhi 18:6a4db94011d3 369 #define OB_WRP1_PAGES128TO143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
sahilmgandhi 18:6a4db94011d3 370 #define OB_WRP1_PAGES144TO159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
sahilmgandhi 18:6a4db94011d3 371 #define OB_WRP1_PAGES160TO175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
sahilmgandhi 18:6a4db94011d3 372 #define OB_WRP1_PAGES176TO191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
sahilmgandhi 18:6a4db94011d3 373 #define OB_WRP1_PAGES192TO207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
sahilmgandhi 18:6a4db94011d3 374 #define OB_WRP1_PAGES208TO223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
sahilmgandhi 18:6a4db94011d3 375 #define OB_WRP1_PAGES224TO239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
sahilmgandhi 18:6a4db94011d3 376 #define OB_WRP1_PAGES240TO255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
sahilmgandhi 18:6a4db94011d3 377 #define OB_WRP1_PAGES256TO271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
sahilmgandhi 18:6a4db94011d3 378 #define OB_WRP1_PAGES272TO287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
sahilmgandhi 18:6a4db94011d3 379 #define OB_WRP1_PAGES288TO303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
sahilmgandhi 18:6a4db94011d3 380 #define OB_WRP1_PAGES304TO319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
sahilmgandhi 18:6a4db94011d3 381 #define OB_WRP1_PAGES320TO335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
sahilmgandhi 18:6a4db94011d3 382 #define OB_WRP1_PAGES336TO351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
sahilmgandhi 18:6a4db94011d3 383 #define OB_WRP1_PAGES352TO367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
sahilmgandhi 18:6a4db94011d3 384 #define OB_WRP1_PAGES368TO383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
sahilmgandhi 18:6a4db94011d3 385 #define OB_WRP1_PAGES384TO399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
sahilmgandhi 18:6a4db94011d3 386 #define OB_WRP1_PAGES400TO415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
sahilmgandhi 18:6a4db94011d3 387 #define OB_WRP1_PAGES416TO431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
sahilmgandhi 18:6a4db94011d3 388 #define OB_WRP1_PAGES432TO447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
sahilmgandhi 18:6a4db94011d3 389 #define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
sahilmgandhi 18:6a4db94011d3 390 #define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
sahilmgandhi 18:6a4db94011d3 391 #define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
sahilmgandhi 18:6a4db94011d3 392 #define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000U) /* Write protection of Sector31 */
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 #define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /**
sahilmgandhi 18:6a4db94011d3 397 * @}
sahilmgandhi 18:6a4db94011d3 398 */
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
sahilmgandhi 18:6a4db94011d3 401 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
sahilmgandhi 18:6a4db94011d3 402 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
sahilmgandhi 18:6a4db94011d3 403 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 404
sahilmgandhi 18:6a4db94011d3 405 /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
sahilmgandhi 18:6a4db94011d3 406 * @{
sahilmgandhi 18:6a4db94011d3 407 */
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Pages for Cat3, Cat4 & Cat5 devices*/
sahilmgandhi 18:6a4db94011d3 410 #define OB_WRP2_PAGES512TO527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
sahilmgandhi 18:6a4db94011d3 411 #define OB_WRP2_PAGES528TO543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
sahilmgandhi 18:6a4db94011d3 412 #define OB_WRP2_PAGES544TO559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
sahilmgandhi 18:6a4db94011d3 413 #define OB_WRP2_PAGES560TO575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
sahilmgandhi 18:6a4db94011d3 414 #define OB_WRP2_PAGES576TO591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
sahilmgandhi 18:6a4db94011d3 415 #define OB_WRP2_PAGES592TO607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
sahilmgandhi 18:6a4db94011d3 416 #define OB_WRP2_PAGES608TO623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
sahilmgandhi 18:6a4db94011d3 417 #define OB_WRP2_PAGES624TO639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
sahilmgandhi 18:6a4db94011d3 418 #define OB_WRP2_PAGES640TO655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
sahilmgandhi 18:6a4db94011d3 419 #define OB_WRP2_PAGES656TO671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
sahilmgandhi 18:6a4db94011d3 420 #define OB_WRP2_PAGES672TO687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
sahilmgandhi 18:6a4db94011d3 421 #define OB_WRP2_PAGES688TO703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
sahilmgandhi 18:6a4db94011d3 422 #define OB_WRP2_PAGES704TO719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
sahilmgandhi 18:6a4db94011d3 423 #define OB_WRP2_PAGES720TO735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
sahilmgandhi 18:6a4db94011d3 424 #define OB_WRP2_PAGES736TO751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
sahilmgandhi 18:6a4db94011d3 425 #define OB_WRP2_PAGES752TO767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
sahilmgandhi 18:6a4db94011d3 428 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
sahilmgandhi 18:6a4db94011d3 429 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \
sahilmgandhi 18:6a4db94011d3 430 || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 #define OB_WRP2_PAGES768TO783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
sahilmgandhi 18:6a4db94011d3 433 #define OB_WRP2_PAGES784TO799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
sahilmgandhi 18:6a4db94011d3 434 #define OB_WRP2_PAGES800TO815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
sahilmgandhi 18:6a4db94011d3 435 #define OB_WRP2_PAGES816TO831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
sahilmgandhi 18:6a4db94011d3 436 #define OB_WRP2_PAGES832TO847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
sahilmgandhi 18:6a4db94011d3 437 #define OB_WRP2_PAGES848TO863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
sahilmgandhi 18:6a4db94011d3 438 #define OB_WRP2_PAGES864TO879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
sahilmgandhi 18:6a4db94011d3 439 #define OB_WRP2_PAGES880TO895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
sahilmgandhi 18:6a4db94011d3 440 #define OB_WRP2_PAGES896TO911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
sahilmgandhi 18:6a4db94011d3 441 #define OB_WRP2_PAGES912TO927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
sahilmgandhi 18:6a4db94011d3 442 #define OB_WRP2_PAGES928TO943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
sahilmgandhi 18:6a4db94011d3 443 #define OB_WRP2_PAGES944TO959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
sahilmgandhi 18:6a4db94011d3 444 #define OB_WRP2_PAGES960TO975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
sahilmgandhi 18:6a4db94011d3 445 #define OB_WRP2_PAGES976TO991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
sahilmgandhi 18:6a4db94011d3 446 #define OB_WRP2_PAGES992TO1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
sahilmgandhi 18:6a4db94011d3 447 #define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* Write protection of Sector63 */
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 #define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 /**
sahilmgandhi 18:6a4db94011d3 454 * @}
sahilmgandhi 18:6a4db94011d3 455 */
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
sahilmgandhi 18:6a4db94011d3 460 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
sahilmgandhi 18:6a4db94011d3 461 || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 /** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
sahilmgandhi 18:6a4db94011d3 464 * @{
sahilmgandhi 18:6a4db94011d3 465 */
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /* Pages for devices with FLASH >= 256KB*/
sahilmgandhi 18:6a4db94011d3 468 #define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
sahilmgandhi 18:6a4db94011d3 469 #define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
sahilmgandhi 18:6a4db94011d3 470 #define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
sahilmgandhi 18:6a4db94011d3 471 #define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
sahilmgandhi 18:6a4db94011d3 472 #define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
sahilmgandhi 18:6a4db94011d3 473 #define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
sahilmgandhi 18:6a4db94011d3 474 #define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
sahilmgandhi 18:6a4db94011d3 475 #define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
sahilmgandhi 18:6a4db94011d3 476 #define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
sahilmgandhi 18:6a4db94011d3 477 #define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
sahilmgandhi 18:6a4db94011d3 478 #define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
sahilmgandhi 18:6a4db94011d3 479 #define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
sahilmgandhi 18:6a4db94011d3 480 #define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
sahilmgandhi 18:6a4db94011d3 481 #define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
sahilmgandhi 18:6a4db94011d3 482 #define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
sahilmgandhi 18:6a4db94011d3 483 #define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
sahilmgandhi 18:6a4db94011d3 484 #define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
sahilmgandhi 18:6a4db94011d3 485 #define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
sahilmgandhi 18:6a4db94011d3 486 #define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
sahilmgandhi 18:6a4db94011d3 487 #define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
sahilmgandhi 18:6a4db94011d3 488 #define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
sahilmgandhi 18:6a4db94011d3 489 #define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
sahilmgandhi 18:6a4db94011d3 490 #define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
sahilmgandhi 18:6a4db94011d3 491 #define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
sahilmgandhi 18:6a4db94011d3 492 #define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
sahilmgandhi 18:6a4db94011d3 493 #define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
sahilmgandhi 18:6a4db94011d3 494 #define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
sahilmgandhi 18:6a4db94011d3 495 #define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
sahilmgandhi 18:6a4db94011d3 496 #define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
sahilmgandhi 18:6a4db94011d3 497 #define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
sahilmgandhi 18:6a4db94011d3 498 #define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
sahilmgandhi 18:6a4db94011d3 499 #define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000U) /* Write protection of Sector95 */
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 #define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /**
sahilmgandhi 18:6a4db94011d3 504 * @}
sahilmgandhi 18:6a4db94011d3 505 */
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
sahilmgandhi 18:6a4db94011d3 510 || defined(STM32L152xDX) || defined(STM32L162xDX)
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 /** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
sahilmgandhi 18:6a4db94011d3 513 * @{
sahilmgandhi 18:6a4db94011d3 514 */
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 /* Pages for Cat5 devices*/
sahilmgandhi 18:6a4db94011d3 517 #define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/
sahilmgandhi 18:6a4db94011d3 518 #define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/
sahilmgandhi 18:6a4db94011d3 519 #define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/
sahilmgandhi 18:6a4db94011d3 520 #define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/
sahilmgandhi 18:6a4db94011d3 521 #define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/
sahilmgandhi 18:6a4db94011d3 522 #define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/
sahilmgandhi 18:6a4db94011d3 523 #define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/
sahilmgandhi 18:6a4db94011d3 524 #define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/
sahilmgandhi 18:6a4db94011d3 525 #define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/
sahilmgandhi 18:6a4db94011d3 526 #define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/
sahilmgandhi 18:6a4db94011d3 527 #define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/
sahilmgandhi 18:6a4db94011d3 528 #define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/
sahilmgandhi 18:6a4db94011d3 529 #define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/
sahilmgandhi 18:6a4db94011d3 530 #define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/
sahilmgandhi 18:6a4db94011d3 531 #define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/
sahilmgandhi 18:6a4db94011d3 532 #define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 #define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/
sahilmgandhi 18:6a4db94011d3 537 #define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/
sahilmgandhi 18:6a4db94011d3 538 #define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/
sahilmgandhi 18:6a4db94011d3 539 #define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/
sahilmgandhi 18:6a4db94011d3 540 #define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/
sahilmgandhi 18:6a4db94011d3 541 #define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/
sahilmgandhi 18:6a4db94011d3 542 #define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/
sahilmgandhi 18:6a4db94011d3 543 #define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/
sahilmgandhi 18:6a4db94011d3 544 #define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/
sahilmgandhi 18:6a4db94011d3 545 #define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/
sahilmgandhi 18:6a4db94011d3 546 #define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/
sahilmgandhi 18:6a4db94011d3 547 #define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/
sahilmgandhi 18:6a4db94011d3 548 #define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/
sahilmgandhi 18:6a4db94011d3 549 #define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/
sahilmgandhi 18:6a4db94011d3 550 #define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/
sahilmgandhi 18:6a4db94011d3 551 #define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000U) /* Write protection of Sector127*/
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 #endif /* STM32L151xE || STM32L152xE || STM32L162xE */
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555 #define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 /**
sahilmgandhi 18:6a4db94011d3 558 * @}
sahilmgandhi 18:6a4db94011d3 559 */
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
sahilmgandhi 18:6a4db94011d3 564 * @{
sahilmgandhi 18:6a4db94011d3 565 */
sahilmgandhi 18:6a4db94011d3 566 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
sahilmgandhi 18:6a4db94011d3 567 #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
sahilmgandhi 18:6a4db94011d3 568 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
sahilmgandhi 18:6a4db94011d3 569 it is no more possible to go back to level 1 or 0 */
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 /**
sahilmgandhi 18:6a4db94011d3 572 * @}
sahilmgandhi 18:6a4db94011d3 573 */
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
sahilmgandhi 18:6a4db94011d3 576 * @{
sahilmgandhi 18:6a4db94011d3 577 */
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579 #define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
sahilmgandhi 18:6a4db94011d3 580 power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
sahilmgandhi 18:6a4db94011d3 581 #define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
sahilmgandhi 18:6a4db94011d3 582 #define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
sahilmgandhi 18:6a4db94011d3 583 #define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
sahilmgandhi 18:6a4db94011d3 584 #define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
sahilmgandhi 18:6a4db94011d3 585 #define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
sahilmgandhi 18:6a4db94011d3 586
sahilmgandhi 18:6a4db94011d3 587 /**
sahilmgandhi 18:6a4db94011d3 588 * @}
sahilmgandhi 18:6a4db94011d3 589 */
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
sahilmgandhi 18:6a4db94011d3 592 * @{
sahilmgandhi 18:6a4db94011d3 593 */
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 #define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
sahilmgandhi 18:6a4db94011d3 596 #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598 /**
sahilmgandhi 18:6a4db94011d3 599 * @}
sahilmgandhi 18:6a4db94011d3 600 */
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
sahilmgandhi 18:6a4db94011d3 603 * @{
sahilmgandhi 18:6a4db94011d3 604 */
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 #define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
sahilmgandhi 18:6a4db94011d3 607 #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
sahilmgandhi 18:6a4db94011d3 608 /**
sahilmgandhi 18:6a4db94011d3 609 * @}
sahilmgandhi 18:6a4db94011d3 610 */
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
sahilmgandhi 18:6a4db94011d3 613 * @{
sahilmgandhi 18:6a4db94011d3 614 */
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 #define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
sahilmgandhi 18:6a4db94011d3 617 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 /**
sahilmgandhi 18:6a4db94011d3 620 * @}
sahilmgandhi 18:6a4db94011d3 621 */
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 #if defined(FLASH_OBR_SPRMOD)
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
sahilmgandhi 18:6a4db94011d3 626 * @{
sahilmgandhi 18:6a4db94011d3 627 */
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 #define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631 /**
sahilmgandhi 18:6a4db94011d3 632 * @}
sahilmgandhi 18:6a4db94011d3 633 */
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 #endif /* FLASH_OBR_SPRMOD */
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 #if defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 638
sahilmgandhi 18:6a4db94011d3 639 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
sahilmgandhi 18:6a4db94011d3 640 * @{
sahilmgandhi 18:6a4db94011d3 641 */
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 #define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 /**
sahilmgandhi 18:6a4db94011d3 646 * @}
sahilmgandhi 18:6a4db94011d3 647 */
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 #endif /* FLASH_OBR_nRST_BFB2 */
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 #if defined(FLASH_OBR_SPRMOD)
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
sahilmgandhi 18:6a4db94011d3 654 * @{
sahilmgandhi 18:6a4db94011d3 655 */
sahilmgandhi 18:6a4db94011d3 656 #define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */
sahilmgandhi 18:6a4db94011d3 657 #define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 /**
sahilmgandhi 18:6a4db94011d3 660 * @}
sahilmgandhi 18:6a4db94011d3 661 */
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
sahilmgandhi 18:6a4db94011d3 664 * @{
sahilmgandhi 18:6a4db94011d3 665 */
sahilmgandhi 18:6a4db94011d3 666 #define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
sahilmgandhi 18:6a4db94011d3 667 #define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
sahilmgandhi 18:6a4db94011d3 668
sahilmgandhi 18:6a4db94011d3 669 /**
sahilmgandhi 18:6a4db94011d3 670 * @}
sahilmgandhi 18:6a4db94011d3 671 */
sahilmgandhi 18:6a4db94011d3 672 #endif /* FLASH_OBR_SPRMOD */
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
sahilmgandhi 18:6a4db94011d3 675 || defined(STM32L162xC)
sahilmgandhi 18:6a4db94011d3 676 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
sahilmgandhi 18:6a4db94011d3 677 * @{
sahilmgandhi 18:6a4db94011d3 678 */
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
sahilmgandhi 18:6a4db94011d3 681 #define OB_PCROP1_PAGES0TO15 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
sahilmgandhi 18:6a4db94011d3 682 #define OB_PCROP1_PAGES16TO31 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
sahilmgandhi 18:6a4db94011d3 683 #define OB_PCROP1_PAGES32TO47 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
sahilmgandhi 18:6a4db94011d3 684 #define OB_PCROP1_PAGES48TO63 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
sahilmgandhi 18:6a4db94011d3 685 #define OB_PCROP1_PAGES64TO79 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
sahilmgandhi 18:6a4db94011d3 686 #define OB_PCROP1_PAGES80TO95 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
sahilmgandhi 18:6a4db94011d3 687 #define OB_PCROP1_PAGES96TO111 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
sahilmgandhi 18:6a4db94011d3 688 #define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
sahilmgandhi 18:6a4db94011d3 689 #define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
sahilmgandhi 18:6a4db94011d3 690 #define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
sahilmgandhi 18:6a4db94011d3 691 #define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
sahilmgandhi 18:6a4db94011d3 692 #define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
sahilmgandhi 18:6a4db94011d3 693 #define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
sahilmgandhi 18:6a4db94011d3 694 #define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
sahilmgandhi 18:6a4db94011d3 695 #define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
sahilmgandhi 18:6a4db94011d3 696 #define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
sahilmgandhi 18:6a4db94011d3 697 #define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */
sahilmgandhi 18:6a4db94011d3 698 #define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */
sahilmgandhi 18:6a4db94011d3 699 #define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */
sahilmgandhi 18:6a4db94011d3 700 #define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */
sahilmgandhi 18:6a4db94011d3 701 #define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */
sahilmgandhi 18:6a4db94011d3 702 #define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */
sahilmgandhi 18:6a4db94011d3 703 #define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */
sahilmgandhi 18:6a4db94011d3 704 #define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */
sahilmgandhi 18:6a4db94011d3 705 #define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */
sahilmgandhi 18:6a4db94011d3 706 #define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */
sahilmgandhi 18:6a4db94011d3 707 #define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */
sahilmgandhi 18:6a4db94011d3 708 #define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */
sahilmgandhi 18:6a4db94011d3 709 #define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */
sahilmgandhi 18:6a4db94011d3 710 #define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */
sahilmgandhi 18:6a4db94011d3 711 #define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */
sahilmgandhi 18:6a4db94011d3 712 #define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 #define OB_PCROP1_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
sahilmgandhi 18:6a4db94011d3 715
sahilmgandhi 18:6a4db94011d3 716 /**
sahilmgandhi 18:6a4db94011d3 717 * @}
sahilmgandhi 18:6a4db94011d3 718 */
sahilmgandhi 18:6a4db94011d3 719 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
sahilmgandhi 18:6a4db94011d3 724 * @{
sahilmgandhi 18:6a4db94011d3 725 */
sahilmgandhi 18:6a4db94011d3 726
sahilmgandhi 18:6a4db94011d3 727 /* Pages for Cat3, Cat4 & Cat5 devices*/
sahilmgandhi 18:6a4db94011d3 728 #define OB_PCROP2_PAGES512TO527 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */
sahilmgandhi 18:6a4db94011d3 729 #define OB_PCROP2_PAGES528TO543 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */
sahilmgandhi 18:6a4db94011d3 730 #define OB_PCROP2_PAGES544TO559 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */
sahilmgandhi 18:6a4db94011d3 731 #define OB_PCROP2_PAGES560TO575 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */
sahilmgandhi 18:6a4db94011d3 732 #define OB_PCROP2_PAGES576TO591 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */
sahilmgandhi 18:6a4db94011d3 733 #define OB_PCROP2_PAGES592TO607 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */
sahilmgandhi 18:6a4db94011d3 734 #define OB_PCROP2_PAGES608TO623 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */
sahilmgandhi 18:6a4db94011d3 735 #define OB_PCROP2_PAGES624TO639 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */
sahilmgandhi 18:6a4db94011d3 736 #define OB_PCROP2_PAGES640TO655 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */
sahilmgandhi 18:6a4db94011d3 737 #define OB_PCROP2_PAGES656TO671 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */
sahilmgandhi 18:6a4db94011d3 738 #define OB_PCROP2_PAGES672TO687 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */
sahilmgandhi 18:6a4db94011d3 739 #define OB_PCROP2_PAGES688TO703 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */
sahilmgandhi 18:6a4db94011d3 740 #define OB_PCROP2_PAGES704TO719 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */
sahilmgandhi 18:6a4db94011d3 741 #define OB_PCROP2_PAGES720TO735 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */
sahilmgandhi 18:6a4db94011d3 742 #define OB_PCROP2_PAGES736TO751 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */
sahilmgandhi 18:6a4db94011d3 743 #define OB_PCROP2_PAGES752TO767 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */
sahilmgandhi 18:6a4db94011d3 744 #define OB_PCROP2_PAGES768TO783 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector48 */
sahilmgandhi 18:6a4db94011d3 745 #define OB_PCROP2_PAGES784TO799 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector49 */
sahilmgandhi 18:6a4db94011d3 746 #define OB_PCROP2_PAGES800TO815 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector50 */
sahilmgandhi 18:6a4db94011d3 747 #define OB_PCROP2_PAGES816TO831 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector51 */
sahilmgandhi 18:6a4db94011d3 748 #define OB_PCROP2_PAGES832TO847 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector52 */
sahilmgandhi 18:6a4db94011d3 749 #define OB_PCROP2_PAGES848TO863 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector53 */
sahilmgandhi 18:6a4db94011d3 750 #define OB_PCROP2_PAGES864TO879 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector54 */
sahilmgandhi 18:6a4db94011d3 751 #define OB_PCROP2_PAGES880TO895 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector55 */
sahilmgandhi 18:6a4db94011d3 752 #define OB_PCROP2_PAGES896TO911 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector56 */
sahilmgandhi 18:6a4db94011d3 753 #define OB_PCROP2_PAGES912TO927 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector57 */
sahilmgandhi 18:6a4db94011d3 754 #define OB_PCROP2_PAGES928TO943 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector58 */
sahilmgandhi 18:6a4db94011d3 755 #define OB_PCROP2_PAGES944TO959 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector59 */
sahilmgandhi 18:6a4db94011d3 756 #define OB_PCROP2_PAGES960TO975 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector60 */
sahilmgandhi 18:6a4db94011d3 757 #define OB_PCROP2_PAGES976TO991 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector61 */
sahilmgandhi 18:6a4db94011d3 758 #define OB_PCROP2_PAGES992TO1007 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector62 */
sahilmgandhi 18:6a4db94011d3 759 #define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector63 */
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 #define OB_PCROP2_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 /**
sahilmgandhi 18:6a4db94011d3 764 * @}
sahilmgandhi 18:6a4db94011d3 765 */
sahilmgandhi 18:6a4db94011d3 766 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 /** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
sahilmgandhi 18:6a4db94011d3 769 * @{
sahilmgandhi 18:6a4db94011d3 770 */
sahilmgandhi 18:6a4db94011d3 771 #define FLASH_TYPEERASEDATA_BYTE ((uint32_t)0x00U) /*!<Erase byte (8-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 772 #define FLASH_TYPEERASEDATA_HALFWORD ((uint32_t)0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 773 #define FLASH_TYPEERASEDATA_WORD ((uint32_t)0x02U) /*!<Erase a word (32-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 774
sahilmgandhi 18:6a4db94011d3 775 /**
sahilmgandhi 18:6a4db94011d3 776 * @}
sahilmgandhi 18:6a4db94011d3 777 */
sahilmgandhi 18:6a4db94011d3 778
sahilmgandhi 18:6a4db94011d3 779 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
sahilmgandhi 18:6a4db94011d3 780 * @{
sahilmgandhi 18:6a4db94011d3 781 */
sahilmgandhi 18:6a4db94011d3 782 #define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 783 #define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 784 #define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 785 #define FLASH_TYPEPROGRAMDATA_FASTBYTE ((uint32_t)0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 786 #define FLASH_TYPEPROGRAMDATA_FASTHALFWORD ((uint32_t)0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 787 #define FLASH_TYPEPROGRAMDATA_FASTWORD ((uint32_t)0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 /**
sahilmgandhi 18:6a4db94011d3 790 * @}
sahilmgandhi 18:6a4db94011d3 791 */
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 #if defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
sahilmgandhi 18:6a4db94011d3 796 * @{
sahilmgandhi 18:6a4db94011d3 797 */
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 #define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
sahilmgandhi 18:6a4db94011d3 800 and this parameter is selected the device will boot from Bank 2
sahilmgandhi 18:6a4db94011d3 801 or Bank 1, depending on the activation of the bank */
sahilmgandhi 18:6a4db94011d3 802 #define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
sahilmgandhi 18:6a4db94011d3 803 and this parameter is selected the device will boot from Bank1(Default) */
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 /**
sahilmgandhi 18:6a4db94011d3 806 * @}
sahilmgandhi 18:6a4db94011d3 807 */
sahilmgandhi 18:6a4db94011d3 808 #endif /* FLASH_OBR_nRST_BFB2 */
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 /**
sahilmgandhi 18:6a4db94011d3 811 * @}
sahilmgandhi 18:6a4db94011d3 812 */
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
sahilmgandhi 18:6a4db94011d3 817 * @{
sahilmgandhi 18:6a4db94011d3 818 */
sahilmgandhi 18:6a4db94011d3 819
sahilmgandhi 18:6a4db94011d3 820 /**
sahilmgandhi 18:6a4db94011d3 821 * @brief Set the FLASH Latency.
sahilmgandhi 18:6a4db94011d3 822 * @param __LATENCY__ FLASH Latency
sahilmgandhi 18:6a4db94011d3 823 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 824 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
sahilmgandhi 18:6a4db94011d3 825 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
sahilmgandhi 18:6a4db94011d3 826 * @retval none
sahilmgandhi 18:6a4db94011d3 827 */
sahilmgandhi 18:6a4db94011d3 828 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \
sahilmgandhi 18:6a4db94011d3 829 if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
sahilmgandhi 18:6a4db94011d3 830 MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
sahilmgandhi 18:6a4db94011d3 831 } while(0)
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 /**
sahilmgandhi 18:6a4db94011d3 834 * @brief Get the FLASH Latency.
sahilmgandhi 18:6a4db94011d3 835 * @retval FLASH Latency
sahilmgandhi 18:6a4db94011d3 836 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 837 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
sahilmgandhi 18:6a4db94011d3 838 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
sahilmgandhi 18:6a4db94011d3 839 */
sahilmgandhi 18:6a4db94011d3 840 #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /**
sahilmgandhi 18:6a4db94011d3 843 * @brief Enable the FLASH 64-bit access.
sahilmgandhi 18:6a4db94011d3 844 * @note Read access 64 bit is used.
sahilmgandhi 18:6a4db94011d3 845 * @note This bit cannot be written at the same time as the LATENCY and
sahilmgandhi 18:6a4db94011d3 846 * PRFTEN bits.
sahilmgandhi 18:6a4db94011d3 847 * @retval none
sahilmgandhi 18:6a4db94011d3 848 */
sahilmgandhi 18:6a4db94011d3 849 #define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
sahilmgandhi 18:6a4db94011d3 850
sahilmgandhi 18:6a4db94011d3 851 /**
sahilmgandhi 18:6a4db94011d3 852 * @brief Disable the FLASH 64-bit access.
sahilmgandhi 18:6a4db94011d3 853 * @note Read access 32 bit is used
sahilmgandhi 18:6a4db94011d3 854 * @note To reset this bit, the LATENCY should be zero wait state and the
sahilmgandhi 18:6a4db94011d3 855 * prefetch off.
sahilmgandhi 18:6a4db94011d3 856 * @retval none
sahilmgandhi 18:6a4db94011d3 857 */
sahilmgandhi 18:6a4db94011d3 858 #define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 /**
sahilmgandhi 18:6a4db94011d3 861 * @brief Enable the FLASH prefetch buffer.
sahilmgandhi 18:6a4db94011d3 862 * @retval none
sahilmgandhi 18:6a4db94011d3 863 */
sahilmgandhi 18:6a4db94011d3 864 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \
sahilmgandhi 18:6a4db94011d3 865 SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
sahilmgandhi 18:6a4db94011d3 866 } while(0)
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 /**
sahilmgandhi 18:6a4db94011d3 869 * @brief Disable the FLASH prefetch buffer.
sahilmgandhi 18:6a4db94011d3 870 * @retval none
sahilmgandhi 18:6a4db94011d3 871 */
sahilmgandhi 18:6a4db94011d3 872 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874 /**
sahilmgandhi 18:6a4db94011d3 875 * @brief Enable the FLASH power down during Sleep mode
sahilmgandhi 18:6a4db94011d3 876 * @retval none
sahilmgandhi 18:6a4db94011d3 877 */
sahilmgandhi 18:6a4db94011d3 878 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 /**
sahilmgandhi 18:6a4db94011d3 881 * @brief Disable the FLASH power down during Sleep mode
sahilmgandhi 18:6a4db94011d3 882 * @retval none
sahilmgandhi 18:6a4db94011d3 883 */
sahilmgandhi 18:6a4db94011d3 884 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
sahilmgandhi 18:6a4db94011d3 885
sahilmgandhi 18:6a4db94011d3 886 /**
sahilmgandhi 18:6a4db94011d3 887 * @brief Enable the Flash Run power down mode.
sahilmgandhi 18:6a4db94011d3 888 * @note Writing this bit to 0 this bit, automatically the keys are
sahilmgandhi 18:6a4db94011d3 889 * loss and a new unlock sequence is necessary to re-write it to 1.
sahilmgandhi 18:6a4db94011d3 890 */
sahilmgandhi 18:6a4db94011d3 891 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
sahilmgandhi 18:6a4db94011d3 892 FLASH->PDKEYR = FLASH_PDKEY2; \
sahilmgandhi 18:6a4db94011d3 893 SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
sahilmgandhi 18:6a4db94011d3 894 } while (0)
sahilmgandhi 18:6a4db94011d3 895
sahilmgandhi 18:6a4db94011d3 896 /**
sahilmgandhi 18:6a4db94011d3 897 * @brief Disable the Flash Run power down mode.
sahilmgandhi 18:6a4db94011d3 898 * @note Writing this bit to 0 this bit, automatically the keys are
sahilmgandhi 18:6a4db94011d3 899 * loss and a new unlock sequence is necessary to re-write it to 1.
sahilmgandhi 18:6a4db94011d3 900 */
sahilmgandhi 18:6a4db94011d3 901 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
sahilmgandhi 18:6a4db94011d3 902 FLASH->PDKEYR = FLASH_PDKEY2; \
sahilmgandhi 18:6a4db94011d3 903 CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
sahilmgandhi 18:6a4db94011d3 904 } while (0)
sahilmgandhi 18:6a4db94011d3 905
sahilmgandhi 18:6a4db94011d3 906 /**
sahilmgandhi 18:6a4db94011d3 907 * @}
sahilmgandhi 18:6a4db94011d3 908 */
sahilmgandhi 18:6a4db94011d3 909
sahilmgandhi 18:6a4db94011d3 910 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 911
sahilmgandhi 18:6a4db94011d3 912 /** @addtogroup FLASHEx_Exported_Functions
sahilmgandhi 18:6a4db94011d3 913 * @{
sahilmgandhi 18:6a4db94011d3 914 */
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /** @addtogroup FLASHEx_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 917 * @{
sahilmgandhi 18:6a4db94011d3 918 */
sahilmgandhi 18:6a4db94011d3 919
sahilmgandhi 18:6a4db94011d3 920 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
sahilmgandhi 18:6a4db94011d3 921 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
sahilmgandhi 18:6a4db94011d3 922
sahilmgandhi 18:6a4db94011d3 923 /**
sahilmgandhi 18:6a4db94011d3 924 * @}
sahilmgandhi 18:6a4db94011d3 925 */
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 /** @addtogroup FLASHEx_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 928 * @{
sahilmgandhi 18:6a4db94011d3 929 */
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
sahilmgandhi 18:6a4db94011d3 932 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
sahilmgandhi 18:6a4db94011d3 937 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
sahilmgandhi 18:6a4db94011d3 938
sahilmgandhi 18:6a4db94011d3 939 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
sahilmgandhi 18:6a4db94011d3 940
sahilmgandhi 18:6a4db94011d3 941 #if defined(FLASH_OBR_SPRMOD)
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
sahilmgandhi 18:6a4db94011d3 944 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
sahilmgandhi 18:6a4db94011d3 945
sahilmgandhi 18:6a4db94011d3 946 #endif /* FLASH_OBR_SPRMOD */
sahilmgandhi 18:6a4db94011d3 947
sahilmgandhi 18:6a4db94011d3 948 /**
sahilmgandhi 18:6a4db94011d3 949 * @}
sahilmgandhi 18:6a4db94011d3 950 */
sahilmgandhi 18:6a4db94011d3 951
sahilmgandhi 18:6a4db94011d3 952 /** @addtogroup FLASHEx_Exported_Functions_Group3
sahilmgandhi 18:6a4db94011d3 953 * @{
sahilmgandhi 18:6a4db94011d3 954 */
sahilmgandhi 18:6a4db94011d3 955
sahilmgandhi 18:6a4db94011d3 956 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
sahilmgandhi 18:6a4db94011d3 957 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
sahilmgandhi 18:6a4db94011d3 958
sahilmgandhi 18:6a4db94011d3 959 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
sahilmgandhi 18:6a4db94011d3 960 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
sahilmgandhi 18:6a4db94011d3 961 void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
sahilmgandhi 18:6a4db94011d3 962 void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 /**
sahilmgandhi 18:6a4db94011d3 965 * @}
sahilmgandhi 18:6a4db94011d3 966 */
sahilmgandhi 18:6a4db94011d3 967
sahilmgandhi 18:6a4db94011d3 968 /**
sahilmgandhi 18:6a4db94011d3 969 * @}
sahilmgandhi 18:6a4db94011d3 970 */
sahilmgandhi 18:6a4db94011d3 971
sahilmgandhi 18:6a4db94011d3 972 /**
sahilmgandhi 18:6a4db94011d3 973 * @}
sahilmgandhi 18:6a4db94011d3 974 */
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /**
sahilmgandhi 18:6a4db94011d3 977 * @}
sahilmgandhi 18:6a4db94011d3 978 */
sahilmgandhi 18:6a4db94011d3 979
sahilmgandhi 18:6a4db94011d3 980 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 981 }
sahilmgandhi 18:6a4db94011d3 982 #endif
sahilmgandhi 18:6a4db94011d3 983
sahilmgandhi 18:6a4db94011d3 984 #endif /* __STM32L1xx_HAL_FLASH_EX_H */
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/