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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_pwr.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l0xx_ll_pwr.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.7.0
sahilmgandhi 18:6a4db94011d3 6 * @date 31-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of PWR LL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32L0xx_LL_PWR_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32L0xx_LL_PWR_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32l0xx.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32L0xx_LL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 #if defined(PWR)
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /** @defgroup PWR_LL PWR
sahilmgandhi 18:6a4db94011d3 56 * @{
sahilmgandhi 18:6a4db94011d3 57 */
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 60 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 67 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 68 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
sahilmgandhi 18:6a4db94011d3 69 * @{
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
sahilmgandhi 18:6a4db94011d3 73 * @brief Flags defines which can be used with LL_PWR_WriteReg function
sahilmgandhi 18:6a4db94011d3 74 * @{
sahilmgandhi 18:6a4db94011d3 75 */
sahilmgandhi 18:6a4db94011d3 76 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
sahilmgandhi 18:6a4db94011d3 77 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
sahilmgandhi 18:6a4db94011d3 78 /**
sahilmgandhi 18:6a4db94011d3 79 * @}
sahilmgandhi 18:6a4db94011d3 80 */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
sahilmgandhi 18:6a4db94011d3 83 * @brief Flags defines which can be used with LL_PWR_ReadReg function
sahilmgandhi 18:6a4db94011d3 84 * @{
sahilmgandhi 18:6a4db94011d3 85 */
sahilmgandhi 18:6a4db94011d3 86 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
sahilmgandhi 18:6a4db94011d3 87 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
sahilmgandhi 18:6a4db94011d3 88 #if defined (PWR_PVD_SUPPORT)
sahilmgandhi 18:6a4db94011d3 89 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
sahilmgandhi 18:6a4db94011d3 90 #endif
sahilmgandhi 18:6a4db94011d3 91 #if defined (PWR_CSR_VREFINTRDYF)
sahilmgandhi 18:6a4db94011d3 92 #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
sahilmgandhi 18:6a4db94011d3 93 #endif
sahilmgandhi 18:6a4db94011d3 94 #define LL_PWR_CSR_VOSF PWR_CSR_VOSF /*!< Voltage scaling select flag */
sahilmgandhi 18:6a4db94011d3 95 #define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */
sahilmgandhi 18:6a4db94011d3 96 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
sahilmgandhi 18:6a4db94011d3 97 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
sahilmgandhi 18:6a4db94011d3 98 #if defined (PWR_CSR_EWUP3)
sahilmgandhi 18:6a4db94011d3 99 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
sahilmgandhi 18:6a4db94011d3 100 #endif /* PWR_CSR_EWUP3 */
sahilmgandhi 18:6a4db94011d3 101 /**
sahilmgandhi 18:6a4db94011d3 102 * @}
sahilmgandhi 18:6a4db94011d3 103 */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
sahilmgandhi 18:6a4db94011d3 106 * @{
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */
sahilmgandhi 18:6a4db94011d3 109 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */
sahilmgandhi 18:6a4db94011d3 110 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */
sahilmgandhi 18:6a4db94011d3 111 /**
sahilmgandhi 18:6a4db94011d3 112 * @}
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
sahilmgandhi 18:6a4db94011d3 116 * @{
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118 #define LL_PWR_MODE_STOP ((uint32_t)0x00000000U) /*!< Enter Stop mode when the CPU enters deepsleep */
sahilmgandhi 18:6a4db94011d3 119 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
sahilmgandhi 18:6a4db94011d3 120 /**
sahilmgandhi 18:6a4db94011d3 121 * @}
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes
sahilmgandhi 18:6a4db94011d3 125 * @{
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127 #define LL_PWR_REGU_LPMODES_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */
sahilmgandhi 18:6a4db94011d3 128 #define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */
sahilmgandhi 18:6a4db94011d3 129 /**
sahilmgandhi 18:6a4db94011d3 130 * @}
sahilmgandhi 18:6a4db94011d3 131 */
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 #if defined(PWR_CR_LPDS)
sahilmgandhi 18:6a4db94011d3 134 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
sahilmgandhi 18:6a4db94011d3 135 * @{
sahilmgandhi 18:6a4db94011d3 136 */
sahilmgandhi 18:6a4db94011d3 137 #define LL_PWR_REGU_DSMODE_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
sahilmgandhi 18:6a4db94011d3 138 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @}
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142 #endif /* PWR_CR_LPDS */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 #if defined (PWR_PVD_SUPPORT)
sahilmgandhi 18:6a4db94011d3 145 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
sahilmgandhi 18:6a4db94011d3 146 * @{
sahilmgandhi 18:6a4db94011d3 147 */
sahilmgandhi 18:6a4db94011d3 148 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */
sahilmgandhi 18:6a4db94011d3 149 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */
sahilmgandhi 18:6a4db94011d3 150 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */
sahilmgandhi 18:6a4db94011d3 151 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
sahilmgandhi 18:6a4db94011d3 152 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */
sahilmgandhi 18:6a4db94011d3 153 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */
sahilmgandhi 18:6a4db94011d3 154 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */
sahilmgandhi 18:6a4db94011d3 155 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */
sahilmgandhi 18:6a4db94011d3 156 /**
sahilmgandhi 18:6a4db94011d3 157 * @}
sahilmgandhi 18:6a4db94011d3 158 */
sahilmgandhi 18:6a4db94011d3 159 #endif
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
sahilmgandhi 18:6a4db94011d3 162 * @{
sahilmgandhi 18:6a4db94011d3 163 */
sahilmgandhi 18:6a4db94011d3 164 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
sahilmgandhi 18:6a4db94011d3 165 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
sahilmgandhi 18:6a4db94011d3 166 #if defined (PWR_CSR_EWUP3)
sahilmgandhi 18:6a4db94011d3 167 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
sahilmgandhi 18:6a4db94011d3 168 #endif /* PWR_CSR_EWUP3 */
sahilmgandhi 18:6a4db94011d3 169 /**
sahilmgandhi 18:6a4db94011d3 170 * @}
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /**
sahilmgandhi 18:6a4db94011d3 174 * @}
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 179 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
sahilmgandhi 18:6a4db94011d3 180 * @{
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
sahilmgandhi 18:6a4db94011d3 184 * @{
sahilmgandhi 18:6a4db94011d3 185 */
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /**
sahilmgandhi 18:6a4db94011d3 188 * @brief Write a value in PWR register
sahilmgandhi 18:6a4db94011d3 189 * @param __REG__ Register to be written
sahilmgandhi 18:6a4db94011d3 190 * @param __VALUE__ Value to be written in the register
sahilmgandhi 18:6a4db94011d3 191 * @retval None
sahilmgandhi 18:6a4db94011d3 192 */
sahilmgandhi 18:6a4db94011d3 193 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /**
sahilmgandhi 18:6a4db94011d3 196 * @brief Read a value in PWR register
sahilmgandhi 18:6a4db94011d3 197 * @param __REG__ Register to be read
sahilmgandhi 18:6a4db94011d3 198 * @retval Register value
sahilmgandhi 18:6a4db94011d3 199 */
sahilmgandhi 18:6a4db94011d3 200 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
sahilmgandhi 18:6a4db94011d3 201 /**
sahilmgandhi 18:6a4db94011d3 202 * @}
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /**
sahilmgandhi 18:6a4db94011d3 206 * @}
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 211 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
sahilmgandhi 18:6a4db94011d3 212 * @{
sahilmgandhi 18:6a4db94011d3 213 */
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /** @defgroup PWR_LL_EF_Configuration Configuration
sahilmgandhi 18:6a4db94011d3 216 * @{
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /**
sahilmgandhi 18:6a4db94011d3 220 * @brief Switch the regulator from main mode to low-power mode
sahilmgandhi 18:6a4db94011d3 221 * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode
sahilmgandhi 18:6a4db94011d3 222 * @note Remind to set the regulator to low power before enabling
sahilmgandhi 18:6a4db94011d3 223 * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
sahilmgandhi 18:6a4db94011d3 224 * @retval None
sahilmgandhi 18:6a4db94011d3 225 */
sahilmgandhi 18:6a4db94011d3 226 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
sahilmgandhi 18:6a4db94011d3 227 {
sahilmgandhi 18:6a4db94011d3 228 SET_BIT(PWR->CR, PWR_CR_LPRUN);
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /**
sahilmgandhi 18:6a4db94011d3 232 * @brief Switch the regulator from low-power mode to main mode
sahilmgandhi 18:6a4db94011d3 233 * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode
sahilmgandhi 18:6a4db94011d3 234 * @retval None
sahilmgandhi 18:6a4db94011d3 235 */
sahilmgandhi 18:6a4db94011d3 236 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
sahilmgandhi 18:6a4db94011d3 237 {
sahilmgandhi 18:6a4db94011d3 238 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
sahilmgandhi 18:6a4db94011d3 239 }
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 /**
sahilmgandhi 18:6a4db94011d3 242 * @brief Check if the regulator is in low-power mode
sahilmgandhi 18:6a4db94011d3 243 * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode
sahilmgandhi 18:6a4db94011d3 244 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
sahilmgandhi 18:6a4db94011d3 247 {
sahilmgandhi 18:6a4db94011d3 248 return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN));
sahilmgandhi 18:6a4db94011d3 249 }
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /**
sahilmgandhi 18:6a4db94011d3 252 * @brief Set voltage regulator to low-power and switch from
sahilmgandhi 18:6a4db94011d3 253 * run main mode to run low-power mode.
sahilmgandhi 18:6a4db94011d3 254 * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n
sahilmgandhi 18:6a4db94011d3 255 * CR LPRUN LL_PWR_EnterLowPowerRunMode
sahilmgandhi 18:6a4db94011d3 256 * @note This "high level" function is introduced to provide functional
sahilmgandhi 18:6a4db94011d3 257 * compatibility with other families. Notice that the two registers
sahilmgandhi 18:6a4db94011d3 258 * have to be written sequentially, so this function is not atomic.
sahilmgandhi 18:6a4db94011d3 259 * To assure atomicity you can call separately the following functions:
sahilmgandhi 18:6a4db94011d3 260 * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER);
sahilmgandhi 18:6a4db94011d3 261 * - @ref LL_PWR_EnableLowPowerRunMode();
sahilmgandhi 18:6a4db94011d3 262 * @retval None
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
sahilmgandhi 18:6a4db94011d3 265 {
sahilmgandhi 18:6a4db94011d3 266 SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */
sahilmgandhi 18:6a4db94011d3 267 SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */
sahilmgandhi 18:6a4db94011d3 268 }
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /**
sahilmgandhi 18:6a4db94011d3 271 * @brief Set voltage regulator to main and switch from
sahilmgandhi 18:6a4db94011d3 272 * run main mode to low-power mode.
sahilmgandhi 18:6a4db94011d3 273 * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n
sahilmgandhi 18:6a4db94011d3 274 * CR LPRUN LL_PWR_ExitLowPowerRunMode
sahilmgandhi 18:6a4db94011d3 275 * @note This "high level" function is introduced to provide functional
sahilmgandhi 18:6a4db94011d3 276 * compatibility with other families. Notice that the two registers
sahilmgandhi 18:6a4db94011d3 277 * have to be written sequentially, so this function is not atomic.
sahilmgandhi 18:6a4db94011d3 278 * To assure atomicity you can call separately the following functions:
sahilmgandhi 18:6a4db94011d3 279 * - @ref LL_PWR_DisableLowPowerRunMode();
sahilmgandhi 18:6a4db94011d3 280 * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN);
sahilmgandhi 18:6a4db94011d3 281 * @retval None
sahilmgandhi 18:6a4db94011d3 282 */
sahilmgandhi 18:6a4db94011d3 283 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
sahilmgandhi 18:6a4db94011d3 284 {
sahilmgandhi 18:6a4db94011d3 285 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */
sahilmgandhi 18:6a4db94011d3 286 CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
sahilmgandhi 18:6a4db94011d3 287 }
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /**
sahilmgandhi 18:6a4db94011d3 290 * @brief Set the main internal regulator output voltage
sahilmgandhi 18:6a4db94011d3 291 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
sahilmgandhi 18:6a4db94011d3 292 * @param VoltageScaling This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 293 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
sahilmgandhi 18:6a4db94011d3 294 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
sahilmgandhi 18:6a4db94011d3 295 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
sahilmgandhi 18:6a4db94011d3 296 * @retval None
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
sahilmgandhi 18:6a4db94011d3 299 {
sahilmgandhi 18:6a4db94011d3 300 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
sahilmgandhi 18:6a4db94011d3 301 }
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 /**
sahilmgandhi 18:6a4db94011d3 304 * @brief Get the main internal regulator output voltage
sahilmgandhi 18:6a4db94011d3 305 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
sahilmgandhi 18:6a4db94011d3 306 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 307 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
sahilmgandhi 18:6a4db94011d3 308 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
sahilmgandhi 18:6a4db94011d3 309 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
sahilmgandhi 18:6a4db94011d3 310 */
sahilmgandhi 18:6a4db94011d3 311 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
sahilmgandhi 18:6a4db94011d3 312 {
sahilmgandhi 18:6a4db94011d3 313 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 /**
sahilmgandhi 18:6a4db94011d3 317 * @brief Enable access to the backup domain
sahilmgandhi 18:6a4db94011d3 318 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
sahilmgandhi 18:6a4db94011d3 319 * @retval None
sahilmgandhi 18:6a4db94011d3 320 */
sahilmgandhi 18:6a4db94011d3 321 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
sahilmgandhi 18:6a4db94011d3 322 {
sahilmgandhi 18:6a4db94011d3 323 SET_BIT(PWR->CR, PWR_CR_DBP);
sahilmgandhi 18:6a4db94011d3 324 }
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 /**
sahilmgandhi 18:6a4db94011d3 327 * @brief Disable access to the backup domain
sahilmgandhi 18:6a4db94011d3 328 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
sahilmgandhi 18:6a4db94011d3 329 * @retval None
sahilmgandhi 18:6a4db94011d3 330 */
sahilmgandhi 18:6a4db94011d3 331 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
sahilmgandhi 18:6a4db94011d3 332 {
sahilmgandhi 18:6a4db94011d3 333 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /**
sahilmgandhi 18:6a4db94011d3 337 * @brief Check if the backup domain is enabled
sahilmgandhi 18:6a4db94011d3 338 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
sahilmgandhi 18:6a4db94011d3 339 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 340 */
sahilmgandhi 18:6a4db94011d3 341 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
sahilmgandhi 18:6a4db94011d3 342 {
sahilmgandhi 18:6a4db94011d3 343 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
sahilmgandhi 18:6a4db94011d3 344 }
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /**
sahilmgandhi 18:6a4db94011d3 347 * @brief Set voltage regulator mode during low power modes
sahilmgandhi 18:6a4db94011d3 348 * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP
sahilmgandhi 18:6a4db94011d3 349 * @param RegulMode This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 350 * @arg @ref LL_PWR_REGU_LPMODES_MAIN
sahilmgandhi 18:6a4db94011d3 351 * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
sahilmgandhi 18:6a4db94011d3 352 * @retval None
sahilmgandhi 18:6a4db94011d3 353 */
sahilmgandhi 18:6a4db94011d3 354 __STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode)
sahilmgandhi 18:6a4db94011d3 355 {
sahilmgandhi 18:6a4db94011d3 356 MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode);
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 /**
sahilmgandhi 18:6a4db94011d3 360 * @brief Get voltage regulator mode during low power modes
sahilmgandhi 18:6a4db94011d3 361 * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP
sahilmgandhi 18:6a4db94011d3 362 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 363 * @arg @ref LL_PWR_REGU_LPMODES_MAIN
sahilmgandhi 18:6a4db94011d3 364 * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
sahilmgandhi 18:6a4db94011d3 365 */
sahilmgandhi 18:6a4db94011d3 366 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void)
sahilmgandhi 18:6a4db94011d3 367 {
sahilmgandhi 18:6a4db94011d3 368 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR));
sahilmgandhi 18:6a4db94011d3 369 }
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 #if defined(PWR_CR_LPDS)
sahilmgandhi 18:6a4db94011d3 372 /**
sahilmgandhi 18:6a4db94011d3 373 * @brief Set voltage regulator mode during deep sleep mode
sahilmgandhi 18:6a4db94011d3 374 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
sahilmgandhi 18:6a4db94011d3 375 * @param RegulMode This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 376 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
sahilmgandhi 18:6a4db94011d3 377 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
sahilmgandhi 18:6a4db94011d3 378 * @retval None
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
sahilmgandhi 18:6a4db94011d3 381 {
sahilmgandhi 18:6a4db94011d3 382 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /**
sahilmgandhi 18:6a4db94011d3 386 * @brief Get voltage regulator mode during deep sleep mode
sahilmgandhi 18:6a4db94011d3 387 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
sahilmgandhi 18:6a4db94011d3 388 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 389 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
sahilmgandhi 18:6a4db94011d3 390 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
sahilmgandhi 18:6a4db94011d3 391 */
sahilmgandhi 18:6a4db94011d3 392 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
sahilmgandhi 18:6a4db94011d3 393 {
sahilmgandhi 18:6a4db94011d3 394 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
sahilmgandhi 18:6a4db94011d3 395 }
sahilmgandhi 18:6a4db94011d3 396 #endif /* PWR_CR_LPDS */
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /**
sahilmgandhi 18:6a4db94011d3 399 * @brief Set power down mode when CPU enters deepsleep
sahilmgandhi 18:6a4db94011d3 400 * @rmtoll CR PDDS LL_PWR_SetPowerMode
sahilmgandhi 18:6a4db94011d3 401 * @param PDMode This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 402 * @arg @ref LL_PWR_MODE_STOP
sahilmgandhi 18:6a4db94011d3 403 * @arg @ref LL_PWR_MODE_STANDBY
sahilmgandhi 18:6a4db94011d3 404 * @note Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)
sahilmgandhi 18:6a4db94011d3 405 * before setting MODE_STOP. If the regulator remains in "main mode",
sahilmgandhi 18:6a4db94011d3 406 * it consumes more power without providing any additional feature.
sahilmgandhi 18:6a4db94011d3 407 * In MODE_STANDBY the regulator is automatically off.
sahilmgandhi 18:6a4db94011d3 408 * @retval None
sahilmgandhi 18:6a4db94011d3 409 */
sahilmgandhi 18:6a4db94011d3 410 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
sahilmgandhi 18:6a4db94011d3 411 {
sahilmgandhi 18:6a4db94011d3 412 MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode);
sahilmgandhi 18:6a4db94011d3 413 }
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /**
sahilmgandhi 18:6a4db94011d3 416 * @brief Get power down mode when CPU enters deepsleep
sahilmgandhi 18:6a4db94011d3 417 * @rmtoll CR PDDS LL_PWR_GetPowerMode
sahilmgandhi 18:6a4db94011d3 418 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 419 * @arg @ref LL_PWR_MODE_STOP
sahilmgandhi 18:6a4db94011d3 420 * @arg @ref LL_PWR_MODE_STANDBY
sahilmgandhi 18:6a4db94011d3 421 */
sahilmgandhi 18:6a4db94011d3 422 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
sahilmgandhi 18:6a4db94011d3 423 {
sahilmgandhi 18:6a4db94011d3 424 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 #if defined (PWR_PVD_SUPPORT)
sahilmgandhi 18:6a4db94011d3 428 /**
sahilmgandhi 18:6a4db94011d3 429 * @brief Configure the voltage threshold detected by the Power Voltage Detector
sahilmgandhi 18:6a4db94011d3 430 * @rmtoll CR PLS LL_PWR_SetPVDLevel
sahilmgandhi 18:6a4db94011d3 431 * @param PVDLevel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 432 * @arg @ref LL_PWR_PVDLEVEL_0
sahilmgandhi 18:6a4db94011d3 433 * @arg @ref LL_PWR_PVDLEVEL_1
sahilmgandhi 18:6a4db94011d3 434 * @arg @ref LL_PWR_PVDLEVEL_2
sahilmgandhi 18:6a4db94011d3 435 * @arg @ref LL_PWR_PVDLEVEL_3
sahilmgandhi 18:6a4db94011d3 436 * @arg @ref LL_PWR_PVDLEVEL_4
sahilmgandhi 18:6a4db94011d3 437 * @arg @ref LL_PWR_PVDLEVEL_5
sahilmgandhi 18:6a4db94011d3 438 * @arg @ref LL_PWR_PVDLEVEL_6
sahilmgandhi 18:6a4db94011d3 439 * @arg @ref LL_PWR_PVDLEVEL_7
sahilmgandhi 18:6a4db94011d3 440 * @retval None
sahilmgandhi 18:6a4db94011d3 441 */
sahilmgandhi 18:6a4db94011d3 442 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
sahilmgandhi 18:6a4db94011d3 443 {
sahilmgandhi 18:6a4db94011d3 444 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
sahilmgandhi 18:6a4db94011d3 445 }
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 /**
sahilmgandhi 18:6a4db94011d3 448 * @brief Get the voltage threshold detection
sahilmgandhi 18:6a4db94011d3 449 * @rmtoll CR PLS LL_PWR_GetPVDLevel
sahilmgandhi 18:6a4db94011d3 450 * @retval Returned value can be one of the following values:
sahilmgandhi 18:6a4db94011d3 451 * @arg @ref LL_PWR_PVDLEVEL_0
sahilmgandhi 18:6a4db94011d3 452 * @arg @ref LL_PWR_PVDLEVEL_1
sahilmgandhi 18:6a4db94011d3 453 * @arg @ref LL_PWR_PVDLEVEL_2
sahilmgandhi 18:6a4db94011d3 454 * @arg @ref LL_PWR_PVDLEVEL_3
sahilmgandhi 18:6a4db94011d3 455 * @arg @ref LL_PWR_PVDLEVEL_4
sahilmgandhi 18:6a4db94011d3 456 * @arg @ref LL_PWR_PVDLEVEL_5
sahilmgandhi 18:6a4db94011d3 457 * @arg @ref LL_PWR_PVDLEVEL_6
sahilmgandhi 18:6a4db94011d3 458 * @arg @ref LL_PWR_PVDLEVEL_7
sahilmgandhi 18:6a4db94011d3 459 */
sahilmgandhi 18:6a4db94011d3 460 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
sahilmgandhi 18:6a4db94011d3 461 {
sahilmgandhi 18:6a4db94011d3 462 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /**
sahilmgandhi 18:6a4db94011d3 466 * @brief Enable Power Voltage Detector
sahilmgandhi 18:6a4db94011d3 467 * @rmtoll CR PVDE LL_PWR_EnablePVD
sahilmgandhi 18:6a4db94011d3 468 * @retval None
sahilmgandhi 18:6a4db94011d3 469 */
sahilmgandhi 18:6a4db94011d3 470 __STATIC_INLINE void LL_PWR_EnablePVD(void)
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 SET_BIT(PWR->CR, PWR_CR_PVDE);
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /**
sahilmgandhi 18:6a4db94011d3 476 * @brief Disable Power Voltage Detector
sahilmgandhi 18:6a4db94011d3 477 * @rmtoll CR PVDE LL_PWR_DisablePVD
sahilmgandhi 18:6a4db94011d3 478 * @retval None
sahilmgandhi 18:6a4db94011d3 479 */
sahilmgandhi 18:6a4db94011d3 480 __STATIC_INLINE void LL_PWR_DisablePVD(void)
sahilmgandhi 18:6a4db94011d3 481 {
sahilmgandhi 18:6a4db94011d3 482 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
sahilmgandhi 18:6a4db94011d3 483 }
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 /**
sahilmgandhi 18:6a4db94011d3 486 * @brief Check if Power Voltage Detector is enabled
sahilmgandhi 18:6a4db94011d3 487 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
sahilmgandhi 18:6a4db94011d3 488 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 489 */
sahilmgandhi 18:6a4db94011d3 490 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
sahilmgandhi 18:6a4db94011d3 491 {
sahilmgandhi 18:6a4db94011d3 492 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494 #endif
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 /**
sahilmgandhi 18:6a4db94011d3 497 * @brief Enable the WakeUp PINx functionality
sahilmgandhi 18:6a4db94011d3 498 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
sahilmgandhi 18:6a4db94011d3 499 * CSR EWUP2 LL_PWR_EnableWakeUpPin\n
sahilmgandhi 18:6a4db94011d3 500 * CSR EWUP3 LL_PWR_EnableWakeUpPin
sahilmgandhi 18:6a4db94011d3 501 * @param WakeUpPin This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 502 * @arg @ref LL_PWR_WAKEUP_PIN1
sahilmgandhi 18:6a4db94011d3 503 * @arg @ref LL_PWR_WAKEUP_PIN2
sahilmgandhi 18:6a4db94011d3 504 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
sahilmgandhi 18:6a4db94011d3 505 *
sahilmgandhi 18:6a4db94011d3 506 * (*) not available on all devices
sahilmgandhi 18:6a4db94011d3 507 * @retval None
sahilmgandhi 18:6a4db94011d3 508 */
sahilmgandhi 18:6a4db94011d3 509 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
sahilmgandhi 18:6a4db94011d3 510 {
sahilmgandhi 18:6a4db94011d3 511 SET_BIT(PWR->CSR, WakeUpPin);
sahilmgandhi 18:6a4db94011d3 512 }
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 /**
sahilmgandhi 18:6a4db94011d3 515 * @brief Disable the WakeUp PINx functionality
sahilmgandhi 18:6a4db94011d3 516 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
sahilmgandhi 18:6a4db94011d3 517 * CSR EWUP2 LL_PWR_DisableWakeUpPin\n
sahilmgandhi 18:6a4db94011d3 518 * CSR EWUP3 LL_PWR_DisableWakeUpPin
sahilmgandhi 18:6a4db94011d3 519 * @param WakeUpPin This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 520 * @arg @ref LL_PWR_WAKEUP_PIN1
sahilmgandhi 18:6a4db94011d3 521 * @arg @ref LL_PWR_WAKEUP_PIN2
sahilmgandhi 18:6a4db94011d3 522 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
sahilmgandhi 18:6a4db94011d3 523 *
sahilmgandhi 18:6a4db94011d3 524 * (*) not available on all devices
sahilmgandhi 18:6a4db94011d3 525 * @retval None
sahilmgandhi 18:6a4db94011d3 526 */
sahilmgandhi 18:6a4db94011d3 527 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
sahilmgandhi 18:6a4db94011d3 528 {
sahilmgandhi 18:6a4db94011d3 529 CLEAR_BIT(PWR->CSR, WakeUpPin);
sahilmgandhi 18:6a4db94011d3 530 }
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 /**
sahilmgandhi 18:6a4db94011d3 533 * @brief Check if the WakeUp PINx functionality is enabled
sahilmgandhi 18:6a4db94011d3 534 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
sahilmgandhi 18:6a4db94011d3 535 * CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
sahilmgandhi 18:6a4db94011d3 536 * CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
sahilmgandhi 18:6a4db94011d3 537 * @param WakeUpPin This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 538 * @arg @ref LL_PWR_WAKEUP_PIN1
sahilmgandhi 18:6a4db94011d3 539 * @arg @ref LL_PWR_WAKEUP_PIN2
sahilmgandhi 18:6a4db94011d3 540 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
sahilmgandhi 18:6a4db94011d3 541 *
sahilmgandhi 18:6a4db94011d3 542 * (*) not available on all devices
sahilmgandhi 18:6a4db94011d3 543 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 544 */
sahilmgandhi 18:6a4db94011d3 545 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
sahilmgandhi 18:6a4db94011d3 546 {
sahilmgandhi 18:6a4db94011d3 547 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
sahilmgandhi 18:6a4db94011d3 548 }
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 /**
sahilmgandhi 18:6a4db94011d3 551 * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes
sahilmgandhi 18:6a4db94011d3 552 * @rmtoll CR ULP LL_PWR_EnableUltraLowPower
sahilmgandhi 18:6a4db94011d3 553 * @retval None
sahilmgandhi 18:6a4db94011d3 554 */
sahilmgandhi 18:6a4db94011d3 555 __STATIC_INLINE void LL_PWR_EnableUltraLowPower(void)
sahilmgandhi 18:6a4db94011d3 556 {
sahilmgandhi 18:6a4db94011d3 557 SET_BIT(PWR->CR, PWR_CR_ULP);
sahilmgandhi 18:6a4db94011d3 558 }
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /**
sahilmgandhi 18:6a4db94011d3 561 * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes
sahilmgandhi 18:6a4db94011d3 562 * @rmtoll CR ULP LL_PWR_DisableUltraLowPower
sahilmgandhi 18:6a4db94011d3 563 * @retval None
sahilmgandhi 18:6a4db94011d3 564 */
sahilmgandhi 18:6a4db94011d3 565 __STATIC_INLINE void LL_PWR_DisableUltraLowPower(void)
sahilmgandhi 18:6a4db94011d3 566 {
sahilmgandhi 18:6a4db94011d3 567 CLEAR_BIT(PWR->CR, PWR_CR_ULP);
sahilmgandhi 18:6a4db94011d3 568 }
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /**
sahilmgandhi 18:6a4db94011d3 571 * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled
sahilmgandhi 18:6a4db94011d3 572 * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower
sahilmgandhi 18:6a4db94011d3 573 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 574 */
sahilmgandhi 18:6a4db94011d3 575 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void)
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP));
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 /**
sahilmgandhi 18:6a4db94011d3 581 * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode
sahilmgandhi 18:6a4db94011d3 582 * @rmtoll CR FWU LL_PWR_EnableFastWakeUp
sahilmgandhi 18:6a4db94011d3 583 * @note Works in conjunction with ultra low power mode.
sahilmgandhi 18:6a4db94011d3 584 * @retval None
sahilmgandhi 18:6a4db94011d3 585 */
sahilmgandhi 18:6a4db94011d3 586 __STATIC_INLINE void LL_PWR_EnableFastWakeUp(void)
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 SET_BIT(PWR->CR, PWR_CR_FWU);
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /**
sahilmgandhi 18:6a4db94011d3 592 * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode
sahilmgandhi 18:6a4db94011d3 593 * @rmtoll CR FWU LL_PWR_DisableFastWakeUp
sahilmgandhi 18:6a4db94011d3 594 * @note Works in conjunction with ultra low power mode.
sahilmgandhi 18:6a4db94011d3 595 * @retval None
sahilmgandhi 18:6a4db94011d3 596 */
sahilmgandhi 18:6a4db94011d3 597 __STATIC_INLINE void LL_PWR_DisableFastWakeUp(void)
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 CLEAR_BIT(PWR->CR, PWR_CR_FWU);
sahilmgandhi 18:6a4db94011d3 600 }
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 /**
sahilmgandhi 18:6a4db94011d3 603 * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored
sahilmgandhi 18:6a4db94011d3 604 * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp
sahilmgandhi 18:6a4db94011d3 605 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 606 */
sahilmgandhi 18:6a4db94011d3 607 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void)
sahilmgandhi 18:6a4db94011d3 608 {
sahilmgandhi 18:6a4db94011d3 609 return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU));
sahilmgandhi 18:6a4db94011d3 610 }
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /**
sahilmgandhi 18:6a4db94011d3 613 * @brief Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
sahilmgandhi 18:6a4db94011d3 614 * @rmtoll CR DS_EE_KOFF LL_PWR_EnableNVMKeptOff
sahilmgandhi 18:6a4db94011d3 615 * @note When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register
sahilmgandhi 18:6a4db94011d3 616 * is also set, the Flash memory will not be woken up when exiting from deepsleep mode.
sahilmgandhi 18:6a4db94011d3 617 * When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set)
sahilmgandhi 18:6a4db94011d3 618 * @retval None
sahilmgandhi 18:6a4db94011d3 619 */
sahilmgandhi 18:6a4db94011d3 620 __STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void)
sahilmgandhi 18:6a4db94011d3 621 {
sahilmgandhi 18:6a4db94011d3 622 SET_BIT(PWR->CR, PWR_CR_DSEEKOFF);
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /**
sahilmgandhi 18:6a4db94011d3 626 * @brief Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
sahilmgandhi 18:6a4db94011d3 627 * @rmtoll CR DS_EE_KOFF LL_PWR_DisableNVMKeptOff
sahilmgandhi 18:6a4db94011d3 628 * @note When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set
sahilmgandhi 18:6a4db94011d3 629 * @retval None
sahilmgandhi 18:6a4db94011d3 630 */
sahilmgandhi 18:6a4db94011d3 631 __STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void)
sahilmgandhi 18:6a4db94011d3 632 {
sahilmgandhi 18:6a4db94011d3 633 CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF);
sahilmgandhi 18:6a4db94011d3 634 }
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636 /**
sahilmgandhi 18:6a4db94011d3 637 * @brief Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled
sahilmgandhi 18:6a4db94011d3 638 * @rmtoll CR DS_EE_KOFF LL_PWR_IsEnabledNVMKeptOff
sahilmgandhi 18:6a4db94011d3 639 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void)
sahilmgandhi 18:6a4db94011d3 642 {
sahilmgandhi 18:6a4db94011d3 643 return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF));
sahilmgandhi 18:6a4db94011d3 644 }
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 /**
sahilmgandhi 18:6a4db94011d3 647 * @}
sahilmgandhi 18:6a4db94011d3 648 */
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
sahilmgandhi 18:6a4db94011d3 651 * @{
sahilmgandhi 18:6a4db94011d3 652 */
sahilmgandhi 18:6a4db94011d3 653
sahilmgandhi 18:6a4db94011d3 654 /**
sahilmgandhi 18:6a4db94011d3 655 * @brief Get Wake-up Flag
sahilmgandhi 18:6a4db94011d3 656 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
sahilmgandhi 18:6a4db94011d3 657 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 658 */
sahilmgandhi 18:6a4db94011d3 659 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
sahilmgandhi 18:6a4db94011d3 660 {
sahilmgandhi 18:6a4db94011d3 661 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
sahilmgandhi 18:6a4db94011d3 662 }
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /**
sahilmgandhi 18:6a4db94011d3 665 * @brief Get Standby Flag
sahilmgandhi 18:6a4db94011d3 666 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
sahilmgandhi 18:6a4db94011d3 667 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 668 */
sahilmgandhi 18:6a4db94011d3 669 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
sahilmgandhi 18:6a4db94011d3 670 {
sahilmgandhi 18:6a4db94011d3 671 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 #if defined (PWR_PVD_SUPPORT)
sahilmgandhi 18:6a4db94011d3 675 /**
sahilmgandhi 18:6a4db94011d3 676 * @brief Indicate whether VDD voltage is below the selected PVD threshold
sahilmgandhi 18:6a4db94011d3 677 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
sahilmgandhi 18:6a4db94011d3 678 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 679 */
sahilmgandhi 18:6a4db94011d3 680 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
sahilmgandhi 18:6a4db94011d3 681 {
sahilmgandhi 18:6a4db94011d3 682 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
sahilmgandhi 18:6a4db94011d3 683 }
sahilmgandhi 18:6a4db94011d3 684 #endif
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 #if defined (PWR_CSR_VREFINTRDYF)
sahilmgandhi 18:6a4db94011d3 687 /**
sahilmgandhi 18:6a4db94011d3 688 * @brief Get Internal Reference VrefInt Flag
sahilmgandhi 18:6a4db94011d3 689 * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
sahilmgandhi 18:6a4db94011d3 690 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 691 */
sahilmgandhi 18:6a4db94011d3 692 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
sahilmgandhi 18:6a4db94011d3 695 }
sahilmgandhi 18:6a4db94011d3 696 #endif
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 /**
sahilmgandhi 18:6a4db94011d3 699 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
sahilmgandhi 18:6a4db94011d3 700 * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOSF
sahilmgandhi 18:6a4db94011d3 701 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 702 */
sahilmgandhi 18:6a4db94011d3 703 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void)
sahilmgandhi 18:6a4db94011d3 704 {
sahilmgandhi 18:6a4db94011d3 705 return (READ_BIT(PWR->CSR, PWR_CSR_VOSF) == (PWR_CSR_VOSF));
sahilmgandhi 18:6a4db94011d3 706 }
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 /**
sahilmgandhi 18:6a4db94011d3 709 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
sahilmgandhi 18:6a4db94011d3 710 * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF
sahilmgandhi 18:6a4db94011d3 711 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
sahilmgandhi 18:6a4db94011d3 712 * @retval State of bit (1 or 0).
sahilmgandhi 18:6a4db94011d3 713 */
sahilmgandhi 18:6a4db94011d3 714 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
sahilmgandhi 18:6a4db94011d3 715 {
sahilmgandhi 18:6a4db94011d3 716 return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF));
sahilmgandhi 18:6a4db94011d3 717 }
sahilmgandhi 18:6a4db94011d3 718
sahilmgandhi 18:6a4db94011d3 719 /**
sahilmgandhi 18:6a4db94011d3 720 * @brief Clear Standby Flag
sahilmgandhi 18:6a4db94011d3 721 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
sahilmgandhi 18:6a4db94011d3 722 * @retval None
sahilmgandhi 18:6a4db94011d3 723 */
sahilmgandhi 18:6a4db94011d3 724 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
sahilmgandhi 18:6a4db94011d3 725 {
sahilmgandhi 18:6a4db94011d3 726 SET_BIT(PWR->CR, PWR_CR_CSBF);
sahilmgandhi 18:6a4db94011d3 727 }
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 /**
sahilmgandhi 18:6a4db94011d3 730 * @brief Clear Wake-up Flags
sahilmgandhi 18:6a4db94011d3 731 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
sahilmgandhi 18:6a4db94011d3 732 * @retval None
sahilmgandhi 18:6a4db94011d3 733 */
sahilmgandhi 18:6a4db94011d3 734 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
sahilmgandhi 18:6a4db94011d3 735 {
sahilmgandhi 18:6a4db94011d3 736 SET_BIT(PWR->CR, PWR_CR_CWUF);
sahilmgandhi 18:6a4db94011d3 737 }
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739
sahilmgandhi 18:6a4db94011d3 740 #if defined(USE_FULL_LL_DRIVER)
sahilmgandhi 18:6a4db94011d3 741 /** @defgroup PWR_LL_EF_Init De-initialization function
sahilmgandhi 18:6a4db94011d3 742 * @{
sahilmgandhi 18:6a4db94011d3 743 */
sahilmgandhi 18:6a4db94011d3 744 ErrorStatus LL_PWR_DeInit(void);
sahilmgandhi 18:6a4db94011d3 745 /**
sahilmgandhi 18:6a4db94011d3 746 * @}
sahilmgandhi 18:6a4db94011d3 747 */
sahilmgandhi 18:6a4db94011d3 748 #endif /* USE_FULL_LL_DRIVER */
sahilmgandhi 18:6a4db94011d3 749
sahilmgandhi 18:6a4db94011d3 750 /**
sahilmgandhi 18:6a4db94011d3 751 * @}
sahilmgandhi 18:6a4db94011d3 752 */
sahilmgandhi 18:6a4db94011d3 753
sahilmgandhi 18:6a4db94011d3 754 /**
sahilmgandhi 18:6a4db94011d3 755 * @}
sahilmgandhi 18:6a4db94011d3 756 */
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 /**
sahilmgandhi 18:6a4db94011d3 759 * @}
sahilmgandhi 18:6a4db94011d3 760 */
sahilmgandhi 18:6a4db94011d3 761
sahilmgandhi 18:6a4db94011d3 762 #endif /* defined(PWR) */
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 /**
sahilmgandhi 18:6a4db94011d3 765 * @}
sahilmgandhi 18:6a4db94011d3 766 */
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 769 }
sahilmgandhi 18:6a4db94011d3 770 #endif
sahilmgandhi 18:6a4db94011d3 771
sahilmgandhi 18:6a4db94011d3 772 #endif /* __STM32L0xx_LL_PWR_H */
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/