MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l073xx.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.7.0
sahilmgandhi 18:6a4db94011d3 6 * @date 31-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
sahilmgandhi 18:6a4db94011d3 8 * This file contains all the peripheral register's definitions, bits
sahilmgandhi 18:6a4db94011d3 9 * definitions and memory mapping for stm32l073xx devices.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * This file contains:
sahilmgandhi 18:6a4db94011d3 12 * - Data structures and the address mapping for all peripherals
sahilmgandhi 18:6a4db94011d3 13 * - Peripheral's registers declarations and bits definition
sahilmgandhi 18:6a4db94011d3 14 * - Macros to access peripheral's registers hardware
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 17 * @attention
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 22 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 23 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 26 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 27 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 29 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 30 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 44 */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /** @addtogroup CMSIS
sahilmgandhi 18:6a4db94011d3 47 * @{
sahilmgandhi 18:6a4db94011d3 48 */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** @addtogroup stm32l073xx
sahilmgandhi 18:6a4db94011d3 51 * @{
sahilmgandhi 18:6a4db94011d3 52 */
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 #ifndef __STM32L073xx_H
sahilmgandhi 18:6a4db94011d3 55 #define __STM32L073xx_H
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 58 extern "C" {
sahilmgandhi 18:6a4db94011d3 59 #endif
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /** @addtogroup Configuration_section_for_CMSIS
sahilmgandhi 18:6a4db94011d3 63 * @{
sahilmgandhi 18:6a4db94011d3 64 */
sahilmgandhi 18:6a4db94011d3 65 /**
sahilmgandhi 18:6a4db94011d3 66 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
sahilmgandhi 18:6a4db94011d3 69 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
sahilmgandhi 18:6a4db94011d3 70 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
sahilmgandhi 18:6a4db94011d3 71 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
sahilmgandhi 18:6a4db94011d3 72 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /**
sahilmgandhi 18:6a4db94011d3 75 * @}
sahilmgandhi 18:6a4db94011d3 76 */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /** @addtogroup Peripheral_interrupt_number_definition
sahilmgandhi 18:6a4db94011d3 79 * @{
sahilmgandhi 18:6a4db94011d3 80 */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 /**
sahilmgandhi 18:6a4db94011d3 83 * @brief stm32l073xx Interrupt Number Definition, according to the selected device
sahilmgandhi 18:6a4db94011d3 84 * in @ref Library_configuration_section
sahilmgandhi 18:6a4db94011d3 85 */
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 /*!< Interrupt Number Definition */
sahilmgandhi 18:6a4db94011d3 88 typedef enum
sahilmgandhi 18:6a4db94011d3 89 {
sahilmgandhi 18:6a4db94011d3 90 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
sahilmgandhi 18:6a4db94011d3 91 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 92 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 93 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 94 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 95 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
sahilmgandhi 18:6a4db94011d3 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
sahilmgandhi 18:6a4db94011d3 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
sahilmgandhi 18:6a4db94011d3 100 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
sahilmgandhi 18:6a4db94011d3 101 FLASH_IRQn = 3, /*!< FLASH Interrupt */
sahilmgandhi 18:6a4db94011d3 102 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
sahilmgandhi 18:6a4db94011d3 103 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
sahilmgandhi 18:6a4db94011d3 104 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
sahilmgandhi 18:6a4db94011d3 105 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
sahilmgandhi 18:6a4db94011d3 106 TSC_IRQn = 8, /*!< TSC Interrupt */
sahilmgandhi 18:6a4db94011d3 107 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 108 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
sahilmgandhi 18:6a4db94011d3 109 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
sahilmgandhi 18:6a4db94011d3 110 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
sahilmgandhi 18:6a4db94011d3 111 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
sahilmgandhi 18:6a4db94011d3 112 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
sahilmgandhi 18:6a4db94011d3 113 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
sahilmgandhi 18:6a4db94011d3 114 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
sahilmgandhi 18:6a4db94011d3 115 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
sahilmgandhi 18:6a4db94011d3 116 TIM7_IRQn = 18, /*!< TIM7 Interrupt */
sahilmgandhi 18:6a4db94011d3 117 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
sahilmgandhi 18:6a4db94011d3 118 I2C3_IRQn = 21, /*!< I2C3 Interrupt */
sahilmgandhi 18:6a4db94011d3 119 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
sahilmgandhi 18:6a4db94011d3 120 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
sahilmgandhi 18:6a4db94011d3 121 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
sahilmgandhi 18:6a4db94011d3 122 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
sahilmgandhi 18:6a4db94011d3 123 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
sahilmgandhi 18:6a4db94011d3 124 USART1_IRQn = 27, /*!< USART1 Interrupt */
sahilmgandhi 18:6a4db94011d3 125 USART2_IRQn = 28, /*!< USART2 Interrupt */
sahilmgandhi 18:6a4db94011d3 126 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
sahilmgandhi 18:6a4db94011d3 127 LCD_IRQn = 30, /*!< LCD Interrupt */
sahilmgandhi 18:6a4db94011d3 128 USB_IRQn = 31, /*!< USB global Interrupt */
sahilmgandhi 18:6a4db94011d3 129 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /**
sahilmgandhi 18:6a4db94011d3 132 * @}
sahilmgandhi 18:6a4db94011d3 133 */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 #include "core_cm0plus.h"
sahilmgandhi 18:6a4db94011d3 136 #include "system_stm32l0xx.h"
sahilmgandhi 18:6a4db94011d3 137 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /** @addtogroup Peripheral_registers_structures
sahilmgandhi 18:6a4db94011d3 140 * @{
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 /**
sahilmgandhi 18:6a4db94011d3 144 * @brief Analog to Digital Converter
sahilmgandhi 18:6a4db94011d3 145 */
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 typedef struct
sahilmgandhi 18:6a4db94011d3 148 {
sahilmgandhi 18:6a4db94011d3 149 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
sahilmgandhi 18:6a4db94011d3 150 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
sahilmgandhi 18:6a4db94011d3 151 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
sahilmgandhi 18:6a4db94011d3 152 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
sahilmgandhi 18:6a4db94011d3 153 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
sahilmgandhi 18:6a4db94011d3 154 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
sahilmgandhi 18:6a4db94011d3 155 uint32_t RESERVED1; /*!< Reserved, 0x18 */
sahilmgandhi 18:6a4db94011d3 156 uint32_t RESERVED2; /*!< Reserved, 0x1C */
sahilmgandhi 18:6a4db94011d3 157 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
sahilmgandhi 18:6a4db94011d3 158 uint32_t RESERVED3; /*!< Reserved, 0x24 */
sahilmgandhi 18:6a4db94011d3 159 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
sahilmgandhi 18:6a4db94011d3 160 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
sahilmgandhi 18:6a4db94011d3 161 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
sahilmgandhi 18:6a4db94011d3 162 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
sahilmgandhi 18:6a4db94011d3 164 } ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 typedef struct
sahilmgandhi 18:6a4db94011d3 167 {
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 169 } ADC_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /**
sahilmgandhi 18:6a4db94011d3 173 * @brief Comparator
sahilmgandhi 18:6a4db94011d3 174 */
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 typedef struct
sahilmgandhi 18:6a4db94011d3 177 {
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 179 } COMP_TypeDef;
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 typedef struct
sahilmgandhi 18:6a4db94011d3 182 {
sahilmgandhi 18:6a4db94011d3 183 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 184 } COMP_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /**
sahilmgandhi 18:6a4db94011d3 188 * @brief CRC calculation unit
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 typedef struct
sahilmgandhi 18:6a4db94011d3 192 {
sahilmgandhi 18:6a4db94011d3 193 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 194 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 195 uint8_t RESERVED0; /*!< Reserved, 0x05 */
sahilmgandhi 18:6a4db94011d3 196 uint16_t RESERVED1; /*!< Reserved, 0x06 */
sahilmgandhi 18:6a4db94011d3 197 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 198 uint32_t RESERVED2; /*!< Reserved, 0x0C */
sahilmgandhi 18:6a4db94011d3 199 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 200 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 201 } CRC_TypeDef;
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /**
sahilmgandhi 18:6a4db94011d3 204 * @brief Clock Recovery System
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 typedef struct
sahilmgandhi 18:6a4db94011d3 208 {
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 210 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 212 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 213 } CRS_TypeDef;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /**
sahilmgandhi 18:6a4db94011d3 216 * @brief Digital to Analog Converter
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 typedef struct
sahilmgandhi 18:6a4db94011d3 220 {
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 226 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 228 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 231 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 232 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 233 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 234 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 235 } DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /**
sahilmgandhi 18:6a4db94011d3 238 * @brief Debug MCU
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 typedef struct
sahilmgandhi 18:6a4db94011d3 242 {
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 244 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 246 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 247 }DBGMCU_TypeDef;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /**
sahilmgandhi 18:6a4db94011d3 250 * @brief DMA Controller
sahilmgandhi 18:6a4db94011d3 251 */
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 typedef struct
sahilmgandhi 18:6a4db94011d3 254 {
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t CCR; /*!< DMA channel x configuration register */
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
sahilmgandhi 18:6a4db94011d3 258 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
sahilmgandhi 18:6a4db94011d3 259 } DMA_Channel_TypeDef;
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 typedef struct
sahilmgandhi 18:6a4db94011d3 262 {
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 264 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 265 } DMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 typedef struct
sahilmgandhi 18:6a4db94011d3 268 {
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
sahilmgandhi 18:6a4db94011d3 270 } DMA_Request_TypeDef;
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /**
sahilmgandhi 18:6a4db94011d3 273 * @brief External Interrupt/Event Controller
sahilmgandhi 18:6a4db94011d3 274 */
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 typedef struct
sahilmgandhi 18:6a4db94011d3 277 {
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 284 }EXTI_TypeDef;
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 /**
sahilmgandhi 18:6a4db94011d3 287 * @brief FLASH Registers
sahilmgandhi 18:6a4db94011d3 288 */
sahilmgandhi 18:6a4db94011d3 289 typedef struct
sahilmgandhi 18:6a4db94011d3 290 {
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 292 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 293 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
sahilmgandhi 18:6a4db94011d3 295 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 296 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 297 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 298 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
sahilmgandhi 18:6a4db94011d3 299 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 300 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 301 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 302 } FLASH_TypeDef;
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /**
sahilmgandhi 18:6a4db94011d3 306 * @brief Option Bytes Registers
sahilmgandhi 18:6a4db94011d3 307 */
sahilmgandhi 18:6a4db94011d3 308 typedef struct
sahilmgandhi 18:6a4db94011d3 309 {
sahilmgandhi 18:6a4db94011d3 310 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 311 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 313 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 314 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 315 } OB_TypeDef;
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 /**
sahilmgandhi 18:6a4db94011d3 319 * @brief General Purpose IO
sahilmgandhi 18:6a4db94011d3 320 */
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 typedef struct
sahilmgandhi 18:6a4db94011d3 323 {
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 325 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 327 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 328 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 332 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 334 }GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /**
sahilmgandhi 18:6a4db94011d3 337 * @brief LPTIMIMER
sahilmgandhi 18:6a4db94011d3 338 */
sahilmgandhi 18:6a4db94011d3 339 typedef struct
sahilmgandhi 18:6a4db94011d3 340 {
sahilmgandhi 18:6a4db94011d3 341 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 343 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 347 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 348 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 349 } LPTIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /**
sahilmgandhi 18:6a4db94011d3 352 * @brief SysTem Configuration
sahilmgandhi 18:6a4db94011d3 353 */
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 typedef struct
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
sahilmgandhi 18:6a4db94011d3 360 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 362 } SYSCFG_TypeDef;
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /**
sahilmgandhi 18:6a4db94011d3 367 * @brief Inter-integrated Circuit Interface
sahilmgandhi 18:6a4db94011d3 368 */
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 typedef struct
sahilmgandhi 18:6a4db94011d3 371 {
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 374 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 376 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 380 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 381 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 382 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 383 }I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /**
sahilmgandhi 18:6a4db94011d3 387 * @brief Independent WATCHDOG
sahilmgandhi 18:6a4db94011d3 388 */
sahilmgandhi 18:6a4db94011d3 389 typedef struct
sahilmgandhi 18:6a4db94011d3 390 {
sahilmgandhi 18:6a4db94011d3 391 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 392 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 393 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 394 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 395 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 396 } IWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /**
sahilmgandhi 18:6a4db94011d3 399 * @brief LCD
sahilmgandhi 18:6a4db94011d3 400 */
sahilmgandhi 18:6a4db94011d3 401 typedef struct
sahilmgandhi 18:6a4db94011d3 402 {
sahilmgandhi 18:6a4db94011d3 403 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 404 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 407 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
sahilmgandhi 18:6a4db94011d3 409 } LCD_TypeDef;
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /**
sahilmgandhi 18:6a4db94011d3 412 * @brief MIFARE Firewall
sahilmgandhi 18:6a4db94011d3 413 */
sahilmgandhi 18:6a4db94011d3 414 typedef struct
sahilmgandhi 18:6a4db94011d3 415 {
sahilmgandhi 18:6a4db94011d3 416 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 421 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 422 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 424 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 } FIREWALL_TypeDef;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /**
sahilmgandhi 18:6a4db94011d3 429 * @brief Power Control
sahilmgandhi 18:6a4db94011d3 430 */
sahilmgandhi 18:6a4db94011d3 431 typedef struct
sahilmgandhi 18:6a4db94011d3 432 {
sahilmgandhi 18:6a4db94011d3 433 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 435 } PWR_TypeDef;
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /**
sahilmgandhi 18:6a4db94011d3 438 * @brief Reset and Clock Control
sahilmgandhi 18:6a4db94011d3 439 */
sahilmgandhi 18:6a4db94011d3 440 typedef struct
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 443 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 445 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 446 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 447 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 450 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 452 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 456 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 459 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 460 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 461 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 462 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 463 } RCC_TypeDef;
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /**
sahilmgandhi 18:6a4db94011d3 466 * @brief Random numbers generator
sahilmgandhi 18:6a4db94011d3 467 */
sahilmgandhi 18:6a4db94011d3 468 typedef struct
sahilmgandhi 18:6a4db94011d3 469 {
sahilmgandhi 18:6a4db94011d3 470 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 471 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 472 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 473 } RNG_TypeDef;
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /**
sahilmgandhi 18:6a4db94011d3 476 * @brief Real-Time Clock
sahilmgandhi 18:6a4db94011d3 477 */
sahilmgandhi 18:6a4db94011d3 478 typedef struct
sahilmgandhi 18:6a4db94011d3 479 {
sahilmgandhi 18:6a4db94011d3 480 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 486 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 487 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 488 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 489 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 495 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 496 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 498 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 499 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
sahilmgandhi 18:6a4db94011d3 500 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 505 } RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 /**
sahilmgandhi 18:6a4db94011d3 509 * @brief Serial Peripheral Interface
sahilmgandhi 18:6a4db94011d3 510 */
sahilmgandhi 18:6a4db94011d3 511 typedef struct
sahilmgandhi 18:6a4db94011d3 512 {
sahilmgandhi 18:6a4db94011d3 513 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 521 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 522 } SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /**
sahilmgandhi 18:6a4db94011d3 525 * @brief TIM
sahilmgandhi 18:6a4db94011d3 526 */
sahilmgandhi 18:6a4db94011d3 527 typedef struct
sahilmgandhi 18:6a4db94011d3 528 {
sahilmgandhi 18:6a4db94011d3 529 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 530 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 531 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 532 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 533 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 535 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 536 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 538 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 539 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 540 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 541 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 542 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 544 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 545 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 546 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 547 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 550 } TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 /**
sahilmgandhi 18:6a4db94011d3 553 * @brief Touch Sensing Controller (TSC)
sahilmgandhi 18:6a4db94011d3 554 */
sahilmgandhi 18:6a4db94011d3 555 typedef struct
sahilmgandhi 18:6a4db94011d3 556 {
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 558 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 559 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 560 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 561 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 562 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 563 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 564 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 565 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 566 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 568 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 569 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
sahilmgandhi 18:6a4db94011d3 571 } TSC_TypeDef;
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 /**
sahilmgandhi 18:6a4db94011d3 574 * @brief Universal Synchronous Asynchronous Receiver Transmitter
sahilmgandhi 18:6a4db94011d3 575 */
sahilmgandhi 18:6a4db94011d3 576 typedef struct
sahilmgandhi 18:6a4db94011d3 577 {
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 581 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 589 } USART_TypeDef;
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /**
sahilmgandhi 18:6a4db94011d3 592 * @brief Window WATCHDOG
sahilmgandhi 18:6a4db94011d3 593 */
sahilmgandhi 18:6a4db94011d3 594 typedef struct
sahilmgandhi 18:6a4db94011d3 595 {
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 599 } WWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 /**
sahilmgandhi 18:6a4db94011d3 602 * @brief Universal Serial Bus Full Speed Device
sahilmgandhi 18:6a4db94011d3 603 */
sahilmgandhi 18:6a4db94011d3 604 typedef struct
sahilmgandhi 18:6a4db94011d3 605 {
sahilmgandhi 18:6a4db94011d3 606 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 607 __IO uint16_t RESERVED0; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 608 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 609 __IO uint16_t RESERVED1; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 610 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 611 __IO uint16_t RESERVED2; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 612 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 613 __IO uint16_t RESERVED3; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 614 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 615 __IO uint16_t RESERVED4; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 616 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 617 __IO uint16_t RESERVED5; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 618 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 619 __IO uint16_t RESERVED6; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 620 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 621 __IO uint16_t RESERVED7[17]; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 622 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 623 __IO uint16_t RESERVED8; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 624 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 625 __IO uint16_t RESERVED9; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 626 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 627 __IO uint16_t RESERVEDA; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 628 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 629 __IO uint16_t RESERVEDB; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 630 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 631 __IO uint16_t RESERVEDC; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 632 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 633 __IO uint16_t RESERVEDD; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 634 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 635 __IO uint16_t RESERVEDE; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 636 } USB_TypeDef;
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /**
sahilmgandhi 18:6a4db94011d3 639 * @}
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 /** @addtogroup Peripheral_memory_map
sahilmgandhi 18:6a4db94011d3 643 * @{
sahilmgandhi 18:6a4db94011d3 644 */
sahilmgandhi 18:6a4db94011d3 645 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
sahilmgandhi 18:6a4db94011d3 646 #define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */
sahilmgandhi 18:6a4db94011d3 647 #define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */
sahilmgandhi 18:6a4db94011d3 648 #define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */
sahilmgandhi 18:6a4db94011d3 649 #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
sahilmgandhi 18:6a4db94011d3 650 #define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */
sahilmgandhi 18:6a4db94011d3 651 #define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */
sahilmgandhi 18:6a4db94011d3 652 #define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */
sahilmgandhi 18:6a4db94011d3 653 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
sahilmgandhi 18:6a4db94011d3 654 #define SRAM_SIZE_MAX ((uint32_t)0x00005000U) /*!< maximum SRAM size (up to 20KBytes) */
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /*!< Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 659 #define APBPERIPH_BASE PERIPH_BASE
sahilmgandhi 18:6a4db94011d3 660 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
sahilmgandhi 18:6a4db94011d3 661 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
sahilmgandhi 18:6a4db94011d3 664 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400U)
sahilmgandhi 18:6a4db94011d3 665 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000U)
sahilmgandhi 18:6a4db94011d3 666 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400U)
sahilmgandhi 18:6a4db94011d3 667 #define LCD_BASE (APBPERIPH_BASE + 0x00002400U)
sahilmgandhi 18:6a4db94011d3 668 #define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
sahilmgandhi 18:6a4db94011d3 669 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
sahilmgandhi 18:6a4db94011d3 670 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
sahilmgandhi 18:6a4db94011d3 671 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800U)
sahilmgandhi 18:6a4db94011d3 672 #define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
sahilmgandhi 18:6a4db94011d3 673 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
sahilmgandhi 18:6a4db94011d3 674 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00U)
sahilmgandhi 18:6a4db94011d3 675 #define USART5_BASE (APBPERIPH_BASE + 0x00005000U)
sahilmgandhi 18:6a4db94011d3 676 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
sahilmgandhi 18:6a4db94011d3 677 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800U)
sahilmgandhi 18:6a4db94011d3 678 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00U)
sahilmgandhi 18:6a4db94011d3 679 #define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
sahilmgandhi 18:6a4db94011d3 680 #define DAC_BASE (APBPERIPH_BASE + 0x00007400U)
sahilmgandhi 18:6a4db94011d3 681 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
sahilmgandhi 18:6a4db94011d3 682 #define I2C3_BASE (APBPERIPH_BASE + 0x00007800U)
sahilmgandhi 18:6a4db94011d3 683
sahilmgandhi 18:6a4db94011d3 684 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
sahilmgandhi 18:6a4db94011d3 685 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
sahilmgandhi 18:6a4db94011d3 686 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
sahilmgandhi 18:6a4db94011d3 687 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
sahilmgandhi 18:6a4db94011d3 688 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
sahilmgandhi 18:6a4db94011d3 689 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
sahilmgandhi 18:6a4db94011d3 690 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
sahilmgandhi 18:6a4db94011d3 691 #define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U)
sahilmgandhi 18:6a4db94011d3 692 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
sahilmgandhi 18:6a4db94011d3 693 #define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
sahilmgandhi 18:6a4db94011d3 694 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
sahilmgandhi 18:6a4db94011d3 695 #define USART1_BASE (APBPERIPH_BASE + 0x00013800U)
sahilmgandhi 18:6a4db94011d3 696 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
sahilmgandhi 18:6a4db94011d3 699 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
sahilmgandhi 18:6a4db94011d3 700 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
sahilmgandhi 18:6a4db94011d3 701 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
sahilmgandhi 18:6a4db94011d3 702 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
sahilmgandhi 18:6a4db94011d3 703 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
sahilmgandhi 18:6a4db94011d3 704 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
sahilmgandhi 18:6a4db94011d3 705 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
sahilmgandhi 18:6a4db94011d3 706 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
sahilmgandhi 18:6a4db94011d3 710 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
sahilmgandhi 18:6a4db94011d3 711 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
sahilmgandhi 18:6a4db94011d3 712 #define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
sahilmgandhi 18:6a4db94011d3 713 #define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
sahilmgandhi 18:6a4db94011d3 714 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
sahilmgandhi 18:6a4db94011d3 715 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000U)
sahilmgandhi 18:6a4db94011d3 716 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000U)
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
sahilmgandhi 18:6a4db94011d3 719 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
sahilmgandhi 18:6a4db94011d3 720 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
sahilmgandhi 18:6a4db94011d3 721 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U)
sahilmgandhi 18:6a4db94011d3 722 #define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000U)
sahilmgandhi 18:6a4db94011d3 723 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725 /**
sahilmgandhi 18:6a4db94011d3 726 * @}
sahilmgandhi 18:6a4db94011d3 727 */
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 /** @addtogroup Peripheral_declaration
sahilmgandhi 18:6a4db94011d3 730 * @{
sahilmgandhi 18:6a4db94011d3 731 */
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 734 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 735 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
sahilmgandhi 18:6a4db94011d3 736 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
sahilmgandhi 18:6a4db94011d3 737 #define RTC ((RTC_TypeDef *) RTC_BASE)
sahilmgandhi 18:6a4db94011d3 738 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
sahilmgandhi 18:6a4db94011d3 739 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
sahilmgandhi 18:6a4db94011d3 740 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 741 #define USART2 ((USART_TypeDef *) USART2_BASE)
sahilmgandhi 18:6a4db94011d3 742 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
sahilmgandhi 18:6a4db94011d3 743 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 744 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 745 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
sahilmgandhi 18:6a4db94011d3 746 #define CRS ((CRS_TypeDef *) CRS_BASE)
sahilmgandhi 18:6a4db94011d3 747 #define PWR ((PWR_TypeDef *) PWR_BASE)
sahilmgandhi 18:6a4db94011d3 748 #define DAC ((DAC_TypeDef *) DAC_BASE)
sahilmgandhi 18:6a4db94011d3 749 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
sahilmgandhi 18:6a4db94011d3 750 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
sahilmgandhi 18:6a4db94011d3 751 #define LCD ((LCD_TypeDef *) LCD_BASE)
sahilmgandhi 18:6a4db94011d3 752 #define USART4 ((USART_TypeDef *) USART4_BASE)
sahilmgandhi 18:6a4db94011d3 753 #define USART5 ((USART_TypeDef *) USART5_BASE)
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
sahilmgandhi 18:6a4db94011d3 756 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
sahilmgandhi 18:6a4db94011d3 757 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
sahilmgandhi 18:6a4db94011d3 758 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
sahilmgandhi 18:6a4db94011d3 759 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
sahilmgandhi 18:6a4db94011d3 760 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
sahilmgandhi 18:6a4db94011d3 761 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
sahilmgandhi 18:6a4db94011d3 762 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 763 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
sahilmgandhi 18:6a4db94011d3 764 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 765 #define ADC ADC1_COMMON
sahilmgandhi 18:6a4db94011d3 766 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 767 #define USART1 ((USART_TypeDef *) USART1_BASE)
sahilmgandhi 18:6a4db94011d3 768 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
sahilmgandhi 18:6a4db94011d3 771 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
sahilmgandhi 18:6a4db94011d3 772 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
sahilmgandhi 18:6a4db94011d3 773 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
sahilmgandhi 18:6a4db94011d3 774 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
sahilmgandhi 18:6a4db94011d3 775 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
sahilmgandhi 18:6a4db94011d3 776 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
sahilmgandhi 18:6a4db94011d3 777 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
sahilmgandhi 18:6a4db94011d3 778 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
sahilmgandhi 18:6a4db94011d3 782 #define OB ((OB_TypeDef *) OB_BASE)
sahilmgandhi 18:6a4db94011d3 783 #define RCC ((RCC_TypeDef *) RCC_BASE)
sahilmgandhi 18:6a4db94011d3 784 #define CRC ((CRC_TypeDef *) CRC_BASE)
sahilmgandhi 18:6a4db94011d3 785 #define TSC ((TSC_TypeDef *) TSC_BASE)
sahilmgandhi 18:6a4db94011d3 786 #define RNG ((RNG_TypeDef *) RNG_BASE)
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
sahilmgandhi 18:6a4db94011d3 789 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
sahilmgandhi 18:6a4db94011d3 790 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 791 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
sahilmgandhi 18:6a4db94011d3 792 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
sahilmgandhi 18:6a4db94011d3 793 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 #define USB ((USB_TypeDef *) USB_BASE)
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 /**
sahilmgandhi 18:6a4db94011d3 798 * @}
sahilmgandhi 18:6a4db94011d3 799 */
sahilmgandhi 18:6a4db94011d3 800
sahilmgandhi 18:6a4db94011d3 801 /** @addtogroup Exported_constants
sahilmgandhi 18:6a4db94011d3 802 * @{
sahilmgandhi 18:6a4db94011d3 803 */
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 /** @addtogroup Peripheral_Registers_Bits_Definition
sahilmgandhi 18:6a4db94011d3 806 * @{
sahilmgandhi 18:6a4db94011d3 807 */
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 810 /* Peripheral Registers Bits Definition */
sahilmgandhi 18:6a4db94011d3 811 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 812 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 813 /* */
sahilmgandhi 18:6a4db94011d3 814 /* Analog to Digital Converter (ADC) */
sahilmgandhi 18:6a4db94011d3 815 /* */
sahilmgandhi 18:6a4db94011d3 816 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 817 /******************** Bits definition for ADC_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 818 #define ADC_ISR_EOCAL_Pos (11U)
sahilmgandhi 18:6a4db94011d3 819 #define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 820 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
sahilmgandhi 18:6a4db94011d3 821 #define ADC_ISR_AWD_Pos (7U)
sahilmgandhi 18:6a4db94011d3 822 #define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 823 #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 824 #define ADC_ISR_OVR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 825 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 826 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
sahilmgandhi 18:6a4db94011d3 827 #define ADC_ISR_EOSEQ_Pos (3U)
sahilmgandhi 18:6a4db94011d3 828 #define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 829 #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
sahilmgandhi 18:6a4db94011d3 830 #define ADC_ISR_EOC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 831 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 832 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
sahilmgandhi 18:6a4db94011d3 833 #define ADC_ISR_EOSMP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 834 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 835 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
sahilmgandhi 18:6a4db94011d3 836 #define ADC_ISR_ADRDY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 837 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 838 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 /* Old EOSEQ bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 841 #define ADC_ISR_EOS ADC_ISR_EOSEQ
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 /******************** Bits definition for ADC_IER register ******************/
sahilmgandhi 18:6a4db94011d3 844 #define ADC_IER_EOCALIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 845 #define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 846 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
sahilmgandhi 18:6a4db94011d3 847 #define ADC_IER_AWDIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 848 #define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 849 #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
sahilmgandhi 18:6a4db94011d3 850 #define ADC_IER_OVRIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 851 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 852 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 853 #define ADC_IER_EOSEQIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 854 #define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 855 #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
sahilmgandhi 18:6a4db94011d3 856 #define ADC_IER_EOCIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 857 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 858 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
sahilmgandhi 18:6a4db94011d3 859 #define ADC_IER_EOSMPIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 860 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 861 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
sahilmgandhi 18:6a4db94011d3 862 #define ADC_IER_ADRDYIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 863 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 864 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /* Old EOSEQIE bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 867 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
sahilmgandhi 18:6a4db94011d3 868
sahilmgandhi 18:6a4db94011d3 869 /******************** Bits definition for ADC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 870 #define ADC_CR_ADCAL_Pos (31U)
sahilmgandhi 18:6a4db94011d3 871 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 872 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
sahilmgandhi 18:6a4db94011d3 873 #define ADC_CR_ADVREGEN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 874 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 875 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
sahilmgandhi 18:6a4db94011d3 876 #define ADC_CR_ADSTP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 877 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 878 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
sahilmgandhi 18:6a4db94011d3 879 #define ADC_CR_ADSTART_Pos (2U)
sahilmgandhi 18:6a4db94011d3 880 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 881 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
sahilmgandhi 18:6a4db94011d3 882 #define ADC_CR_ADDIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 883 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 884 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
sahilmgandhi 18:6a4db94011d3 885 #define ADC_CR_ADEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 886 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 887 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 /******************* Bits definition for ADC_CFGR1 register *****************/
sahilmgandhi 18:6a4db94011d3 890 #define ADC_CFGR1_AWDCH_Pos (26U)
sahilmgandhi 18:6a4db94011d3 891 #define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
sahilmgandhi 18:6a4db94011d3 892 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
sahilmgandhi 18:6a4db94011d3 893 #define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 894 #define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 895 #define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 896 #define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 897 #define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 898 #define ADC_CFGR1_AWDEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 899 #define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 900 #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
sahilmgandhi 18:6a4db94011d3 901 #define ADC_CFGR1_AWDSGL_Pos (22U)
sahilmgandhi 18:6a4db94011d3 902 #define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 903 #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
sahilmgandhi 18:6a4db94011d3 904 #define ADC_CFGR1_DISCEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 905 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 906 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
sahilmgandhi 18:6a4db94011d3 907 #define ADC_CFGR1_AUTOFF_Pos (15U)
sahilmgandhi 18:6a4db94011d3 908 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 909 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
sahilmgandhi 18:6a4db94011d3 910 #define ADC_CFGR1_WAIT_Pos (14U)
sahilmgandhi 18:6a4db94011d3 911 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 912 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
sahilmgandhi 18:6a4db94011d3 913 #define ADC_CFGR1_CONT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 914 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 915 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
sahilmgandhi 18:6a4db94011d3 916 #define ADC_CFGR1_OVRMOD_Pos (12U)
sahilmgandhi 18:6a4db94011d3 917 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 918 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
sahilmgandhi 18:6a4db94011d3 919 #define ADC_CFGR1_EXTEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 920 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 921 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
sahilmgandhi 18:6a4db94011d3 922 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 923 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 924 #define ADC_CFGR1_EXTSEL_Pos (6U)
sahilmgandhi 18:6a4db94011d3 925 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
sahilmgandhi 18:6a4db94011d3 926 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
sahilmgandhi 18:6a4db94011d3 927 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 928 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 929 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 930 #define ADC_CFGR1_ALIGN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 931 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 932 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
sahilmgandhi 18:6a4db94011d3 933 #define ADC_CFGR1_RES_Pos (3U)
sahilmgandhi 18:6a4db94011d3 934 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 935 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
sahilmgandhi 18:6a4db94011d3 936 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 937 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 938 #define ADC_CFGR1_SCANDIR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 939 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 940 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
sahilmgandhi 18:6a4db94011d3 941 #define ADC_CFGR1_DMACFG_Pos (1U)
sahilmgandhi 18:6a4db94011d3 942 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 943 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
sahilmgandhi 18:6a4db94011d3 944 #define ADC_CFGR1_DMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 945 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 946 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
sahilmgandhi 18:6a4db94011d3 947
sahilmgandhi 18:6a4db94011d3 948 /* Old WAIT bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 949 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 /******************* Bits definition for ADC_CFGR2 register *****************/
sahilmgandhi 18:6a4db94011d3 952 #define ADC_CFGR2_TOVS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 953 #define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
sahilmgandhi 18:6a4db94011d3 954 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
sahilmgandhi 18:6a4db94011d3 955 #define ADC_CFGR2_OVSS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 956 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
sahilmgandhi 18:6a4db94011d3 957 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
sahilmgandhi 18:6a4db94011d3 958 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 959 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 960 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 961 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 962 #define ADC_CFGR2_OVSR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 963 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
sahilmgandhi 18:6a4db94011d3 964 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
sahilmgandhi 18:6a4db94011d3 965 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 966 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 967 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 968 #define ADC_CFGR2_OVSE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 969 #define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 970 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
sahilmgandhi 18:6a4db94011d3 971 #define ADC_CFGR2_CKMODE_Pos (30U)
sahilmgandhi 18:6a4db94011d3 972 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 973 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
sahilmgandhi 18:6a4db94011d3 974 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 975 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 976
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 /****************** Bit definition for ADC_SMPR register ********************/
sahilmgandhi 18:6a4db94011d3 979 #define ADC_SMPR_SMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 980 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 981 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
sahilmgandhi 18:6a4db94011d3 982 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 983 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 984 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 987 #define ADC_SMPR_SMPR ADC_SMPR_SMP
sahilmgandhi 18:6a4db94011d3 988 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
sahilmgandhi 18:6a4db94011d3 989 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
sahilmgandhi 18:6a4db94011d3 990 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 /******************* Bit definition for ADC_TR register ********************/
sahilmgandhi 18:6a4db94011d3 993 #define ADC_TR_HT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 994 #define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 995 #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
sahilmgandhi 18:6a4db94011d3 996 #define ADC_TR_LT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 997 #define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 998 #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /****************** Bit definition for ADC_CHSELR register ******************/
sahilmgandhi 18:6a4db94011d3 1001 #define ADC_CHSELR_CHSEL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1002 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
sahilmgandhi 18:6a4db94011d3 1003 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
sahilmgandhi 18:6a4db94011d3 1004 #define ADC_CHSELR_CHSEL18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1005 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1006 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
sahilmgandhi 18:6a4db94011d3 1007 #define ADC_CHSELR_CHSEL17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1008 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1009 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
sahilmgandhi 18:6a4db94011d3 1010 #define ADC_CHSELR_CHSEL16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1011 #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1012 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */
sahilmgandhi 18:6a4db94011d3 1013 #define ADC_CHSELR_CHSEL15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1014 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1015 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
sahilmgandhi 18:6a4db94011d3 1016 #define ADC_CHSELR_CHSEL14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1017 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1018 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
sahilmgandhi 18:6a4db94011d3 1019 #define ADC_CHSELR_CHSEL13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1020 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1021 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
sahilmgandhi 18:6a4db94011d3 1022 #define ADC_CHSELR_CHSEL12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1023 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1024 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
sahilmgandhi 18:6a4db94011d3 1025 #define ADC_CHSELR_CHSEL11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1026 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1027 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
sahilmgandhi 18:6a4db94011d3 1028 #define ADC_CHSELR_CHSEL10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1029 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1030 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
sahilmgandhi 18:6a4db94011d3 1031 #define ADC_CHSELR_CHSEL9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1032 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1033 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
sahilmgandhi 18:6a4db94011d3 1034 #define ADC_CHSELR_CHSEL8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1035 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1036 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
sahilmgandhi 18:6a4db94011d3 1037 #define ADC_CHSELR_CHSEL7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1038 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1039 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
sahilmgandhi 18:6a4db94011d3 1040 #define ADC_CHSELR_CHSEL6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1041 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1042 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
sahilmgandhi 18:6a4db94011d3 1043 #define ADC_CHSELR_CHSEL5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1044 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1045 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
sahilmgandhi 18:6a4db94011d3 1046 #define ADC_CHSELR_CHSEL4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1047 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1048 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
sahilmgandhi 18:6a4db94011d3 1049 #define ADC_CHSELR_CHSEL3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1050 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1051 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
sahilmgandhi 18:6a4db94011d3 1052 #define ADC_CHSELR_CHSEL2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1053 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1054 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
sahilmgandhi 18:6a4db94011d3 1055 #define ADC_CHSELR_CHSEL1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1056 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1057 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
sahilmgandhi 18:6a4db94011d3 1058 #define ADC_CHSELR_CHSEL0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1059 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1060 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /******************** Bit definition for ADC_DR register ********************/
sahilmgandhi 18:6a4db94011d3 1063 #define ADC_DR_DATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1064 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1065 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
sahilmgandhi 18:6a4db94011d3 1066
sahilmgandhi 18:6a4db94011d3 1067 /******************** Bit definition for ADC_CALFACT register ********************/
sahilmgandhi 18:6a4db94011d3 1068 #define ADC_CALFACT_CALFACT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1069 #define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 1070 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /******************* Bit definition for ADC_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 1073 #define ADC_CCR_LFMEN_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1074 #define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1075 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
sahilmgandhi 18:6a4db94011d3 1076 #define ADC_CCR_VLCDEN_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1077 #define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1078 #define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */
sahilmgandhi 18:6a4db94011d3 1079 #define ADC_CCR_TSEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1080 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1081 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
sahilmgandhi 18:6a4db94011d3 1082 #define ADC_CCR_VREFEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1083 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1084 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
sahilmgandhi 18:6a4db94011d3 1085 #define ADC_CCR_PRESC_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1086 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
sahilmgandhi 18:6a4db94011d3 1087 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
sahilmgandhi 18:6a4db94011d3 1088 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1089 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1090 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1091 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1092
sahilmgandhi 18:6a4db94011d3 1093 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1094 /* */
sahilmgandhi 18:6a4db94011d3 1095 /* Analog Comparators (COMP) */
sahilmgandhi 18:6a4db94011d3 1096 /* */
sahilmgandhi 18:6a4db94011d3 1097 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1098 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
sahilmgandhi 18:6a4db94011d3 1099 /* COMP1 bits definition */
sahilmgandhi 18:6a4db94011d3 1100 #define COMP_CSR_COMP1EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1101 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1102 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
sahilmgandhi 18:6a4db94011d3 1103 #define COMP_CSR_COMP1INNSEL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1104 #define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 1105 #define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
sahilmgandhi 18:6a4db94011d3 1106 #define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1107 #define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1108 #define COMP_CSR_COMP1WM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1109 #define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1110 #define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
sahilmgandhi 18:6a4db94011d3 1111 #define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1112 #define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1113 #define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
sahilmgandhi 18:6a4db94011d3 1114 #define COMP_CSR_COMP1POLARITY_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1115 #define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1116 #define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
sahilmgandhi 18:6a4db94011d3 1117 #define COMP_CSR_COMP1VALUE_Pos (30U)
sahilmgandhi 18:6a4db94011d3 1118 #define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1119 #define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
sahilmgandhi 18:6a4db94011d3 1120 #define COMP_CSR_COMP1LOCK_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1121 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1122 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
sahilmgandhi 18:6a4db94011d3 1123 /* COMP2 bits definition */
sahilmgandhi 18:6a4db94011d3 1124 #define COMP_CSR_COMP2EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1125 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1126 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
sahilmgandhi 18:6a4db94011d3 1127 #define COMP_CSR_COMP2SPEED_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1128 #define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1129 #define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
sahilmgandhi 18:6a4db94011d3 1130 #define COMP_CSR_COMP2INNSEL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1131 #define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 1132 #define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
sahilmgandhi 18:6a4db94011d3 1133 #define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1134 #define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1135 #define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1136 #define COMP_CSR_COMP2INPSEL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1137 #define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 1138 #define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
sahilmgandhi 18:6a4db94011d3 1139 #define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1140 #define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1141 #define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1142 #define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1143 #define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1144 #define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
sahilmgandhi 18:6a4db94011d3 1145 #define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1146 #define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1147 #define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
sahilmgandhi 18:6a4db94011d3 1148 #define COMP_CSR_COMP2POLARITY_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1149 #define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1150 #define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
sahilmgandhi 18:6a4db94011d3 1151 #define COMP_CSR_COMP2VALUE_Pos (30U)
sahilmgandhi 18:6a4db94011d3 1152 #define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1153 #define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
sahilmgandhi 18:6a4db94011d3 1154 #define COMP_CSR_COMP2LOCK_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1155 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1156 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 /********************** Bit definition for COMP_CSR register common ****************/
sahilmgandhi 18:6a4db94011d3 1159 #define COMP_CSR_COMPxEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1160 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1161 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
sahilmgandhi 18:6a4db94011d3 1162 #define COMP_CSR_COMPxPOLARITY_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1163 #define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1164 #define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
sahilmgandhi 18:6a4db94011d3 1165 #define COMP_CSR_COMPxOUTVALUE_Pos (30U)
sahilmgandhi 18:6a4db94011d3 1166 #define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1167 #define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
sahilmgandhi 18:6a4db94011d3 1168 #define COMP_CSR_COMPxLOCK_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1169 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1170 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 1173 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
sahilmgandhi 18:6a4db94011d3 1174
sahilmgandhi 18:6a4db94011d3 1175 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1176 /* */
sahilmgandhi 18:6a4db94011d3 1177 /* CRC calculation unit (CRC) */
sahilmgandhi 18:6a4db94011d3 1178 /* */
sahilmgandhi 18:6a4db94011d3 1179 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1180 /******************* Bit definition for CRC_DR register *********************/
sahilmgandhi 18:6a4db94011d3 1181 #define CRC_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1182 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1183 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
sahilmgandhi 18:6a4db94011d3 1184
sahilmgandhi 18:6a4db94011d3 1185 /******************* Bit definition for CRC_IDR register ********************/
sahilmgandhi 18:6a4db94011d3 1186 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
sahilmgandhi 18:6a4db94011d3 1187
sahilmgandhi 18:6a4db94011d3 1188 /******************** Bit definition for CRC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 1189 #define CRC_CR_RESET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1190 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1191 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
sahilmgandhi 18:6a4db94011d3 1192 #define CRC_CR_POLYSIZE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1193 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 1194 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
sahilmgandhi 18:6a4db94011d3 1195 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1196 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1197 #define CRC_CR_REV_IN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1198 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 1199 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
sahilmgandhi 18:6a4db94011d3 1200 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1201 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1202 #define CRC_CR_REV_OUT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1203 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1204 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
sahilmgandhi 18:6a4db94011d3 1205
sahilmgandhi 18:6a4db94011d3 1206 /******************* Bit definition for CRC_INIT register *******************/
sahilmgandhi 18:6a4db94011d3 1207 #define CRC_INIT_INIT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1208 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1209 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
sahilmgandhi 18:6a4db94011d3 1210
sahilmgandhi 18:6a4db94011d3 1211 /******************* Bit definition for CRC_POL register ********************/
sahilmgandhi 18:6a4db94011d3 1212 #define CRC_POL_POL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1213 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1214 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
sahilmgandhi 18:6a4db94011d3 1215
sahilmgandhi 18:6a4db94011d3 1216 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1217 /* */
sahilmgandhi 18:6a4db94011d3 1218 /* CRS Clock Recovery System */
sahilmgandhi 18:6a4db94011d3 1219 /* */
sahilmgandhi 18:6a4db94011d3 1220 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 /******************* Bit definition for CRS_CR register *********************/
sahilmgandhi 18:6a4db94011d3 1223 #define CRS_CR_SYNCOKIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1224 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1225 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
sahilmgandhi 18:6a4db94011d3 1226 #define CRS_CR_SYNCWARNIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1227 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1228 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
sahilmgandhi 18:6a4db94011d3 1229 #define CRS_CR_ERRIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1230 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1231 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
sahilmgandhi 18:6a4db94011d3 1232 #define CRS_CR_ESYNCIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1233 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1234 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
sahilmgandhi 18:6a4db94011d3 1235 #define CRS_CR_CEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1236 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1237 #define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
sahilmgandhi 18:6a4db94011d3 1238 #define CRS_CR_AUTOTRIMEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1239 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1240 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
sahilmgandhi 18:6a4db94011d3 1241 #define CRS_CR_SWSYNC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1242 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1243 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
sahilmgandhi 18:6a4db94011d3 1244 #define CRS_CR_TRIM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1245 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
sahilmgandhi 18:6a4db94011d3 1246 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
sahilmgandhi 18:6a4db94011d3 1247
sahilmgandhi 18:6a4db94011d3 1248 /******************* Bit definition for CRS_CFGR register *********************/
sahilmgandhi 18:6a4db94011d3 1249 #define CRS_CFGR_RELOAD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1250 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1251 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
sahilmgandhi 18:6a4db94011d3 1252 #define CRS_CFGR_FELIM_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1253 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 1254 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
sahilmgandhi 18:6a4db94011d3 1255
sahilmgandhi 18:6a4db94011d3 1256 #define CRS_CFGR_SYNCDIV_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1257 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
sahilmgandhi 18:6a4db94011d3 1258 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
sahilmgandhi 18:6a4db94011d3 1259 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1260 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1261 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1262
sahilmgandhi 18:6a4db94011d3 1263 #define CRS_CFGR_SYNCSRC_Pos (28U)
sahilmgandhi 18:6a4db94011d3 1264 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 1265 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
sahilmgandhi 18:6a4db94011d3 1266 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1267 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1268
sahilmgandhi 18:6a4db94011d3 1269 #define CRS_CFGR_SYNCPOL_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1270 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1271 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
sahilmgandhi 18:6a4db94011d3 1272
sahilmgandhi 18:6a4db94011d3 1273 /******************* Bit definition for CRS_ISR register *********************/
sahilmgandhi 18:6a4db94011d3 1274 #define CRS_ISR_SYNCOKF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1275 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1276 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
sahilmgandhi 18:6a4db94011d3 1277 #define CRS_ISR_SYNCWARNF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1278 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1279 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
sahilmgandhi 18:6a4db94011d3 1280 #define CRS_ISR_ERRF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1281 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1282 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
sahilmgandhi 18:6a4db94011d3 1283 #define CRS_ISR_ESYNCF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1284 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1285 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
sahilmgandhi 18:6a4db94011d3 1286 #define CRS_ISR_SYNCERR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1287 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1288 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
sahilmgandhi 18:6a4db94011d3 1289 #define CRS_ISR_SYNCMISS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1290 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1291 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
sahilmgandhi 18:6a4db94011d3 1292 #define CRS_ISR_TRIMOVF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1293 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1294 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
sahilmgandhi 18:6a4db94011d3 1295 #define CRS_ISR_FEDIR_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1296 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1297 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
sahilmgandhi 18:6a4db94011d3 1298 #define CRS_ISR_FECAP_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1299 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 1300 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
sahilmgandhi 18:6a4db94011d3 1301
sahilmgandhi 18:6a4db94011d3 1302 /******************* Bit definition for CRS_ICR register *********************/
sahilmgandhi 18:6a4db94011d3 1303 #define CRS_ICR_SYNCOKC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1304 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1305 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
sahilmgandhi 18:6a4db94011d3 1306 #define CRS_ICR_SYNCWARNC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1307 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1308 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
sahilmgandhi 18:6a4db94011d3 1309 #define CRS_ICR_ERRC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1310 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1311 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
sahilmgandhi 18:6a4db94011d3 1312 #define CRS_ICR_ESYNCC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1313 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1314 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
sahilmgandhi 18:6a4db94011d3 1315
sahilmgandhi 18:6a4db94011d3 1316 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1317 /* */
sahilmgandhi 18:6a4db94011d3 1318 /* Digital to Analog Converter (DAC) */
sahilmgandhi 18:6a4db94011d3 1319 /* */
sahilmgandhi 18:6a4db94011d3 1320 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1321
sahilmgandhi 18:6a4db94011d3 1322 /*
sahilmgandhi 18:6a4db94011d3 1323 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
sahilmgandhi 18:6a4db94011d3 1324 */
sahilmgandhi 18:6a4db94011d3 1325 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
sahilmgandhi 18:6a4db94011d3 1326
sahilmgandhi 18:6a4db94011d3 1327 /******************** Bit definition for DAC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 1328 #define DAC_CR_EN1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1329 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1330 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
sahilmgandhi 18:6a4db94011d3 1331 #define DAC_CR_BOFF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1332 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1333 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
sahilmgandhi 18:6a4db94011d3 1334 #define DAC_CR_TEN1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1335 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1336 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
sahilmgandhi 18:6a4db94011d3 1337
sahilmgandhi 18:6a4db94011d3 1338 #define DAC_CR_TSEL1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1339 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 1340 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 1341 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1342 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1343 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1344
sahilmgandhi 18:6a4db94011d3 1345 #define DAC_CR_WAVE1_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1346 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 1347 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
sahilmgandhi 18:6a4db94011d3 1348 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1349 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1350
sahilmgandhi 18:6a4db94011d3 1351 #define DAC_CR_MAMP1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1352 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 1353 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
sahilmgandhi 18:6a4db94011d3 1354 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1355 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1356 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1357 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1358
sahilmgandhi 18:6a4db94011d3 1359 #define DAC_CR_DMAEN1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1360 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1361 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
sahilmgandhi 18:6a4db94011d3 1362 #define DAC_CR_DMAUDRIE1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1363 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1364 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 1365
sahilmgandhi 18:6a4db94011d3 1366 #define DAC_CR_EN2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1367 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1368 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
sahilmgandhi 18:6a4db94011d3 1369 #define DAC_CR_BOFF2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1370 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1371 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
sahilmgandhi 18:6a4db94011d3 1372 #define DAC_CR_TEN2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1373 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1374 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
sahilmgandhi 18:6a4db94011d3 1375
sahilmgandhi 18:6a4db94011d3 1376 #define DAC_CR_TSEL2_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1377 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
sahilmgandhi 18:6a4db94011d3 1378 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 1379 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1380 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1381 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1382
sahilmgandhi 18:6a4db94011d3 1383 #define DAC_CR_WAVE2_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1384 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 1385 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
sahilmgandhi 18:6a4db94011d3 1386 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1387 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1388
sahilmgandhi 18:6a4db94011d3 1389 #define DAC_CR_MAMP2_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1390 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 1391 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
sahilmgandhi 18:6a4db94011d3 1392 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1393 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1394 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1395 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 #define DAC_CR_DMAEN2_Pos (28U)
sahilmgandhi 18:6a4db94011d3 1398 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1399 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
sahilmgandhi 18:6a4db94011d3 1400 #define DAC_CR_DMAUDRIE2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 1401 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1402 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 1403
sahilmgandhi 18:6a4db94011d3 1404 /***************** Bit definition for DAC_SWTRIGR register ******************/
sahilmgandhi 18:6a4db94011d3 1405 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1406 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1407 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
sahilmgandhi 18:6a4db94011d3 1408 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1409 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1410 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
sahilmgandhi 18:6a4db94011d3 1411
sahilmgandhi 18:6a4db94011d3 1412 /***************** Bit definition for DAC_DHR12R1 register ******************/
sahilmgandhi 18:6a4db94011d3 1413 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1414 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1415 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1416
sahilmgandhi 18:6a4db94011d3 1417 /***************** Bit definition for DAC_DHR12L1 register ******************/
sahilmgandhi 18:6a4db94011d3 1418 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1419 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 1420 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 1421
sahilmgandhi 18:6a4db94011d3 1422 /****************** Bit definition for DAC_DHR8R1 register ******************/
sahilmgandhi 18:6a4db94011d3 1423 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1424 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 1425 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1426
sahilmgandhi 18:6a4db94011d3 1427 /***************** Bit definition for DAC_DHR12R2 register ******************/
sahilmgandhi 18:6a4db94011d3 1428 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1429 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1430 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1431
sahilmgandhi 18:6a4db94011d3 1432 /***************** Bit definition for DAC_DHR12L2 register ******************/
sahilmgandhi 18:6a4db94011d3 1433 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1434 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 1435 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 1436
sahilmgandhi 18:6a4db94011d3 1437 /****************** Bit definition for DAC_DHR8R2 register ******************/
sahilmgandhi 18:6a4db94011d3 1438 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1439 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 1440 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1441
sahilmgandhi 18:6a4db94011d3 1442 /***************** Bit definition for DAC_DHR12RD register ******************/
sahilmgandhi 18:6a4db94011d3 1443 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1444 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1445 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1446 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1447 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 1448 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1449
sahilmgandhi 18:6a4db94011d3 1450 /***************** Bit definition for DAC_DHR12LD register ******************/
sahilmgandhi 18:6a4db94011d3 1451 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1452 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 1453 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 1454 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1455 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
sahilmgandhi 18:6a4db94011d3 1456 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 1457
sahilmgandhi 18:6a4db94011d3 1458 /****************** Bit definition for DAC_DHR8RD register ******************/
sahilmgandhi 18:6a4db94011d3 1459 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1460 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 1461 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1462 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1463 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 1464 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1465
sahilmgandhi 18:6a4db94011d3 1466 /******************* Bit definition for DAC_DOR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1467 #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
sahilmgandhi 18:6a4db94011d3 1468
sahilmgandhi 18:6a4db94011d3 1469 /******************* Bit definition for DAC_DOR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1470 #define DAC_DOR2_DACC2DOR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1471 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1472 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
sahilmgandhi 18:6a4db94011d3 1473
sahilmgandhi 18:6a4db94011d3 1474 /******************** Bit definition for DAC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 1475 #define DAC_SR_DMAUDR1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1476 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1477 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 1478 #define DAC_SR_DMAUDR2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 1479 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1480 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 1481
sahilmgandhi 18:6a4db94011d3 1482 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1483 /* */
sahilmgandhi 18:6a4db94011d3 1484 /* Debug MCU (DBGMCU) */
sahilmgandhi 18:6a4db94011d3 1485 /* */
sahilmgandhi 18:6a4db94011d3 1486 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1487
sahilmgandhi 18:6a4db94011d3 1488 /**************** Bit definition for DBGMCU_IDCODE register *****************/
sahilmgandhi 18:6a4db94011d3 1489 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1490 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1491 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
sahilmgandhi 18:6a4db94011d3 1492
sahilmgandhi 18:6a4db94011d3 1493 #define DBGMCU_IDCODE_DIV_ID_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1494 #define DBGMCU_IDCODE_DIV_ID_Msk (0xFU << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 1495 #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */
sahilmgandhi 18:6a4db94011d3 1496 #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1497 #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3U << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 1498 #define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */
sahilmgandhi 18:6a4db94011d3 1499 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1500 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 1501 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
sahilmgandhi 18:6a4db94011d3 1502 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1503 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1504 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1505 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1506 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1507 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1508 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1509 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1510 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1511 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1512 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1513 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1514 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1515 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1516 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1517 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1518
sahilmgandhi 18:6a4db94011d3 1519 /****************** Bit definition for DBGMCU_CR register *******************/
sahilmgandhi 18:6a4db94011d3 1520 #define DBGMCU_CR_DBG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1521 #define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 1522 #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
sahilmgandhi 18:6a4db94011d3 1523 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1524 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1525 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
sahilmgandhi 18:6a4db94011d3 1526 #define DBGMCU_CR_DBG_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1527 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1528 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
sahilmgandhi 18:6a4db94011d3 1529 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1530 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1531 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
sahilmgandhi 18:6a4db94011d3 1532
sahilmgandhi 18:6a4db94011d3 1533 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
sahilmgandhi 18:6a4db94011d3 1534 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1535 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1536 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1537 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1538 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1539 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
sahilmgandhi 18:6a4db94011d3 1540 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1541 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1542 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1543 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1544 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1545 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
sahilmgandhi 18:6a4db94011d3 1546 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1547 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1548 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
sahilmgandhi 18:6a4db94011d3 1549 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1550 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1551 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1552 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1553 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1554 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1555 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1556 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1557 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1558 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1559 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1560 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1561 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1562 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1563 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1564 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1565 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1566 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1567 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
sahilmgandhi 18:6a4db94011d3 1568 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1569 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1570 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1571 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1572 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1573 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1574
sahilmgandhi 18:6a4db94011d3 1575 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1576 /* */
sahilmgandhi 18:6a4db94011d3 1577 /* DMA Controller (DMA) */
sahilmgandhi 18:6a4db94011d3 1578 /* */
sahilmgandhi 18:6a4db94011d3 1579 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1580
sahilmgandhi 18:6a4db94011d3 1581 /******************* Bit definition for DMA_ISR register ********************/
sahilmgandhi 18:6a4db94011d3 1582 #define DMA_ISR_GIF1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1583 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1584 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1585 #define DMA_ISR_TCIF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1586 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1587 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1588 #define DMA_ISR_HTIF1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1589 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1590 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1591 #define DMA_ISR_TEIF1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1592 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1593 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1594 #define DMA_ISR_GIF2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1595 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1596 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1597 #define DMA_ISR_TCIF2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1598 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1599 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1600 #define DMA_ISR_HTIF2_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1601 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1602 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1603 #define DMA_ISR_TEIF2_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1604 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1605 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1606 #define DMA_ISR_GIF3_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1607 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1608 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1609 #define DMA_ISR_TCIF3_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1610 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1611 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1612 #define DMA_ISR_HTIF3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1613 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1614 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1615 #define DMA_ISR_TEIF3_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1616 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1617 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1618 #define DMA_ISR_GIF4_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1619 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1620 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1621 #define DMA_ISR_TCIF4_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1622 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1623 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1624 #define DMA_ISR_HTIF4_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1625 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1626 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1627 #define DMA_ISR_TEIF4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1628 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1629 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1630 #define DMA_ISR_GIF5_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1631 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1632 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1633 #define DMA_ISR_TCIF5_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1634 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1635 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1636 #define DMA_ISR_HTIF5_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1637 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1638 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1639 #define DMA_ISR_TEIF5_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1640 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1641 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1642 #define DMA_ISR_GIF6_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1643 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1644 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1645 #define DMA_ISR_TCIF6_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1646 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1647 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1648 #define DMA_ISR_HTIF6_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1649 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1650 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1651 #define DMA_ISR_TEIF6_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1652 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1653 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1654 #define DMA_ISR_GIF7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1655 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1656 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1657 #define DMA_ISR_TCIF7_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1658 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1659 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1660 #define DMA_ISR_HTIF7_Pos (26U)
sahilmgandhi 18:6a4db94011d3 1661 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1662 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1663 #define DMA_ISR_TEIF7_Pos (27U)
sahilmgandhi 18:6a4db94011d3 1664 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1665 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1666
sahilmgandhi 18:6a4db94011d3 1667 /******************* Bit definition for DMA_IFCR register *******************/
sahilmgandhi 18:6a4db94011d3 1668 #define DMA_IFCR_CGIF1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1669 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1670 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1671 #define DMA_IFCR_CTCIF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1672 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1673 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1674 #define DMA_IFCR_CHTIF1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1675 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1676 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1677 #define DMA_IFCR_CTEIF1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1678 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1679 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1680 #define DMA_IFCR_CGIF2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1681 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1682 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1683 #define DMA_IFCR_CTCIF2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1684 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1685 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1686 #define DMA_IFCR_CHTIF2_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1687 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1688 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1689 #define DMA_IFCR_CTEIF2_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1690 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1691 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1692 #define DMA_IFCR_CGIF3_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1693 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1694 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1695 #define DMA_IFCR_CTCIF3_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1696 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1697 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1698 #define DMA_IFCR_CHTIF3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1699 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1700 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1701 #define DMA_IFCR_CTEIF3_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1702 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1703 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1704 #define DMA_IFCR_CGIF4_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1705 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1706 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1707 #define DMA_IFCR_CTCIF4_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1708 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1709 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1710 #define DMA_IFCR_CHTIF4_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1711 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1712 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1713 #define DMA_IFCR_CTEIF4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1714 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1715 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1716 #define DMA_IFCR_CGIF5_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1717 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1718 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1719 #define DMA_IFCR_CTCIF5_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1720 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1721 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1722 #define DMA_IFCR_CHTIF5_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1723 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1724 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1725 #define DMA_IFCR_CTEIF5_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1726 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1727 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1728 #define DMA_IFCR_CGIF6_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1729 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1730 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1731 #define DMA_IFCR_CTCIF6_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1732 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1733 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1734 #define DMA_IFCR_CHTIF6_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1735 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1736 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1737 #define DMA_IFCR_CTEIF6_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1738 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1739 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1740 #define DMA_IFCR_CGIF7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1741 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1742 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1743 #define DMA_IFCR_CTCIF7_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1744 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1745 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1746 #define DMA_IFCR_CHTIF7_Pos (26U)
sahilmgandhi 18:6a4db94011d3 1747 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1748 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1749 #define DMA_IFCR_CTEIF7_Pos (27U)
sahilmgandhi 18:6a4db94011d3 1750 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1751 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1752
sahilmgandhi 18:6a4db94011d3 1753 /******************* Bit definition for DMA_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 1754 #define DMA_CCR_EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1755 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1756 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
sahilmgandhi 18:6a4db94011d3 1757 #define DMA_CCR_TCIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1758 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1759 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
sahilmgandhi 18:6a4db94011d3 1760 #define DMA_CCR_HTIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1761 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1762 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
sahilmgandhi 18:6a4db94011d3 1763 #define DMA_CCR_TEIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1764 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1765 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
sahilmgandhi 18:6a4db94011d3 1766 #define DMA_CCR_DIR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1767 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1768 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
sahilmgandhi 18:6a4db94011d3 1769 #define DMA_CCR_CIRC_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1770 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1771 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
sahilmgandhi 18:6a4db94011d3 1772 #define DMA_CCR_PINC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1773 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1774 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
sahilmgandhi 18:6a4db94011d3 1775 #define DMA_CCR_MINC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1776 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1777 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
sahilmgandhi 18:6a4db94011d3 1778
sahilmgandhi 18:6a4db94011d3 1779 #define DMA_CCR_PSIZE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1780 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 1781 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
sahilmgandhi 18:6a4db94011d3 1782 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1783 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1784
sahilmgandhi 18:6a4db94011d3 1785 #define DMA_CCR_MSIZE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1786 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 1787 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
sahilmgandhi 18:6a4db94011d3 1788 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1789 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1790
sahilmgandhi 18:6a4db94011d3 1791 #define DMA_CCR_PL_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1792 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 1793 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
sahilmgandhi 18:6a4db94011d3 1794 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1795 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1796
sahilmgandhi 18:6a4db94011d3 1797 #define DMA_CCR_MEM2MEM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1798 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1799 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
sahilmgandhi 18:6a4db94011d3 1800
sahilmgandhi 18:6a4db94011d3 1801 /****************** Bit definition for DMA_CNDTR register *******************/
sahilmgandhi 18:6a4db94011d3 1802 #define DMA_CNDTR_NDT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1803 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1804 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
sahilmgandhi 18:6a4db94011d3 1805
sahilmgandhi 18:6a4db94011d3 1806 /****************** Bit definition for DMA_CPAR register ********************/
sahilmgandhi 18:6a4db94011d3 1807 #define DMA_CPAR_PA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1808 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1809 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
sahilmgandhi 18:6a4db94011d3 1810
sahilmgandhi 18:6a4db94011d3 1811 /****************** Bit definition for DMA_CMAR register ********************/
sahilmgandhi 18:6a4db94011d3 1812 #define DMA_CMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1813 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1814 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 1815
sahilmgandhi 18:6a4db94011d3 1816
sahilmgandhi 18:6a4db94011d3 1817 /******************* Bit definition for DMA_CSELR register *******************/
sahilmgandhi 18:6a4db94011d3 1818 #define DMA_CSELR_C1S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1819 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 1820 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
sahilmgandhi 18:6a4db94011d3 1821 #define DMA_CSELR_C2S_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1822 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 1823 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
sahilmgandhi 18:6a4db94011d3 1824 #define DMA_CSELR_C3S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1825 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 1826 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
sahilmgandhi 18:6a4db94011d3 1827 #define DMA_CSELR_C4S_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1828 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 1829 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
sahilmgandhi 18:6a4db94011d3 1830 #define DMA_CSELR_C5S_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1831 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 1832 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
sahilmgandhi 18:6a4db94011d3 1833 #define DMA_CSELR_C6S_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1834 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 1835 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
sahilmgandhi 18:6a4db94011d3 1836 #define DMA_CSELR_C7S_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1837 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 1838 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
sahilmgandhi 18:6a4db94011d3 1839
sahilmgandhi 18:6a4db94011d3 1840 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1841 /* */
sahilmgandhi 18:6a4db94011d3 1842 /* External Interrupt/Event Controller (EXTI) */
sahilmgandhi 18:6a4db94011d3 1843 /* */
sahilmgandhi 18:6a4db94011d3 1844 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1845
sahilmgandhi 18:6a4db94011d3 1846 /******************* Bit definition for EXTI_IMR register *******************/
sahilmgandhi 18:6a4db94011d3 1847 #define EXTI_IMR_IM0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1848 #define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1849 #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 1850 #define EXTI_IMR_IM1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1851 #define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1852 #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 1853 #define EXTI_IMR_IM2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1854 #define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1855 #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 1856 #define EXTI_IMR_IM3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1857 #define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1858 #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 1859 #define EXTI_IMR_IM4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1860 #define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1861 #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 1862 #define EXTI_IMR_IM5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1863 #define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1864 #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 1865 #define EXTI_IMR_IM6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1866 #define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1867 #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 1868 #define EXTI_IMR_IM7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1869 #define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1870 #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 1871 #define EXTI_IMR_IM8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1872 #define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1873 #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 1874 #define EXTI_IMR_IM9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1875 #define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1876 #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 1877 #define EXTI_IMR_IM10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1878 #define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1879 #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 1880 #define EXTI_IMR_IM11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1881 #define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1882 #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 1883 #define EXTI_IMR_IM12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1884 #define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1885 #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 1886 #define EXTI_IMR_IM13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1887 #define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1888 #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 1889 #define EXTI_IMR_IM14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1890 #define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1891 #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 1892 #define EXTI_IMR_IM15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1893 #define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1894 #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 1895 #define EXTI_IMR_IM16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1896 #define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1897 #define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 1898 #define EXTI_IMR_IM17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1899 #define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1900 #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 1901 #define EXTI_IMR_IM18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1902 #define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1903 #define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 1904 #define EXTI_IMR_IM19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1905 #define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1906 #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 1907 #define EXTI_IMR_IM20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1908 #define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1909 #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 1910 #define EXTI_IMR_IM21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1911 #define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1912 #define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 1913 #define EXTI_IMR_IM22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1914 #define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1915 #define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 1916 #define EXTI_IMR_IM23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1917 #define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1918 #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
sahilmgandhi 18:6a4db94011d3 1919 #define EXTI_IMR_IM24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1920 #define EXTI_IMR_IM24_Msk (0x1U << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1921 #define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
sahilmgandhi 18:6a4db94011d3 1922 #define EXTI_IMR_IM25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1923 #define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1924 #define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
sahilmgandhi 18:6a4db94011d3 1925 #define EXTI_IMR_IM26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 1926 #define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1927 #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
sahilmgandhi 18:6a4db94011d3 1928 #define EXTI_IMR_IM28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 1929 #define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1930 #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
sahilmgandhi 18:6a4db94011d3 1931 #define EXTI_IMR_IM29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 1932 #define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1933 #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
sahilmgandhi 18:6a4db94011d3 1934
sahilmgandhi 18:6a4db94011d3 1935 #define EXTI_IMR_IM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1936 #define EXTI_IMR_IM_Msk (0x37FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
sahilmgandhi 18:6a4db94011d3 1937 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
sahilmgandhi 18:6a4db94011d3 1938
sahilmgandhi 18:6a4db94011d3 1939 /****************** Bit definition for EXTI_EMR register ********************/
sahilmgandhi 18:6a4db94011d3 1940 #define EXTI_EMR_EM0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1941 #define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1942 #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 1943 #define EXTI_EMR_EM1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1944 #define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1945 #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 1946 #define EXTI_EMR_EM2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1947 #define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1948 #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 1949 #define EXTI_EMR_EM3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1950 #define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1951 #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 1952 #define EXTI_EMR_EM4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1953 #define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1954 #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 1955 #define EXTI_EMR_EM5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1956 #define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1957 #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 1958 #define EXTI_EMR_EM6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1959 #define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1960 #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 1961 #define EXTI_EMR_EM7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1962 #define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1963 #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 1964 #define EXTI_EMR_EM8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1965 #define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1966 #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 1967 #define EXTI_EMR_EM9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1968 #define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1969 #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 1970 #define EXTI_EMR_EM10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1971 #define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1972 #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 1973 #define EXTI_EMR_EM11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1974 #define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1975 #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 1976 #define EXTI_EMR_EM12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1977 #define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1978 #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 1979 #define EXTI_EMR_EM13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1980 #define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1981 #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 1982 #define EXTI_EMR_EM14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1983 #define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1984 #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 1985 #define EXTI_EMR_EM15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1986 #define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1987 #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 1988 #define EXTI_EMR_EM16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1989 #define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1990 #define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 1991 #define EXTI_EMR_EM17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1992 #define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1993 #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 1994 #define EXTI_EMR_EM18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1995 #define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1996 #define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 1997 #define EXTI_EMR_EM19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1998 #define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1999 #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 2000 #define EXTI_EMR_EM20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2001 #define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2002 #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 2003 #define EXTI_EMR_EM21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2004 #define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2005 #define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 2006 #define EXTI_EMR_EM22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2007 #define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2008 #define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 2009 #define EXTI_EMR_EM23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2010 #define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2011 #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
sahilmgandhi 18:6a4db94011d3 2012 #define EXTI_EMR_EM24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2013 #define EXTI_EMR_EM24_Msk (0x1U << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2014 #define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
sahilmgandhi 18:6a4db94011d3 2015 #define EXTI_EMR_EM25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2016 #define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2017 #define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
sahilmgandhi 18:6a4db94011d3 2018 #define EXTI_EMR_EM26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2019 #define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2020 #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
sahilmgandhi 18:6a4db94011d3 2021 #define EXTI_EMR_EM28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2022 #define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2023 #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
sahilmgandhi 18:6a4db94011d3 2024 #define EXTI_EMR_EM29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 2025 #define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2026 #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
sahilmgandhi 18:6a4db94011d3 2027
sahilmgandhi 18:6a4db94011d3 2028 /******************* Bit definition for EXTI_RTSR register ******************/
sahilmgandhi 18:6a4db94011d3 2029 #define EXTI_RTSR_RT0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2030 #define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2031 #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 2032 #define EXTI_RTSR_RT1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2033 #define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2034 #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 2035 #define EXTI_RTSR_RT2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2036 #define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2037 #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 2038 #define EXTI_RTSR_RT3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2039 #define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2040 #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 2041 #define EXTI_RTSR_RT4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2042 #define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2043 #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 2044 #define EXTI_RTSR_RT5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2045 #define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2046 #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 2047 #define EXTI_RTSR_RT6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2048 #define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2049 #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 2050 #define EXTI_RTSR_RT7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2051 #define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2052 #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 2053 #define EXTI_RTSR_RT8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2054 #define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2055 #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 2056 #define EXTI_RTSR_RT9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2057 #define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2058 #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 2059 #define EXTI_RTSR_RT10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2060 #define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2061 #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 2062 #define EXTI_RTSR_RT11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2063 #define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2064 #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 2065 #define EXTI_RTSR_RT12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2066 #define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2067 #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 2068 #define EXTI_RTSR_RT13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2069 #define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2070 #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 2071 #define EXTI_RTSR_RT14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2072 #define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2073 #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 2074 #define EXTI_RTSR_RT15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2075 #define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2076 #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 2077 #define EXTI_RTSR_RT16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2078 #define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2079 #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 2080 #define EXTI_RTSR_RT17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2081 #define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2082 #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 2083 #define EXTI_RTSR_RT19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2084 #define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2085 #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 2086 #define EXTI_RTSR_RT20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2087 #define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2088 #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 2089 #define EXTI_RTSR_RT21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2090 #define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2091 #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 2092 #define EXTI_RTSR_RT22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2093 #define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2094 #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 2095
sahilmgandhi 18:6a4db94011d3 2096 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 2097 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0
sahilmgandhi 18:6a4db94011d3 2098 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1
sahilmgandhi 18:6a4db94011d3 2099 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2
sahilmgandhi 18:6a4db94011d3 2100 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3
sahilmgandhi 18:6a4db94011d3 2101 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4
sahilmgandhi 18:6a4db94011d3 2102 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5
sahilmgandhi 18:6a4db94011d3 2103 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6
sahilmgandhi 18:6a4db94011d3 2104 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7
sahilmgandhi 18:6a4db94011d3 2105 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8
sahilmgandhi 18:6a4db94011d3 2106 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9
sahilmgandhi 18:6a4db94011d3 2107 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10
sahilmgandhi 18:6a4db94011d3 2108 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11
sahilmgandhi 18:6a4db94011d3 2109 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12
sahilmgandhi 18:6a4db94011d3 2110 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13
sahilmgandhi 18:6a4db94011d3 2111 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14
sahilmgandhi 18:6a4db94011d3 2112 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15
sahilmgandhi 18:6a4db94011d3 2113 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16
sahilmgandhi 18:6a4db94011d3 2114 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17
sahilmgandhi 18:6a4db94011d3 2115 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19
sahilmgandhi 18:6a4db94011d3 2116 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20
sahilmgandhi 18:6a4db94011d3 2117 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21
sahilmgandhi 18:6a4db94011d3 2118 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22
sahilmgandhi 18:6a4db94011d3 2119
sahilmgandhi 18:6a4db94011d3 2120 /******************* Bit definition for EXTI_FTSR register *******************/
sahilmgandhi 18:6a4db94011d3 2121 #define EXTI_FTSR_FT0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2122 #define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2123 #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 2124 #define EXTI_FTSR_FT1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2125 #define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2126 #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 2127 #define EXTI_FTSR_FT2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2128 #define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2129 #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 2130 #define EXTI_FTSR_FT3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2131 #define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2132 #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 2133 #define EXTI_FTSR_FT4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2134 #define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2135 #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 2136 #define EXTI_FTSR_FT5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2137 #define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2138 #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 2139 #define EXTI_FTSR_FT6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2140 #define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2141 #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 2142 #define EXTI_FTSR_FT7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2143 #define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2144 #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 2145 #define EXTI_FTSR_FT8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2146 #define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2147 #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 2148 #define EXTI_FTSR_FT9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2149 #define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2150 #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 2151 #define EXTI_FTSR_FT10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2152 #define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2153 #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 2154 #define EXTI_FTSR_FT11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2155 #define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2156 #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 2157 #define EXTI_FTSR_FT12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2158 #define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2159 #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 2160 #define EXTI_FTSR_FT13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2161 #define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2162 #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 2163 #define EXTI_FTSR_FT14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2164 #define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2165 #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 2166 #define EXTI_FTSR_FT15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2167 #define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2168 #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 2169 #define EXTI_FTSR_FT16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2170 #define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2171 #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 2172 #define EXTI_FTSR_FT17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2173 #define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2174 #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 2175 #define EXTI_FTSR_FT19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2176 #define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2177 #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 2178 #define EXTI_FTSR_FT20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2179 #define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2180 #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 2181 #define EXTI_FTSR_FT21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2182 #define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2183 #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 2184 #define EXTI_FTSR_FT22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2185 #define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2186 #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 2187
sahilmgandhi 18:6a4db94011d3 2188 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 2189 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0
sahilmgandhi 18:6a4db94011d3 2190 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1
sahilmgandhi 18:6a4db94011d3 2191 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2
sahilmgandhi 18:6a4db94011d3 2192 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3
sahilmgandhi 18:6a4db94011d3 2193 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4
sahilmgandhi 18:6a4db94011d3 2194 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5
sahilmgandhi 18:6a4db94011d3 2195 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6
sahilmgandhi 18:6a4db94011d3 2196 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7
sahilmgandhi 18:6a4db94011d3 2197 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8
sahilmgandhi 18:6a4db94011d3 2198 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9
sahilmgandhi 18:6a4db94011d3 2199 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10
sahilmgandhi 18:6a4db94011d3 2200 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11
sahilmgandhi 18:6a4db94011d3 2201 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12
sahilmgandhi 18:6a4db94011d3 2202 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13
sahilmgandhi 18:6a4db94011d3 2203 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14
sahilmgandhi 18:6a4db94011d3 2204 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15
sahilmgandhi 18:6a4db94011d3 2205 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16
sahilmgandhi 18:6a4db94011d3 2206 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17
sahilmgandhi 18:6a4db94011d3 2207 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19
sahilmgandhi 18:6a4db94011d3 2208 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20
sahilmgandhi 18:6a4db94011d3 2209 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21
sahilmgandhi 18:6a4db94011d3 2210 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22
sahilmgandhi 18:6a4db94011d3 2211
sahilmgandhi 18:6a4db94011d3 2212 /******************* Bit definition for EXTI_SWIER register *******************/
sahilmgandhi 18:6a4db94011d3 2213 #define EXTI_SWIER_SWI0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2214 #define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2215 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
sahilmgandhi 18:6a4db94011d3 2216 #define EXTI_SWIER_SWI1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2217 #define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2218 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
sahilmgandhi 18:6a4db94011d3 2219 #define EXTI_SWIER_SWI2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2220 #define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2221 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
sahilmgandhi 18:6a4db94011d3 2222 #define EXTI_SWIER_SWI3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2223 #define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2224 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
sahilmgandhi 18:6a4db94011d3 2225 #define EXTI_SWIER_SWI4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2226 #define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2227 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
sahilmgandhi 18:6a4db94011d3 2228 #define EXTI_SWIER_SWI5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2229 #define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2230 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
sahilmgandhi 18:6a4db94011d3 2231 #define EXTI_SWIER_SWI6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2232 #define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2233 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
sahilmgandhi 18:6a4db94011d3 2234 #define EXTI_SWIER_SWI7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2235 #define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2236 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
sahilmgandhi 18:6a4db94011d3 2237 #define EXTI_SWIER_SWI8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2238 #define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2239 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
sahilmgandhi 18:6a4db94011d3 2240 #define EXTI_SWIER_SWI9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2241 #define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2242 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
sahilmgandhi 18:6a4db94011d3 2243 #define EXTI_SWIER_SWI10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2244 #define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2245 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
sahilmgandhi 18:6a4db94011d3 2246 #define EXTI_SWIER_SWI11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2247 #define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2248 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
sahilmgandhi 18:6a4db94011d3 2249 #define EXTI_SWIER_SWI12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2250 #define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2251 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
sahilmgandhi 18:6a4db94011d3 2252 #define EXTI_SWIER_SWI13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2253 #define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2254 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
sahilmgandhi 18:6a4db94011d3 2255 #define EXTI_SWIER_SWI14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2256 #define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2257 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
sahilmgandhi 18:6a4db94011d3 2258 #define EXTI_SWIER_SWI15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2259 #define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2260 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
sahilmgandhi 18:6a4db94011d3 2261 #define EXTI_SWIER_SWI16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2262 #define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2263 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
sahilmgandhi 18:6a4db94011d3 2264 #define EXTI_SWIER_SWI17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2265 #define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2266 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
sahilmgandhi 18:6a4db94011d3 2267 #define EXTI_SWIER_SWI19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2268 #define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2269 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
sahilmgandhi 18:6a4db94011d3 2270 #define EXTI_SWIER_SWI20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2271 #define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2272 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
sahilmgandhi 18:6a4db94011d3 2273 #define EXTI_SWIER_SWI21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2274 #define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2275 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
sahilmgandhi 18:6a4db94011d3 2276 #define EXTI_SWIER_SWI22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2277 #define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2278 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
sahilmgandhi 18:6a4db94011d3 2279
sahilmgandhi 18:6a4db94011d3 2280 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 2281 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
sahilmgandhi 18:6a4db94011d3 2282 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
sahilmgandhi 18:6a4db94011d3 2283 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
sahilmgandhi 18:6a4db94011d3 2284 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
sahilmgandhi 18:6a4db94011d3 2285 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
sahilmgandhi 18:6a4db94011d3 2286 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
sahilmgandhi 18:6a4db94011d3 2287 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
sahilmgandhi 18:6a4db94011d3 2288 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
sahilmgandhi 18:6a4db94011d3 2289 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
sahilmgandhi 18:6a4db94011d3 2290 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
sahilmgandhi 18:6a4db94011d3 2291 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
sahilmgandhi 18:6a4db94011d3 2292 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
sahilmgandhi 18:6a4db94011d3 2293 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
sahilmgandhi 18:6a4db94011d3 2294 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
sahilmgandhi 18:6a4db94011d3 2295 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
sahilmgandhi 18:6a4db94011d3 2296 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
sahilmgandhi 18:6a4db94011d3 2297 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
sahilmgandhi 18:6a4db94011d3 2298 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
sahilmgandhi 18:6a4db94011d3 2299 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
sahilmgandhi 18:6a4db94011d3 2300 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
sahilmgandhi 18:6a4db94011d3 2301 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
sahilmgandhi 18:6a4db94011d3 2302 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
sahilmgandhi 18:6a4db94011d3 2303
sahilmgandhi 18:6a4db94011d3 2304 /****************** Bit definition for EXTI_PR register *********************/
sahilmgandhi 18:6a4db94011d3 2305 #define EXTI_PR_PIF0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2306 #define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2307 #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
sahilmgandhi 18:6a4db94011d3 2308 #define EXTI_PR_PIF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2309 #define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2310 #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
sahilmgandhi 18:6a4db94011d3 2311 #define EXTI_PR_PIF2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2312 #define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2313 #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
sahilmgandhi 18:6a4db94011d3 2314 #define EXTI_PR_PIF3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2315 #define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2316 #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
sahilmgandhi 18:6a4db94011d3 2317 #define EXTI_PR_PIF4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2318 #define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2319 #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
sahilmgandhi 18:6a4db94011d3 2320 #define EXTI_PR_PIF5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2321 #define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2322 #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
sahilmgandhi 18:6a4db94011d3 2323 #define EXTI_PR_PIF6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2324 #define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2325 #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
sahilmgandhi 18:6a4db94011d3 2326 #define EXTI_PR_PIF7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2327 #define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2328 #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
sahilmgandhi 18:6a4db94011d3 2329 #define EXTI_PR_PIF8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2330 #define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2331 #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
sahilmgandhi 18:6a4db94011d3 2332 #define EXTI_PR_PIF9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2333 #define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2334 #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
sahilmgandhi 18:6a4db94011d3 2335 #define EXTI_PR_PIF10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2336 #define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2337 #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
sahilmgandhi 18:6a4db94011d3 2338 #define EXTI_PR_PIF11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2339 #define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2340 #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
sahilmgandhi 18:6a4db94011d3 2341 #define EXTI_PR_PIF12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2342 #define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2343 #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
sahilmgandhi 18:6a4db94011d3 2344 #define EXTI_PR_PIF13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2345 #define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2346 #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
sahilmgandhi 18:6a4db94011d3 2347 #define EXTI_PR_PIF14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2348 #define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2349 #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
sahilmgandhi 18:6a4db94011d3 2350 #define EXTI_PR_PIF15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2351 #define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2352 #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
sahilmgandhi 18:6a4db94011d3 2353 #define EXTI_PR_PIF16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2354 #define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2355 #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
sahilmgandhi 18:6a4db94011d3 2356 #define EXTI_PR_PIF17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2357 #define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2358 #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
sahilmgandhi 18:6a4db94011d3 2359 #define EXTI_PR_PIF19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2360 #define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2361 #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
sahilmgandhi 18:6a4db94011d3 2362 #define EXTI_PR_PIF20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2363 #define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2364 #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
sahilmgandhi 18:6a4db94011d3 2365 #define EXTI_PR_PIF21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2366 #define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2367 #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
sahilmgandhi 18:6a4db94011d3 2368 #define EXTI_PR_PIF22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2369 #define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2370 #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
sahilmgandhi 18:6a4db94011d3 2371
sahilmgandhi 18:6a4db94011d3 2372 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 2373 #define EXTI_PR_PR0 EXTI_PR_PIF0
sahilmgandhi 18:6a4db94011d3 2374 #define EXTI_PR_PR1 EXTI_PR_PIF1
sahilmgandhi 18:6a4db94011d3 2375 #define EXTI_PR_PR2 EXTI_PR_PIF2
sahilmgandhi 18:6a4db94011d3 2376 #define EXTI_PR_PR3 EXTI_PR_PIF3
sahilmgandhi 18:6a4db94011d3 2377 #define EXTI_PR_PR4 EXTI_PR_PIF4
sahilmgandhi 18:6a4db94011d3 2378 #define EXTI_PR_PR5 EXTI_PR_PIF5
sahilmgandhi 18:6a4db94011d3 2379 #define EXTI_PR_PR6 EXTI_PR_PIF6
sahilmgandhi 18:6a4db94011d3 2380 #define EXTI_PR_PR7 EXTI_PR_PIF7
sahilmgandhi 18:6a4db94011d3 2381 #define EXTI_PR_PR8 EXTI_PR_PIF8
sahilmgandhi 18:6a4db94011d3 2382 #define EXTI_PR_PR9 EXTI_PR_PIF9
sahilmgandhi 18:6a4db94011d3 2383 #define EXTI_PR_PR10 EXTI_PR_PIF10
sahilmgandhi 18:6a4db94011d3 2384 #define EXTI_PR_PR11 EXTI_PR_PIF11
sahilmgandhi 18:6a4db94011d3 2385 #define EXTI_PR_PR12 EXTI_PR_PIF12
sahilmgandhi 18:6a4db94011d3 2386 #define EXTI_PR_PR13 EXTI_PR_PIF13
sahilmgandhi 18:6a4db94011d3 2387 #define EXTI_PR_PR14 EXTI_PR_PIF14
sahilmgandhi 18:6a4db94011d3 2388 #define EXTI_PR_PR15 EXTI_PR_PIF15
sahilmgandhi 18:6a4db94011d3 2389 #define EXTI_PR_PR16 EXTI_PR_PIF16
sahilmgandhi 18:6a4db94011d3 2390 #define EXTI_PR_PR17 EXTI_PR_PIF17
sahilmgandhi 18:6a4db94011d3 2391 #define EXTI_PR_PR19 EXTI_PR_PIF19
sahilmgandhi 18:6a4db94011d3 2392 #define EXTI_PR_PR20 EXTI_PR_PIF20
sahilmgandhi 18:6a4db94011d3 2393 #define EXTI_PR_PR21 EXTI_PR_PIF21
sahilmgandhi 18:6a4db94011d3 2394 #define EXTI_PR_PR22 EXTI_PR_PIF22
sahilmgandhi 18:6a4db94011d3 2395
sahilmgandhi 18:6a4db94011d3 2396 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2397 /* */
sahilmgandhi 18:6a4db94011d3 2398 /* FLASH and Option Bytes Registers */
sahilmgandhi 18:6a4db94011d3 2399 /* */
sahilmgandhi 18:6a4db94011d3 2400 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2401
sahilmgandhi 18:6a4db94011d3 2402 /******************* Bit definition for FLASH_ACR register ******************/
sahilmgandhi 18:6a4db94011d3 2403 #define FLASH_ACR_LATENCY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2404 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2405 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
sahilmgandhi 18:6a4db94011d3 2406 #define FLASH_ACR_PRFTEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2407 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2408 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
sahilmgandhi 18:6a4db94011d3 2409 #define FLASH_ACR_SLEEP_PD_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2410 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2411 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
sahilmgandhi 18:6a4db94011d3 2412 #define FLASH_ACR_RUN_PD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2413 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2414 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
sahilmgandhi 18:6a4db94011d3 2415 #define FLASH_ACR_DISAB_BUF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2416 #define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2417 #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
sahilmgandhi 18:6a4db94011d3 2418 #define FLASH_ACR_PRE_READ_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2419 #define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2420 #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
sahilmgandhi 18:6a4db94011d3 2421
sahilmgandhi 18:6a4db94011d3 2422 /******************* Bit definition for FLASH_PECR register ******************/
sahilmgandhi 18:6a4db94011d3 2423 #define FLASH_PECR_PELOCK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2424 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2425 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
sahilmgandhi 18:6a4db94011d3 2426 #define FLASH_PECR_PRGLOCK_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2427 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2428 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
sahilmgandhi 18:6a4db94011d3 2429 #define FLASH_PECR_OPTLOCK_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2430 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2431 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
sahilmgandhi 18:6a4db94011d3 2432 #define FLASH_PECR_PROG_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2433 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2434 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
sahilmgandhi 18:6a4db94011d3 2435 #define FLASH_PECR_DATA_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2436 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2437 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
sahilmgandhi 18:6a4db94011d3 2438 #define FLASH_PECR_FIX_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2439 #define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2440 #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
sahilmgandhi 18:6a4db94011d3 2441 #define FLASH_PECR_ERASE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2442 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2443 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
sahilmgandhi 18:6a4db94011d3 2444 #define FLASH_PECR_FPRG_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2445 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2446 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
sahilmgandhi 18:6a4db94011d3 2447 #define FLASH_PECR_PARALLBANK_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2448 #define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2449 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
sahilmgandhi 18:6a4db94011d3 2450 #define FLASH_PECR_EOPIE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2451 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2452 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
sahilmgandhi 18:6a4db94011d3 2453 #define FLASH_PECR_ERRIE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2454 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2455 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
sahilmgandhi 18:6a4db94011d3 2456 #define FLASH_PECR_OBL_LAUNCH_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2457 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2458 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
sahilmgandhi 18:6a4db94011d3 2459 #define FLASH_PECR_HALF_ARRAY_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2460 #define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2461 #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
sahilmgandhi 18:6a4db94011d3 2462 #define FLASH_PECR_NZDISABLE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2463 #define FLASH_PECR_NZDISABLE_Msk (0x1U << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2464 #define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
sahilmgandhi 18:6a4db94011d3 2465
sahilmgandhi 18:6a4db94011d3 2466 /****************** Bit definition for FLASH_PDKEYR register ******************/
sahilmgandhi 18:6a4db94011d3 2467 #define FLASH_PDKEYR_PDKEYR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2468 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2469 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
sahilmgandhi 18:6a4db94011d3 2470
sahilmgandhi 18:6a4db94011d3 2471 /****************** Bit definition for FLASH_PEKEYR register ******************/
sahilmgandhi 18:6a4db94011d3 2472 #define FLASH_PEKEYR_PEKEYR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2473 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2474 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
sahilmgandhi 18:6a4db94011d3 2475
sahilmgandhi 18:6a4db94011d3 2476 /****************** Bit definition for FLASH_PRGKEYR register ******************/
sahilmgandhi 18:6a4db94011d3 2477 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2478 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2479 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
sahilmgandhi 18:6a4db94011d3 2480
sahilmgandhi 18:6a4db94011d3 2481 /****************** Bit definition for FLASH_OPTKEYR register ******************/
sahilmgandhi 18:6a4db94011d3 2482 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2483 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2484 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
sahilmgandhi 18:6a4db94011d3 2485
sahilmgandhi 18:6a4db94011d3 2486 /****************** Bit definition for FLASH_SR register *******************/
sahilmgandhi 18:6a4db94011d3 2487 #define FLASH_SR_BSY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2488 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2489 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
sahilmgandhi 18:6a4db94011d3 2490 #define FLASH_SR_EOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2491 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2492 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
sahilmgandhi 18:6a4db94011d3 2493 #define FLASH_SR_HVOFF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2494 #define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2495 #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
sahilmgandhi 18:6a4db94011d3 2496 #define FLASH_SR_READY_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2497 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2498 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
sahilmgandhi 18:6a4db94011d3 2499
sahilmgandhi 18:6a4db94011d3 2500 #define FLASH_SR_WRPERR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2501 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2502 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
sahilmgandhi 18:6a4db94011d3 2503 #define FLASH_SR_PGAERR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2504 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2505 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
sahilmgandhi 18:6a4db94011d3 2506 #define FLASH_SR_SIZERR_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2507 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2508 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
sahilmgandhi 18:6a4db94011d3 2509 #define FLASH_SR_OPTVERR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2510 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2511 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
sahilmgandhi 18:6a4db94011d3 2512 #define FLASH_SR_RDERR_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2513 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2514 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
sahilmgandhi 18:6a4db94011d3 2515 #define FLASH_SR_NOTZEROERR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2516 #define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2517 #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
sahilmgandhi 18:6a4db94011d3 2518 #define FLASH_SR_FWWERR_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2519 #define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2520 #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
sahilmgandhi 18:6a4db94011d3 2521
sahilmgandhi 18:6a4db94011d3 2522 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 2523 #define FLASH_SR_FWWER FLASH_SR_FWWERR
sahilmgandhi 18:6a4db94011d3 2524 #define FLASH_SR_ENHV FLASH_SR_HVOFF
sahilmgandhi 18:6a4db94011d3 2525 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
sahilmgandhi 18:6a4db94011d3 2526
sahilmgandhi 18:6a4db94011d3 2527 /****************** Bit definition for FLASH_OPTR register *******************/
sahilmgandhi 18:6a4db94011d3 2528 #define FLASH_OPTR_RDPROT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2529 #define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2530 #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
sahilmgandhi 18:6a4db94011d3 2531 #define FLASH_OPTR_WPRMOD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2532 #define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2533 #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
sahilmgandhi 18:6a4db94011d3 2534 #define FLASH_OPTR_BOR_LEV_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2535 #define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 2536 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
sahilmgandhi 18:6a4db94011d3 2537 #define FLASH_OPTR_IWDG_SW_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2538 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2539 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
sahilmgandhi 18:6a4db94011d3 2540 #define FLASH_OPTR_nRST_STOP_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2541 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2542 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
sahilmgandhi 18:6a4db94011d3 2543 #define FLASH_OPTR_nRST_STDBY_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2544 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2545 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
sahilmgandhi 18:6a4db94011d3 2546 #define FLASH_OPTR_BFB2_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2547 #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2548 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
sahilmgandhi 18:6a4db94011d3 2549 #define FLASH_OPTR_USER_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2550 #define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
sahilmgandhi 18:6a4db94011d3 2551 #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
sahilmgandhi 18:6a4db94011d3 2552 #define FLASH_OPTR_BOOT1_Pos (31U)
sahilmgandhi 18:6a4db94011d3 2553 #define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2554 #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
sahilmgandhi 18:6a4db94011d3 2555
sahilmgandhi 18:6a4db94011d3 2556 /****************** Bit definition for FLASH_WRPR register ******************/
sahilmgandhi 18:6a4db94011d3 2557 #define FLASH_WRPR_WRP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2558 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 2559 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
sahilmgandhi 18:6a4db94011d3 2560
sahilmgandhi 18:6a4db94011d3 2561 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2562 /* */
sahilmgandhi 18:6a4db94011d3 2563 /* General Purpose IOs (GPIO) */
sahilmgandhi 18:6a4db94011d3 2564 /* */
sahilmgandhi 18:6a4db94011d3 2565 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2566 /******************* Bit definition for GPIO_MODER register *****************/
sahilmgandhi 18:6a4db94011d3 2567 #define GPIO_MODER_MODE0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2568 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2569 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
sahilmgandhi 18:6a4db94011d3 2570 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2571 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2572 #define GPIO_MODER_MODE1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2573 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 2574 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
sahilmgandhi 18:6a4db94011d3 2575 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2576 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2577 #define GPIO_MODER_MODE2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2578 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 2579 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
sahilmgandhi 18:6a4db94011d3 2580 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2581 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2582 #define GPIO_MODER_MODE3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2583 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 2584 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
sahilmgandhi 18:6a4db94011d3 2585 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2586 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2587 #define GPIO_MODER_MODE4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2588 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 2589 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
sahilmgandhi 18:6a4db94011d3 2590 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2591 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2592 #define GPIO_MODER_MODE5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2593 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 2594 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
sahilmgandhi 18:6a4db94011d3 2595 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2596 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2597 #define GPIO_MODER_MODE6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2598 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 2599 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
sahilmgandhi 18:6a4db94011d3 2600 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2601 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2602 #define GPIO_MODER_MODE7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2603 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 2604 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
sahilmgandhi 18:6a4db94011d3 2605 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2606 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2607 #define GPIO_MODER_MODE8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2608 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 2609 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
sahilmgandhi 18:6a4db94011d3 2610 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2611 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2612 #define GPIO_MODER_MODE9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2613 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 2614 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
sahilmgandhi 18:6a4db94011d3 2615 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2616 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2617 #define GPIO_MODER_MODE10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2618 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 2619 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
sahilmgandhi 18:6a4db94011d3 2620 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2621 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2622 #define GPIO_MODER_MODE11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2623 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 2624 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
sahilmgandhi 18:6a4db94011d3 2625 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2626 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2627 #define GPIO_MODER_MODE12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2628 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2629 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
sahilmgandhi 18:6a4db94011d3 2630 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2631 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2632 #define GPIO_MODER_MODE13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2633 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 2634 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
sahilmgandhi 18:6a4db94011d3 2635 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2636 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2637 #define GPIO_MODER_MODE14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2638 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 2639 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
sahilmgandhi 18:6a4db94011d3 2640 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2641 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2642 #define GPIO_MODER_MODE15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2643 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 2644 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
sahilmgandhi 18:6a4db94011d3 2645 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2646 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2647
sahilmgandhi 18:6a4db94011d3 2648 /****************** Bit definition for GPIO_OTYPER register *****************/
sahilmgandhi 18:6a4db94011d3 2649 #define GPIO_OTYPER_OT_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2650 #define GPIO_OTYPER_OT_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2651 #define GPIO_OTYPER_OT_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2652 #define GPIO_OTYPER_OT_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2653 #define GPIO_OTYPER_OT_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2654 #define GPIO_OTYPER_OT_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2655 #define GPIO_OTYPER_OT_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2656 #define GPIO_OTYPER_OT_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2657 #define GPIO_OTYPER_OT_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2658 #define GPIO_OTYPER_OT_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2659 #define GPIO_OTYPER_OT_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2660 #define GPIO_OTYPER_OT_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2661 #define GPIO_OTYPER_OT_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2662 #define GPIO_OTYPER_OT_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2663 #define GPIO_OTYPER_OT_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2664 #define GPIO_OTYPER_OT_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2665
sahilmgandhi 18:6a4db94011d3 2666 /**************** Bit definition for GPIO_OSPEEDR register ******************/
sahilmgandhi 18:6a4db94011d3 2667 #define GPIO_OSPEEDER_OSPEED0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2668 #define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2669 #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
sahilmgandhi 18:6a4db94011d3 2670 #define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2671 #define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2672 #define GPIO_OSPEEDER_OSPEED1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2673 #define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 2674 #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
sahilmgandhi 18:6a4db94011d3 2675 #define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2676 #define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2677 #define GPIO_OSPEEDER_OSPEED2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2678 #define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 2679 #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
sahilmgandhi 18:6a4db94011d3 2680 #define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2681 #define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2682 #define GPIO_OSPEEDER_OSPEED3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2683 #define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 2684 #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
sahilmgandhi 18:6a4db94011d3 2685 #define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2686 #define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2687 #define GPIO_OSPEEDER_OSPEED4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2688 #define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 2689 #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
sahilmgandhi 18:6a4db94011d3 2690 #define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2691 #define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2692 #define GPIO_OSPEEDER_OSPEED5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2693 #define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 2694 #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
sahilmgandhi 18:6a4db94011d3 2695 #define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2696 #define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2697 #define GPIO_OSPEEDER_OSPEED6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2698 #define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 2699 #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
sahilmgandhi 18:6a4db94011d3 2700 #define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2701 #define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2702 #define GPIO_OSPEEDER_OSPEED7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2703 #define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 2704 #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
sahilmgandhi 18:6a4db94011d3 2705 #define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2706 #define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2707 #define GPIO_OSPEEDER_OSPEED8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2708 #define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 2709 #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
sahilmgandhi 18:6a4db94011d3 2710 #define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2711 #define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2712 #define GPIO_OSPEEDER_OSPEED9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2713 #define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 2714 #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
sahilmgandhi 18:6a4db94011d3 2715 #define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2716 #define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2717 #define GPIO_OSPEEDER_OSPEED10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2718 #define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 2719 #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
sahilmgandhi 18:6a4db94011d3 2720 #define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2721 #define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2722 #define GPIO_OSPEEDER_OSPEED11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2723 #define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 2724 #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
sahilmgandhi 18:6a4db94011d3 2725 #define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2726 #define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2727 #define GPIO_OSPEEDER_OSPEED12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2728 #define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2729 #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
sahilmgandhi 18:6a4db94011d3 2730 #define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2731 #define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2732 #define GPIO_OSPEEDER_OSPEED13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2733 #define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 2734 #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
sahilmgandhi 18:6a4db94011d3 2735 #define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2736 #define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2737 #define GPIO_OSPEEDER_OSPEED14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2738 #define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 2739 #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
sahilmgandhi 18:6a4db94011d3 2740 #define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2741 #define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2742 #define GPIO_OSPEEDER_OSPEED15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2743 #define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 2744 #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
sahilmgandhi 18:6a4db94011d3 2745 #define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2746 #define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2747
sahilmgandhi 18:6a4db94011d3 2748 /******************* Bit definition for GPIO_PUPDR register ******************/
sahilmgandhi 18:6a4db94011d3 2749 #define GPIO_PUPDR_PUPD0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2750 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2751 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
sahilmgandhi 18:6a4db94011d3 2752 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2753 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2754 #define GPIO_PUPDR_PUPD1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2755 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 2756 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
sahilmgandhi 18:6a4db94011d3 2757 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2758 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2759 #define GPIO_PUPDR_PUPD2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2760 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 2761 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
sahilmgandhi 18:6a4db94011d3 2762 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2763 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2764 #define GPIO_PUPDR_PUPD3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2765 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 2766 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
sahilmgandhi 18:6a4db94011d3 2767 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2768 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2769 #define GPIO_PUPDR_PUPD4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2770 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 2771 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
sahilmgandhi 18:6a4db94011d3 2772 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2773 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2774 #define GPIO_PUPDR_PUPD5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2775 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 2776 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
sahilmgandhi 18:6a4db94011d3 2777 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2778 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2779 #define GPIO_PUPDR_PUPD6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2780 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 2781 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
sahilmgandhi 18:6a4db94011d3 2782 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2783 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2784 #define GPIO_PUPDR_PUPD7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2785 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 2786 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
sahilmgandhi 18:6a4db94011d3 2787 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2788 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2789 #define GPIO_PUPDR_PUPD8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2790 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 2791 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
sahilmgandhi 18:6a4db94011d3 2792 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2793 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2794 #define GPIO_PUPDR_PUPD9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2795 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 2796 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
sahilmgandhi 18:6a4db94011d3 2797 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2798 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2799 #define GPIO_PUPDR_PUPD10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2800 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 2801 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
sahilmgandhi 18:6a4db94011d3 2802 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2803 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2804 #define GPIO_PUPDR_PUPD11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2805 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 2806 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
sahilmgandhi 18:6a4db94011d3 2807 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2808 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2809 #define GPIO_PUPDR_PUPD12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2810 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2811 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
sahilmgandhi 18:6a4db94011d3 2812 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2813 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2814 #define GPIO_PUPDR_PUPD13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2815 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 2816 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
sahilmgandhi 18:6a4db94011d3 2817 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2818 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2819 #define GPIO_PUPDR_PUPD14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2820 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 2821 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
sahilmgandhi 18:6a4db94011d3 2822 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2823 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2824 #define GPIO_PUPDR_PUPD15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2825 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 2826 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
sahilmgandhi 18:6a4db94011d3 2827 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2828 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2829
sahilmgandhi 18:6a4db94011d3 2830 /******************* Bit definition for GPIO_IDR register *******************/
sahilmgandhi 18:6a4db94011d3 2831 #define GPIO_IDR_ID0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2832 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2833 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
sahilmgandhi 18:6a4db94011d3 2834 #define GPIO_IDR_ID1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2835 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2836 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
sahilmgandhi 18:6a4db94011d3 2837 #define GPIO_IDR_ID2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2838 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2839 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
sahilmgandhi 18:6a4db94011d3 2840 #define GPIO_IDR_ID3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2841 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2842 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
sahilmgandhi 18:6a4db94011d3 2843 #define GPIO_IDR_ID4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2844 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2845 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
sahilmgandhi 18:6a4db94011d3 2846 #define GPIO_IDR_ID5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2847 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2848 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
sahilmgandhi 18:6a4db94011d3 2849 #define GPIO_IDR_ID6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2850 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2851 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
sahilmgandhi 18:6a4db94011d3 2852 #define GPIO_IDR_ID7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2853 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2854 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
sahilmgandhi 18:6a4db94011d3 2855 #define GPIO_IDR_ID8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2856 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2857 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
sahilmgandhi 18:6a4db94011d3 2858 #define GPIO_IDR_ID9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2859 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2860 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
sahilmgandhi 18:6a4db94011d3 2861 #define GPIO_IDR_ID10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2862 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2863 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
sahilmgandhi 18:6a4db94011d3 2864 #define GPIO_IDR_ID11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2865 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2866 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
sahilmgandhi 18:6a4db94011d3 2867 #define GPIO_IDR_ID12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2868 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2869 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
sahilmgandhi 18:6a4db94011d3 2870 #define GPIO_IDR_ID13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2871 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2872 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
sahilmgandhi 18:6a4db94011d3 2873 #define GPIO_IDR_ID14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2874 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2875 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
sahilmgandhi 18:6a4db94011d3 2876 #define GPIO_IDR_ID15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2877 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2878 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
sahilmgandhi 18:6a4db94011d3 2879
sahilmgandhi 18:6a4db94011d3 2880 /****************** Bit definition for GPIO_ODR register ********************/
sahilmgandhi 18:6a4db94011d3 2881 #define GPIO_ODR_OD0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2882 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2883 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
sahilmgandhi 18:6a4db94011d3 2884 #define GPIO_ODR_OD1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2885 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2886 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
sahilmgandhi 18:6a4db94011d3 2887 #define GPIO_ODR_OD2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2888 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2889 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
sahilmgandhi 18:6a4db94011d3 2890 #define GPIO_ODR_OD3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2891 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2892 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
sahilmgandhi 18:6a4db94011d3 2893 #define GPIO_ODR_OD4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2894 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2895 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
sahilmgandhi 18:6a4db94011d3 2896 #define GPIO_ODR_OD5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2897 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2898 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
sahilmgandhi 18:6a4db94011d3 2899 #define GPIO_ODR_OD6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2900 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2901 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
sahilmgandhi 18:6a4db94011d3 2902 #define GPIO_ODR_OD7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2903 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2904 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
sahilmgandhi 18:6a4db94011d3 2905 #define GPIO_ODR_OD8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2906 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2907 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
sahilmgandhi 18:6a4db94011d3 2908 #define GPIO_ODR_OD9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2909 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2910 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
sahilmgandhi 18:6a4db94011d3 2911 #define GPIO_ODR_OD10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2912 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2913 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
sahilmgandhi 18:6a4db94011d3 2914 #define GPIO_ODR_OD11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2915 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2916 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
sahilmgandhi 18:6a4db94011d3 2917 #define GPIO_ODR_OD12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2918 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2919 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
sahilmgandhi 18:6a4db94011d3 2920 #define GPIO_ODR_OD13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2921 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2922 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
sahilmgandhi 18:6a4db94011d3 2923 #define GPIO_ODR_OD14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2924 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2925 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
sahilmgandhi 18:6a4db94011d3 2926 #define GPIO_ODR_OD15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2927 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2928 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
sahilmgandhi 18:6a4db94011d3 2929
sahilmgandhi 18:6a4db94011d3 2930 /****************** Bit definition for GPIO_BSRR register ********************/
sahilmgandhi 18:6a4db94011d3 2931 #define GPIO_BSRR_BS_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2932 #define GPIO_BSRR_BS_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2933 #define GPIO_BSRR_BS_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2934 #define GPIO_BSRR_BS_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2935 #define GPIO_BSRR_BS_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2936 #define GPIO_BSRR_BS_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2937 #define GPIO_BSRR_BS_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2938 #define GPIO_BSRR_BS_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2939 #define GPIO_BSRR_BS_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2940 #define GPIO_BSRR_BS_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2941 #define GPIO_BSRR_BS_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2942 #define GPIO_BSRR_BS_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2943 #define GPIO_BSRR_BS_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2944 #define GPIO_BSRR_BS_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2945 #define GPIO_BSRR_BS_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2946 #define GPIO_BSRR_BS_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2947 #define GPIO_BSRR_BR_0 (0x00010000U)
sahilmgandhi 18:6a4db94011d3 2948 #define GPIO_BSRR_BR_1 (0x00020000U)
sahilmgandhi 18:6a4db94011d3 2949 #define GPIO_BSRR_BR_2 (0x00040000U)
sahilmgandhi 18:6a4db94011d3 2950 #define GPIO_BSRR_BR_3 (0x00080000U)
sahilmgandhi 18:6a4db94011d3 2951 #define GPIO_BSRR_BR_4 (0x00100000U)
sahilmgandhi 18:6a4db94011d3 2952 #define GPIO_BSRR_BR_5 (0x00200000U)
sahilmgandhi 18:6a4db94011d3 2953 #define GPIO_BSRR_BR_6 (0x00400000U)
sahilmgandhi 18:6a4db94011d3 2954 #define GPIO_BSRR_BR_7 (0x00800000U)
sahilmgandhi 18:6a4db94011d3 2955 #define GPIO_BSRR_BR_8 (0x01000000U)
sahilmgandhi 18:6a4db94011d3 2956 #define GPIO_BSRR_BR_9 (0x02000000U)
sahilmgandhi 18:6a4db94011d3 2957 #define GPIO_BSRR_BR_10 (0x04000000U)
sahilmgandhi 18:6a4db94011d3 2958 #define GPIO_BSRR_BR_11 (0x08000000U)
sahilmgandhi 18:6a4db94011d3 2959 #define GPIO_BSRR_BR_12 (0x10000000U)
sahilmgandhi 18:6a4db94011d3 2960 #define GPIO_BSRR_BR_13 (0x20000000U)
sahilmgandhi 18:6a4db94011d3 2961 #define GPIO_BSRR_BR_14 (0x40000000U)
sahilmgandhi 18:6a4db94011d3 2962 #define GPIO_BSRR_BR_15 (0x80000000U)
sahilmgandhi 18:6a4db94011d3 2963
sahilmgandhi 18:6a4db94011d3 2964 /****************** Bit definition for GPIO_LCKR register ********************/
sahilmgandhi 18:6a4db94011d3 2965 #define GPIO_LCKR_LCK0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2966 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2967 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
sahilmgandhi 18:6a4db94011d3 2968 #define GPIO_LCKR_LCK1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2969 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2970 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
sahilmgandhi 18:6a4db94011d3 2971 #define GPIO_LCKR_LCK2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2972 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2973 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
sahilmgandhi 18:6a4db94011d3 2974 #define GPIO_LCKR_LCK3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2975 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2976 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
sahilmgandhi 18:6a4db94011d3 2977 #define GPIO_LCKR_LCK4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2978 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2979 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
sahilmgandhi 18:6a4db94011d3 2980 #define GPIO_LCKR_LCK5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2981 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2982 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
sahilmgandhi 18:6a4db94011d3 2983 #define GPIO_LCKR_LCK6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2984 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2985 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
sahilmgandhi 18:6a4db94011d3 2986 #define GPIO_LCKR_LCK7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2987 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2988 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
sahilmgandhi 18:6a4db94011d3 2989 #define GPIO_LCKR_LCK8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2990 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2991 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
sahilmgandhi 18:6a4db94011d3 2992 #define GPIO_LCKR_LCK9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2993 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2994 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
sahilmgandhi 18:6a4db94011d3 2995 #define GPIO_LCKR_LCK10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2996 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2997 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
sahilmgandhi 18:6a4db94011d3 2998 #define GPIO_LCKR_LCK11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2999 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3000 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
sahilmgandhi 18:6a4db94011d3 3001 #define GPIO_LCKR_LCK12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3002 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3003 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
sahilmgandhi 18:6a4db94011d3 3004 #define GPIO_LCKR_LCK13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3005 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3006 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
sahilmgandhi 18:6a4db94011d3 3007 #define GPIO_LCKR_LCK14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3008 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3009 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
sahilmgandhi 18:6a4db94011d3 3010 #define GPIO_LCKR_LCK15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3011 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3012 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
sahilmgandhi 18:6a4db94011d3 3013 #define GPIO_LCKR_LCKK_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3014 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3015 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
sahilmgandhi 18:6a4db94011d3 3016
sahilmgandhi 18:6a4db94011d3 3017 /****************** Bit definition for GPIO_AFRL register ********************/
sahilmgandhi 18:6a4db94011d3 3018 #define GPIO_AFRL_AFRL0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3019 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 3020 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
sahilmgandhi 18:6a4db94011d3 3021 #define GPIO_AFRL_AFRL1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3022 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 3023 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
sahilmgandhi 18:6a4db94011d3 3024 #define GPIO_AFRL_AFRL2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3025 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 3026 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
sahilmgandhi 18:6a4db94011d3 3027 #define GPIO_AFRL_AFRL3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3028 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 3029 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
sahilmgandhi 18:6a4db94011d3 3030 #define GPIO_AFRL_AFRL4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3031 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 3032 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
sahilmgandhi 18:6a4db94011d3 3033 #define GPIO_AFRL_AFRL5_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3034 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 3035 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
sahilmgandhi 18:6a4db94011d3 3036 #define GPIO_AFRL_AFRL6_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3037 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 3038 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
sahilmgandhi 18:6a4db94011d3 3039 #define GPIO_AFRL_AFRL7_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3040 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 3041 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
sahilmgandhi 18:6a4db94011d3 3042
sahilmgandhi 18:6a4db94011d3 3043 /****************** Bit definition for GPIO_AFRH register ********************/
sahilmgandhi 18:6a4db94011d3 3044 #define GPIO_AFRH_AFRH0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3045 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 3046 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
sahilmgandhi 18:6a4db94011d3 3047 #define GPIO_AFRH_AFRH1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3048 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 3049 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
sahilmgandhi 18:6a4db94011d3 3050 #define GPIO_AFRH_AFRH2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3051 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 3052 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
sahilmgandhi 18:6a4db94011d3 3053 #define GPIO_AFRH_AFRH3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3054 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 3055 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
sahilmgandhi 18:6a4db94011d3 3056 #define GPIO_AFRH_AFRH4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3057 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 3058 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
sahilmgandhi 18:6a4db94011d3 3059 #define GPIO_AFRH_AFRH5_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3060 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 3061 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
sahilmgandhi 18:6a4db94011d3 3062 #define GPIO_AFRH_AFRH6_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3063 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 3064 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
sahilmgandhi 18:6a4db94011d3 3065 #define GPIO_AFRH_AFRH7_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3066 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 3067 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
sahilmgandhi 18:6a4db94011d3 3068
sahilmgandhi 18:6a4db94011d3 3069 /****************** Bit definition for GPIO_BRR register *********************/
sahilmgandhi 18:6a4db94011d3 3070 #define GPIO_BRR_BR_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 3071 #define GPIO_BRR_BR_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 3072 #define GPIO_BRR_BR_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 3073 #define GPIO_BRR_BR_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 3074 #define GPIO_BRR_BR_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 3075 #define GPIO_BRR_BR_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 3076 #define GPIO_BRR_BR_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 3077 #define GPIO_BRR_BR_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 3078 #define GPIO_BRR_BR_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 3079 #define GPIO_BRR_BR_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 3080 #define GPIO_BRR_BR_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 3081 #define GPIO_BRR_BR_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 3082 #define GPIO_BRR_BR_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 3083 #define GPIO_BRR_BR_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 3084 #define GPIO_BRR_BR_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 3085 #define GPIO_BRR_BR_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 3086
sahilmgandhi 18:6a4db94011d3 3087 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3088 /* */
sahilmgandhi 18:6a4db94011d3 3089 /* Inter-integrated Circuit Interface (I2C) */
sahilmgandhi 18:6a4db94011d3 3090 /* */
sahilmgandhi 18:6a4db94011d3 3091 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3092
sahilmgandhi 18:6a4db94011d3 3093 /******************* Bit definition for I2C_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 3094 #define I2C_CR1_PE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3095 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3096 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
sahilmgandhi 18:6a4db94011d3 3097 #define I2C_CR1_TXIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3098 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3099 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
sahilmgandhi 18:6a4db94011d3 3100 #define I2C_CR1_RXIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3101 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3102 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
sahilmgandhi 18:6a4db94011d3 3103 #define I2C_CR1_ADDRIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3104 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3105 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
sahilmgandhi 18:6a4db94011d3 3106 #define I2C_CR1_NACKIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3107 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3108 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
sahilmgandhi 18:6a4db94011d3 3109 #define I2C_CR1_STOPIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3110 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3111 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
sahilmgandhi 18:6a4db94011d3 3112 #define I2C_CR1_TCIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3113 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3114 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
sahilmgandhi 18:6a4db94011d3 3115 #define I2C_CR1_ERRIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3116 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3117 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
sahilmgandhi 18:6a4db94011d3 3118 #define I2C_CR1_DNF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3119 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 3120 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
sahilmgandhi 18:6a4db94011d3 3121 #define I2C_CR1_ANFOFF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3122 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3123 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
sahilmgandhi 18:6a4db94011d3 3124 #define I2C_CR1_TXDMAEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3125 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3126 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
sahilmgandhi 18:6a4db94011d3 3127 #define I2C_CR1_RXDMAEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3128 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3129 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
sahilmgandhi 18:6a4db94011d3 3130 #define I2C_CR1_SBC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3131 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3132 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
sahilmgandhi 18:6a4db94011d3 3133 #define I2C_CR1_NOSTRETCH_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3134 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3135 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
sahilmgandhi 18:6a4db94011d3 3136 #define I2C_CR1_WUPEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3137 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3138 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
sahilmgandhi 18:6a4db94011d3 3139 #define I2C_CR1_GCEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3140 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3141 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
sahilmgandhi 18:6a4db94011d3 3142 #define I2C_CR1_SMBHEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3143 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3144 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
sahilmgandhi 18:6a4db94011d3 3145 #define I2C_CR1_SMBDEN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3146 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3147 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
sahilmgandhi 18:6a4db94011d3 3148 #define I2C_CR1_ALERTEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3149 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3150 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
sahilmgandhi 18:6a4db94011d3 3151 #define I2C_CR1_PECEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3152 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3153 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
sahilmgandhi 18:6a4db94011d3 3154
sahilmgandhi 18:6a4db94011d3 3155 /****************** Bit definition for I2C_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 3156 #define I2C_CR2_SADD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3157 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
sahilmgandhi 18:6a4db94011d3 3158 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
sahilmgandhi 18:6a4db94011d3 3159 #define I2C_CR2_RD_WRN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3160 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3161 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
sahilmgandhi 18:6a4db94011d3 3162 #define I2C_CR2_ADD10_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3163 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3164 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
sahilmgandhi 18:6a4db94011d3 3165 #define I2C_CR2_HEAD10R_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3166 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3167 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
sahilmgandhi 18:6a4db94011d3 3168 #define I2C_CR2_START_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3169 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3170 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
sahilmgandhi 18:6a4db94011d3 3171 #define I2C_CR2_STOP_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3172 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3173 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
sahilmgandhi 18:6a4db94011d3 3174 #define I2C_CR2_NACK_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3175 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3176 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
sahilmgandhi 18:6a4db94011d3 3177 #define I2C_CR2_NBYTES_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3178 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 3179 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
sahilmgandhi 18:6a4db94011d3 3180 #define I2C_CR2_RELOAD_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3181 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3182 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
sahilmgandhi 18:6a4db94011d3 3183 #define I2C_CR2_AUTOEND_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3184 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3185 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
sahilmgandhi 18:6a4db94011d3 3186 #define I2C_CR2_PECBYTE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3187 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3188 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
sahilmgandhi 18:6a4db94011d3 3189
sahilmgandhi 18:6a4db94011d3 3190 /******************* Bit definition for I2C_OAR1 register ******************/
sahilmgandhi 18:6a4db94011d3 3191 #define I2C_OAR1_OA1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3192 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
sahilmgandhi 18:6a4db94011d3 3193 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
sahilmgandhi 18:6a4db94011d3 3194 #define I2C_OAR1_OA1MODE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3195 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3196 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
sahilmgandhi 18:6a4db94011d3 3197 #define I2C_OAR1_OA1EN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3198 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3199 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
sahilmgandhi 18:6a4db94011d3 3200
sahilmgandhi 18:6a4db94011d3 3201 /******************* Bit definition for I2C_OAR2 register ******************/
sahilmgandhi 18:6a4db94011d3 3202 #define I2C_OAR2_OA2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3203 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
sahilmgandhi 18:6a4db94011d3 3204 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
sahilmgandhi 18:6a4db94011d3 3205 #define I2C_OAR2_OA2MSK_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3206 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3207 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
sahilmgandhi 18:6a4db94011d3 3208 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
sahilmgandhi 18:6a4db94011d3 3209 #define I2C_OAR2_OA2MASK01_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3210 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3211 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
sahilmgandhi 18:6a4db94011d3 3212 #define I2C_OAR2_OA2MASK02_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3213 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3214 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
sahilmgandhi 18:6a4db94011d3 3215 #define I2C_OAR2_OA2MASK03_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3216 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 3217 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
sahilmgandhi 18:6a4db94011d3 3218 #define I2C_OAR2_OA2MASK04_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3219 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3220 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
sahilmgandhi 18:6a4db94011d3 3221 #define I2C_OAR2_OA2MASK05_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3222 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
sahilmgandhi 18:6a4db94011d3 3223 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
sahilmgandhi 18:6a4db94011d3 3224 #define I2C_OAR2_OA2MASK06_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3225 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
sahilmgandhi 18:6a4db94011d3 3226 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
sahilmgandhi 18:6a4db94011d3 3227 #define I2C_OAR2_OA2MASK07_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3228 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3229 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
sahilmgandhi 18:6a4db94011d3 3230 #define I2C_OAR2_OA2EN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3231 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3232 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
sahilmgandhi 18:6a4db94011d3 3233
sahilmgandhi 18:6a4db94011d3 3234 /******************* Bit definition for I2C_TIMINGR register *******************/
sahilmgandhi 18:6a4db94011d3 3235 #define I2C_TIMINGR_SCLL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3236 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3237 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
sahilmgandhi 18:6a4db94011d3 3238 #define I2C_TIMINGR_SCLH_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3239 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 3240 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
sahilmgandhi 18:6a4db94011d3 3241 #define I2C_TIMINGR_SDADEL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3242 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 3243 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
sahilmgandhi 18:6a4db94011d3 3244 #define I2C_TIMINGR_SCLDEL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3245 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 3246 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
sahilmgandhi 18:6a4db94011d3 3247 #define I2C_TIMINGR_PRESC_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3248 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 3249 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
sahilmgandhi 18:6a4db94011d3 3250
sahilmgandhi 18:6a4db94011d3 3251 /******************* Bit definition for I2C_TIMEOUTR register *******************/
sahilmgandhi 18:6a4db94011d3 3252 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3253 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 3254 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
sahilmgandhi 18:6a4db94011d3 3255 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3256 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3257 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
sahilmgandhi 18:6a4db94011d3 3258 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3259 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3260 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
sahilmgandhi 18:6a4db94011d3 3261 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3262 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 3263 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
sahilmgandhi 18:6a4db94011d3 3264 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3265 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3266 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
sahilmgandhi 18:6a4db94011d3 3267
sahilmgandhi 18:6a4db94011d3 3268 /****************** Bit definition for I2C_ISR register *********************/
sahilmgandhi 18:6a4db94011d3 3269 #define I2C_ISR_TXE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3270 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3271 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
sahilmgandhi 18:6a4db94011d3 3272 #define I2C_ISR_TXIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3273 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3274 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
sahilmgandhi 18:6a4db94011d3 3275 #define I2C_ISR_RXNE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3276 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3277 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
sahilmgandhi 18:6a4db94011d3 3278 #define I2C_ISR_ADDR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3279 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3280 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
sahilmgandhi 18:6a4db94011d3 3281 #define I2C_ISR_NACKF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3282 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3283 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
sahilmgandhi 18:6a4db94011d3 3284 #define I2C_ISR_STOPF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3285 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3286 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
sahilmgandhi 18:6a4db94011d3 3287 #define I2C_ISR_TC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3288 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3289 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
sahilmgandhi 18:6a4db94011d3 3290 #define I2C_ISR_TCR_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3291 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3292 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
sahilmgandhi 18:6a4db94011d3 3293 #define I2C_ISR_BERR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3294 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3295 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
sahilmgandhi 18:6a4db94011d3 3296 #define I2C_ISR_ARLO_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3297 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3298 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
sahilmgandhi 18:6a4db94011d3 3299 #define I2C_ISR_OVR_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3300 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3301 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
sahilmgandhi 18:6a4db94011d3 3302 #define I2C_ISR_PECERR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3303 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3304 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
sahilmgandhi 18:6a4db94011d3 3305 #define I2C_ISR_TIMEOUT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3306 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3307 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
sahilmgandhi 18:6a4db94011d3 3308 #define I2C_ISR_ALERT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3309 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3310 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
sahilmgandhi 18:6a4db94011d3 3311 #define I2C_ISR_BUSY_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3312 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3313 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
sahilmgandhi 18:6a4db94011d3 3314 #define I2C_ISR_DIR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3315 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3316 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
sahilmgandhi 18:6a4db94011d3 3317 #define I2C_ISR_ADDCODE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3318 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
sahilmgandhi 18:6a4db94011d3 3319 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
sahilmgandhi 18:6a4db94011d3 3320
sahilmgandhi 18:6a4db94011d3 3321 /****************** Bit definition for I2C_ICR register *********************/
sahilmgandhi 18:6a4db94011d3 3322 #define I2C_ICR_ADDRCF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3323 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3324 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
sahilmgandhi 18:6a4db94011d3 3325 #define I2C_ICR_NACKCF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3326 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3327 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
sahilmgandhi 18:6a4db94011d3 3328 #define I2C_ICR_STOPCF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3329 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3330 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
sahilmgandhi 18:6a4db94011d3 3331 #define I2C_ICR_BERRCF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3332 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3333 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
sahilmgandhi 18:6a4db94011d3 3334 #define I2C_ICR_ARLOCF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3335 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3336 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
sahilmgandhi 18:6a4db94011d3 3337 #define I2C_ICR_OVRCF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3338 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3339 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
sahilmgandhi 18:6a4db94011d3 3340 #define I2C_ICR_PECCF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3341 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3342 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
sahilmgandhi 18:6a4db94011d3 3343 #define I2C_ICR_TIMOUTCF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3344 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3345 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
sahilmgandhi 18:6a4db94011d3 3346 #define I2C_ICR_ALERTCF_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3347 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3348 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
sahilmgandhi 18:6a4db94011d3 3349
sahilmgandhi 18:6a4db94011d3 3350 /****************** Bit definition for I2C_PECR register *********************/
sahilmgandhi 18:6a4db94011d3 3351 #define I2C_PECR_PEC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3352 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3353 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
sahilmgandhi 18:6a4db94011d3 3354
sahilmgandhi 18:6a4db94011d3 3355 /****************** Bit definition for I2C_RXDR register *********************/
sahilmgandhi 18:6a4db94011d3 3356 #define I2C_RXDR_RXDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3357 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3358 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
sahilmgandhi 18:6a4db94011d3 3359
sahilmgandhi 18:6a4db94011d3 3360 /****************** Bit definition for I2C_TXDR register *********************/
sahilmgandhi 18:6a4db94011d3 3361 #define I2C_TXDR_TXDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3362 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3363 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
sahilmgandhi 18:6a4db94011d3 3364
sahilmgandhi 18:6a4db94011d3 3365 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3366 /* */
sahilmgandhi 18:6a4db94011d3 3367 /* Independent WATCHDOG (IWDG) */
sahilmgandhi 18:6a4db94011d3 3368 /* */
sahilmgandhi 18:6a4db94011d3 3369 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3370 /******************* Bit definition for IWDG_KR register ********************/
sahilmgandhi 18:6a4db94011d3 3371 #define IWDG_KR_KEY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3372 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 3373 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
sahilmgandhi 18:6a4db94011d3 3374
sahilmgandhi 18:6a4db94011d3 3375 /******************* Bit definition for IWDG_PR register ********************/
sahilmgandhi 18:6a4db94011d3 3376 #define IWDG_PR_PR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3377 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 3378 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
sahilmgandhi 18:6a4db94011d3 3379 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3380 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3381 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3382
sahilmgandhi 18:6a4db94011d3 3383 /******************* Bit definition for IWDG_RLR register *******************/
sahilmgandhi 18:6a4db94011d3 3384 #define IWDG_RLR_RL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3385 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 3386 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
sahilmgandhi 18:6a4db94011d3 3387
sahilmgandhi 18:6a4db94011d3 3388 /******************* Bit definition for IWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 3389 #define IWDG_SR_PVU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3390 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3391 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
sahilmgandhi 18:6a4db94011d3 3392 #define IWDG_SR_RVU_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3393 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3394 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
sahilmgandhi 18:6a4db94011d3 3395 #define IWDG_SR_WVU_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3396 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3397 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
sahilmgandhi 18:6a4db94011d3 3398
sahilmgandhi 18:6a4db94011d3 3399 /******************* Bit definition for IWDG_KR register ********************/
sahilmgandhi 18:6a4db94011d3 3400 #define IWDG_WINR_WIN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3401 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 3402 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
sahilmgandhi 18:6a4db94011d3 3403
sahilmgandhi 18:6a4db94011d3 3404 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3405 /* */
sahilmgandhi 18:6a4db94011d3 3406 /* LCD Controller (LCD) */
sahilmgandhi 18:6a4db94011d3 3407 /* */
sahilmgandhi 18:6a4db94011d3 3408 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3409
sahilmgandhi 18:6a4db94011d3 3410 /******************* Bit definition for LCD_CR register *********************/
sahilmgandhi 18:6a4db94011d3 3411 #define LCD_CR_LCDEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3412 #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3413 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
sahilmgandhi 18:6a4db94011d3 3414 #define LCD_CR_VSEL_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3415 #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3416 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
sahilmgandhi 18:6a4db94011d3 3417
sahilmgandhi 18:6a4db94011d3 3418 #define LCD_CR_DUTY_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3419 #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
sahilmgandhi 18:6a4db94011d3 3420 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
sahilmgandhi 18:6a4db94011d3 3421 #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3422 #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3423 #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3424
sahilmgandhi 18:6a4db94011d3 3425 #define LCD_CR_BIAS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3426 #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 3427 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
sahilmgandhi 18:6a4db94011d3 3428 #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3429 #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3430
sahilmgandhi 18:6a4db94011d3 3431 #define LCD_CR_MUX_SEG_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3432 #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3433 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
sahilmgandhi 18:6a4db94011d3 3434
sahilmgandhi 18:6a4db94011d3 3435 #define LCD_CR_BUFEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3436 #define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3437 #define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */
sahilmgandhi 18:6a4db94011d3 3438
sahilmgandhi 18:6a4db94011d3 3439 /******************* Bit definition for LCD_FCR register ********************/
sahilmgandhi 18:6a4db94011d3 3440 #define LCD_FCR_HD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3441 #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3442 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
sahilmgandhi 18:6a4db94011d3 3443 #define LCD_FCR_SOFIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3444 #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3445 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
sahilmgandhi 18:6a4db94011d3 3446 #define LCD_FCR_UDDIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3447 #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3448 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
sahilmgandhi 18:6a4db94011d3 3449
sahilmgandhi 18:6a4db94011d3 3450 #define LCD_FCR_PON_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3451 #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 3452 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
sahilmgandhi 18:6a4db94011d3 3453 #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3454 #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3455 #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3456
sahilmgandhi 18:6a4db94011d3 3457 #define LCD_FCR_DEAD_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3458 #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
sahilmgandhi 18:6a4db94011d3 3459 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
sahilmgandhi 18:6a4db94011d3 3460 #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3461 #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3462 #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3463
sahilmgandhi 18:6a4db94011d3 3464 #define LCD_FCR_CC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3465 #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
sahilmgandhi 18:6a4db94011d3 3466 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
sahilmgandhi 18:6a4db94011d3 3467 #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3468 #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3469 #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3470
sahilmgandhi 18:6a4db94011d3 3471 #define LCD_FCR_BLINKF_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3472 #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 3473 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
sahilmgandhi 18:6a4db94011d3 3474 #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3475 #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3476 #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3477
sahilmgandhi 18:6a4db94011d3 3478 #define LCD_FCR_BLINK_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3479 #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 3480 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
sahilmgandhi 18:6a4db94011d3 3481 #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3482 #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3483
sahilmgandhi 18:6a4db94011d3 3484 #define LCD_FCR_DIV_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3485 #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
sahilmgandhi 18:6a4db94011d3 3486 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
sahilmgandhi 18:6a4db94011d3 3487 #define LCD_FCR_PS_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3488 #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
sahilmgandhi 18:6a4db94011d3 3489 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
sahilmgandhi 18:6a4db94011d3 3490
sahilmgandhi 18:6a4db94011d3 3491 /******************* Bit definition for LCD_SR register *********************/
sahilmgandhi 18:6a4db94011d3 3492 #define LCD_SR_ENS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3493 #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3494 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
sahilmgandhi 18:6a4db94011d3 3495 #define LCD_SR_SOF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3496 #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3497 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
sahilmgandhi 18:6a4db94011d3 3498 #define LCD_SR_UDR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3499 #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3500 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
sahilmgandhi 18:6a4db94011d3 3501 #define LCD_SR_UDD_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3502 #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3503 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
sahilmgandhi 18:6a4db94011d3 3504 #define LCD_SR_RDY_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3505 #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3506 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
sahilmgandhi 18:6a4db94011d3 3507 #define LCD_SR_FCRSR_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3508 #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3509 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
sahilmgandhi 18:6a4db94011d3 3510
sahilmgandhi 18:6a4db94011d3 3511 /******************* Bit definition for LCD_CLR register ********************/
sahilmgandhi 18:6a4db94011d3 3512 #define LCD_CLR_SOFC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3513 #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3514 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
sahilmgandhi 18:6a4db94011d3 3515 #define LCD_CLR_UDDC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3516 #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3517 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
sahilmgandhi 18:6a4db94011d3 3518
sahilmgandhi 18:6a4db94011d3 3519 /******************* Bit definition for LCD_RAM register ********************/
sahilmgandhi 18:6a4db94011d3 3520 #define LCD_RAM_SEGMENT_DATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3521 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 3522 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
sahilmgandhi 18:6a4db94011d3 3523
sahilmgandhi 18:6a4db94011d3 3524 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3525 /* */
sahilmgandhi 18:6a4db94011d3 3526 /* Low Power Timer (LPTTIM) */
sahilmgandhi 18:6a4db94011d3 3527 /* */
sahilmgandhi 18:6a4db94011d3 3528 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3529 /****************** Bit definition for LPTIM_ISR register *******************/
sahilmgandhi 18:6a4db94011d3 3530 #define LPTIM_ISR_CMPM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3531 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3532 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
sahilmgandhi 18:6a4db94011d3 3533 #define LPTIM_ISR_ARRM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3534 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3535 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
sahilmgandhi 18:6a4db94011d3 3536 #define LPTIM_ISR_EXTTRIG_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3537 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3538 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
sahilmgandhi 18:6a4db94011d3 3539 #define LPTIM_ISR_CMPOK_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3540 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3541 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
sahilmgandhi 18:6a4db94011d3 3542 #define LPTIM_ISR_ARROK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3543 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3544 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
sahilmgandhi 18:6a4db94011d3 3545 #define LPTIM_ISR_UP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3546 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3547 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
sahilmgandhi 18:6a4db94011d3 3548 #define LPTIM_ISR_DOWN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3549 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3550 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
sahilmgandhi 18:6a4db94011d3 3551
sahilmgandhi 18:6a4db94011d3 3552 /****************** Bit definition for LPTIM_ICR register *******************/
sahilmgandhi 18:6a4db94011d3 3553 #define LPTIM_ICR_CMPMCF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3554 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3555 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
sahilmgandhi 18:6a4db94011d3 3556 #define LPTIM_ICR_ARRMCF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3557 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3558 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
sahilmgandhi 18:6a4db94011d3 3559 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3560 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3561 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
sahilmgandhi 18:6a4db94011d3 3562 #define LPTIM_ICR_CMPOKCF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3563 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3564 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
sahilmgandhi 18:6a4db94011d3 3565 #define LPTIM_ICR_ARROKCF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3566 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3567 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
sahilmgandhi 18:6a4db94011d3 3568 #define LPTIM_ICR_UPCF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3569 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3570 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
sahilmgandhi 18:6a4db94011d3 3571 #define LPTIM_ICR_DOWNCF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3572 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3573 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
sahilmgandhi 18:6a4db94011d3 3574
sahilmgandhi 18:6a4db94011d3 3575 /****************** Bit definition for LPTIM_IER register ********************/
sahilmgandhi 18:6a4db94011d3 3576 #define LPTIM_IER_CMPMIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3577 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3578 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3579 #define LPTIM_IER_ARRMIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3580 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3581 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3582 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3583 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3584 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3585 #define LPTIM_IER_CMPOKIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3586 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3587 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3588 #define LPTIM_IER_ARROKIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3589 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3590 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3591 #define LPTIM_IER_UPIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3592 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3593 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3594 #define LPTIM_IER_DOWNIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3595 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3596 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3597
sahilmgandhi 18:6a4db94011d3 3598 /****************** Bit definition for LPTIM_CFGR register *******************/
sahilmgandhi 18:6a4db94011d3 3599 #define LPTIM_CFGR_CKSEL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3600 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3601 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
sahilmgandhi 18:6a4db94011d3 3602
sahilmgandhi 18:6a4db94011d3 3603 #define LPTIM_CFGR_CKPOL_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3604 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 3605 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
sahilmgandhi 18:6a4db94011d3 3606 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3607 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3608
sahilmgandhi 18:6a4db94011d3 3609 #define LPTIM_CFGR_CKFLT_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3610 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 3611 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
sahilmgandhi 18:6a4db94011d3 3612 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3613 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3614
sahilmgandhi 18:6a4db94011d3 3615 #define LPTIM_CFGR_TRGFLT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3616 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 3617 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
sahilmgandhi 18:6a4db94011d3 3618 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3619 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3620
sahilmgandhi 18:6a4db94011d3 3621 #define LPTIM_CFGR_PRESC_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3622 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
sahilmgandhi 18:6a4db94011d3 3623 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
sahilmgandhi 18:6a4db94011d3 3624 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3625 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3626 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3627
sahilmgandhi 18:6a4db94011d3 3628 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3629 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 3630 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
sahilmgandhi 18:6a4db94011d3 3631 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3632 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3633 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3634
sahilmgandhi 18:6a4db94011d3 3635 #define LPTIM_CFGR_TRIGEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3636 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
sahilmgandhi 18:6a4db94011d3 3637 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
sahilmgandhi 18:6a4db94011d3 3638 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3639 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3640
sahilmgandhi 18:6a4db94011d3 3641 #define LPTIM_CFGR_TIMOUT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3642 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3643 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
sahilmgandhi 18:6a4db94011d3 3644 #define LPTIM_CFGR_WAVE_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3645 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3646 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
sahilmgandhi 18:6a4db94011d3 3647 #define LPTIM_CFGR_WAVPOL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3648 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3649 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
sahilmgandhi 18:6a4db94011d3 3650 #define LPTIM_CFGR_PRELOAD_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3651 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3652 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
sahilmgandhi 18:6a4db94011d3 3653 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3654 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3655 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
sahilmgandhi 18:6a4db94011d3 3656 #define LPTIM_CFGR_ENC_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3657 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3658 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
sahilmgandhi 18:6a4db94011d3 3659
sahilmgandhi 18:6a4db94011d3 3660 /****************** Bit definition for LPTIM_CR register ********************/
sahilmgandhi 18:6a4db94011d3 3661 #define LPTIM_CR_ENABLE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3662 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3663 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
sahilmgandhi 18:6a4db94011d3 3664 #define LPTIM_CR_SNGSTRT_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3665 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3666 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
sahilmgandhi 18:6a4db94011d3 3667 #define LPTIM_CR_CNTSTRT_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3668 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3669 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
sahilmgandhi 18:6a4db94011d3 3670
sahilmgandhi 18:6a4db94011d3 3671 /****************** Bit definition for LPTIM_CMP register *******************/
sahilmgandhi 18:6a4db94011d3 3672 #define LPTIM_CMP_CMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3673 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 3674 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
sahilmgandhi 18:6a4db94011d3 3675
sahilmgandhi 18:6a4db94011d3 3676 /****************** Bit definition for LPTIM_ARR register *******************/
sahilmgandhi 18:6a4db94011d3 3677 #define LPTIM_ARR_ARR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3678 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 3679 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
sahilmgandhi 18:6a4db94011d3 3680
sahilmgandhi 18:6a4db94011d3 3681 /****************** Bit definition for LPTIM_CNT register *******************/
sahilmgandhi 18:6a4db94011d3 3682 #define LPTIM_CNT_CNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3683 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 3684 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
sahilmgandhi 18:6a4db94011d3 3685
sahilmgandhi 18:6a4db94011d3 3686 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3687 /* */
sahilmgandhi 18:6a4db94011d3 3688 /* MIFARE Firewall */
sahilmgandhi 18:6a4db94011d3 3689 /* */
sahilmgandhi 18:6a4db94011d3 3690 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3691
sahilmgandhi 18:6a4db94011d3 3692 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
sahilmgandhi 18:6a4db94011d3 3693 #define FW_CSSA_ADD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3694 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
sahilmgandhi 18:6a4db94011d3 3695 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
sahilmgandhi 18:6a4db94011d3 3696 #define FW_CSL_LENG_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3697 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
sahilmgandhi 18:6a4db94011d3 3698 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
sahilmgandhi 18:6a4db94011d3 3699 #define FW_NVDSSA_ADD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3700 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
sahilmgandhi 18:6a4db94011d3 3701 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
sahilmgandhi 18:6a4db94011d3 3702 #define FW_NVDSL_LENG_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3703 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
sahilmgandhi 18:6a4db94011d3 3704 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
sahilmgandhi 18:6a4db94011d3 3705 #define FW_VDSSA_ADD_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3706 #define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
sahilmgandhi 18:6a4db94011d3 3707 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
sahilmgandhi 18:6a4db94011d3 3708 #define FW_VDSL_LENG_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3709 #define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
sahilmgandhi 18:6a4db94011d3 3710 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
sahilmgandhi 18:6a4db94011d3 3711
sahilmgandhi 18:6a4db94011d3 3712 /**************************Bit definition for CR register *********************/
sahilmgandhi 18:6a4db94011d3 3713 #define FW_CR_FPA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3714 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3715 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
sahilmgandhi 18:6a4db94011d3 3716 #define FW_CR_VDS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3717 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3718 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
sahilmgandhi 18:6a4db94011d3 3719 #define FW_CR_VDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3720 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3721 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
sahilmgandhi 18:6a4db94011d3 3722
sahilmgandhi 18:6a4db94011d3 3723 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3724 /* */
sahilmgandhi 18:6a4db94011d3 3725 /* Power Control (PWR) */
sahilmgandhi 18:6a4db94011d3 3726 /* */
sahilmgandhi 18:6a4db94011d3 3727 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3728
sahilmgandhi 18:6a4db94011d3 3729 #define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
sahilmgandhi 18:6a4db94011d3 3730
sahilmgandhi 18:6a4db94011d3 3731 /******************** Bit definition for PWR_CR register ********************/
sahilmgandhi 18:6a4db94011d3 3732 #define PWR_CR_LPSDSR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3733 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3734 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
sahilmgandhi 18:6a4db94011d3 3735 #define PWR_CR_PDDS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3736 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3737 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
sahilmgandhi 18:6a4db94011d3 3738 #define PWR_CR_CWUF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3739 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3740 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 3741 #define PWR_CR_CSBF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3742 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3743 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
sahilmgandhi 18:6a4db94011d3 3744 #define PWR_CR_PVDE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3745 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3746 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
sahilmgandhi 18:6a4db94011d3 3747
sahilmgandhi 18:6a4db94011d3 3748 #define PWR_CR_PLS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3749 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
sahilmgandhi 18:6a4db94011d3 3750 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
sahilmgandhi 18:6a4db94011d3 3751 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3752 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3753 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3754
sahilmgandhi 18:6a4db94011d3 3755 /*!< PVD level configuration */
sahilmgandhi 18:6a4db94011d3 3756 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
sahilmgandhi 18:6a4db94011d3 3757 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
sahilmgandhi 18:6a4db94011d3 3758 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
sahilmgandhi 18:6a4db94011d3 3759 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
sahilmgandhi 18:6a4db94011d3 3760 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
sahilmgandhi 18:6a4db94011d3 3761 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
sahilmgandhi 18:6a4db94011d3 3762 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
sahilmgandhi 18:6a4db94011d3 3763 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
sahilmgandhi 18:6a4db94011d3 3764
sahilmgandhi 18:6a4db94011d3 3765 #define PWR_CR_DBP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3766 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3767 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
sahilmgandhi 18:6a4db94011d3 3768 #define PWR_CR_ULP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3769 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3770 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
sahilmgandhi 18:6a4db94011d3 3771 #define PWR_CR_FWU_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3772 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3773 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
sahilmgandhi 18:6a4db94011d3 3774
sahilmgandhi 18:6a4db94011d3 3775 #define PWR_CR_VOS_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3776 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 3777 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
sahilmgandhi 18:6a4db94011d3 3778 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3779 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3780 #define PWR_CR_DSEEKOFF_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3781 #define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3782 #define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
sahilmgandhi 18:6a4db94011d3 3783 #define PWR_CR_LPRUN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3784 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3785 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
sahilmgandhi 18:6a4db94011d3 3786
sahilmgandhi 18:6a4db94011d3 3787 /******************* Bit definition for PWR_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 3788 #define PWR_CSR_WUF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3789 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3790 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 3791 #define PWR_CSR_SBF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3792 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3793 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
sahilmgandhi 18:6a4db94011d3 3794 #define PWR_CSR_PVDO_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3795 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3796 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
sahilmgandhi 18:6a4db94011d3 3797 #define PWR_CSR_VREFINTRDYF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3798 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3799 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
sahilmgandhi 18:6a4db94011d3 3800 #define PWR_CSR_VOSF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3801 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3802 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
sahilmgandhi 18:6a4db94011d3 3803 #define PWR_CSR_REGLPF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3804 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3805 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
sahilmgandhi 18:6a4db94011d3 3806
sahilmgandhi 18:6a4db94011d3 3807 #define PWR_CSR_EWUP1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3808 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3809 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
sahilmgandhi 18:6a4db94011d3 3810 #define PWR_CSR_EWUP2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3811 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3812 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
sahilmgandhi 18:6a4db94011d3 3813 #define PWR_CSR_EWUP3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3814 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3815 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
sahilmgandhi 18:6a4db94011d3 3816
sahilmgandhi 18:6a4db94011d3 3817 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3818 /* */
sahilmgandhi 18:6a4db94011d3 3819 /* Reset and Clock Control */
sahilmgandhi 18:6a4db94011d3 3820 /* */
sahilmgandhi 18:6a4db94011d3 3821 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3822
sahilmgandhi 18:6a4db94011d3 3823 #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
sahilmgandhi 18:6a4db94011d3 3824 #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
sahilmgandhi 18:6a4db94011d3 3825
sahilmgandhi 18:6a4db94011d3 3826 /******************** Bit definition for RCC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 3827 #define RCC_CR_HSION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3828 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3829 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
sahilmgandhi 18:6a4db94011d3 3830 #define RCC_CR_HSIKERON_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3831 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3832 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
sahilmgandhi 18:6a4db94011d3 3833 #define RCC_CR_HSIRDY_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3834 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3835 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
sahilmgandhi 18:6a4db94011d3 3836 #define RCC_CR_HSIDIVEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3837 #define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3838 #define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
sahilmgandhi 18:6a4db94011d3 3839 #define RCC_CR_HSIDIVF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3840 #define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3841 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
sahilmgandhi 18:6a4db94011d3 3842 #define RCC_CR_HSIOUTEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3843 #define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3844 #define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
sahilmgandhi 18:6a4db94011d3 3845 #define RCC_CR_MSION_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3846 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3847 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
sahilmgandhi 18:6a4db94011d3 3848 #define RCC_CR_MSIRDY_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3849 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3850 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
sahilmgandhi 18:6a4db94011d3 3851 #define RCC_CR_HSEON_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3852 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3853 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
sahilmgandhi 18:6a4db94011d3 3854 #define RCC_CR_HSERDY_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3855 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3856 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
sahilmgandhi 18:6a4db94011d3 3857 #define RCC_CR_HSEBYP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3858 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3859 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
sahilmgandhi 18:6a4db94011d3 3860 #define RCC_CR_CSSHSEON_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3861 #define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3862 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
sahilmgandhi 18:6a4db94011d3 3863 #define RCC_CR_RTCPRE_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3864 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 3865 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */
sahilmgandhi 18:6a4db94011d3 3866 #define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3867 #define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3868 #define RCC_CR_PLLON_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3869 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3870 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
sahilmgandhi 18:6a4db94011d3 3871 #define RCC_CR_PLLRDY_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3872 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3873 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
sahilmgandhi 18:6a4db94011d3 3874
sahilmgandhi 18:6a4db94011d3 3875 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 3876 #define RCC_CR_CSSON RCC_CR_CSSHSEON
sahilmgandhi 18:6a4db94011d3 3877
sahilmgandhi 18:6a4db94011d3 3878 /******************** Bit definition for RCC_ICSCR register *****************/
sahilmgandhi 18:6a4db94011d3 3879 #define RCC_ICSCR_HSICAL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3880 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3881 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
sahilmgandhi 18:6a4db94011d3 3882 #define RCC_ICSCR_HSITRIM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3883 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
sahilmgandhi 18:6a4db94011d3 3884 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
sahilmgandhi 18:6a4db94011d3 3885
sahilmgandhi 18:6a4db94011d3 3886 #define RCC_ICSCR_MSIRANGE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3887 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 3888 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
sahilmgandhi 18:6a4db94011d3 3889 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
sahilmgandhi 18:6a4db94011d3 3890 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3891 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3892 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 3893 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3894 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
sahilmgandhi 18:6a4db94011d3 3895 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 3896 #define RCC_ICSCR_MSICAL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3897 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 3898 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
sahilmgandhi 18:6a4db94011d3 3899 #define RCC_ICSCR_MSITRIM_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3900 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 3901 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
sahilmgandhi 18:6a4db94011d3 3902
sahilmgandhi 18:6a4db94011d3 3903 /******************** Bit definition for RCC_CRRCR register *****************/
sahilmgandhi 18:6a4db94011d3 3904 #define RCC_CRRCR_HSI48ON_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3905 #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3906 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
sahilmgandhi 18:6a4db94011d3 3907 #define RCC_CRRCR_HSI48RDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3908 #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3909 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
sahilmgandhi 18:6a4db94011d3 3910 #define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3911 #define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1U << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3912 #define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */
sahilmgandhi 18:6a4db94011d3 3913 #define RCC_CRRCR_HSI48CAL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3914 #define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 3915 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
sahilmgandhi 18:6a4db94011d3 3916
sahilmgandhi 18:6a4db94011d3 3917 /******************* Bit definition for RCC_CFGR register *******************/
sahilmgandhi 18:6a4db94011d3 3918 /*!< SW configuration */
sahilmgandhi 18:6a4db94011d3 3919 #define RCC_CFGR_SW_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3920 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 3921 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
sahilmgandhi 18:6a4db94011d3 3922 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3923 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3924
sahilmgandhi 18:6a4db94011d3 3925 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
sahilmgandhi 18:6a4db94011d3 3926 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
sahilmgandhi 18:6a4db94011d3 3927 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
sahilmgandhi 18:6a4db94011d3 3928 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
sahilmgandhi 18:6a4db94011d3 3929
sahilmgandhi 18:6a4db94011d3 3930 /*!< SWS configuration */
sahilmgandhi 18:6a4db94011d3 3931 #define RCC_CFGR_SWS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3932 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 3933 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
sahilmgandhi 18:6a4db94011d3 3934 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3935 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3936
sahilmgandhi 18:6a4db94011d3 3937 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 3938 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 3939 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 3940 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 3941
sahilmgandhi 18:6a4db94011d3 3942 /*!< HPRE configuration */
sahilmgandhi 18:6a4db94011d3 3943 #define RCC_CFGR_HPRE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3944 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 3945 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
sahilmgandhi 18:6a4db94011d3 3946 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3947 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3948 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3949 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3950
sahilmgandhi 18:6a4db94011d3 3951 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
sahilmgandhi 18:6a4db94011d3 3952 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 3953 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 3954 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 3955 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 3956 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
sahilmgandhi 18:6a4db94011d3 3957 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
sahilmgandhi 18:6a4db94011d3 3958 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
sahilmgandhi 18:6a4db94011d3 3959 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
sahilmgandhi 18:6a4db94011d3 3960
sahilmgandhi 18:6a4db94011d3 3961 /*!< PPRE1 configuration */
sahilmgandhi 18:6a4db94011d3 3962 #define RCC_CFGR_PPRE1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3963 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3964 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
sahilmgandhi 18:6a4db94011d3 3965 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3966 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3967 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3968
sahilmgandhi 18:6a4db94011d3 3969 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 3970 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 3971 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 3972 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 3973 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 3974
sahilmgandhi 18:6a4db94011d3 3975 /*!< PPRE2 configuration */
sahilmgandhi 18:6a4db94011d3 3976 #define RCC_CFGR_PPRE2_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3977 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
sahilmgandhi 18:6a4db94011d3 3978 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
sahilmgandhi 18:6a4db94011d3 3979 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3980 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3981 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3982
sahilmgandhi 18:6a4db94011d3 3983 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 3984 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 3985 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 3986 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 3987 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 3988
sahilmgandhi 18:6a4db94011d3 3989 #define RCC_CFGR_STOPWUCK_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3990 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3991 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
sahilmgandhi 18:6a4db94011d3 3992
sahilmgandhi 18:6a4db94011d3 3993 /*!< PLL entry clock source*/
sahilmgandhi 18:6a4db94011d3 3994 #define RCC_CFGR_PLLSRC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3995 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3996 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
sahilmgandhi 18:6a4db94011d3 3997
sahilmgandhi 18:6a4db94011d3 3998 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
sahilmgandhi 18:6a4db94011d3 3999 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
sahilmgandhi 18:6a4db94011d3 4000
sahilmgandhi 18:6a4db94011d3 4001
sahilmgandhi 18:6a4db94011d3 4002 /*!< PLLMUL configuration */
sahilmgandhi 18:6a4db94011d3 4003 #define RCC_CFGR_PLLMUL_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4004 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
sahilmgandhi 18:6a4db94011d3 4005 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
sahilmgandhi 18:6a4db94011d3 4006 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4007 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4008 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4009 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4010
sahilmgandhi 18:6a4db94011d3 4011 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
sahilmgandhi 18:6a4db94011d3 4012 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
sahilmgandhi 18:6a4db94011d3 4013 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
sahilmgandhi 18:6a4db94011d3 4014 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
sahilmgandhi 18:6a4db94011d3 4015 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
sahilmgandhi 18:6a4db94011d3 4016 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
sahilmgandhi 18:6a4db94011d3 4017 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
sahilmgandhi 18:6a4db94011d3 4018 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
sahilmgandhi 18:6a4db94011d3 4019 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
sahilmgandhi 18:6a4db94011d3 4020
sahilmgandhi 18:6a4db94011d3 4021 /*!< PLLDIV configuration */
sahilmgandhi 18:6a4db94011d3 4022 #define RCC_CFGR_PLLDIV_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4023 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 4024 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
sahilmgandhi 18:6a4db94011d3 4025 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4026 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4027
sahilmgandhi 18:6a4db94011d3 4028 #define RCC_CFGR_PLLDIV2_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4029 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4030 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
sahilmgandhi 18:6a4db94011d3 4031 #define RCC_CFGR_PLLDIV3_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4032 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4033 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
sahilmgandhi 18:6a4db94011d3 4034 #define RCC_CFGR_PLLDIV4_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4035 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 4036 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
sahilmgandhi 18:6a4db94011d3 4037
sahilmgandhi 18:6a4db94011d3 4038 /*!< MCO configuration */
sahilmgandhi 18:6a4db94011d3 4039 #define RCC_CFGR_MCOSEL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4040 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 4041 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
sahilmgandhi 18:6a4db94011d3 4042 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4043 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4044 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4045 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4046
sahilmgandhi 18:6a4db94011d3 4047 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
sahilmgandhi 18:6a4db94011d3 4048 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4049 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4050 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 4051 #define RCC_CFGR_MCOSEL_HSI_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4052 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4053 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
sahilmgandhi 18:6a4db94011d3 4054 #define RCC_CFGR_MCOSEL_MSI_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4055 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 4056 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
sahilmgandhi 18:6a4db94011d3 4057 #define RCC_CFGR_MCOSEL_HSE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4058 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4059 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
sahilmgandhi 18:6a4db94011d3 4060 #define RCC_CFGR_MCOSEL_PLL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4061 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
sahilmgandhi 18:6a4db94011d3 4062 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
sahilmgandhi 18:6a4db94011d3 4063 #define RCC_CFGR_MCOSEL_LSI_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4064 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
sahilmgandhi 18:6a4db94011d3 4065 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
sahilmgandhi 18:6a4db94011d3 4066 #define RCC_CFGR_MCOSEL_LSE_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4067 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
sahilmgandhi 18:6a4db94011d3 4068 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
sahilmgandhi 18:6a4db94011d3 4069 #define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4070 #define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4071 #define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 4072
sahilmgandhi 18:6a4db94011d3 4073 #define RCC_CFGR_MCOPRE_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4074 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
sahilmgandhi 18:6a4db94011d3 4075 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
sahilmgandhi 18:6a4db94011d3 4076 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4077 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4078 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4079
sahilmgandhi 18:6a4db94011d3 4080 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
sahilmgandhi 18:6a4db94011d3 4081 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
sahilmgandhi 18:6a4db94011d3 4082 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
sahilmgandhi 18:6a4db94011d3 4083 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
sahilmgandhi 18:6a4db94011d3 4084 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
sahilmgandhi 18:6a4db94011d3 4085
sahilmgandhi 18:6a4db94011d3 4086 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 4087 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
sahilmgandhi 18:6a4db94011d3 4088 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
sahilmgandhi 18:6a4db94011d3 4089 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
sahilmgandhi 18:6a4db94011d3 4090 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
sahilmgandhi 18:6a4db94011d3 4091 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
sahilmgandhi 18:6a4db94011d3 4092 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
sahilmgandhi 18:6a4db94011d3 4093 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
sahilmgandhi 18:6a4db94011d3 4094 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
sahilmgandhi 18:6a4db94011d3 4095 #define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
sahilmgandhi 18:6a4db94011d3 4096
sahilmgandhi 18:6a4db94011d3 4097 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
sahilmgandhi 18:6a4db94011d3 4098 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
sahilmgandhi 18:6a4db94011d3 4099 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
sahilmgandhi 18:6a4db94011d3 4100 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
sahilmgandhi 18:6a4db94011d3 4101 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
sahilmgandhi 18:6a4db94011d3 4102 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
sahilmgandhi 18:6a4db94011d3 4103
sahilmgandhi 18:6a4db94011d3 4104 /*!<****************** Bit definition for RCC_CIER register ********************/
sahilmgandhi 18:6a4db94011d3 4105 #define RCC_CIER_LSIRDYIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4106 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4107 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4108 #define RCC_CIER_LSERDYIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4109 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4110 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4111 #define RCC_CIER_HSIRDYIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4112 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4113 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4114 #define RCC_CIER_HSERDYIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4115 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4116 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4117 #define RCC_CIER_PLLRDYIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4118 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4119 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4120 #define RCC_CIER_MSIRDYIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4121 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4122 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4123 #define RCC_CIER_HSI48RDYIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4124 #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4125 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4126 #define RCC_CIER_CSSLSE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4127 #define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4128 #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4129
sahilmgandhi 18:6a4db94011d3 4130 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4131 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
sahilmgandhi 18:6a4db94011d3 4132
sahilmgandhi 18:6a4db94011d3 4133 /*!<****************** Bit definition for RCC_CIFR register ********************/
sahilmgandhi 18:6a4db94011d3 4134 #define RCC_CIFR_LSIRDYF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4135 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4136 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4137 #define RCC_CIFR_LSERDYF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4138 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4139 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4140 #define RCC_CIFR_HSIRDYF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4141 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4142 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4143 #define RCC_CIFR_HSERDYF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4144 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4145 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4146 #define RCC_CIFR_PLLRDYF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4147 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4148 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4149 #define RCC_CIFR_MSIRDYF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4150 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4151 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4152 #define RCC_CIFR_HSI48RDYF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4153 #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4154 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4155 #define RCC_CIFR_CSSLSEF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4156 #define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4157 #define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4158 #define RCC_CIFR_CSSHSEF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4159 #define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4160 #define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
sahilmgandhi 18:6a4db94011d3 4161
sahilmgandhi 18:6a4db94011d3 4162 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4163 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
sahilmgandhi 18:6a4db94011d3 4164 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
sahilmgandhi 18:6a4db94011d3 4165
sahilmgandhi 18:6a4db94011d3 4166 /*!<****************** Bit definition for RCC_CICR register ********************/
sahilmgandhi 18:6a4db94011d3 4167 #define RCC_CICR_LSIRDYC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4168 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4169 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4170 #define RCC_CICR_LSERDYC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4171 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4172 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4173 #define RCC_CICR_HSIRDYC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4174 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4175 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4176 #define RCC_CICR_HSERDYC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4177 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4178 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4179 #define RCC_CICR_PLLRDYC_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4180 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4181 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4182 #define RCC_CICR_MSIRDYC_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4183 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4184 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4185 #define RCC_CICR_HSI48RDYC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4186 #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4187 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4188 #define RCC_CICR_CSSLSEC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4189 #define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4190 #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4191 #define RCC_CICR_CSSHSEC_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4192 #define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4193 #define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 4194
sahilmgandhi 18:6a4db94011d3 4195 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4196 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
sahilmgandhi 18:6a4db94011d3 4197 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC
sahilmgandhi 18:6a4db94011d3 4198 /***************** Bit definition for RCC_IOPRSTR register ******************/
sahilmgandhi 18:6a4db94011d3 4199 #define RCC_IOPRSTR_IOPARST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4200 #define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4201 #define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
sahilmgandhi 18:6a4db94011d3 4202 #define RCC_IOPRSTR_IOPBRST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4203 #define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4204 #define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
sahilmgandhi 18:6a4db94011d3 4205 #define RCC_IOPRSTR_IOPCRST_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4206 #define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4207 #define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
sahilmgandhi 18:6a4db94011d3 4208 #define RCC_IOPRSTR_IOPDRST_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4209 #define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4210 #define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
sahilmgandhi 18:6a4db94011d3 4211 #define RCC_IOPRSTR_IOPERST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4212 #define RCC_IOPRSTR_IOPERST_Msk (0x1U << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4213 #define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
sahilmgandhi 18:6a4db94011d3 4214 #define RCC_IOPRSTR_IOPHRST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4215 #define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4216 #define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
sahilmgandhi 18:6a4db94011d3 4217
sahilmgandhi 18:6a4db94011d3 4218 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4219 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
sahilmgandhi 18:6a4db94011d3 4220 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
sahilmgandhi 18:6a4db94011d3 4221 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
sahilmgandhi 18:6a4db94011d3 4222 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
sahilmgandhi 18:6a4db94011d3 4223 #define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
sahilmgandhi 18:6a4db94011d3 4224 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
sahilmgandhi 18:6a4db94011d3 4225
sahilmgandhi 18:6a4db94011d3 4226
sahilmgandhi 18:6a4db94011d3 4227 /****************** Bit definition for RCC_AHBRST register ******************/
sahilmgandhi 18:6a4db94011d3 4228 #define RCC_AHBRSTR_DMARST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4229 #define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4230 #define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
sahilmgandhi 18:6a4db94011d3 4231 #define RCC_AHBRSTR_MIFRST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4232 #define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4233 #define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */
sahilmgandhi 18:6a4db94011d3 4234 #define RCC_AHBRSTR_CRCRST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4235 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4236 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
sahilmgandhi 18:6a4db94011d3 4237 #define RCC_AHBRSTR_TSCRST_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4238 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4239 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
sahilmgandhi 18:6a4db94011d3 4240 #define RCC_AHBRSTR_RNGRST_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4241 #define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4242 #define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
sahilmgandhi 18:6a4db94011d3 4243
sahilmgandhi 18:6a4db94011d3 4244 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4245 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
sahilmgandhi 18:6a4db94011d3 4246
sahilmgandhi 18:6a4db94011d3 4247 /***************** Bit definition for RCC_APB2RSTR register *****************/
sahilmgandhi 18:6a4db94011d3 4248 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4249 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4250 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
sahilmgandhi 18:6a4db94011d3 4251 #define RCC_APB2RSTR_TIM21RST_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4252 #define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4253 #define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */
sahilmgandhi 18:6a4db94011d3 4254 #define RCC_APB2RSTR_TIM22RST_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4255 #define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4256 #define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */
sahilmgandhi 18:6a4db94011d3 4257 #define RCC_APB2RSTR_ADCRST_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4258 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4259 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */
sahilmgandhi 18:6a4db94011d3 4260 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4261 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4262 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
sahilmgandhi 18:6a4db94011d3 4263 #define RCC_APB2RSTR_USART1RST_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4264 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4265 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
sahilmgandhi 18:6a4db94011d3 4266 #define RCC_APB2RSTR_DBGRST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4267 #define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4268 #define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */
sahilmgandhi 18:6a4db94011d3 4269
sahilmgandhi 18:6a4db94011d3 4270 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4271 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
sahilmgandhi 18:6a4db94011d3 4272 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
sahilmgandhi 18:6a4db94011d3 4273
sahilmgandhi 18:6a4db94011d3 4274 /***************** Bit definition for RCC_APB1RSTR register *****************/
sahilmgandhi 18:6a4db94011d3 4275 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4276 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4277 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
sahilmgandhi 18:6a4db94011d3 4278 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4279 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4280 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
sahilmgandhi 18:6a4db94011d3 4281 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4282 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4283 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
sahilmgandhi 18:6a4db94011d3 4284 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4285 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4286 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */
sahilmgandhi 18:6a4db94011d3 4287 #define RCC_APB1RSTR_LCDRST_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4288 #define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4289 #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD clock reset */
sahilmgandhi 18:6a4db94011d3 4290 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4291 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4292 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
sahilmgandhi 18:6a4db94011d3 4293 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4294 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4295 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
sahilmgandhi 18:6a4db94011d3 4296 #define RCC_APB1RSTR_USART2RST_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4297 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4298 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
sahilmgandhi 18:6a4db94011d3 4299 #define RCC_APB1RSTR_LPUART1RST_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4300 #define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4301 #define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */
sahilmgandhi 18:6a4db94011d3 4302 #define RCC_APB1RSTR_USART4RST_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4303 #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4304 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 clock reset */
sahilmgandhi 18:6a4db94011d3 4305 #define RCC_APB1RSTR_USART5RST_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4306 #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4307 #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 clock reset */
sahilmgandhi 18:6a4db94011d3 4308 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4309 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4310 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
sahilmgandhi 18:6a4db94011d3 4311 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4312 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4313 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
sahilmgandhi 18:6a4db94011d3 4314 #define RCC_APB1RSTR_USBRST_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4315 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4316 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */
sahilmgandhi 18:6a4db94011d3 4317 #define RCC_APB1RSTR_CRSRST_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4318 #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4319 #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */
sahilmgandhi 18:6a4db94011d3 4320 #define RCC_APB1RSTR_PWRRST_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4321 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4322 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
sahilmgandhi 18:6a4db94011d3 4323 #define RCC_APB1RSTR_DACRST_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4324 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4325 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */
sahilmgandhi 18:6a4db94011d3 4326 #define RCC_APB1RSTR_I2C3RST_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4327 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4328 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 clock reset */
sahilmgandhi 18:6a4db94011d3 4329 #define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4330 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4331 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */
sahilmgandhi 18:6a4db94011d3 4332
sahilmgandhi 18:6a4db94011d3 4333 /***************** Bit definition for RCC_IOPENR register ******************/
sahilmgandhi 18:6a4db94011d3 4334 #define RCC_IOPENR_IOPAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4335 #define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4336 #define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
sahilmgandhi 18:6a4db94011d3 4337 #define RCC_IOPENR_IOPBEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4338 #define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4339 #define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
sahilmgandhi 18:6a4db94011d3 4340 #define RCC_IOPENR_IOPCEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4341 #define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4342 #define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
sahilmgandhi 18:6a4db94011d3 4343 #define RCC_IOPENR_IOPDEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4344 #define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4345 #define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
sahilmgandhi 18:6a4db94011d3 4346 #define RCC_IOPENR_IOPEEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4347 #define RCC_IOPENR_IOPEEN_Msk (0x1U << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4348 #define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
sahilmgandhi 18:6a4db94011d3 4349 #define RCC_IOPENR_IOPHEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4350 #define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4351 #define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
sahilmgandhi 18:6a4db94011d3 4352
sahilmgandhi 18:6a4db94011d3 4353 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4354 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
sahilmgandhi 18:6a4db94011d3 4355 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
sahilmgandhi 18:6a4db94011d3 4356 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
sahilmgandhi 18:6a4db94011d3 4357 #define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
sahilmgandhi 18:6a4db94011d3 4358 #define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
sahilmgandhi 18:6a4db94011d3 4359 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
sahilmgandhi 18:6a4db94011d3 4360
sahilmgandhi 18:6a4db94011d3 4361 /***************** Bit definition for RCC_AHBENR register ******************/
sahilmgandhi 18:6a4db94011d3 4362 #define RCC_AHBENR_DMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4363 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4364 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
sahilmgandhi 18:6a4db94011d3 4365 #define RCC_AHBENR_MIFEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4366 #define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4367 #define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
sahilmgandhi 18:6a4db94011d3 4368 #define RCC_AHBENR_CRCEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4369 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4370 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
sahilmgandhi 18:6a4db94011d3 4371 #define RCC_AHBENR_TSCEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4372 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4373 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
sahilmgandhi 18:6a4db94011d3 4374 #define RCC_AHBENR_RNGEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4375 #define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4376 #define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
sahilmgandhi 18:6a4db94011d3 4377
sahilmgandhi 18:6a4db94011d3 4378 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4379 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
sahilmgandhi 18:6a4db94011d3 4380
sahilmgandhi 18:6a4db94011d3 4381 /***************** Bit definition for RCC_APB2ENR register ******************/
sahilmgandhi 18:6a4db94011d3 4382 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4383 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4384 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
sahilmgandhi 18:6a4db94011d3 4385 #define RCC_APB2ENR_TIM21EN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4386 #define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4387 #define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
sahilmgandhi 18:6a4db94011d3 4388 #define RCC_APB2ENR_TIM22EN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4389 #define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4390 #define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
sahilmgandhi 18:6a4db94011d3 4391 #define RCC_APB2ENR_FWEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4392 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4393 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
sahilmgandhi 18:6a4db94011d3 4394 #define RCC_APB2ENR_ADCEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4395 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4396 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
sahilmgandhi 18:6a4db94011d3 4397 #define RCC_APB2ENR_SPI1EN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4398 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4399 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
sahilmgandhi 18:6a4db94011d3 4400 #define RCC_APB2ENR_USART1EN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4401 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4402 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
sahilmgandhi 18:6a4db94011d3 4403 #define RCC_APB2ENR_DBGEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4404 #define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4405 #define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
sahilmgandhi 18:6a4db94011d3 4406
sahilmgandhi 18:6a4db94011d3 4407 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4408
sahilmgandhi 18:6a4db94011d3 4409 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
sahilmgandhi 18:6a4db94011d3 4410 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
sahilmgandhi 18:6a4db94011d3 4411 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
sahilmgandhi 18:6a4db94011d3 4412
sahilmgandhi 18:6a4db94011d3 4413 /***************** Bit definition for RCC_APB1ENR register ******************/
sahilmgandhi 18:6a4db94011d3 4414 #define RCC_APB1ENR_TIM2EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4415 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4416 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
sahilmgandhi 18:6a4db94011d3 4417 #define RCC_APB1ENR_TIM3EN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4418 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4419 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
sahilmgandhi 18:6a4db94011d3 4420 #define RCC_APB1ENR_TIM6EN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4421 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4422 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
sahilmgandhi 18:6a4db94011d3 4423 #define RCC_APB1ENR_TIM7EN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4424 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4425 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
sahilmgandhi 18:6a4db94011d3 4426 #define RCC_APB1ENR_LCDEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4427 #define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4428 #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
sahilmgandhi 18:6a4db94011d3 4429 #define RCC_APB1ENR_WWDGEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4430 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4431 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
sahilmgandhi 18:6a4db94011d3 4432 #define RCC_APB1ENR_SPI2EN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4433 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4434 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
sahilmgandhi 18:6a4db94011d3 4435 #define RCC_APB1ENR_USART2EN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4436 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4437 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
sahilmgandhi 18:6a4db94011d3 4438 #define RCC_APB1ENR_LPUART1EN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4439 #define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4440 #define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
sahilmgandhi 18:6a4db94011d3 4441 #define RCC_APB1ENR_USART4EN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4442 #define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4443 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
sahilmgandhi 18:6a4db94011d3 4444 #define RCC_APB1ENR_USART5EN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4445 #define RCC_APB1ENR_USART5EN_Msk (0x1U << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4446 #define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
sahilmgandhi 18:6a4db94011d3 4447 #define RCC_APB1ENR_I2C1EN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4448 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4449 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
sahilmgandhi 18:6a4db94011d3 4450 #define RCC_APB1ENR_I2C2EN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4451 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4452 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
sahilmgandhi 18:6a4db94011d3 4453 #define RCC_APB1ENR_USBEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4454 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4455 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
sahilmgandhi 18:6a4db94011d3 4456 #define RCC_APB1ENR_CRSEN_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4457 #define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4458 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
sahilmgandhi 18:6a4db94011d3 4459 #define RCC_APB1ENR_PWREN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4460 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4461 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
sahilmgandhi 18:6a4db94011d3 4462 #define RCC_APB1ENR_DACEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4463 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4464 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
sahilmgandhi 18:6a4db94011d3 4465 #define RCC_APB1ENR_I2C3EN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4466 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4467 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */
sahilmgandhi 18:6a4db94011d3 4468 #define RCC_APB1ENR_LPTIM1EN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4469 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4470 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
sahilmgandhi 18:6a4db94011d3 4471
sahilmgandhi 18:6a4db94011d3 4472 /****************** Bit definition for RCC_IOPSMENR register ****************/
sahilmgandhi 18:6a4db94011d3 4473 #define RCC_IOPSMENR_IOPASMEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4474 #define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4475 #define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4476 #define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4477 #define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4478 #define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4479 #define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4480 #define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4481 #define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4482 #define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4483 #define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4484 #define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4485 #define RCC_IOPSMENR_IOPESMEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4486 #define RCC_IOPSMENR_IOPESMEN_Msk (0x1U << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4487 #define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4488 #define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4489 #define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4490 #define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4491
sahilmgandhi 18:6a4db94011d3 4492 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4493 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4494 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4495 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4496 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4497 #define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4498 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4499
sahilmgandhi 18:6a4db94011d3 4500 /***************** Bit definition for RCC_AHBSMENR register ******************/
sahilmgandhi 18:6a4db94011d3 4501 #define RCC_AHBSMENR_DMASMEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4502 #define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4503 #define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4504 #define RCC_AHBSMENR_MIFSMEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4505 #define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4506 #define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
sahilmgandhi 18:6a4db94011d3 4507 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4508 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4509 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4510 #define RCC_AHBSMENR_CRCSMEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4511 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4512 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4513 #define RCC_AHBSMENR_TSCSMEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4514 #define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4515 #define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4516 #define RCC_AHBSMENR_RNGSMEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4517 #define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4518 #define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4519
sahilmgandhi 18:6a4db94011d3 4520 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4521 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4522
sahilmgandhi 18:6a4db94011d3 4523 /***************** Bit definition for RCC_APB2SMENR register ******************/
sahilmgandhi 18:6a4db94011d3 4524 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4525 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4526 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4527 #define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4528 #define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4529 #define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4530 #define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4531 #define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4532 #define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4533 #define RCC_APB2SMENR_ADCSMEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4534 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4535 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4536 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4537 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4538 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4539 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4540 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4541 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4542 #define RCC_APB2SMENR_DBGSMEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4543 #define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4544 #define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4545
sahilmgandhi 18:6a4db94011d3 4546 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4547 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4548 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4549
sahilmgandhi 18:6a4db94011d3 4550 /***************** Bit definition for RCC_APB1SMENR register ******************/
sahilmgandhi 18:6a4db94011d3 4551 #define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4552 #define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4553 #define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4554 #define RCC_APB1SMENR_TIM3SMEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4555 #define RCC_APB1SMENR_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4556 #define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4557 #define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4558 #define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4559 #define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4560 #define RCC_APB1SMENR_TIM7SMEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4561 #define RCC_APB1SMENR_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4562 #define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4563 #define RCC_APB1SMENR_LCDSMEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4564 #define RCC_APB1SMENR_LCDSMEN_Msk (0x1U << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4565 #define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4566 #define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4567 #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4568 #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4569 #define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4570 #define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4571 #define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4572 #define RCC_APB1SMENR_USART2SMEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4573 #define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4574 #define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4575 #define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4576 #define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4577 #define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4578 #define RCC_APB1SMENR_USART4SMEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4579 #define RCC_APB1SMENR_USART4SMEN_Msk (0x1U << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4580 #define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4581 #define RCC_APB1SMENR_USART5SMEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4582 #define RCC_APB1SMENR_USART5SMEN_Msk (0x1U << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4583 #define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4584 #define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4585 #define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4586 #define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4587 #define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4588 #define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4589 #define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4590 #define RCC_APB1SMENR_USBSMEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4591 #define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4592 #define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4593 #define RCC_APB1SMENR_CRSSMEN_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4594 #define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4595 #define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4596 #define RCC_APB1SMENR_PWRSMEN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4597 #define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4598 #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4599 #define RCC_APB1SMENR_DACSMEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4600 #define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4601 #define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4602 #define RCC_APB1SMENR_I2C3SMEN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4603 #define RCC_APB1SMENR_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4604 #define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4605 #define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4606 #define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4607 #define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
sahilmgandhi 18:6a4db94011d3 4608
sahilmgandhi 18:6a4db94011d3 4609 /******************* Bit definition for RCC_CCIPR register *******************/
sahilmgandhi 18:6a4db94011d3 4610 /*!< USART1 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4611 #define RCC_CCIPR_USART1SEL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4612 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 4613 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
sahilmgandhi 18:6a4db94011d3 4614 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4615 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4616
sahilmgandhi 18:6a4db94011d3 4617 /*!< USART2 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4618 #define RCC_CCIPR_USART2SEL_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4619 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 4620 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
sahilmgandhi 18:6a4db94011d3 4621 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4622 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4623
sahilmgandhi 18:6a4db94011d3 4624 /*!< LPUART1 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4625 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4626 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 4627 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
sahilmgandhi 18:6a4db94011d3 4628 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
sahilmgandhi 18:6a4db94011d3 4629 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
sahilmgandhi 18:6a4db94011d3 4630
sahilmgandhi 18:6a4db94011d3 4631 /*!< I2C1 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4632 #define RCC_CCIPR_I2C1SEL_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4633 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 4634 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
sahilmgandhi 18:6a4db94011d3 4635 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4636 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4637
sahilmgandhi 18:6a4db94011d3 4638 /*!< I2C3 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4639 #define RCC_CCIPR_I2C3SEL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4640 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 4641 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */
sahilmgandhi 18:6a4db94011d3 4642 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4643 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4644
sahilmgandhi 18:6a4db94011d3 4645 /*!< LPTIM1 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4646 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4647 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 4648 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
sahilmgandhi 18:6a4db94011d3 4649 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4650 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4651
sahilmgandhi 18:6a4db94011d3 4652 /*!< HSI48 Clock source selection */
sahilmgandhi 18:6a4db94011d3 4653 #define RCC_CCIPR_HSI48SEL_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4654 #define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4655 #define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
sahilmgandhi 18:6a4db94011d3 4656
sahilmgandhi 18:6a4db94011d3 4657 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 4658 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
sahilmgandhi 18:6a4db94011d3 4659
sahilmgandhi 18:6a4db94011d3 4660 /******************* Bit definition for RCC_CSR register *******************/
sahilmgandhi 18:6a4db94011d3 4661 #define RCC_CSR_LSION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4662 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4663 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
sahilmgandhi 18:6a4db94011d3 4664 #define RCC_CSR_LSIRDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4665 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4666 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
sahilmgandhi 18:6a4db94011d3 4667
sahilmgandhi 18:6a4db94011d3 4668 #define RCC_CSR_LSEON_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4669 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4670 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
sahilmgandhi 18:6a4db94011d3 4671 #define RCC_CSR_LSERDY_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4672 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4673 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
sahilmgandhi 18:6a4db94011d3 4674 #define RCC_CSR_LSEBYP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4675 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4676 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
sahilmgandhi 18:6a4db94011d3 4677
sahilmgandhi 18:6a4db94011d3 4678 #define RCC_CSR_LSEDRV_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4679 #define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 4680 #define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
sahilmgandhi 18:6a4db94011d3 4681 #define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4682 #define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4683
sahilmgandhi 18:6a4db94011d3 4684 #define RCC_CSR_LSECSSON_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4685 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4686 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
sahilmgandhi 18:6a4db94011d3 4687 #define RCC_CSR_LSECSSD_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4688 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4689 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
sahilmgandhi 18:6a4db94011d3 4690
sahilmgandhi 18:6a4db94011d3 4691 /*!< RTC congiguration */
sahilmgandhi 18:6a4db94011d3 4692 #define RCC_CSR_RTCSEL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4693 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 4694 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
sahilmgandhi 18:6a4db94011d3 4695 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4696 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4697
sahilmgandhi 18:6a4db94011d3 4698 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
sahilmgandhi 18:6a4db94011d3 4699 #define RCC_CSR_RTCSEL_LSE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4700 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4701 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
sahilmgandhi 18:6a4db94011d3 4702 #define RCC_CSR_RTCSEL_LSI_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4703 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4704 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
sahilmgandhi 18:6a4db94011d3 4705 #define RCC_CSR_RTCSEL_HSE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4706 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 4707 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
sahilmgandhi 18:6a4db94011d3 4708
sahilmgandhi 18:6a4db94011d3 4709 #define RCC_CSR_RTCEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4710 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4711 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
sahilmgandhi 18:6a4db94011d3 4712 #define RCC_CSR_RTCRST_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4713 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4714 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
sahilmgandhi 18:6a4db94011d3 4715
sahilmgandhi 18:6a4db94011d3 4716 #define RCC_CSR_RMVF_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4717 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4718 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
sahilmgandhi 18:6a4db94011d3 4719 #define RCC_CSR_FWRSTF_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4720 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4721 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
sahilmgandhi 18:6a4db94011d3 4722 #define RCC_CSR_OBLRSTF_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4723 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4724 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
sahilmgandhi 18:6a4db94011d3 4725 #define RCC_CSR_PINRSTF_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4726 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4727 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
sahilmgandhi 18:6a4db94011d3 4728 #define RCC_CSR_PORRSTF_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4729 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4730 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
sahilmgandhi 18:6a4db94011d3 4731 #define RCC_CSR_SFTRSTF_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4732 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4733 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
sahilmgandhi 18:6a4db94011d3 4734 #define RCC_CSR_IWDGRSTF_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4735 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4736 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
sahilmgandhi 18:6a4db94011d3 4737 #define RCC_CSR_WWDGRSTF_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4738 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4739 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
sahilmgandhi 18:6a4db94011d3 4740 #define RCC_CSR_LPWRRSTF_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4741 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4742 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
sahilmgandhi 18:6a4db94011d3 4743
sahilmgandhi 18:6a4db94011d3 4744 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4745 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
sahilmgandhi 18:6a4db94011d3 4746
sahilmgandhi 18:6a4db94011d3 4747
sahilmgandhi 18:6a4db94011d3 4748 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4749 /* */
sahilmgandhi 18:6a4db94011d3 4750 /* RNG */
sahilmgandhi 18:6a4db94011d3 4751 /* */
sahilmgandhi 18:6a4db94011d3 4752 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4753 /******************** Bits definition for RNG_CR register *******************/
sahilmgandhi 18:6a4db94011d3 4754 #define RNG_CR_RNGEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4755 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4756 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
sahilmgandhi 18:6a4db94011d3 4757 #define RNG_CR_IE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4758 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4759 #define RNG_CR_IE RNG_CR_IE_Msk
sahilmgandhi 18:6a4db94011d3 4760
sahilmgandhi 18:6a4db94011d3 4761 /******************** Bits definition for RNG_SR register *******************/
sahilmgandhi 18:6a4db94011d3 4762 #define RNG_SR_DRDY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4763 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4764 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
sahilmgandhi 18:6a4db94011d3 4765 #define RNG_SR_CECS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4766 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4767 #define RNG_SR_CECS RNG_SR_CECS_Msk
sahilmgandhi 18:6a4db94011d3 4768 #define RNG_SR_SECS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4769 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4770 #define RNG_SR_SECS RNG_SR_SECS_Msk
sahilmgandhi 18:6a4db94011d3 4771 #define RNG_SR_CEIS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4772 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4773 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
sahilmgandhi 18:6a4db94011d3 4774 #define RNG_SR_SEIS_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4775 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4776 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
sahilmgandhi 18:6a4db94011d3 4777
sahilmgandhi 18:6a4db94011d3 4778 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4779 /* */
sahilmgandhi 18:6a4db94011d3 4780 /* Real-Time Clock (RTC) */
sahilmgandhi 18:6a4db94011d3 4781 /* */
sahilmgandhi 18:6a4db94011d3 4782 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4783 /*
sahilmgandhi 18:6a4db94011d3 4784 * @brief Specific device feature definitions
sahilmgandhi 18:6a4db94011d3 4785 */
sahilmgandhi 18:6a4db94011d3 4786 #define RTC_TAMPER1_SUPPORT
sahilmgandhi 18:6a4db94011d3 4787 #define RTC_TAMPER2_SUPPORT
sahilmgandhi 18:6a4db94011d3 4788 #define RTC_TAMPER3_SUPPORT
sahilmgandhi 18:6a4db94011d3 4789 #define RTC_WAKEUP_SUPPORT
sahilmgandhi 18:6a4db94011d3 4790 #define RTC_BACKUP_SUPPORT
sahilmgandhi 18:6a4db94011d3 4791
sahilmgandhi 18:6a4db94011d3 4792 /******************** Bits definition for RTC_TR register *******************/
sahilmgandhi 18:6a4db94011d3 4793 #define RTC_TR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4794 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4795 #define RTC_TR_PM RTC_TR_PM_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4796 #define RTC_TR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4797 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 4798 #define RTC_TR_HT RTC_TR_HT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4799 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4800 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4801 #define RTC_TR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4802 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 4803 #define RTC_TR_HU RTC_TR_HU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4804 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4805 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4806 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4807 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4808 #define RTC_TR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4809 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 4810 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4811 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4812 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4813 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4814 #define RTC_TR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4815 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4816 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4817 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4818 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4819 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4820 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4821 #define RTC_TR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4822 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 4823 #define RTC_TR_ST RTC_TR_ST_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4824 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4825 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4826 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4827 #define RTC_TR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4828 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4829 #define RTC_TR_SU RTC_TR_SU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4830 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4831 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4832 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4833 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4834
sahilmgandhi 18:6a4db94011d3 4835 /******************** Bits definition for RTC_DR register *******************/
sahilmgandhi 18:6a4db94011d3 4836 #define RTC_DR_YT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4837 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 4838 #define RTC_DR_YT RTC_DR_YT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4839 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4840 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4841 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4842 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4843 #define RTC_DR_YU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4844 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 4845 #define RTC_DR_YU RTC_DR_YU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4846 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4847 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4848 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4849 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4850 #define RTC_DR_WDU_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4851 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 4852 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4853 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4854 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4855 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4856 #define RTC_DR_MT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4857 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4858 #define RTC_DR_MT RTC_DR_MT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4859 #define RTC_DR_MU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4860 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4861 #define RTC_DR_MU RTC_DR_MU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4862 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4863 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4864 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4865 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4866 #define RTC_DR_DT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4867 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 4868 #define RTC_DR_DT RTC_DR_DT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4869 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4870 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4871 #define RTC_DR_DU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4872 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4873 #define RTC_DR_DU RTC_DR_DU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4874 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4875 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4876 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4877 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4878
sahilmgandhi 18:6a4db94011d3 4879 /******************** Bits definition for RTC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 4880 #define RTC_CR_COE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4881 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4882 #define RTC_CR_COE RTC_CR_COE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4883 #define RTC_CR_OSEL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4884 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 4885 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4886 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4887 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4888 #define RTC_CR_POL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4889 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4890 #define RTC_CR_POL RTC_CR_POL_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4891 #define RTC_CR_COSEL_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4892 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4893 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4894 #define RTC_CR_BCK_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4895 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4896 #define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4897 #define RTC_CR_SUB1H_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4898 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4899 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4900 #define RTC_CR_ADD1H_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4901 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4902 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4903 #define RTC_CR_TSIE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4904 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4905 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4906 #define RTC_CR_WUTIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4907 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4908 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4909 #define RTC_CR_ALRBIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4910 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4911 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4912 #define RTC_CR_ALRAIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4913 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4914 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4915 #define RTC_CR_TSE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4916 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4917 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4918 #define RTC_CR_WUTE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4919 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4920 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4921 #define RTC_CR_ALRBE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4922 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4923 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4924 #define RTC_CR_ALRAE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4925 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4926 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4927 #define RTC_CR_FMT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4928 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4929 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4930 #define RTC_CR_BYPSHAD_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4931 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4932 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4933 #define RTC_CR_REFCKON_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4934 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4935 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4936 #define RTC_CR_TSEDGE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4937 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4938 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4939 #define RTC_CR_WUCKSEL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4940 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 4941 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4942 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4943 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4944 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4945
sahilmgandhi 18:6a4db94011d3 4946 /******************** Bits definition for RTC_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 4947 #define RTC_ISR_RECALPF_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4948 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4949 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4950 #define RTC_ISR_TAMP3F_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4951 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4952 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4953 #define RTC_ISR_TAMP2F_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4954 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4955 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4956 #define RTC_ISR_TAMP1F_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4957 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4958 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4959 #define RTC_ISR_TSOVF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4960 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4961 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4962 #define RTC_ISR_TSF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4963 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4964 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4965 #define RTC_ISR_WUTF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4966 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4967 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4968 #define RTC_ISR_ALRBF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4969 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4970 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4971 #define RTC_ISR_ALRAF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4972 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4973 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4974 #define RTC_ISR_INIT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4975 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4976 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4977 #define RTC_ISR_INITF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4978 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4979 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4980 #define RTC_ISR_RSF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4981 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4982 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4983 #define RTC_ISR_INITS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4984 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4985 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4986 #define RTC_ISR_SHPF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4987 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4988 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4989 #define RTC_ISR_WUTWF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4990 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4991 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4992 #define RTC_ISR_ALRBWF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4993 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4994 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4995 #define RTC_ISR_ALRAWF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4996 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4997 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 4998
sahilmgandhi 18:6a4db94011d3 4999 /******************** Bits definition for RTC_PRER register *****************/
sahilmgandhi 18:6a4db94011d3 5000 #define RTC_PRER_PREDIV_A_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5001 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
sahilmgandhi 18:6a4db94011d3 5002 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5003 #define RTC_PRER_PREDIV_S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5004 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 5005 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5006
sahilmgandhi 18:6a4db94011d3 5007 /******************** Bits definition for RTC_WUTR register *****************/
sahilmgandhi 18:6a4db94011d3 5008 #define RTC_WUTR_WUT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5009 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5010 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
sahilmgandhi 18:6a4db94011d3 5011
sahilmgandhi 18:6a4db94011d3 5012 /******************** Bits definition for RTC_ALRMAR register ***************/
sahilmgandhi 18:6a4db94011d3 5013 #define RTC_ALRMAR_MSK4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5014 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5015 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5016 #define RTC_ALRMAR_WDSEL_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5017 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5018 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5019 #define RTC_ALRMAR_DT_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5020 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 5021 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5022 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5023 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5024 #define RTC_ALRMAR_DU_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5025 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 5026 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5027 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5028 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5029 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5030 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5031 #define RTC_ALRMAR_MSK3_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5032 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5033 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5034 #define RTC_ALRMAR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5035 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5036 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5037 #define RTC_ALRMAR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5038 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 5039 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5040 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5041 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5042 #define RTC_ALRMAR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5043 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 5044 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5045 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5046 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5047 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5048 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5049 #define RTC_ALRMAR_MSK2_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5050 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5051 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5052 #define RTC_ALRMAR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5053 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 5054 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5055 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5056 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5057 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5058 #define RTC_ALRMAR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5059 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5060 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5061 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5062 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5063 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5064 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5065 #define RTC_ALRMAR_MSK1_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5066 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5067 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5068 #define RTC_ALRMAR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5069 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5070 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5071 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5072 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5073 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5074 #define RTC_ALRMAR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5075 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5076 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5077 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5078 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5079 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5080 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5081
sahilmgandhi 18:6a4db94011d3 5082 /******************** Bits definition for RTC_ALRMBR register ***************/
sahilmgandhi 18:6a4db94011d3 5083 #define RTC_ALRMBR_MSK4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5084 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5085 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5086 #define RTC_ALRMBR_WDSEL_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5087 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5088 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5089 #define RTC_ALRMBR_DT_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5090 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 5091 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5092 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5093 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5094 #define RTC_ALRMBR_DU_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5095 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 5096 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5097 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5098 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5099 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5100 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5101 #define RTC_ALRMBR_MSK3_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5102 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5103 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5104 #define RTC_ALRMBR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5105 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5106 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5107 #define RTC_ALRMBR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5108 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 5109 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5110 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5111 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5112 #define RTC_ALRMBR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5113 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 5114 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5115 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5116 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5117 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5118 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5119 #define RTC_ALRMBR_MSK2_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5120 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5121 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5122 #define RTC_ALRMBR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5123 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 5124 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5125 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5126 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5127 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5128 #define RTC_ALRMBR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5129 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5130 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5131 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5132 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5133 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5134 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5135 #define RTC_ALRMBR_MSK1_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5136 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5137 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5138 #define RTC_ALRMBR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5139 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5140 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5141 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5142 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5143 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5144 #define RTC_ALRMBR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5145 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5146 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5147 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5148 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5149 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5150 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5151
sahilmgandhi 18:6a4db94011d3 5152 /******************** Bits definition for RTC_WPR register ******************/
sahilmgandhi 18:6a4db94011d3 5153 #define RTC_WPR_KEY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5154 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5155 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5156
sahilmgandhi 18:6a4db94011d3 5157 /******************** Bits definition for RTC_SSR register ******************/
sahilmgandhi 18:6a4db94011d3 5158 #define RTC_SSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5159 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5160 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5161
sahilmgandhi 18:6a4db94011d3 5162 /******************** Bits definition for RTC_SHIFTR register ***************/
sahilmgandhi 18:6a4db94011d3 5163 #define RTC_SHIFTR_SUBFS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5164 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 5165 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5166 #define RTC_SHIFTR_ADD1S_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5167 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5168 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5169
sahilmgandhi 18:6a4db94011d3 5170 /******************** Bits definition for RTC_TSTR register *****************/
sahilmgandhi 18:6a4db94011d3 5171 #define RTC_TSTR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5172 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5173 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5174 #define RTC_TSTR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5175 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 5176 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5177 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5178 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5179 #define RTC_TSTR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5180 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 5181 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5182 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5183 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5184 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5185 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5186 #define RTC_TSTR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5187 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 5188 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5189 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5190 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5191 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5192 #define RTC_TSTR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5193 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5194 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5195 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5196 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5197 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5198 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5199 #define RTC_TSTR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5200 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5201 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5202 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5203 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5204 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5205 #define RTC_TSTR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5206 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5207 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5208 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5209 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5210 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5211 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5212
sahilmgandhi 18:6a4db94011d3 5213 /******************** Bits definition for RTC_TSDR register *****************/
sahilmgandhi 18:6a4db94011d3 5214 #define RTC_TSDR_WDU_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5215 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 5216 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5217 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5218 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5219 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5220 #define RTC_TSDR_MT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5221 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5222 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5223 #define RTC_TSDR_MU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5224 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5225 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5226 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5227 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5228 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5229 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5230 #define RTC_TSDR_DT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5231 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 5232 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5233 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5234 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5235 #define RTC_TSDR_DU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5236 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5237 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5238 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5239 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5240 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5241 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5242
sahilmgandhi 18:6a4db94011d3 5243 /******************** Bits definition for RTC_TSSSR register ****************/
sahilmgandhi 18:6a4db94011d3 5244 #define RTC_TSSSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5245 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5246 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 5247
sahilmgandhi 18:6a4db94011d3 5248 /******************** Bits definition for RTC_CALR register *****************/
sahilmgandhi 18:6a4db94011d3 5249 #define RTC_CALR_CALP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5250 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5251 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5252 #define RTC_CALR_CALW8_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5253 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5254 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5255 #define RTC_CALR_CALW16_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5256 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5257 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5258 #define RTC_CALR_CALM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5259 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
sahilmgandhi 18:6a4db94011d3 5260 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5261 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5262 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5263 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5264 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5265 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5266 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5267 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5268 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5269 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5270
sahilmgandhi 18:6a4db94011d3 5271 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 5272 #define RTC_CAL_CALP RTC_CALR_CALP
sahilmgandhi 18:6a4db94011d3 5273 #define RTC_CAL_CALW8 RTC_CALR_CALW8
sahilmgandhi 18:6a4db94011d3 5274 #define RTC_CAL_CALW16 RTC_CALR_CALW16
sahilmgandhi 18:6a4db94011d3 5275 #define RTC_CAL_CALM RTC_CALR_CALM
sahilmgandhi 18:6a4db94011d3 5276 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0
sahilmgandhi 18:6a4db94011d3 5277 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1
sahilmgandhi 18:6a4db94011d3 5278 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2
sahilmgandhi 18:6a4db94011d3 5279 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3
sahilmgandhi 18:6a4db94011d3 5280 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4
sahilmgandhi 18:6a4db94011d3 5281 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5
sahilmgandhi 18:6a4db94011d3 5282 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6
sahilmgandhi 18:6a4db94011d3 5283 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7
sahilmgandhi 18:6a4db94011d3 5284 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8
sahilmgandhi 18:6a4db94011d3 5285
sahilmgandhi 18:6a4db94011d3 5286 /******************** Bits definition for RTC_TAMPCR register ****************/
sahilmgandhi 18:6a4db94011d3 5287 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5288 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5289 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5290 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5291 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5292 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5293 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5294 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5295 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5296 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5297 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5298 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5299 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5300 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5301 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5302 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5303 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5304 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5305 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5306 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5307 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5308 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5309 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5310 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5311 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5312 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5313 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5314 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5315 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5316 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5317 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5318 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 5319 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5320 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5321 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5322 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5323 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 5324 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5325 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5326 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5327 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5328 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 5329 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5330 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5331 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5332 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5333 #define RTC_TAMPCR_TAMPTS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5334 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5335 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5336 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5337 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5338 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5339 #define RTC_TAMPCR_TAMP3E_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5340 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5341 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5342 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5343 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5344 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5345 #define RTC_TAMPCR_TAMP2E_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5346 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5347 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5348 #define RTC_TAMPCR_TAMPIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5349 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5350 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5351 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5352 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5353 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5354 #define RTC_TAMPCR_TAMP1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5355 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5356 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5357
sahilmgandhi 18:6a4db94011d3 5358 /******************** Bits definition for RTC_ALRMASSR register *************/
sahilmgandhi 18:6a4db94011d3 5359 #define RTC_ALRMASSR_MASKSS_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5360 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 5361 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
sahilmgandhi 18:6a4db94011d3 5362 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5363 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5364 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5365 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5366 #define RTC_ALRMASSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5367 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 5368 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 5369
sahilmgandhi 18:6a4db94011d3 5370 /******************** Bits definition for RTC_ALRMBSSR register *************/
sahilmgandhi 18:6a4db94011d3 5371 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5372 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 5373 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
sahilmgandhi 18:6a4db94011d3 5374 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5375 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5376 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5377 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5378 #define RTC_ALRMBSSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5379 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 5380 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 5381
sahilmgandhi 18:6a4db94011d3 5382 /******************** Bits definition for RTC_OR register ****************/
sahilmgandhi 18:6a4db94011d3 5383 #define RTC_OR_OUT_RMP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5384 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5385 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5386 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5387 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5388 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5389
sahilmgandhi 18:6a4db94011d3 5390 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 5391 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
sahilmgandhi 18:6a4db94011d3 5392
sahilmgandhi 18:6a4db94011d3 5393 /******************** Bits definition for RTC_BKP0R register ****************/
sahilmgandhi 18:6a4db94011d3 5394 #define RTC_BKP0R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5395 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5396 #define RTC_BKP0R RTC_BKP0R_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5397
sahilmgandhi 18:6a4db94011d3 5398 /******************** Bits definition for RTC_BKP1R register ****************/
sahilmgandhi 18:6a4db94011d3 5399 #define RTC_BKP1R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5400 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5401 #define RTC_BKP1R RTC_BKP1R_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5402
sahilmgandhi 18:6a4db94011d3 5403 /******************** Bits definition for RTC_BKP2R register ****************/
sahilmgandhi 18:6a4db94011d3 5404 #define RTC_BKP2R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5405 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5406 #define RTC_BKP2R RTC_BKP2R_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5407
sahilmgandhi 18:6a4db94011d3 5408 /******************** Bits definition for RTC_BKP3R register ****************/
sahilmgandhi 18:6a4db94011d3 5409 #define RTC_BKP3R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5410 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5411 #define RTC_BKP3R RTC_BKP3R_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5412
sahilmgandhi 18:6a4db94011d3 5413 /******************** Bits definition for RTC_BKP4R register ****************/
sahilmgandhi 18:6a4db94011d3 5414 #define RTC_BKP4R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5415 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5416 #define RTC_BKP4R RTC_BKP4R_Msk /*!< */
sahilmgandhi 18:6a4db94011d3 5417
sahilmgandhi 18:6a4db94011d3 5418 /******************** Number of backup registers ******************************/
sahilmgandhi 18:6a4db94011d3 5419 #define RTC_BKP_NUMBER (0x00000005U) /*!< */
sahilmgandhi 18:6a4db94011d3 5420
sahilmgandhi 18:6a4db94011d3 5421 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5422 /* */
sahilmgandhi 18:6a4db94011d3 5423 /* Serial Peripheral Interface (SPI) */
sahilmgandhi 18:6a4db94011d3 5424 /* */
sahilmgandhi 18:6a4db94011d3 5425 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5426
sahilmgandhi 18:6a4db94011d3 5427 /*
sahilmgandhi 18:6a4db94011d3 5428 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
sahilmgandhi 18:6a4db94011d3 5429 */
sahilmgandhi 18:6a4db94011d3 5430 #define SPI_I2S_SUPPORT /*!< I2S support */
sahilmgandhi 18:6a4db94011d3 5431
sahilmgandhi 18:6a4db94011d3 5432 /******************* Bit definition for SPI_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 5433 #define SPI_CR1_CPHA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5434 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5435 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
sahilmgandhi 18:6a4db94011d3 5436 #define SPI_CR1_CPOL_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5437 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5438 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
sahilmgandhi 18:6a4db94011d3 5439 #define SPI_CR1_MSTR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5440 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5441 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
sahilmgandhi 18:6a4db94011d3 5442 #define SPI_CR1_BR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5443 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 5444 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
sahilmgandhi 18:6a4db94011d3 5445 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5446 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5447 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5448 #define SPI_CR1_SPE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5449 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5450 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
sahilmgandhi 18:6a4db94011d3 5451 #define SPI_CR1_LSBFIRST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5452 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5453 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
sahilmgandhi 18:6a4db94011d3 5454 #define SPI_CR1_SSI_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5455 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5456 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
sahilmgandhi 18:6a4db94011d3 5457 #define SPI_CR1_SSM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5458 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5459 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
sahilmgandhi 18:6a4db94011d3 5460 #define SPI_CR1_RXONLY_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5461 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5462 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
sahilmgandhi 18:6a4db94011d3 5463 #define SPI_CR1_DFF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5464 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5465 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
sahilmgandhi 18:6a4db94011d3 5466 #define SPI_CR1_CRCNEXT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5467 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5468 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
sahilmgandhi 18:6a4db94011d3 5469 #define SPI_CR1_CRCEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5470 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5471 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
sahilmgandhi 18:6a4db94011d3 5472 #define SPI_CR1_BIDIOE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5473 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5474 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
sahilmgandhi 18:6a4db94011d3 5475 #define SPI_CR1_BIDIMODE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5476 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5477 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
sahilmgandhi 18:6a4db94011d3 5478
sahilmgandhi 18:6a4db94011d3 5479 /******************* Bit definition for SPI_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 5480 #define SPI_CR2_RXDMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5481 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5482 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 5483 #define SPI_CR2_TXDMAEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5484 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5485 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 5486 #define SPI_CR2_SSOE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5487 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5488 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
sahilmgandhi 18:6a4db94011d3 5489 #define SPI_CR2_FRF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5490 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5491 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
sahilmgandhi 18:6a4db94011d3 5492 #define SPI_CR2_ERRIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5493 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5494 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5495 #define SPI_CR2_RXNEIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5496 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5497 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5498 #define SPI_CR2_TXEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5499 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5500 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5501
sahilmgandhi 18:6a4db94011d3 5502 /******************** Bit definition for SPI_SR register ********************/
sahilmgandhi 18:6a4db94011d3 5503 #define SPI_SR_RXNE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5504 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5505 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
sahilmgandhi 18:6a4db94011d3 5506 #define SPI_SR_TXE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5507 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5508 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
sahilmgandhi 18:6a4db94011d3 5509 #define SPI_SR_CHSIDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5510 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5511 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
sahilmgandhi 18:6a4db94011d3 5512 #define SPI_SR_UDR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5513 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5514 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
sahilmgandhi 18:6a4db94011d3 5515 #define SPI_SR_CRCERR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5516 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5517 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
sahilmgandhi 18:6a4db94011d3 5518 #define SPI_SR_MODF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5519 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5520 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
sahilmgandhi 18:6a4db94011d3 5521 #define SPI_SR_OVR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5522 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5523 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
sahilmgandhi 18:6a4db94011d3 5524 #define SPI_SR_BSY_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5525 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5526 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
sahilmgandhi 18:6a4db94011d3 5527 #define SPI_SR_FRE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5528 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5529 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
sahilmgandhi 18:6a4db94011d3 5530
sahilmgandhi 18:6a4db94011d3 5531 /******************** Bit definition for SPI_DR register ********************/
sahilmgandhi 18:6a4db94011d3 5532 #define SPI_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5533 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5534 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
sahilmgandhi 18:6a4db94011d3 5535
sahilmgandhi 18:6a4db94011d3 5536 /******************* Bit definition for SPI_CRCPR register ******************/
sahilmgandhi 18:6a4db94011d3 5537 #define SPI_CRCPR_CRCPOLY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5538 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5539 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
sahilmgandhi 18:6a4db94011d3 5540
sahilmgandhi 18:6a4db94011d3 5541 /****************** Bit definition for SPI_RXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 5542 #define SPI_RXCRCR_RXCRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5543 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5544 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
sahilmgandhi 18:6a4db94011d3 5545
sahilmgandhi 18:6a4db94011d3 5546 /****************** Bit definition for SPI_TXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 5547 #define SPI_TXCRCR_TXCRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5548 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5549 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
sahilmgandhi 18:6a4db94011d3 5550
sahilmgandhi 18:6a4db94011d3 5551 /****************** Bit definition for SPI_I2SCFGR register *****************/
sahilmgandhi 18:6a4db94011d3 5552 #define SPI_I2SCFGR_CHLEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5553 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5554 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
sahilmgandhi 18:6a4db94011d3 5555 #define SPI_I2SCFGR_DATLEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5556 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 5557 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
sahilmgandhi 18:6a4db94011d3 5558 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5559 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5560 #define SPI_I2SCFGR_CKPOL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5561 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5562 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
sahilmgandhi 18:6a4db94011d3 5563 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5564 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 5565 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
sahilmgandhi 18:6a4db94011d3 5566 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5567 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5568 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5569 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5570 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
sahilmgandhi 18:6a4db94011d3 5571 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5572 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5573 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
sahilmgandhi 18:6a4db94011d3 5574 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5575 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5576 #define SPI_I2SCFGR_I2SE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5577 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5578 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
sahilmgandhi 18:6a4db94011d3 5579 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5580 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5581 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
sahilmgandhi 18:6a4db94011d3 5582 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5583 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5584 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
sahilmgandhi 18:6a4db94011d3 5585 /****************** Bit definition for SPI_I2SPR register *******************/
sahilmgandhi 18:6a4db94011d3 5586 #define SPI_I2SPR_I2SDIV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5587 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5588 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
sahilmgandhi 18:6a4db94011d3 5589 #define SPI_I2SPR_ODD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5590 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5591 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
sahilmgandhi 18:6a4db94011d3 5592 #define SPI_I2SPR_MCKOE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5593 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5594 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
sahilmgandhi 18:6a4db94011d3 5595
sahilmgandhi 18:6a4db94011d3 5596 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5597 /* */
sahilmgandhi 18:6a4db94011d3 5598 /* System Configuration (SYSCFG) */
sahilmgandhi 18:6a4db94011d3 5599 /* */
sahilmgandhi 18:6a4db94011d3 5600 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5601 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
sahilmgandhi 18:6a4db94011d3 5602 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5603 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 5604 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
sahilmgandhi 18:6a4db94011d3 5605 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5606 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5607 #define SYSCFG_CFGR1_UFB_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5608 #define SYSCFG_CFGR1_UFB_Msk (0x1U << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5609 #define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */
sahilmgandhi 18:6a4db94011d3 5610 #define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5611 #define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5612 #define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
sahilmgandhi 18:6a4db94011d3 5613 #define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5614 #define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5615
sahilmgandhi 18:6a4db94011d3 5616 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
sahilmgandhi 18:6a4db94011d3 5617 #define SYSCFG_CFGR2_FWDISEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5618 #define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5619 #define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
sahilmgandhi 18:6a4db94011d3 5620 #define SYSCFG_CFGR2_CAPA_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5621 #define SYSCFG_CFGR2_CAPA_Msk (0x1FU << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000003E */
sahilmgandhi 18:6a4db94011d3 5622 #define SYSCFG_CFGR2_CAPA SYSCFG_CFGR2_CAPA_Msk /*!< Connection of internal Vlcd rail to external capacitors */
sahilmgandhi 18:6a4db94011d3 5623 #define SYSCFG_CFGR2_CAPA_0 (0x01U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5624 #define SYSCFG_CFGR2_CAPA_1 (0x02U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5625 #define SYSCFG_CFGR2_CAPA_2 (0x04U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5626 #define SYSCFG_CFGR2_CAPA_3 (0x08U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5627 #define SYSCFG_CFGR2_CAPA_4 (0x10U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5628 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5629 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5630 #define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5631 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5632 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5633 #define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5634 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5635 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5636 #define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5637 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5638 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5639 #define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5640 #define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5641 #define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5642 #define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5643 #define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5644 #define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5645 #define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5646 #define SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5647 #define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5648 #define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 5649
sahilmgandhi 18:6a4db94011d3 5650 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
sahilmgandhi 18:6a4db94011d3 5651 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5652 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5653 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
sahilmgandhi 18:6a4db94011d3 5654 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5655 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 5656 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
sahilmgandhi 18:6a4db94011d3 5657 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5658 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5659 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
sahilmgandhi 18:6a4db94011d3 5660 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5661 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 5662 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
sahilmgandhi 18:6a4db94011d3 5663
sahilmgandhi 18:6a4db94011d3 5664 /**
sahilmgandhi 18:6a4db94011d3 5665 * @brief EXTI0 configuration
sahilmgandhi 18:6a4db94011d3 5666 */
sahilmgandhi 18:6a4db94011d3 5667 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
sahilmgandhi 18:6a4db94011d3 5668 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
sahilmgandhi 18:6a4db94011d3 5669 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
sahilmgandhi 18:6a4db94011d3 5670 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
sahilmgandhi 18:6a4db94011d3 5671 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
sahilmgandhi 18:6a4db94011d3 5672 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
sahilmgandhi 18:6a4db94011d3 5673
sahilmgandhi 18:6a4db94011d3 5674 /**
sahilmgandhi 18:6a4db94011d3 5675 * @brief EXTI1 configuration
sahilmgandhi 18:6a4db94011d3 5676 */
sahilmgandhi 18:6a4db94011d3 5677 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
sahilmgandhi 18:6a4db94011d3 5678 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
sahilmgandhi 18:6a4db94011d3 5679 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
sahilmgandhi 18:6a4db94011d3 5680 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
sahilmgandhi 18:6a4db94011d3 5681 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
sahilmgandhi 18:6a4db94011d3 5682 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
sahilmgandhi 18:6a4db94011d3 5683
sahilmgandhi 18:6a4db94011d3 5684 /**
sahilmgandhi 18:6a4db94011d3 5685 * @brief EXTI2 configuration
sahilmgandhi 18:6a4db94011d3 5686 */
sahilmgandhi 18:6a4db94011d3 5687 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
sahilmgandhi 18:6a4db94011d3 5688 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
sahilmgandhi 18:6a4db94011d3 5689 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
sahilmgandhi 18:6a4db94011d3 5690 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
sahilmgandhi 18:6a4db94011d3 5691 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
sahilmgandhi 18:6a4db94011d3 5692
sahilmgandhi 18:6a4db94011d3 5693 /**
sahilmgandhi 18:6a4db94011d3 5694 * @brief EXTI3 configuration
sahilmgandhi 18:6a4db94011d3 5695 */
sahilmgandhi 18:6a4db94011d3 5696 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
sahilmgandhi 18:6a4db94011d3 5697 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
sahilmgandhi 18:6a4db94011d3 5698 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
sahilmgandhi 18:6a4db94011d3 5699 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
sahilmgandhi 18:6a4db94011d3 5700 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
sahilmgandhi 18:6a4db94011d3 5701
sahilmgandhi 18:6a4db94011d3 5702 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
sahilmgandhi 18:6a4db94011d3 5703 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5704 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5705 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
sahilmgandhi 18:6a4db94011d3 5706 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5707 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 5708 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
sahilmgandhi 18:6a4db94011d3 5709 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5710 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5711 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
sahilmgandhi 18:6a4db94011d3 5712 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5713 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 5714 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
sahilmgandhi 18:6a4db94011d3 5715
sahilmgandhi 18:6a4db94011d3 5716 /**
sahilmgandhi 18:6a4db94011d3 5717 * @brief EXTI4 configuration
sahilmgandhi 18:6a4db94011d3 5718 */
sahilmgandhi 18:6a4db94011d3 5719 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
sahilmgandhi 18:6a4db94011d3 5720 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
sahilmgandhi 18:6a4db94011d3 5721 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
sahilmgandhi 18:6a4db94011d3 5722 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
sahilmgandhi 18:6a4db94011d3 5723 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
sahilmgandhi 18:6a4db94011d3 5724
sahilmgandhi 18:6a4db94011d3 5725 /**
sahilmgandhi 18:6a4db94011d3 5726 * @brief EXTI5 configuration
sahilmgandhi 18:6a4db94011d3 5727 */
sahilmgandhi 18:6a4db94011d3 5728 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
sahilmgandhi 18:6a4db94011d3 5729 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
sahilmgandhi 18:6a4db94011d3 5730 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
sahilmgandhi 18:6a4db94011d3 5731 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
sahilmgandhi 18:6a4db94011d3 5732 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
sahilmgandhi 18:6a4db94011d3 5733
sahilmgandhi 18:6a4db94011d3 5734 /**
sahilmgandhi 18:6a4db94011d3 5735 * @brief EXTI6 configuration
sahilmgandhi 18:6a4db94011d3 5736 */
sahilmgandhi 18:6a4db94011d3 5737 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
sahilmgandhi 18:6a4db94011d3 5738 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
sahilmgandhi 18:6a4db94011d3 5739 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
sahilmgandhi 18:6a4db94011d3 5740 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
sahilmgandhi 18:6a4db94011d3 5741 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
sahilmgandhi 18:6a4db94011d3 5742
sahilmgandhi 18:6a4db94011d3 5743 /**
sahilmgandhi 18:6a4db94011d3 5744 * @brief EXTI7 configuration
sahilmgandhi 18:6a4db94011d3 5745 */
sahilmgandhi 18:6a4db94011d3 5746 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
sahilmgandhi 18:6a4db94011d3 5747 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
sahilmgandhi 18:6a4db94011d3 5748 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
sahilmgandhi 18:6a4db94011d3 5749 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
sahilmgandhi 18:6a4db94011d3 5750 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
sahilmgandhi 18:6a4db94011d3 5751
sahilmgandhi 18:6a4db94011d3 5752 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
sahilmgandhi 18:6a4db94011d3 5753 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5754 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5755 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
sahilmgandhi 18:6a4db94011d3 5756 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5757 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 5758 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
sahilmgandhi 18:6a4db94011d3 5759 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5760 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5761 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
sahilmgandhi 18:6a4db94011d3 5762 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5763 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 5764 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
sahilmgandhi 18:6a4db94011d3 5765
sahilmgandhi 18:6a4db94011d3 5766 /**
sahilmgandhi 18:6a4db94011d3 5767 * @brief EXTI8 configuration
sahilmgandhi 18:6a4db94011d3 5768 */
sahilmgandhi 18:6a4db94011d3 5769 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
sahilmgandhi 18:6a4db94011d3 5770 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
sahilmgandhi 18:6a4db94011d3 5771 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
sahilmgandhi 18:6a4db94011d3 5772 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
sahilmgandhi 18:6a4db94011d3 5773 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
sahilmgandhi 18:6a4db94011d3 5774
sahilmgandhi 18:6a4db94011d3 5775 /**
sahilmgandhi 18:6a4db94011d3 5776 * @brief EXTI9 configuration
sahilmgandhi 18:6a4db94011d3 5777 */
sahilmgandhi 18:6a4db94011d3 5778 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
sahilmgandhi 18:6a4db94011d3 5779 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
sahilmgandhi 18:6a4db94011d3 5780 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
sahilmgandhi 18:6a4db94011d3 5781 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
sahilmgandhi 18:6a4db94011d3 5782 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
sahilmgandhi 18:6a4db94011d3 5783 #define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */
sahilmgandhi 18:6a4db94011d3 5784
sahilmgandhi 18:6a4db94011d3 5785 /**
sahilmgandhi 18:6a4db94011d3 5786 * @brief EXTI10 configuration
sahilmgandhi 18:6a4db94011d3 5787 */
sahilmgandhi 18:6a4db94011d3 5788 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
sahilmgandhi 18:6a4db94011d3 5789 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
sahilmgandhi 18:6a4db94011d3 5790 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
sahilmgandhi 18:6a4db94011d3 5791 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
sahilmgandhi 18:6a4db94011d3 5792 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
sahilmgandhi 18:6a4db94011d3 5793 #define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */
sahilmgandhi 18:6a4db94011d3 5794
sahilmgandhi 18:6a4db94011d3 5795 /**
sahilmgandhi 18:6a4db94011d3 5796 * @brief EXTI11 configuration
sahilmgandhi 18:6a4db94011d3 5797 */
sahilmgandhi 18:6a4db94011d3 5798 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
sahilmgandhi 18:6a4db94011d3 5799 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
sahilmgandhi 18:6a4db94011d3 5800 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
sahilmgandhi 18:6a4db94011d3 5801 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
sahilmgandhi 18:6a4db94011d3 5802 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
sahilmgandhi 18:6a4db94011d3 5803
sahilmgandhi 18:6a4db94011d3 5804 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
sahilmgandhi 18:6a4db94011d3 5805 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5806 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 5807 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
sahilmgandhi 18:6a4db94011d3 5808 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5809 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 5810 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
sahilmgandhi 18:6a4db94011d3 5811 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5812 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5813 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
sahilmgandhi 18:6a4db94011d3 5814 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5815 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 5816 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
sahilmgandhi 18:6a4db94011d3 5817
sahilmgandhi 18:6a4db94011d3 5818 /**
sahilmgandhi 18:6a4db94011d3 5819 * @brief EXTI12 configuration
sahilmgandhi 18:6a4db94011d3 5820 */
sahilmgandhi 18:6a4db94011d3 5821 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
sahilmgandhi 18:6a4db94011d3 5822 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
sahilmgandhi 18:6a4db94011d3 5823 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
sahilmgandhi 18:6a4db94011d3 5824 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
sahilmgandhi 18:6a4db94011d3 5825 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
sahilmgandhi 18:6a4db94011d3 5826
sahilmgandhi 18:6a4db94011d3 5827 /**
sahilmgandhi 18:6a4db94011d3 5828 * @brief EXTI13 configuration
sahilmgandhi 18:6a4db94011d3 5829 */
sahilmgandhi 18:6a4db94011d3 5830 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
sahilmgandhi 18:6a4db94011d3 5831 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
sahilmgandhi 18:6a4db94011d3 5832 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
sahilmgandhi 18:6a4db94011d3 5833 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
sahilmgandhi 18:6a4db94011d3 5834 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
sahilmgandhi 18:6a4db94011d3 5835
sahilmgandhi 18:6a4db94011d3 5836 /**
sahilmgandhi 18:6a4db94011d3 5837 * @brief EXTI14 configuration
sahilmgandhi 18:6a4db94011d3 5838 */
sahilmgandhi 18:6a4db94011d3 5839 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
sahilmgandhi 18:6a4db94011d3 5840 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
sahilmgandhi 18:6a4db94011d3 5841 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
sahilmgandhi 18:6a4db94011d3 5842 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
sahilmgandhi 18:6a4db94011d3 5843 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
sahilmgandhi 18:6a4db94011d3 5844
sahilmgandhi 18:6a4db94011d3 5845 /**
sahilmgandhi 18:6a4db94011d3 5846 * @brief EXTI15 configuration
sahilmgandhi 18:6a4db94011d3 5847 */
sahilmgandhi 18:6a4db94011d3 5848 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
sahilmgandhi 18:6a4db94011d3 5849 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
sahilmgandhi 18:6a4db94011d3 5850 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
sahilmgandhi 18:6a4db94011d3 5851 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
sahilmgandhi 18:6a4db94011d3 5852 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
sahilmgandhi 18:6a4db94011d3 5853
sahilmgandhi 18:6a4db94011d3 5854
sahilmgandhi 18:6a4db94011d3 5855 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
sahilmgandhi 18:6a4db94011d3 5856 #define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5857 #define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 5858 #define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
sahilmgandhi 18:6a4db94011d3 5859 #define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5860 #define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5861 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5862 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5863 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
sahilmgandhi 18:6a4db94011d3 5864 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5865 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5866 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
sahilmgandhi 18:6a4db94011d3 5867 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5868 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5869 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
sahilmgandhi 18:6a4db94011d3 5870 #define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5871 #define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5872 #define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
sahilmgandhi 18:6a4db94011d3 5873 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5874 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5875 #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
sahilmgandhi 18:6a4db94011d3 5876 #define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5877 #define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5878 #define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
sahilmgandhi 18:6a4db94011d3 5879
sahilmgandhi 18:6a4db94011d3 5880 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 5881
sahilmgandhi 18:6a4db94011d3 5882 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
sahilmgandhi 18:6a4db94011d3 5883 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
sahilmgandhi 18:6a4db94011d3 5884 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
sahilmgandhi 18:6a4db94011d3 5885 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
sahilmgandhi 18:6a4db94011d3 5886 #define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
sahilmgandhi 18:6a4db94011d3 5887 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
sahilmgandhi 18:6a4db94011d3 5888 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
sahilmgandhi 18:6a4db94011d3 5889 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
sahilmgandhi 18:6a4db94011d3 5890 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
sahilmgandhi 18:6a4db94011d3 5891
sahilmgandhi 18:6a4db94011d3 5892 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5893 /* */
sahilmgandhi 18:6a4db94011d3 5894 /* Timers (TIM) */
sahilmgandhi 18:6a4db94011d3 5895 /* */
sahilmgandhi 18:6a4db94011d3 5896 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5897 /*
sahilmgandhi 18:6a4db94011d3 5898 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
sahilmgandhi 18:6a4db94011d3 5899 */
sahilmgandhi 18:6a4db94011d3 5900 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
sahilmgandhi 18:6a4db94011d3 5901 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
sahilmgandhi 18:6a4db94011d3 5902 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
sahilmgandhi 18:6a4db94011d3 5903 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
sahilmgandhi 18:6a4db94011d3 5904 #else
sahilmgandhi 18:6a4db94011d3 5905 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
sahilmgandhi 18:6a4db94011d3 5906 #endif
sahilmgandhi 18:6a4db94011d3 5907
sahilmgandhi 18:6a4db94011d3 5908 /******************* Bit definition for TIM_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 5909 #define TIM_CR1_CEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5910 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5911 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
sahilmgandhi 18:6a4db94011d3 5912 #define TIM_CR1_UDIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5913 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5914 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
sahilmgandhi 18:6a4db94011d3 5915 #define TIM_CR1_URS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5916 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5917 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
sahilmgandhi 18:6a4db94011d3 5918 #define TIM_CR1_OPM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5919 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5920 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
sahilmgandhi 18:6a4db94011d3 5921 #define TIM_CR1_DIR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5922 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5923 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
sahilmgandhi 18:6a4db94011d3 5924
sahilmgandhi 18:6a4db94011d3 5925 #define TIM_CR1_CMS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5926 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 5927 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
sahilmgandhi 18:6a4db94011d3 5928 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5929 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5930
sahilmgandhi 18:6a4db94011d3 5931 #define TIM_CR1_ARPE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5932 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5933 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
sahilmgandhi 18:6a4db94011d3 5934
sahilmgandhi 18:6a4db94011d3 5935 #define TIM_CR1_CKD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5936 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5937 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
sahilmgandhi 18:6a4db94011d3 5938 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5939 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5940
sahilmgandhi 18:6a4db94011d3 5941 /******************* Bit definition for TIM_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 5942 #define TIM_CR2_CCDS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5943 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5944 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
sahilmgandhi 18:6a4db94011d3 5945
sahilmgandhi 18:6a4db94011d3 5946 #define TIM_CR2_MMS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5947 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5948 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
sahilmgandhi 18:6a4db94011d3 5949 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5950 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5951 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5952
sahilmgandhi 18:6a4db94011d3 5953 #define TIM_CR2_TI1S_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5954 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5955 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
sahilmgandhi 18:6a4db94011d3 5956
sahilmgandhi 18:6a4db94011d3 5957 /******************* Bit definition for TIM_SMCR register *******************/
sahilmgandhi 18:6a4db94011d3 5958 #define TIM_SMCR_SMS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5959 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 5960 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
sahilmgandhi 18:6a4db94011d3 5961 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5962 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5963 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5964
sahilmgandhi 18:6a4db94011d3 5965 #define TIM_SMCR_OCCS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5966 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5967 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
sahilmgandhi 18:6a4db94011d3 5968
sahilmgandhi 18:6a4db94011d3 5969 #define TIM_SMCR_TS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5970 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5971 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
sahilmgandhi 18:6a4db94011d3 5972 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5973 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5974 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5975
sahilmgandhi 18:6a4db94011d3 5976 #define TIM_SMCR_MSM_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5977 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5978 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
sahilmgandhi 18:6a4db94011d3 5979
sahilmgandhi 18:6a4db94011d3 5980 #define TIM_SMCR_ETF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5981 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5982 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
sahilmgandhi 18:6a4db94011d3 5983 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5984 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5985 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5986 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5987
sahilmgandhi 18:6a4db94011d3 5988 #define TIM_SMCR_ETPS_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5989 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 5990 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
sahilmgandhi 18:6a4db94011d3 5991 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5992 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5993
sahilmgandhi 18:6a4db94011d3 5994 #define TIM_SMCR_ECE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5995 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5996 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
sahilmgandhi 18:6a4db94011d3 5997 #define TIM_SMCR_ETP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5998 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5999 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
sahilmgandhi 18:6a4db94011d3 6000
sahilmgandhi 18:6a4db94011d3 6001 /******************* Bit definition for TIM_DIER register *******************/
sahilmgandhi 18:6a4db94011d3 6002 #define TIM_DIER_UIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6003 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6004 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
sahilmgandhi 18:6a4db94011d3 6005 #define TIM_DIER_CC1IE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6006 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6007 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6008 #define TIM_DIER_CC2IE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6009 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6010 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6011 #define TIM_DIER_CC3IE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6012 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6013 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6014 #define TIM_DIER_CC4IE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6015 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6016 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6017 #define TIM_DIER_TIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6018 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6019 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
sahilmgandhi 18:6a4db94011d3 6020 #define TIM_DIER_UDE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6021 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6022 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
sahilmgandhi 18:6a4db94011d3 6023 #define TIM_DIER_CC1DE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6024 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6025 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6026 #define TIM_DIER_CC2DE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6027 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6028 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6029 #define TIM_DIER_CC3DE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6030 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6031 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6032 #define TIM_DIER_CC4DE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6033 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6034 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6035 #define TIM_DIER_TDE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6036 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6037 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
sahilmgandhi 18:6a4db94011d3 6038
sahilmgandhi 18:6a4db94011d3 6039 /******************** Bit definition for TIM_SR register ********************/
sahilmgandhi 18:6a4db94011d3 6040 #define TIM_SR_UIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6041 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6042 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6043 #define TIM_SR_CC1IF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6044 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6045 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6046 #define TIM_SR_CC2IF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6047 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6048 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6049 #define TIM_SR_CC3IF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6050 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6051 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6052 #define TIM_SR_CC4IF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6053 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6054 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6055 #define TIM_SR_TIF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6056 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6057 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6058 #define TIM_SR_CC1OF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6059 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6060 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6061 #define TIM_SR_CC2OF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6062 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6063 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6064 #define TIM_SR_CC3OF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6065 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6066 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6067 #define TIM_SR_CC4OF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6068 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6069 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6070
sahilmgandhi 18:6a4db94011d3 6071 /******************* Bit definition for TIM_EGR register ********************/
sahilmgandhi 18:6a4db94011d3 6072 #define TIM_EGR_UG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6073 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6074 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
sahilmgandhi 18:6a4db94011d3 6075 #define TIM_EGR_CC1G_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6076 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6077 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
sahilmgandhi 18:6a4db94011d3 6078 #define TIM_EGR_CC2G_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6079 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6080 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
sahilmgandhi 18:6a4db94011d3 6081 #define TIM_EGR_CC3G_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6082 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6083 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
sahilmgandhi 18:6a4db94011d3 6084 #define TIM_EGR_CC4G_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6085 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6086 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
sahilmgandhi 18:6a4db94011d3 6087 #define TIM_EGR_TG_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6088 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6089 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
sahilmgandhi 18:6a4db94011d3 6090
sahilmgandhi 18:6a4db94011d3 6091 /****************** Bit definition for TIM_CCMR1 register *******************/
sahilmgandhi 18:6a4db94011d3 6092 #define TIM_CCMR1_CC1S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6093 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 6094 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
sahilmgandhi 18:6a4db94011d3 6095 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6096 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6097
sahilmgandhi 18:6a4db94011d3 6098 #define TIM_CCMR1_OC1FE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6099 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6100 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
sahilmgandhi 18:6a4db94011d3 6101 #define TIM_CCMR1_OC1PE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6102 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6103 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
sahilmgandhi 18:6a4db94011d3 6104
sahilmgandhi 18:6a4db94011d3 6105 #define TIM_CCMR1_OC1M_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6106 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 6107 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
sahilmgandhi 18:6a4db94011d3 6108 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6109 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6110 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6111
sahilmgandhi 18:6a4db94011d3 6112 #define TIM_CCMR1_OC1CE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6113 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6114 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
sahilmgandhi 18:6a4db94011d3 6115
sahilmgandhi 18:6a4db94011d3 6116 #define TIM_CCMR1_CC2S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6117 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 6118 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
sahilmgandhi 18:6a4db94011d3 6119 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6120 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6121
sahilmgandhi 18:6a4db94011d3 6122 #define TIM_CCMR1_OC2FE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6123 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6124 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
sahilmgandhi 18:6a4db94011d3 6125 #define TIM_CCMR1_OC2PE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6126 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6127 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
sahilmgandhi 18:6a4db94011d3 6128
sahilmgandhi 18:6a4db94011d3 6129 #define TIM_CCMR1_OC2M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6130 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 6131 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
sahilmgandhi 18:6a4db94011d3 6132 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6133 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6134 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6135
sahilmgandhi 18:6a4db94011d3 6136 #define TIM_CCMR1_OC2CE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6137 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6138 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
sahilmgandhi 18:6a4db94011d3 6139
sahilmgandhi 18:6a4db94011d3 6140 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 6141
sahilmgandhi 18:6a4db94011d3 6142 #define TIM_CCMR1_IC1PSC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6143 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 6144 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6145 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6146 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6147
sahilmgandhi 18:6a4db94011d3 6148 #define TIM_CCMR1_IC1F_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6149 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 6150 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
sahilmgandhi 18:6a4db94011d3 6151 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6152 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6153 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6154 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6155
sahilmgandhi 18:6a4db94011d3 6156 #define TIM_CCMR1_IC2PSC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6157 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 6158 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6159 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6160 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6161
sahilmgandhi 18:6a4db94011d3 6162 #define TIM_CCMR1_IC2F_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6163 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 6164 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
sahilmgandhi 18:6a4db94011d3 6165 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6166 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6167 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6168 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6169
sahilmgandhi 18:6a4db94011d3 6170 /****************** Bit definition for TIM_CCMR2 register *******************/
sahilmgandhi 18:6a4db94011d3 6171 #define TIM_CCMR2_CC3S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6172 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 6173 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
sahilmgandhi 18:6a4db94011d3 6174 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6175 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6176
sahilmgandhi 18:6a4db94011d3 6177 #define TIM_CCMR2_OC3FE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6178 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6179 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
sahilmgandhi 18:6a4db94011d3 6180 #define TIM_CCMR2_OC3PE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6181 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6182 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
sahilmgandhi 18:6a4db94011d3 6183
sahilmgandhi 18:6a4db94011d3 6184 #define TIM_CCMR2_OC3M_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6185 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 6186 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
sahilmgandhi 18:6a4db94011d3 6187 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6188 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6189 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6190
sahilmgandhi 18:6a4db94011d3 6191 #define TIM_CCMR2_OC3CE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6192 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6193 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
sahilmgandhi 18:6a4db94011d3 6194
sahilmgandhi 18:6a4db94011d3 6195 #define TIM_CCMR2_CC4S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6196 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 6197 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
sahilmgandhi 18:6a4db94011d3 6198 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6199 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6200
sahilmgandhi 18:6a4db94011d3 6201 #define TIM_CCMR2_OC4FE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6202 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6203 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
sahilmgandhi 18:6a4db94011d3 6204 #define TIM_CCMR2_OC4PE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6205 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6206 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
sahilmgandhi 18:6a4db94011d3 6207
sahilmgandhi 18:6a4db94011d3 6208 #define TIM_CCMR2_OC4M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6209 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 6210 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
sahilmgandhi 18:6a4db94011d3 6211 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6212 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6213 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6214
sahilmgandhi 18:6a4db94011d3 6215 #define TIM_CCMR2_OC4CE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6216 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6217 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
sahilmgandhi 18:6a4db94011d3 6218
sahilmgandhi 18:6a4db94011d3 6219 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 6220
sahilmgandhi 18:6a4db94011d3 6221 #define TIM_CCMR2_IC3PSC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6222 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 6223 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6224 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6225 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6226
sahilmgandhi 18:6a4db94011d3 6227 #define TIM_CCMR2_IC3F_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6228 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 6229 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
sahilmgandhi 18:6a4db94011d3 6230 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6231 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6232 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6233 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6234
sahilmgandhi 18:6a4db94011d3 6235 #define TIM_CCMR2_IC4PSC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6236 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 6237 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6238 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6239 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6240
sahilmgandhi 18:6a4db94011d3 6241 #define TIM_CCMR2_IC4F_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6242 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 6243 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
sahilmgandhi 18:6a4db94011d3 6244 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6245 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6246 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6247 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6248
sahilmgandhi 18:6a4db94011d3 6249 /******************* Bit definition for TIM_CCER register *******************/
sahilmgandhi 18:6a4db94011d3 6250 #define TIM_CCER_CC1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6251 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6252 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
sahilmgandhi 18:6a4db94011d3 6253 #define TIM_CCER_CC1P_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6254 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6255 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
sahilmgandhi 18:6a4db94011d3 6256 #define TIM_CCER_CC1NP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6257 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6258 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6259 #define TIM_CCER_CC2E_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6260 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6261 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
sahilmgandhi 18:6a4db94011d3 6262 #define TIM_CCER_CC2P_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6263 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6264 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
sahilmgandhi 18:6a4db94011d3 6265 #define TIM_CCER_CC2NP_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6266 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6267 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6268 #define TIM_CCER_CC3E_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6269 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6270 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
sahilmgandhi 18:6a4db94011d3 6271 #define TIM_CCER_CC3P_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6272 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6273 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
sahilmgandhi 18:6a4db94011d3 6274 #define TIM_CCER_CC3NP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6275 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6276 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6277 #define TIM_CCER_CC4E_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6278 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6279 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
sahilmgandhi 18:6a4db94011d3 6280 #define TIM_CCER_CC4P_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6281 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6282 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
sahilmgandhi 18:6a4db94011d3 6283 #define TIM_CCER_CC4NP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6284 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6285 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6286
sahilmgandhi 18:6a4db94011d3 6287 /******************* Bit definition for TIM_CNT register ********************/
sahilmgandhi 18:6a4db94011d3 6288 #define TIM_CNT_CNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6289 #define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6290 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
sahilmgandhi 18:6a4db94011d3 6291
sahilmgandhi 18:6a4db94011d3 6292 /******************* Bit definition for TIM_PSC register ********************/
sahilmgandhi 18:6a4db94011d3 6293 #define TIM_PSC_PSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6294 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6295 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
sahilmgandhi 18:6a4db94011d3 6296
sahilmgandhi 18:6a4db94011d3 6297 /******************* Bit definition for TIM_ARR register ********************/
sahilmgandhi 18:6a4db94011d3 6298 #define TIM_ARR_ARR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6299 #define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6300 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
sahilmgandhi 18:6a4db94011d3 6301
sahilmgandhi 18:6a4db94011d3 6302 /******************* Bit definition for TIM_CCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 6303 #define TIM_CCR1_CCR1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6304 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6305 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
sahilmgandhi 18:6a4db94011d3 6306
sahilmgandhi 18:6a4db94011d3 6307 /******************* Bit definition for TIM_CCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 6308 #define TIM_CCR2_CCR2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6309 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6310 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
sahilmgandhi 18:6a4db94011d3 6311
sahilmgandhi 18:6a4db94011d3 6312 /******************* Bit definition for TIM_CCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 6313 #define TIM_CCR3_CCR3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6314 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6315 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
sahilmgandhi 18:6a4db94011d3 6316
sahilmgandhi 18:6a4db94011d3 6317 /******************* Bit definition for TIM_CCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 6318 #define TIM_CCR4_CCR4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6319 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6320 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
sahilmgandhi 18:6a4db94011d3 6321
sahilmgandhi 18:6a4db94011d3 6322 /******************* Bit definition for TIM_DCR register ********************/
sahilmgandhi 18:6a4db94011d3 6323 #define TIM_DCR_DBA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6324 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 6325 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
sahilmgandhi 18:6a4db94011d3 6326 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6327 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6328 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6329 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6330 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6331
sahilmgandhi 18:6a4db94011d3 6332 #define TIM_DCR_DBL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6333 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
sahilmgandhi 18:6a4db94011d3 6334 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
sahilmgandhi 18:6a4db94011d3 6335 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6336 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6337 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6338 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6339 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6340
sahilmgandhi 18:6a4db94011d3 6341 /******************* Bit definition for TIM_DMAR register *******************/
sahilmgandhi 18:6a4db94011d3 6342 #define TIM_DMAR_DMAB_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6343 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6344 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
sahilmgandhi 18:6a4db94011d3 6345
sahilmgandhi 18:6a4db94011d3 6346 /******************* Bit definition for TIM_OR register *********************/
sahilmgandhi 18:6a4db94011d3 6347 #define TIM2_OR_ETR_RMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6348 #define TIM2_OR_ETR_RMP_Msk (0x7U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 6349 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
sahilmgandhi 18:6a4db94011d3 6350 #define TIM2_OR_ETR_RMP_0 (0x1U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6351 #define TIM2_OR_ETR_RMP_1 (0x2U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6352 #define TIM2_OR_ETR_RMP_2 (0x4U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6353 #define TIM2_OR_TI4_RMP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6354 #define TIM2_OR_TI4_RMP_Msk (0x3U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 6355 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
sahilmgandhi 18:6a4db94011d3 6356 #define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6357 #define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6358
sahilmgandhi 18:6a4db94011d3 6359 #define TIM21_OR_ETR_RMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6360 #define TIM21_OR_ETR_RMP_Msk (0x3U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 6361 #define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
sahilmgandhi 18:6a4db94011d3 6362 #define TIM21_OR_ETR_RMP_0 (0x1U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6363 #define TIM21_OR_ETR_RMP_1 (0x2U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6364 #define TIM21_OR_TI1_RMP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6365 #define TIM21_OR_TI1_RMP_Msk (0x7U << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
sahilmgandhi 18:6a4db94011d3 6366 #define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
sahilmgandhi 18:6a4db94011d3 6367 #define TIM21_OR_TI1_RMP_0 (0x1U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6368 #define TIM21_OR_TI1_RMP_1 (0x2U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6369 #define TIM21_OR_TI1_RMP_2 (0x4U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6370 #define TIM21_OR_TI2_RMP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6371 #define TIM21_OR_TI2_RMP_Msk (0x1U << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6372 #define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
sahilmgandhi 18:6a4db94011d3 6373
sahilmgandhi 18:6a4db94011d3 6374 #define TIM22_OR_ETR_RMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6375 #define TIM22_OR_ETR_RMP_Msk (0x3U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 6376 #define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
sahilmgandhi 18:6a4db94011d3 6377 #define TIM22_OR_ETR_RMP_0 (0x1U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6378 #define TIM22_OR_ETR_RMP_1 (0x2U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6379 #define TIM22_OR_TI1_RMP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6380 #define TIM22_OR_TI1_RMP_Msk (0x3U << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 6381 #define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
sahilmgandhi 18:6a4db94011d3 6382 #define TIM22_OR_TI1_RMP_0 (0x1U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6383 #define TIM22_OR_TI1_RMP_1 (0x2U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6384
sahilmgandhi 18:6a4db94011d3 6385 #define TIM3_OR_ETR_RMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6386 #define TIM3_OR_ETR_RMP_Msk (0x3U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 6387 #define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
sahilmgandhi 18:6a4db94011d3 6388 #define TIM3_OR_ETR_RMP_0 (0x1U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6389 #define TIM3_OR_ETR_RMP_1 (0x2U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6390 #define TIM3_OR_TI1_RMP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6391 #define TIM3_OR_TI1_RMP_Msk (0x1U << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6392 #define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */
sahilmgandhi 18:6a4db94011d3 6393 #define TIM3_OR_TI2_RMP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6394 #define TIM3_OR_TI2_RMP_Msk (0x1U << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6395 #define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */
sahilmgandhi 18:6a4db94011d3 6396 #define TIM3_OR_TI4_RMP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6397 #define TIM3_OR_TI4_RMP_Msk (0x1U << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6398 #define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */
sahilmgandhi 18:6a4db94011d3 6399
sahilmgandhi 18:6a4db94011d3 6400
sahilmgandhi 18:6a4db94011d3 6401 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6402 /* */
sahilmgandhi 18:6a4db94011d3 6403 /* Touch Sensing Controller (TSC) */
sahilmgandhi 18:6a4db94011d3 6404 /* */
sahilmgandhi 18:6a4db94011d3 6405 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6406 /******************* Bit definition for TSC_CR register *********************/
sahilmgandhi 18:6a4db94011d3 6407 #define TSC_CR_TSCE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6408 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6409 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
sahilmgandhi 18:6a4db94011d3 6410 #define TSC_CR_START_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6411 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6412 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
sahilmgandhi 18:6a4db94011d3 6413 #define TSC_CR_AM_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6414 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6415 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
sahilmgandhi 18:6a4db94011d3 6416 #define TSC_CR_SYNCPOL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6417 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6418 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
sahilmgandhi 18:6a4db94011d3 6419 #define TSC_CR_IODEF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6420 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6421 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
sahilmgandhi 18:6a4db94011d3 6422
sahilmgandhi 18:6a4db94011d3 6423 #define TSC_CR_MCV_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6424 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
sahilmgandhi 18:6a4db94011d3 6425 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
sahilmgandhi 18:6a4db94011d3 6426 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6427 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6428 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6429
sahilmgandhi 18:6a4db94011d3 6430 #define TSC_CR_PGPSC_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6431 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 6432 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
sahilmgandhi 18:6a4db94011d3 6433 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6434 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6435 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6436
sahilmgandhi 18:6a4db94011d3 6437 #define TSC_CR_SSPSC_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6438 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6439 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
sahilmgandhi 18:6a4db94011d3 6440 #define TSC_CR_SSE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6441 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6442 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
sahilmgandhi 18:6a4db94011d3 6443
sahilmgandhi 18:6a4db94011d3 6444 #define TSC_CR_SSD_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6445 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
sahilmgandhi 18:6a4db94011d3 6446 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
sahilmgandhi 18:6a4db94011d3 6447 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6448 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6449 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6450 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6451 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6452 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6453 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6454
sahilmgandhi 18:6a4db94011d3 6455 #define TSC_CR_CTPL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6456 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 6457 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
sahilmgandhi 18:6a4db94011d3 6458 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6459 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6460 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6461 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6462
sahilmgandhi 18:6a4db94011d3 6463 #define TSC_CR_CTPH_Pos (28U)
sahilmgandhi 18:6a4db94011d3 6464 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 6465 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
sahilmgandhi 18:6a4db94011d3 6466 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 6467 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 6468 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 6469 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 6470
sahilmgandhi 18:6a4db94011d3 6471 /******************* Bit definition for TSC_IER register ********************/
sahilmgandhi 18:6a4db94011d3 6472 #define TSC_IER_EOAIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6473 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6474 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
sahilmgandhi 18:6a4db94011d3 6475 #define TSC_IER_MCEIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6476 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6477 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
sahilmgandhi 18:6a4db94011d3 6478
sahilmgandhi 18:6a4db94011d3 6479 /******************* Bit definition for TSC_ICR register ********************/
sahilmgandhi 18:6a4db94011d3 6480 #define TSC_ICR_EOAIC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6481 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6482 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
sahilmgandhi 18:6a4db94011d3 6483 #define TSC_ICR_MCEIC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6484 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6485 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
sahilmgandhi 18:6a4db94011d3 6486
sahilmgandhi 18:6a4db94011d3 6487 /******************* Bit definition for TSC_ISR register ********************/
sahilmgandhi 18:6a4db94011d3 6488 #define TSC_ISR_EOAF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6489 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6490 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
sahilmgandhi 18:6a4db94011d3 6491 #define TSC_ISR_MCEF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6492 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6493 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
sahilmgandhi 18:6a4db94011d3 6494
sahilmgandhi 18:6a4db94011d3 6495 /******************* Bit definition for TSC_IOHCR register ******************/
sahilmgandhi 18:6a4db94011d3 6496 #define TSC_IOHCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6497 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6498 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6499 #define TSC_IOHCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6500 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6501 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6502 #define TSC_IOHCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6503 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6504 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6505 #define TSC_IOHCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6506 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6507 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6508 #define TSC_IOHCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6509 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6510 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6511 #define TSC_IOHCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6512 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6513 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6514 #define TSC_IOHCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6515 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6516 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6517 #define TSC_IOHCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6518 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6519 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6520 #define TSC_IOHCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6521 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6522 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6523 #define TSC_IOHCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6524 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6525 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6526 #define TSC_IOHCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6527 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6528 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6529 #define TSC_IOHCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6530 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6531 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6532 #define TSC_IOHCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6533 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6534 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6535 #define TSC_IOHCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6536 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6537 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6538 #define TSC_IOHCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6539 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6540 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6541 #define TSC_IOHCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6542 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6543 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6544 #define TSC_IOHCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6545 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6546 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6547 #define TSC_IOHCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6548 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6549 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6550 #define TSC_IOHCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6551 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6552 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6553 #define TSC_IOHCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6554 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6555 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6556 #define TSC_IOHCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6557 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6558 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6559 #define TSC_IOHCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6560 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6561 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6562 #define TSC_IOHCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6563 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6564 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6565 #define TSC_IOHCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6566 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6567 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6568 #define TSC_IOHCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6569 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6570 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6571 #define TSC_IOHCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6572 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6573 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6574 #define TSC_IOHCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6575 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6576 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6577 #define TSC_IOHCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6578 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6579 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6580 #define TSC_IOHCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 6581 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 6582 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6583 #define TSC_IOHCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 6584 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 6585 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6586 #define TSC_IOHCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 6587 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 6588 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6589 #define TSC_IOHCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 6590 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 6591 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 6592
sahilmgandhi 18:6a4db94011d3 6593 /******************* Bit definition for TSC_IOASCR register *****************/
sahilmgandhi 18:6a4db94011d3 6594 #define TSC_IOASCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6595 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6596 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6597 #define TSC_IOASCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6598 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6599 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6600 #define TSC_IOASCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6601 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6602 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6603 #define TSC_IOASCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6604 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6605 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6606 #define TSC_IOASCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6607 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6608 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6609 #define TSC_IOASCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6610 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6611 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6612 #define TSC_IOASCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6613 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6614 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6615 #define TSC_IOASCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6616 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6617 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6618 #define TSC_IOASCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6619 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6620 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6621 #define TSC_IOASCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6622 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6623 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6624 #define TSC_IOASCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6625 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6626 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6627 #define TSC_IOASCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6628 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6629 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6630 #define TSC_IOASCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6631 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6632 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6633 #define TSC_IOASCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6634 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6635 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6636 #define TSC_IOASCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6637 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6638 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6639 #define TSC_IOASCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6640 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6641 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6642 #define TSC_IOASCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6643 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6644 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6645 #define TSC_IOASCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6646 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6647 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6648 #define TSC_IOASCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6649 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6650 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6651 #define TSC_IOASCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6652 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6653 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6654 #define TSC_IOASCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6655 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6656 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6657 #define TSC_IOASCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6658 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6659 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6660 #define TSC_IOASCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6661 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6662 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6663 #define TSC_IOASCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6664 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6665 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6666 #define TSC_IOASCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6667 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6668 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6669 #define TSC_IOASCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6670 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6671 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6672 #define TSC_IOASCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6673 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6674 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6675 #define TSC_IOASCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6676 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6677 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6678 #define TSC_IOASCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 6679 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 6680 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6681 #define TSC_IOASCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 6682 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 6683 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6684 #define TSC_IOASCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 6685 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 6686 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6687 #define TSC_IOASCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 6688 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 6689 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 6690
sahilmgandhi 18:6a4db94011d3 6691 /******************* Bit definition for TSC_IOSCR register ******************/
sahilmgandhi 18:6a4db94011d3 6692 #define TSC_IOSCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6693 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6694 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6695 #define TSC_IOSCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6696 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6697 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6698 #define TSC_IOSCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6699 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6700 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6701 #define TSC_IOSCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6702 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6703 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6704 #define TSC_IOSCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6705 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6706 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6707 #define TSC_IOSCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6708 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6709 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6710 #define TSC_IOSCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6711 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6712 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6713 #define TSC_IOSCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6714 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6715 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6716 #define TSC_IOSCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6717 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6718 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6719 #define TSC_IOSCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6720 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6721 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6722 #define TSC_IOSCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6723 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6724 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6725 #define TSC_IOSCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6726 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6727 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6728 #define TSC_IOSCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6729 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6730 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6731 #define TSC_IOSCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6732 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6733 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6734 #define TSC_IOSCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6735 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6736 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6737 #define TSC_IOSCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6738 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6739 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6740 #define TSC_IOSCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6741 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6742 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6743 #define TSC_IOSCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6744 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6745 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6746 #define TSC_IOSCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6747 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6748 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6749 #define TSC_IOSCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6750 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6751 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6752 #define TSC_IOSCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6753 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6754 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6755 #define TSC_IOSCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6756 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6757 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6758 #define TSC_IOSCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6759 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6760 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6761 #define TSC_IOSCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6762 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6763 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6764 #define TSC_IOSCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6765 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6766 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6767 #define TSC_IOSCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6768 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6769 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6770 #define TSC_IOSCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6771 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6772 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6773 #define TSC_IOSCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6774 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6775 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6776 #define TSC_IOSCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 6777 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 6778 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 6779 #define TSC_IOSCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 6780 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 6781 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 6782 #define TSC_IOSCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 6783 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 6784 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 6785 #define TSC_IOSCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 6786 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 6787 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 6788
sahilmgandhi 18:6a4db94011d3 6789 /******************* Bit definition for TSC_IOCCR register ******************/
sahilmgandhi 18:6a4db94011d3 6790 #define TSC_IOCCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6791 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6792 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6793 #define TSC_IOCCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6794 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6795 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6796 #define TSC_IOCCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6797 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6798 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6799 #define TSC_IOCCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6800 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6801 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6802 #define TSC_IOCCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6803 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6804 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6805 #define TSC_IOCCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6806 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6807 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6808 #define TSC_IOCCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6809 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6810 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6811 #define TSC_IOCCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6812 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6813 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6814 #define TSC_IOCCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6815 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6816 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6817 #define TSC_IOCCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6818 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6819 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6820 #define TSC_IOCCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6821 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6822 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6823 #define TSC_IOCCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6824 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6825 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6826 #define TSC_IOCCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6827 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6828 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6829 #define TSC_IOCCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6830 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6831 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6832 #define TSC_IOCCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6833 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6834 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6835 #define TSC_IOCCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6836 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6837 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6838 #define TSC_IOCCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6839 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6840 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6841 #define TSC_IOCCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6842 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6843 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6844 #define TSC_IOCCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6845 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6846 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6847 #define TSC_IOCCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6848 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6849 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6850 #define TSC_IOCCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6851 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6852 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6853 #define TSC_IOCCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6854 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6855 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6856 #define TSC_IOCCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6857 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6858 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6859 #define TSC_IOCCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6860 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6861 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6862 #define TSC_IOCCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6863 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6864 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6865 #define TSC_IOCCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6866 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6867 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6868 #define TSC_IOCCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6869 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6870 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6871 #define TSC_IOCCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6872 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6873 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6874 #define TSC_IOCCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 6875 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 6876 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 6877 #define TSC_IOCCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 6878 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 6879 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 6880 #define TSC_IOCCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 6881 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 6882 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 6883 #define TSC_IOCCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 6884 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 6885 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 6886
sahilmgandhi 18:6a4db94011d3 6887 /******************* Bit definition for TSC_IOGCSR register *****************/
sahilmgandhi 18:6a4db94011d3 6888 #define TSC_IOGCSR_G1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6889 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6890 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
sahilmgandhi 18:6a4db94011d3 6891 #define TSC_IOGCSR_G2E_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6892 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6893 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
sahilmgandhi 18:6a4db94011d3 6894 #define TSC_IOGCSR_G3E_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6895 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6896 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
sahilmgandhi 18:6a4db94011d3 6897 #define TSC_IOGCSR_G4E_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6898 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6899 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
sahilmgandhi 18:6a4db94011d3 6900 #define TSC_IOGCSR_G5E_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6901 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6902 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
sahilmgandhi 18:6a4db94011d3 6903 #define TSC_IOGCSR_G6E_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6904 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6905 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
sahilmgandhi 18:6a4db94011d3 6906 #define TSC_IOGCSR_G7E_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6907 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6908 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
sahilmgandhi 18:6a4db94011d3 6909 #define TSC_IOGCSR_G8E_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6910 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6911 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
sahilmgandhi 18:6a4db94011d3 6912 #define TSC_IOGCSR_G1S_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6913 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6914 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
sahilmgandhi 18:6a4db94011d3 6915 #define TSC_IOGCSR_G2S_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6916 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6917 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
sahilmgandhi 18:6a4db94011d3 6918 #define TSC_IOGCSR_G3S_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6919 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6920 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
sahilmgandhi 18:6a4db94011d3 6921 #define TSC_IOGCSR_G4S_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6922 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6923 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
sahilmgandhi 18:6a4db94011d3 6924 #define TSC_IOGCSR_G5S_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6925 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6926 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
sahilmgandhi 18:6a4db94011d3 6927 #define TSC_IOGCSR_G6S_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6928 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6929 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
sahilmgandhi 18:6a4db94011d3 6930 #define TSC_IOGCSR_G7S_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6931 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6932 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
sahilmgandhi 18:6a4db94011d3 6933 #define TSC_IOGCSR_G8S_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6934 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6935 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
sahilmgandhi 18:6a4db94011d3 6936
sahilmgandhi 18:6a4db94011d3 6937 /******************* Bit definition for TSC_IOGXCR register *****************/
sahilmgandhi 18:6a4db94011d3 6938 #define TSC_IOGXCR_CNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6939 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 6940 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
sahilmgandhi 18:6a4db94011d3 6941
sahilmgandhi 18:6a4db94011d3 6942 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6943 /* */
sahilmgandhi 18:6a4db94011d3 6944 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
sahilmgandhi 18:6a4db94011d3 6945 /* */
sahilmgandhi 18:6a4db94011d3 6946 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6947
sahilmgandhi 18:6a4db94011d3 6948 /*
sahilmgandhi 18:6a4db94011d3 6949 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
sahilmgandhi 18:6a4db94011d3 6950 */
sahilmgandhi 18:6a4db94011d3 6951 /* Note: No specific macro feature on this device */
sahilmgandhi 18:6a4db94011d3 6952
sahilmgandhi 18:6a4db94011d3 6953 /****************** Bit definition for USART_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 6954 #define USART_CR1_UE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6955 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6956 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
sahilmgandhi 18:6a4db94011d3 6957 #define USART_CR1_UESM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6958 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6959 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
sahilmgandhi 18:6a4db94011d3 6960 #define USART_CR1_RE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6961 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6962 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
sahilmgandhi 18:6a4db94011d3 6963 #define USART_CR1_TE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6964 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6965 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
sahilmgandhi 18:6a4db94011d3 6966 #define USART_CR1_IDLEIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6967 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6968 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6969 #define USART_CR1_RXNEIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6970 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6971 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6972 #define USART_CR1_TCIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6973 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6974 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6975 #define USART_CR1_TXEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6976 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6977 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6978 #define USART_CR1_PEIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6979 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6980 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6981 #define USART_CR1_PS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6982 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6983 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
sahilmgandhi 18:6a4db94011d3 6984 #define USART_CR1_PCE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6985 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6986 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
sahilmgandhi 18:6a4db94011d3 6987 #define USART_CR1_WAKE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6988 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6989 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
sahilmgandhi 18:6a4db94011d3 6990 #define USART_CR1_M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6991 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
sahilmgandhi 18:6a4db94011d3 6992 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
sahilmgandhi 18:6a4db94011d3 6993 #define USART_CR1_M0_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6994 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6995 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
sahilmgandhi 18:6a4db94011d3 6996 #define USART_CR1_MME_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6997 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6998 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
sahilmgandhi 18:6a4db94011d3 6999 #define USART_CR1_CMIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7000 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7001 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
sahilmgandhi 18:6a4db94011d3 7002 #define USART_CR1_OVER8_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7003 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7004 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
sahilmgandhi 18:6a4db94011d3 7005 #define USART_CR1_DEDT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7006 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
sahilmgandhi 18:6a4db94011d3 7007 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
sahilmgandhi 18:6a4db94011d3 7008 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7009 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7010 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7011 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7012 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7013 #define USART_CR1_DEAT_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7014 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
sahilmgandhi 18:6a4db94011d3 7015 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
sahilmgandhi 18:6a4db94011d3 7016 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7017 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7018 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7019 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7020 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 7021 #define USART_CR1_RTOIE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 7022 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 7023 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
sahilmgandhi 18:6a4db94011d3 7024 #define USART_CR1_EOBIE_Pos (27U)
sahilmgandhi 18:6a4db94011d3 7025 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 7026 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
sahilmgandhi 18:6a4db94011d3 7027 #define USART_CR1_M1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7028 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7029 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
sahilmgandhi 18:6a4db94011d3 7030 /****************** Bit definition for USART_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 7031 #define USART_CR2_ADDM7_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7032 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7033 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
sahilmgandhi 18:6a4db94011d3 7034 #define USART_CR2_LBDL_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7035 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7036 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
sahilmgandhi 18:6a4db94011d3 7037 #define USART_CR2_LBDIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7038 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7039 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 7040 #define USART_CR2_LBCL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7041 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7042 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
sahilmgandhi 18:6a4db94011d3 7043 #define USART_CR2_CPHA_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7044 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7045 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
sahilmgandhi 18:6a4db94011d3 7046 #define USART_CR2_CPOL_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7047 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7048 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
sahilmgandhi 18:6a4db94011d3 7049 #define USART_CR2_CLKEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7050 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7051 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
sahilmgandhi 18:6a4db94011d3 7052 #define USART_CR2_STOP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7053 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 7054 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
sahilmgandhi 18:6a4db94011d3 7055 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7056 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7057 #define USART_CR2_LINEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7058 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7059 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
sahilmgandhi 18:6a4db94011d3 7060 #define USART_CR2_SWAP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7061 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7062 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
sahilmgandhi 18:6a4db94011d3 7063 #define USART_CR2_RXINV_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7064 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7065 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
sahilmgandhi 18:6a4db94011d3 7066 #define USART_CR2_TXINV_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7067 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7068 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
sahilmgandhi 18:6a4db94011d3 7069 #define USART_CR2_DATAINV_Pos (18U)
sahilmgandhi 18:6a4db94011d3 7070 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7071 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
sahilmgandhi 18:6a4db94011d3 7072 #define USART_CR2_MSBFIRST_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7073 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7074 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
sahilmgandhi 18:6a4db94011d3 7075 #define USART_CR2_ABREN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7076 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7077 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
sahilmgandhi 18:6a4db94011d3 7078 #define USART_CR2_ABRMODE_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7079 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 7080 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
sahilmgandhi 18:6a4db94011d3 7081 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7082 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7083 #define USART_CR2_RTOEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 7084 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7085 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
sahilmgandhi 18:6a4db94011d3 7086 #define USART_CR2_ADD_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7087 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 7088 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
sahilmgandhi 18:6a4db94011d3 7089
sahilmgandhi 18:6a4db94011d3 7090 /****************** Bit definition for USART_CR3 register *******************/
sahilmgandhi 18:6a4db94011d3 7091 #define USART_CR3_EIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7092 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7093 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 7094 #define USART_CR3_IREN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7095 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7096 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
sahilmgandhi 18:6a4db94011d3 7097 #define USART_CR3_IRLP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7098 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7099 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
sahilmgandhi 18:6a4db94011d3 7100 #define USART_CR3_HDSEL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7101 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7102 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
sahilmgandhi 18:6a4db94011d3 7103 #define USART_CR3_NACK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7104 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7105 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
sahilmgandhi 18:6a4db94011d3 7106 #define USART_CR3_SCEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7107 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7108 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
sahilmgandhi 18:6a4db94011d3 7109 #define USART_CR3_DMAR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7110 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7111 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
sahilmgandhi 18:6a4db94011d3 7112 #define USART_CR3_DMAT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7113 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7114 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
sahilmgandhi 18:6a4db94011d3 7115 #define USART_CR3_RTSE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7116 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7117 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
sahilmgandhi 18:6a4db94011d3 7118 #define USART_CR3_CTSE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7119 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7120 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
sahilmgandhi 18:6a4db94011d3 7121 #define USART_CR3_CTSIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7122 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7123 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 7124 #define USART_CR3_ONEBIT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7125 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7126 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
sahilmgandhi 18:6a4db94011d3 7127 #define USART_CR3_OVRDIS_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7128 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7129 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
sahilmgandhi 18:6a4db94011d3 7130 #define USART_CR3_DDRE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7131 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7132 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
sahilmgandhi 18:6a4db94011d3 7133 #define USART_CR3_DEM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7134 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7135 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
sahilmgandhi 18:6a4db94011d3 7136 #define USART_CR3_DEP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7137 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7138 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
sahilmgandhi 18:6a4db94011d3 7139 #define USART_CR3_SCARCNT_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7140 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 7141 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
sahilmgandhi 18:6a4db94011d3 7142 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7143 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7144 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7145 #define USART_CR3_WUS_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7146 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 7147 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
sahilmgandhi 18:6a4db94011d3 7148 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7149 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7150 #define USART_CR3_WUFIE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 7151 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7152 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 7153 #define USART_CR3_UCESM_Pos (23U)
sahilmgandhi 18:6a4db94011d3 7154 #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7155 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
sahilmgandhi 18:6a4db94011d3 7156
sahilmgandhi 18:6a4db94011d3 7157 /****************** Bit definition for USART_BRR register *******************/
sahilmgandhi 18:6a4db94011d3 7158 #define USART_BRR_DIV_FRACTION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7159 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7160 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
sahilmgandhi 18:6a4db94011d3 7161 #define USART_BRR_DIV_MANTISSA_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7162 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 7163 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
sahilmgandhi 18:6a4db94011d3 7164
sahilmgandhi 18:6a4db94011d3 7165 /****************** Bit definition for USART_GTPR register ******************/
sahilmgandhi 18:6a4db94011d3 7166 #define USART_GTPR_PSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7167 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 7168 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
sahilmgandhi 18:6a4db94011d3 7169 #define USART_GTPR_GT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7170 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7171 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
sahilmgandhi 18:6a4db94011d3 7172
sahilmgandhi 18:6a4db94011d3 7173
sahilmgandhi 18:6a4db94011d3 7174 /******************* Bit definition for USART_RTOR register *****************/
sahilmgandhi 18:6a4db94011d3 7175 #define USART_RTOR_RTO_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7176 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
sahilmgandhi 18:6a4db94011d3 7177 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
sahilmgandhi 18:6a4db94011d3 7178 #define USART_RTOR_BLEN_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7179 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 7180 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
sahilmgandhi 18:6a4db94011d3 7181
sahilmgandhi 18:6a4db94011d3 7182 /******************* Bit definition for USART_RQR register ******************/
sahilmgandhi 18:6a4db94011d3 7183 #define USART_RQR_ABRRQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7184 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7185 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
sahilmgandhi 18:6a4db94011d3 7186 #define USART_RQR_SBKRQ_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7187 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7188 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
sahilmgandhi 18:6a4db94011d3 7189 #define USART_RQR_MMRQ_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7190 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7191 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
sahilmgandhi 18:6a4db94011d3 7192 #define USART_RQR_RXFRQ_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7193 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7194 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
sahilmgandhi 18:6a4db94011d3 7195 #define USART_RQR_TXFRQ_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7196 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7197 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
sahilmgandhi 18:6a4db94011d3 7198
sahilmgandhi 18:6a4db94011d3 7199 /******************* Bit definition for USART_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 7200 #define USART_ISR_PE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7201 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7202 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
sahilmgandhi 18:6a4db94011d3 7203 #define USART_ISR_FE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7204 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7205 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
sahilmgandhi 18:6a4db94011d3 7206 #define USART_ISR_NE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7207 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7208 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
sahilmgandhi 18:6a4db94011d3 7209 #define USART_ISR_ORE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7210 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7211 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
sahilmgandhi 18:6a4db94011d3 7212 #define USART_ISR_IDLE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7213 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7214 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
sahilmgandhi 18:6a4db94011d3 7215 #define USART_ISR_RXNE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7216 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7217 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
sahilmgandhi 18:6a4db94011d3 7218 #define USART_ISR_TC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7219 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7220 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
sahilmgandhi 18:6a4db94011d3 7221 #define USART_ISR_TXE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7222 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7223 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
sahilmgandhi 18:6a4db94011d3 7224 #define USART_ISR_LBDF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7225 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7226 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
sahilmgandhi 18:6a4db94011d3 7227 #define USART_ISR_CTSIF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7228 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7229 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
sahilmgandhi 18:6a4db94011d3 7230 #define USART_ISR_CTS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7231 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7232 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
sahilmgandhi 18:6a4db94011d3 7233 #define USART_ISR_RTOF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7234 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7235 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
sahilmgandhi 18:6a4db94011d3 7236 #define USART_ISR_EOBF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7237 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7238 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
sahilmgandhi 18:6a4db94011d3 7239 #define USART_ISR_ABRE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7240 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7241 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
sahilmgandhi 18:6a4db94011d3 7242 #define USART_ISR_ABRF_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7243 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7244 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
sahilmgandhi 18:6a4db94011d3 7245 #define USART_ISR_BUSY_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7246 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7247 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
sahilmgandhi 18:6a4db94011d3 7248 #define USART_ISR_CMF_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7249 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7250 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
sahilmgandhi 18:6a4db94011d3 7251 #define USART_ISR_SBKF_Pos (18U)
sahilmgandhi 18:6a4db94011d3 7252 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7253 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
sahilmgandhi 18:6a4db94011d3 7254 #define USART_ISR_RWU_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7255 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7256 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
sahilmgandhi 18:6a4db94011d3 7257 #define USART_ISR_WUF_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7258 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7259 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
sahilmgandhi 18:6a4db94011d3 7260 #define USART_ISR_TEACK_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7261 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7262 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
sahilmgandhi 18:6a4db94011d3 7263 #define USART_ISR_REACK_Pos (22U)
sahilmgandhi 18:6a4db94011d3 7264 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7265 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
sahilmgandhi 18:6a4db94011d3 7266
sahilmgandhi 18:6a4db94011d3 7267 /******************* Bit definition for USART_ICR register ******************/
sahilmgandhi 18:6a4db94011d3 7268 #define USART_ICR_PECF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7269 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7270 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
sahilmgandhi 18:6a4db94011d3 7271 #define USART_ICR_FECF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7272 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7273 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
sahilmgandhi 18:6a4db94011d3 7274 #define USART_ICR_NCF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7275 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7276 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
sahilmgandhi 18:6a4db94011d3 7277 #define USART_ICR_ORECF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7278 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7279 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
sahilmgandhi 18:6a4db94011d3 7280 #define USART_ICR_IDLECF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7281 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7282 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
sahilmgandhi 18:6a4db94011d3 7283 #define USART_ICR_TCCF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7284 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7285 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
sahilmgandhi 18:6a4db94011d3 7286 #define USART_ICR_LBDCF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7287 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7288 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
sahilmgandhi 18:6a4db94011d3 7289 #define USART_ICR_CTSCF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7290 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7291 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
sahilmgandhi 18:6a4db94011d3 7292 #define USART_ICR_RTOCF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7293 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7294 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
sahilmgandhi 18:6a4db94011d3 7295 #define USART_ICR_EOBCF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7296 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7297 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
sahilmgandhi 18:6a4db94011d3 7298 #define USART_ICR_CMCF_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7299 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7300 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
sahilmgandhi 18:6a4db94011d3 7301 #define USART_ICR_WUCF_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7302 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7303 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
sahilmgandhi 18:6a4db94011d3 7304
sahilmgandhi 18:6a4db94011d3 7305 /******************* Bit definition for USART_RDR register ******************/
sahilmgandhi 18:6a4db94011d3 7306 #define USART_RDR_RDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7307 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
sahilmgandhi 18:6a4db94011d3 7308 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
sahilmgandhi 18:6a4db94011d3 7309
sahilmgandhi 18:6a4db94011d3 7310 /******************* Bit definition for USART_TDR register ******************/
sahilmgandhi 18:6a4db94011d3 7311 #define USART_TDR_TDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7312 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
sahilmgandhi 18:6a4db94011d3 7313 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
sahilmgandhi 18:6a4db94011d3 7314
sahilmgandhi 18:6a4db94011d3 7315 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7316 /* */
sahilmgandhi 18:6a4db94011d3 7317 /* USB Device General registers */
sahilmgandhi 18:6a4db94011d3 7318 /* */
sahilmgandhi 18:6a4db94011d3 7319 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7320 #define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
sahilmgandhi 18:6a4db94011d3 7321 #define USB_PMAADDR_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7322 #define USB_PMAADDR_Msk (0x20003U << USB_PMAADDR_Pos) /*!< 0x40006000 */
sahilmgandhi 18:6a4db94011d3 7323 #define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
sahilmgandhi 18:6a4db94011d3 7324
sahilmgandhi 18:6a4db94011d3 7325 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
sahilmgandhi 18:6a4db94011d3 7326 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
sahilmgandhi 18:6a4db94011d3 7327 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
sahilmgandhi 18:6a4db94011d3 7328 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
sahilmgandhi 18:6a4db94011d3 7329 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
sahilmgandhi 18:6a4db94011d3 7330 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
sahilmgandhi 18:6a4db94011d3 7331 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
sahilmgandhi 18:6a4db94011d3 7332
sahilmgandhi 18:6a4db94011d3 7333 /**************************** ISTR interrupt events *************************/
sahilmgandhi 18:6a4db94011d3 7334 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7335 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7336 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7337 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7338 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7339 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7340 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7341 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
sahilmgandhi 18:6a4db94011d3 7342 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
sahilmgandhi 18:6a4db94011d3 7343 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
sahilmgandhi 18:6a4db94011d3 7344 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
sahilmgandhi 18:6a4db94011d3 7345
sahilmgandhi 18:6a4db94011d3 7346 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
sahilmgandhi 18:6a4db94011d3 7347 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
sahilmgandhi 18:6a4db94011d3 7348 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
sahilmgandhi 18:6a4db94011d3 7349 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
sahilmgandhi 18:6a4db94011d3 7350 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
sahilmgandhi 18:6a4db94011d3 7351 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
sahilmgandhi 18:6a4db94011d3 7352 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
sahilmgandhi 18:6a4db94011d3 7353 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
sahilmgandhi 18:6a4db94011d3 7354 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
sahilmgandhi 18:6a4db94011d3 7355 /************************* CNTR control register bits definitions ***********/
sahilmgandhi 18:6a4db94011d3 7356 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
sahilmgandhi 18:6a4db94011d3 7357 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
sahilmgandhi 18:6a4db94011d3 7358 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
sahilmgandhi 18:6a4db94011d3 7359 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
sahilmgandhi 18:6a4db94011d3 7360 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
sahilmgandhi 18:6a4db94011d3 7361 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
sahilmgandhi 18:6a4db94011d3 7362 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
sahilmgandhi 18:6a4db94011d3 7363 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
sahilmgandhi 18:6a4db94011d3 7364 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
sahilmgandhi 18:6a4db94011d3 7365 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
sahilmgandhi 18:6a4db94011d3 7366 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
sahilmgandhi 18:6a4db94011d3 7367 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
sahilmgandhi 18:6a4db94011d3 7368 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
sahilmgandhi 18:6a4db94011d3 7369 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
sahilmgandhi 18:6a4db94011d3 7370 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
sahilmgandhi 18:6a4db94011d3 7371 /************************* BCDR control register bits definitions ***********/
sahilmgandhi 18:6a4db94011d3 7372 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
sahilmgandhi 18:6a4db94011d3 7373 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
sahilmgandhi 18:6a4db94011d3 7374 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
sahilmgandhi 18:6a4db94011d3 7375 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
sahilmgandhi 18:6a4db94011d3 7376 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
sahilmgandhi 18:6a4db94011d3 7377 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
sahilmgandhi 18:6a4db94011d3 7378 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
sahilmgandhi 18:6a4db94011d3 7379 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
sahilmgandhi 18:6a4db94011d3 7380 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
sahilmgandhi 18:6a4db94011d3 7381 /*************************** LPM register bits definitions ******************/
sahilmgandhi 18:6a4db94011d3 7382 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
sahilmgandhi 18:6a4db94011d3 7383 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
sahilmgandhi 18:6a4db94011d3 7384 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
sahilmgandhi 18:6a4db94011d3 7385 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
sahilmgandhi 18:6a4db94011d3 7386 /******************** FNR Frame Number Register bit definitions ************/
sahilmgandhi 18:6a4db94011d3 7387 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
sahilmgandhi 18:6a4db94011d3 7388 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
sahilmgandhi 18:6a4db94011d3 7389 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
sahilmgandhi 18:6a4db94011d3 7390 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
sahilmgandhi 18:6a4db94011d3 7391 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
sahilmgandhi 18:6a4db94011d3 7392 /******************** DADDR Device ADDRess bit definitions ****************/
sahilmgandhi 18:6a4db94011d3 7393 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
sahilmgandhi 18:6a4db94011d3 7394 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
sahilmgandhi 18:6a4db94011d3 7395 /****************************** Endpoint register *************************/
sahilmgandhi 18:6a4db94011d3 7396 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
sahilmgandhi 18:6a4db94011d3 7397 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
sahilmgandhi 18:6a4db94011d3 7398 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
sahilmgandhi 18:6a4db94011d3 7399 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
sahilmgandhi 18:6a4db94011d3 7400 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
sahilmgandhi 18:6a4db94011d3 7401 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
sahilmgandhi 18:6a4db94011d3 7402 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
sahilmgandhi 18:6a4db94011d3 7403 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
sahilmgandhi 18:6a4db94011d3 7404 /* bit positions */
sahilmgandhi 18:6a4db94011d3 7405 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
sahilmgandhi 18:6a4db94011d3 7406 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
sahilmgandhi 18:6a4db94011d3 7407 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
sahilmgandhi 18:6a4db94011d3 7408 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
sahilmgandhi 18:6a4db94011d3 7409 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
sahilmgandhi 18:6a4db94011d3 7410 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
sahilmgandhi 18:6a4db94011d3 7411 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
sahilmgandhi 18:6a4db94011d3 7412 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
sahilmgandhi 18:6a4db94011d3 7413 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
sahilmgandhi 18:6a4db94011d3 7414 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
sahilmgandhi 18:6a4db94011d3 7415
sahilmgandhi 18:6a4db94011d3 7416 /* EndPoint REGister MASK (no toggle fields) */
sahilmgandhi 18:6a4db94011d3 7417 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
sahilmgandhi 18:6a4db94011d3 7418 /*!< EP_TYPE[1:0] EndPoint TYPE */
sahilmgandhi 18:6a4db94011d3 7419 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
sahilmgandhi 18:6a4db94011d3 7420 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
sahilmgandhi 18:6a4db94011d3 7421 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
sahilmgandhi 18:6a4db94011d3 7422 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
sahilmgandhi 18:6a4db94011d3 7423 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
sahilmgandhi 18:6a4db94011d3 7424 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
sahilmgandhi 18:6a4db94011d3 7425
sahilmgandhi 18:6a4db94011d3 7426 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
sahilmgandhi 18:6a4db94011d3 7427 /*!< STAT_TX[1:0] STATus for TX transfer */
sahilmgandhi 18:6a4db94011d3 7428 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
sahilmgandhi 18:6a4db94011d3 7429 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
sahilmgandhi 18:6a4db94011d3 7430 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
sahilmgandhi 18:6a4db94011d3 7431 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
sahilmgandhi 18:6a4db94011d3 7432 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
sahilmgandhi 18:6a4db94011d3 7433 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
sahilmgandhi 18:6a4db94011d3 7434 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
sahilmgandhi 18:6a4db94011d3 7435 /*!< STAT_RX[1:0] STATus for RX transfer */
sahilmgandhi 18:6a4db94011d3 7436 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
sahilmgandhi 18:6a4db94011d3 7437 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
sahilmgandhi 18:6a4db94011d3 7438 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
sahilmgandhi 18:6a4db94011d3 7439 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
sahilmgandhi 18:6a4db94011d3 7440 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
sahilmgandhi 18:6a4db94011d3 7441 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
sahilmgandhi 18:6a4db94011d3 7442 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
sahilmgandhi 18:6a4db94011d3 7443
sahilmgandhi 18:6a4db94011d3 7444 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7445 /* */
sahilmgandhi 18:6a4db94011d3 7446 /* Window WATCHDOG (WWDG) */
sahilmgandhi 18:6a4db94011d3 7447 /* */
sahilmgandhi 18:6a4db94011d3 7448 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7449
sahilmgandhi 18:6a4db94011d3 7450 /******************* Bit definition for WWDG_CR register ********************/
sahilmgandhi 18:6a4db94011d3 7451 #define WWDG_CR_T_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7452 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 7453 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
sahilmgandhi 18:6a4db94011d3 7454 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7455 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7456 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7457 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7458 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7459 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7460 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7461
sahilmgandhi 18:6a4db94011d3 7462 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 7463 #define WWDG_CR_T0 WWDG_CR_T_0
sahilmgandhi 18:6a4db94011d3 7464 #define WWDG_CR_T1 WWDG_CR_T_1
sahilmgandhi 18:6a4db94011d3 7465 #define WWDG_CR_T2 WWDG_CR_T_2
sahilmgandhi 18:6a4db94011d3 7466 #define WWDG_CR_T3 WWDG_CR_T_3
sahilmgandhi 18:6a4db94011d3 7467 #define WWDG_CR_T4 WWDG_CR_T_4
sahilmgandhi 18:6a4db94011d3 7468 #define WWDG_CR_T5 WWDG_CR_T_5
sahilmgandhi 18:6a4db94011d3 7469 #define WWDG_CR_T6 WWDG_CR_T_6
sahilmgandhi 18:6a4db94011d3 7470
sahilmgandhi 18:6a4db94011d3 7471 #define WWDG_CR_WDGA_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7472 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7473 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
sahilmgandhi 18:6a4db94011d3 7474
sahilmgandhi 18:6a4db94011d3 7475 /******************* Bit definition for WWDG_CFR register *******************/
sahilmgandhi 18:6a4db94011d3 7476 #define WWDG_CFR_W_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7477 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 7478 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
sahilmgandhi 18:6a4db94011d3 7479 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7480 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7481 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7482 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7483 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7484 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7485 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7486
sahilmgandhi 18:6a4db94011d3 7487 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 7488 #define WWDG_CFR_W0 WWDG_CFR_W_0
sahilmgandhi 18:6a4db94011d3 7489 #define WWDG_CFR_W1 WWDG_CFR_W_1
sahilmgandhi 18:6a4db94011d3 7490 #define WWDG_CFR_W2 WWDG_CFR_W_2
sahilmgandhi 18:6a4db94011d3 7491 #define WWDG_CFR_W3 WWDG_CFR_W_3
sahilmgandhi 18:6a4db94011d3 7492 #define WWDG_CFR_W4 WWDG_CFR_W_4
sahilmgandhi 18:6a4db94011d3 7493 #define WWDG_CFR_W5 WWDG_CFR_W_5
sahilmgandhi 18:6a4db94011d3 7494 #define WWDG_CFR_W6 WWDG_CFR_W_6
sahilmgandhi 18:6a4db94011d3 7495
sahilmgandhi 18:6a4db94011d3 7496 #define WWDG_CFR_WDGTB_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7497 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
sahilmgandhi 18:6a4db94011d3 7498 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
sahilmgandhi 18:6a4db94011d3 7499 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7500 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7501
sahilmgandhi 18:6a4db94011d3 7502 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 7503 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
sahilmgandhi 18:6a4db94011d3 7504 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
sahilmgandhi 18:6a4db94011d3 7505
sahilmgandhi 18:6a4db94011d3 7506 #define WWDG_CFR_EWI_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7507 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7508 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 7509
sahilmgandhi 18:6a4db94011d3 7510 /******************* Bit definition for WWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 7511 #define WWDG_SR_EWIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7512 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7513 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 7514
sahilmgandhi 18:6a4db94011d3 7515 /**
sahilmgandhi 18:6a4db94011d3 7516 * @}
sahilmgandhi 18:6a4db94011d3 7517 */
sahilmgandhi 18:6a4db94011d3 7518
sahilmgandhi 18:6a4db94011d3 7519 /**
sahilmgandhi 18:6a4db94011d3 7520 * @}
sahilmgandhi 18:6a4db94011d3 7521 */
sahilmgandhi 18:6a4db94011d3 7522
sahilmgandhi 18:6a4db94011d3 7523 /** @addtogroup Exported_macros
sahilmgandhi 18:6a4db94011d3 7524 * @{
sahilmgandhi 18:6a4db94011d3 7525 */
sahilmgandhi 18:6a4db94011d3 7526
sahilmgandhi 18:6a4db94011d3 7527 /******************************* ADC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7528 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
sahilmgandhi 18:6a4db94011d3 7529 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
sahilmgandhi 18:6a4db94011d3 7530
sahilmgandhi 18:6a4db94011d3 7531 /******************************* COMP Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7532 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
sahilmgandhi 18:6a4db94011d3 7533 ((INSTANCE) == COMP2))
sahilmgandhi 18:6a4db94011d3 7534
sahilmgandhi 18:6a4db94011d3 7535 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
sahilmgandhi 18:6a4db94011d3 7536
sahilmgandhi 18:6a4db94011d3 7537 /******************************* CRC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7538 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
sahilmgandhi 18:6a4db94011d3 7539
sahilmgandhi 18:6a4db94011d3 7540 /******************************* DAC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 7541 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
sahilmgandhi 18:6a4db94011d3 7542
sahilmgandhi 18:6a4db94011d3 7543 /******************************* DMA Instances *********************************/
sahilmgandhi 18:6a4db94011d3 7544 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
sahilmgandhi 18:6a4db94011d3 7545 ((INSTANCE) == DMA1_Channel2) || \
sahilmgandhi 18:6a4db94011d3 7546 ((INSTANCE) == DMA1_Channel3) || \
sahilmgandhi 18:6a4db94011d3 7547 ((INSTANCE) == DMA1_Channel4) || \
sahilmgandhi 18:6a4db94011d3 7548 ((INSTANCE) == DMA1_Channel5) || \
sahilmgandhi 18:6a4db94011d3 7549 ((INSTANCE) == DMA1_Channel6) || \
sahilmgandhi 18:6a4db94011d3 7550 ((INSTANCE) == DMA1_Channel7))
sahilmgandhi 18:6a4db94011d3 7551
sahilmgandhi 18:6a4db94011d3 7552 /******************************* GPIO Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7553 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 7554 ((INSTANCE) == GPIOB) || \
sahilmgandhi 18:6a4db94011d3 7555 ((INSTANCE) == GPIOC) || \
sahilmgandhi 18:6a4db94011d3 7556 ((INSTANCE) == GPIOD) || \
sahilmgandhi 18:6a4db94011d3 7557 ((INSTANCE) == GPIOE) || \
sahilmgandhi 18:6a4db94011d3 7558 ((INSTANCE) == GPIOH))
sahilmgandhi 18:6a4db94011d3 7559
sahilmgandhi 18:6a4db94011d3 7560 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 7561 ((INSTANCE) == GPIOB) || \
sahilmgandhi 18:6a4db94011d3 7562 ((INSTANCE) == GPIOC) || \
sahilmgandhi 18:6a4db94011d3 7563 ((INSTANCE) == GPIOD) || \
sahilmgandhi 18:6a4db94011d3 7564 ((INSTANCE) == GPIOE) || \
sahilmgandhi 18:6a4db94011d3 7565 ((INSTANCE) == GPIOH))
sahilmgandhi 18:6a4db94011d3 7566
sahilmgandhi 18:6a4db94011d3 7567 /******************************** I2C Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7568 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 7569 ((INSTANCE) == I2C2) || \
sahilmgandhi 18:6a4db94011d3 7570 ((INSTANCE) == I2C3))
sahilmgandhi 18:6a4db94011d3 7571
sahilmgandhi 18:6a4db94011d3 7572 /****************** I2C Instances : wakeup capability from stop modes *********/
sahilmgandhi 18:6a4db94011d3 7573 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 7574 ((INSTANCE) == I2C3))
sahilmgandhi 18:6a4db94011d3 7575
sahilmgandhi 18:6a4db94011d3 7576
sahilmgandhi 18:6a4db94011d3 7577 /******************************** I2S Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7578 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
sahilmgandhi 18:6a4db94011d3 7579
sahilmgandhi 18:6a4db94011d3 7580 /******************************* RNG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7581 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
sahilmgandhi 18:6a4db94011d3 7582
sahilmgandhi 18:6a4db94011d3 7583 /****************************** RTC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 7584 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
sahilmgandhi 18:6a4db94011d3 7585
sahilmgandhi 18:6a4db94011d3 7586 /******************************** SMBUS Instances *****************************/
sahilmgandhi 18:6a4db94011d3 7587 #define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 7588 ((INSTANCE) == I2C3))
sahilmgandhi 18:6a4db94011d3 7589
sahilmgandhi 18:6a4db94011d3 7590 /******************************** SPI Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7591 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 7592 ((INSTANCE) == SPI2))
sahilmgandhi 18:6a4db94011d3 7593
sahilmgandhi 18:6a4db94011d3 7594 /****************** LPTIM Instances : All supported instances *****************/
sahilmgandhi 18:6a4db94011d3 7595 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
sahilmgandhi 18:6a4db94011d3 7596
sahilmgandhi 18:6a4db94011d3 7597 /****************** TIM Instances : All supported instances *******************/
sahilmgandhi 18:6a4db94011d3 7598 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7599 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7600 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 7601 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 7602 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7603 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7604
sahilmgandhi 18:6a4db94011d3 7605 /****************** TIM Instances : supporting counting mode selection ********/
sahilmgandhi 18:6a4db94011d3 7606 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7607 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7608 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7609 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7610
sahilmgandhi 18:6a4db94011d3 7611 /****************** TIM Instances : supporting clock division *****************/
sahilmgandhi 18:6a4db94011d3 7612 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7613 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7614 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7615 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7616
sahilmgandhi 18:6a4db94011d3 7617 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
sahilmgandhi 18:6a4db94011d3 7618 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7619 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7620 ((INSTANCE) == TIM21))
sahilmgandhi 18:6a4db94011d3 7621
sahilmgandhi 18:6a4db94011d3 7622 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
sahilmgandhi 18:6a4db94011d3 7623 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7624 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7625 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7626 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7627
sahilmgandhi 18:6a4db94011d3 7628 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
sahilmgandhi 18:6a4db94011d3 7629 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7630 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7631 ((INSTANCE) == TIM21))
sahilmgandhi 18:6a4db94011d3 7632
sahilmgandhi 18:6a4db94011d3 7633 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
sahilmgandhi 18:6a4db94011d3 7634 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7635 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7636 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7637 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7638
sahilmgandhi 18:6a4db94011d3 7639 /************* TIM Instances : at least 1 capture/compare channel *************/
sahilmgandhi 18:6a4db94011d3 7640 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7641 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7642 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7643 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7644
sahilmgandhi 18:6a4db94011d3 7645 /************ TIM Instances : at least 2 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 7646 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7647 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7648 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7649 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7650
sahilmgandhi 18:6a4db94011d3 7651 /************ TIM Instances : at least 3 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 7652 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7653 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7654
sahilmgandhi 18:6a4db94011d3 7655 /************ TIM Instances : at least 4 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 7656 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7657 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7658
sahilmgandhi 18:6a4db94011d3 7659 /******************** TIM Instances : Advanced-control timers *****************/
sahilmgandhi 18:6a4db94011d3 7660
sahilmgandhi 18:6a4db94011d3 7661 /******************* TIM Instances : Timer input XOR function *****************/
sahilmgandhi 18:6a4db94011d3 7662 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7663 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7664
sahilmgandhi 18:6a4db94011d3 7665 /****************** TIM Instances : DMA requests generation (UDE) *************/
sahilmgandhi 18:6a4db94011d3 7666 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7667 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7668 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 7669 ((INSTANCE) == TIM7))
sahilmgandhi 18:6a4db94011d3 7670
sahilmgandhi 18:6a4db94011d3 7671 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
sahilmgandhi 18:6a4db94011d3 7672 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7673 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7674
sahilmgandhi 18:6a4db94011d3 7675 /************ TIM Instances : DMA requests generation (COMDE) *****************/
sahilmgandhi 18:6a4db94011d3 7676 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7677 (INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7678
sahilmgandhi 18:6a4db94011d3 7679 /******************** TIM Instances : DMA burst feature ***********************/
sahilmgandhi 18:6a4db94011d3 7680 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7681 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7682
sahilmgandhi 18:6a4db94011d3 7683 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
sahilmgandhi 18:6a4db94011d3 7684 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7685 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7686 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 7687 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 7688 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7689 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7690
sahilmgandhi 18:6a4db94011d3 7691 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
sahilmgandhi 18:6a4db94011d3 7692 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7693 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7694 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7695 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7696
sahilmgandhi 18:6a4db94011d3 7697 /********************** TIM Instances : 32 bit Counter ************************/
sahilmgandhi 18:6a4db94011d3 7698
sahilmgandhi 18:6a4db94011d3 7699 /***************** TIM Instances : external trigger input availabe ************/
sahilmgandhi 18:6a4db94011d3 7700 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7701 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7702 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7703 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7704
sahilmgandhi 18:6a4db94011d3 7705 /****************** TIM Instances : remapping capability **********************/
sahilmgandhi 18:6a4db94011d3 7706 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7707 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7708 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7709 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7710
sahilmgandhi 18:6a4db94011d3 7711 /****************** TIM Instances : supporting encoder interface **************/
sahilmgandhi 18:6a4db94011d3 7712 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7713 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7714 ((INSTANCE) == TIM21) || \
sahilmgandhi 18:6a4db94011d3 7715 ((INSTANCE) == TIM22))
sahilmgandhi 18:6a4db94011d3 7716
sahilmgandhi 18:6a4db94011d3 7717 /******************* TIM Instances : output(s) OCXEC register *****************/
sahilmgandhi 18:6a4db94011d3 7718 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7719 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 7720
sahilmgandhi 18:6a4db94011d3 7721 /******************* TIM Instances : output(s) available **********************/
sahilmgandhi 18:6a4db94011d3 7722 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 7723 (((((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7724 ((INSTANCE) == TIM3)) \
sahilmgandhi 18:6a4db94011d3 7725 && \
sahilmgandhi 18:6a4db94011d3 7726 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7727 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 7728 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 7729 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 7730 || \
sahilmgandhi 18:6a4db94011d3 7731 (((INSTANCE) == TIM21) && \
sahilmgandhi 18:6a4db94011d3 7732 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7733 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 7734 || \
sahilmgandhi 18:6a4db94011d3 7735 (((INSTANCE) == TIM22) && \
sahilmgandhi 18:6a4db94011d3 7736 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7737 ((CHANNEL) == TIM_CHANNEL_2))))
sahilmgandhi 18:6a4db94011d3 7738
sahilmgandhi 18:6a4db94011d3 7739 /******************** UART Instances : Asynchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 7740 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7741 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 7742 ((INSTANCE) == USART4) || \
sahilmgandhi 18:6a4db94011d3 7743 ((INSTANCE) == USART5) || \
sahilmgandhi 18:6a4db94011d3 7744 ((INSTANCE) == LPUART1))
sahilmgandhi 18:6a4db94011d3 7745
sahilmgandhi 18:6a4db94011d3 7746 /******************** USART Instances : Synchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 7747 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7748 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 7749 ((INSTANCE) == USART4) || \
sahilmgandhi 18:6a4db94011d3 7750 ((INSTANCE) == USART5))
sahilmgandhi 18:6a4db94011d3 7751
sahilmgandhi 18:6a4db94011d3 7752 /****************** USART Instances : Auto Baud Rate detection ****************/
sahilmgandhi 18:6a4db94011d3 7753
sahilmgandhi 18:6a4db94011d3 7754 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7755 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 7756
sahilmgandhi 18:6a4db94011d3 7757 /******************** UART Instances : Half-Duplex mode **********************/
sahilmgandhi 18:6a4db94011d3 7758 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7759 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 7760 ((INSTANCE) == USART4) || \
sahilmgandhi 18:6a4db94011d3 7761 ((INSTANCE) == USART5) || \
sahilmgandhi 18:6a4db94011d3 7762 ((INSTANCE) == LPUART1))
sahilmgandhi 18:6a4db94011d3 7763
sahilmgandhi 18:6a4db94011d3 7764 /******************** UART Instances : LIN mode **********************/
sahilmgandhi 18:6a4db94011d3 7765 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7766 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 7767
sahilmgandhi 18:6a4db94011d3 7768 /******************** UART Instances : Wake-up from Stop mode **********************/
sahilmgandhi 18:6a4db94011d3 7769 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7770 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 7771 ((INSTANCE) == LPUART1))
sahilmgandhi 18:6a4db94011d3 7772 /****************** UART Instances : Hardware Flow control ********************/
sahilmgandhi 18:6a4db94011d3 7773 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7774 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 7775 ((INSTANCE) == USART4) || \
sahilmgandhi 18:6a4db94011d3 7776 ((INSTANCE) == USART5) || \
sahilmgandhi 18:6a4db94011d3 7777 ((INSTANCE) == LPUART1))
sahilmgandhi 18:6a4db94011d3 7778
sahilmgandhi 18:6a4db94011d3 7779 /********************* UART Instances : Smard card mode ***********************/
sahilmgandhi 18:6a4db94011d3 7780 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7781 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 7782
sahilmgandhi 18:6a4db94011d3 7783 /*********************** UART Instances : IRDA mode ***************************/
sahilmgandhi 18:6a4db94011d3 7784 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 7785 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 7786
sahilmgandhi 18:6a4db94011d3 7787 /******************** LPUART Instance *****************************************/
sahilmgandhi 18:6a4db94011d3 7788 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
sahilmgandhi 18:6a4db94011d3 7789
sahilmgandhi 18:6a4db94011d3 7790 /****************************** IWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7791 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
sahilmgandhi 18:6a4db94011d3 7792
sahilmgandhi 18:6a4db94011d3 7793 /****************************** USB Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7794 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
sahilmgandhi 18:6a4db94011d3 7795
sahilmgandhi 18:6a4db94011d3 7796 /****************************** WWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7797 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
sahilmgandhi 18:6a4db94011d3 7798
sahilmgandhi 18:6a4db94011d3 7799 /****************************** LCD Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7800 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
sahilmgandhi 18:6a4db94011d3 7801
sahilmgandhi 18:6a4db94011d3 7802 /**
sahilmgandhi 18:6a4db94011d3 7803 * @}
sahilmgandhi 18:6a4db94011d3 7804 */
sahilmgandhi 18:6a4db94011d3 7805
sahilmgandhi 18:6a4db94011d3 7806 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7807 /* For a painless codes migration between the STM32L0xx device product */
sahilmgandhi 18:6a4db94011d3 7808 /* lines, the aliases defined below are put in place to overcome the */
sahilmgandhi 18:6a4db94011d3 7809 /* differences in the interrupt handlers and IRQn definitions. */
sahilmgandhi 18:6a4db94011d3 7810 /* No need to update developed interrupt code when moving across */
sahilmgandhi 18:6a4db94011d3 7811 /* product lines within the same STM32L0 Family */
sahilmgandhi 18:6a4db94011d3 7812 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7813
sahilmgandhi 18:6a4db94011d3 7814 /* Aliases for __IRQn */
sahilmgandhi 18:6a4db94011d3 7815
sahilmgandhi 18:6a4db94011d3 7816 #define LPUART1_IRQn RNG_LPUART1_IRQn
sahilmgandhi 18:6a4db94011d3 7817 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
sahilmgandhi 18:6a4db94011d3 7818 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
sahilmgandhi 18:6a4db94011d3 7819 #define TIM6_IRQn TIM6_DAC_IRQn
sahilmgandhi 18:6a4db94011d3 7820 #define RCC_IRQn RCC_CRS_IRQn
sahilmgandhi 18:6a4db94011d3 7821
sahilmgandhi 18:6a4db94011d3 7822 /* Aliases for __IRQHandler */
sahilmgandhi 18:6a4db94011d3 7823 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 7824 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 7825 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 7826 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
sahilmgandhi 18:6a4db94011d3 7827 #define RCC_IRQHandler RCC_CRS_IRQHandler
sahilmgandhi 18:6a4db94011d3 7828
sahilmgandhi 18:6a4db94011d3 7829 /**
sahilmgandhi 18:6a4db94011d3 7830 * @}
sahilmgandhi 18:6a4db94011d3 7831 */
sahilmgandhi 18:6a4db94011d3 7832
sahilmgandhi 18:6a4db94011d3 7833 /**
sahilmgandhi 18:6a4db94011d3 7834 * @}
sahilmgandhi 18:6a4db94011d3 7835 */
sahilmgandhi 18:6a4db94011d3 7836
sahilmgandhi 18:6a4db94011d3 7837 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 7838 }
sahilmgandhi 18:6a4db94011d3 7839 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 7840
sahilmgandhi 18:6a4db94011d3 7841 #endif /* __STM32L073xx_H */
sahilmgandhi 18:6a4db94011d3 7842
sahilmgandhi 18:6a4db94011d3 7843
sahilmgandhi 18:6a4db94011d3 7844
sahilmgandhi 18:6a4db94011d3 7845 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/