MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_ll_fmc.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of FMC HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_LL_FMC_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_LL_FMC_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup FMC_LL
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 57 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 58 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 59 /** @defgroup FMC_LL_Private_Types FMC Private Types
sahilmgandhi 18:6a4db94011d3 60 * @{
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /**
sahilmgandhi 18:6a4db94011d3 64 * @brief FMC NORSRAM Configuration Structure definition
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 typedef struct
sahilmgandhi 18:6a4db94011d3 67 {
sahilmgandhi 18:6a4db94011d3 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
sahilmgandhi 18:6a4db94011d3 69 This parameter can be a value of @ref FMC_NORSRAM_Bank */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
sahilmgandhi 18:6a4db94011d3 72 multiplexed on the data bus or not.
sahilmgandhi 18:6a4db94011d3 73 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
sahilmgandhi 18:6a4db94011d3 76 the corresponding memory device.
sahilmgandhi 18:6a4db94011d3 77 This parameter can be a value of @ref FMC_Memory_Type */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
sahilmgandhi 18:6a4db94011d3 80 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
sahilmgandhi 18:6a4db94011d3 83 valid only with synchronous burst Flash memories.
sahilmgandhi 18:6a4db94011d3 84 This parameter can be a value of @ref FMC_Burst_Access_Mode */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
sahilmgandhi 18:6a4db94011d3 87 the Flash memory in burst mode.
sahilmgandhi 18:6a4db94011d3 88 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
sahilmgandhi 18:6a4db94011d3 91 memory, valid only when accessing Flash memories in burst mode.
sahilmgandhi 18:6a4db94011d3 92 This parameter can be a value of @ref FMC_Wrap_Mode
sahilmgandhi 18:6a4db94011d3 93 This mode is not available for the STM32F446/467/479xx devices */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
sahilmgandhi 18:6a4db94011d3 96 clock cycle before the wait state or during the wait state,
sahilmgandhi 18:6a4db94011d3 97 valid only when accessing memories in burst mode.
sahilmgandhi 18:6a4db94011d3 98 This parameter can be a value of @ref FMC_Wait_Timing */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
sahilmgandhi 18:6a4db94011d3 101 This parameter can be a value of @ref FMC_Write_Operation */
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
sahilmgandhi 18:6a4db94011d3 104 signal, valid for Flash memory access in burst mode.
sahilmgandhi 18:6a4db94011d3 105 This parameter can be a value of @ref FMC_Wait_Signal */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
sahilmgandhi 18:6a4db94011d3 108 This parameter can be a value of @ref FMC_Extended_Mode */
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
sahilmgandhi 18:6a4db94011d3 111 valid only with asynchronous Flash memories.
sahilmgandhi 18:6a4db94011d3 112 This parameter can be a value of @ref FMC_AsynchronousWait */
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
sahilmgandhi 18:6a4db94011d3 115 This parameter can be a value of @ref FMC_Write_Burst */
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
sahilmgandhi 18:6a4db94011d3 118 This parameter is only enabled through the FMC_BCR1 register, and don't care
sahilmgandhi 18:6a4db94011d3 119 through FMC_BCR2..4 registers.
sahilmgandhi 18:6a4db94011d3 120 This parameter can be a value of @ref FMC_Continous_Clock */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
sahilmgandhi 18:6a4db94011d3 123 This parameter is only enabled through the FMC_BCR1 register, and don't care
sahilmgandhi 18:6a4db94011d3 124 through FMC_BCR2..4 registers.
sahilmgandhi 18:6a4db94011d3 125 This parameter can be a value of @ref FMC_Write_FIFO
sahilmgandhi 18:6a4db94011d3 126 This mode is available only for the STM32F446/469/479xx devices */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 uint32_t PageSize; /*!< Specifies the memory page size.
sahilmgandhi 18:6a4db94011d3 129 This parameter can be a value of @ref FMC_Page_Size */
sahilmgandhi 18:6a4db94011d3 130 }FMC_NORSRAM_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /**
sahilmgandhi 18:6a4db94011d3 133 * @brief FMC NORSRAM Timing parameters structure definition
sahilmgandhi 18:6a4db94011d3 134 */
sahilmgandhi 18:6a4db94011d3 135 typedef struct
sahilmgandhi 18:6a4db94011d3 136 {
sahilmgandhi 18:6a4db94011d3 137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
sahilmgandhi 18:6a4db94011d3 138 the duration of the address setup time.
sahilmgandhi 18:6a4db94011d3 139 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
sahilmgandhi 18:6a4db94011d3 140 @note This parameter is not used with synchronous NOR Flash memories. */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
sahilmgandhi 18:6a4db94011d3 143 the duration of the address hold time.
sahilmgandhi 18:6a4db94011d3 144 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
sahilmgandhi 18:6a4db94011d3 145 @note This parameter is not used with synchronous NOR Flash memories. */
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
sahilmgandhi 18:6a4db94011d3 148 the duration of the data setup time.
sahilmgandhi 18:6a4db94011d3 149 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
sahilmgandhi 18:6a4db94011d3 150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
sahilmgandhi 18:6a4db94011d3 151 NOR Flash memories. */
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
sahilmgandhi 18:6a4db94011d3 154 the duration of the bus turnaround.
sahilmgandhi 18:6a4db94011d3 155 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
sahilmgandhi 18:6a4db94011d3 156 @note This parameter is only used for multiplexed NOR Flash memories. */
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
sahilmgandhi 18:6a4db94011d3 159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
sahilmgandhi 18:6a4db94011d3 160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
sahilmgandhi 18:6a4db94011d3 161 accesses. */
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
sahilmgandhi 18:6a4db94011d3 164 to the memory before getting the first data.
sahilmgandhi 18:6a4db94011d3 165 The parameter value depends on the memory type as shown below:
sahilmgandhi 18:6a4db94011d3 166 - It must be set to 0 in case of a CRAM
sahilmgandhi 18:6a4db94011d3 167 - It is don't care in asynchronous NOR, SRAM or ROM accesses
sahilmgandhi 18:6a4db94011d3 168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
sahilmgandhi 18:6a4db94011d3 169 with synchronous burst mode enable */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
sahilmgandhi 18:6a4db94011d3 172 This parameter can be a value of @ref FMC_Access_Mode */
sahilmgandhi 18:6a4db94011d3 173 }FMC_NORSRAM_TimingTypeDef;
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /**
sahilmgandhi 18:6a4db94011d3 176 * @brief FMC NAND Configuration Structure definition
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178 typedef struct
sahilmgandhi 18:6a4db94011d3 179 {
sahilmgandhi 18:6a4db94011d3 180 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
sahilmgandhi 18:6a4db94011d3 181 This parameter can be a value of @ref FMC_NAND_Bank */
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
sahilmgandhi 18:6a4db94011d3 184 This parameter can be any value of @ref FMC_Wait_feature */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
sahilmgandhi 18:6a4db94011d3 187 This parameter can be any value of @ref FMC_NAND_Data_Width */
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
sahilmgandhi 18:6a4db94011d3 190 This parameter can be any value of @ref FMC_ECC */
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
sahilmgandhi 18:6a4db94011d3 193 This parameter can be any value of @ref FMC_ECC_Page_Size */
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
sahilmgandhi 18:6a4db94011d3 196 delay between CLE low and RE low.
sahilmgandhi 18:6a4db94011d3 197 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
sahilmgandhi 18:6a4db94011d3 200 delay between ALE low and RE low.
sahilmgandhi 18:6a4db94011d3 201 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 202 }FMC_NAND_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 /**
sahilmgandhi 18:6a4db94011d3 205 * @brief FMC NAND/PCCARD Timing parameters structure definition
sahilmgandhi 18:6a4db94011d3 206 */
sahilmgandhi 18:6a4db94011d3 207 typedef struct
sahilmgandhi 18:6a4db94011d3 208 {
sahilmgandhi 18:6a4db94011d3 209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
sahilmgandhi 18:6a4db94011d3 210 the command assertion for NAND-Flash read or write access
sahilmgandhi 18:6a4db94011d3 211 to common/Attribute or I/O memory space (depending on
sahilmgandhi 18:6a4db94011d3 212 the memory space timing to be configured).
sahilmgandhi 18:6a4db94011d3 213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
sahilmgandhi 18:6a4db94011d3 216 command for NAND-Flash read or write access to
sahilmgandhi 18:6a4db94011d3 217 common/Attribute or I/O memory space (depending on the
sahilmgandhi 18:6a4db94011d3 218 memory space timing to be configured).
sahilmgandhi 18:6a4db94011d3 219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
sahilmgandhi 18:6a4db94011d3 222 (and data for write access) after the command de-assertion
sahilmgandhi 18:6a4db94011d3 223 for NAND-Flash read or write access to common/Attribute
sahilmgandhi 18:6a4db94011d3 224 or I/O memory space (depending on the memory space timing
sahilmgandhi 18:6a4db94011d3 225 to be configured).
sahilmgandhi 18:6a4db94011d3 226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
sahilmgandhi 18:6a4db94011d3 229 data bus is kept in HiZ after the start of a NAND-Flash
sahilmgandhi 18:6a4db94011d3 230 write access to common/Attribute or I/O memory space (depending
sahilmgandhi 18:6a4db94011d3 231 on the memory space timing to be configured).
sahilmgandhi 18:6a4db94011d3 232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 233 }FMC_NAND_PCC_TimingTypeDef;
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 /**
sahilmgandhi 18:6a4db94011d3 236 * @brief FMC NAND Configuration Structure definition
sahilmgandhi 18:6a4db94011d3 237 */
sahilmgandhi 18:6a4db94011d3 238 typedef struct
sahilmgandhi 18:6a4db94011d3 239 {
sahilmgandhi 18:6a4db94011d3 240 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
sahilmgandhi 18:6a4db94011d3 241 This parameter can be any value of @ref FMC_Wait_feature */
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
sahilmgandhi 18:6a4db94011d3 244 delay between CLE low and RE low.
sahilmgandhi 18:6a4db94011d3 245 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
sahilmgandhi 18:6a4db94011d3 248 delay between ALE low and RE low.
sahilmgandhi 18:6a4db94011d3 249 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
sahilmgandhi 18:6a4db94011d3 250 }FMC_PCCARD_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /**
sahilmgandhi 18:6a4db94011d3 253 * @brief FMC SDRAM Configuration Structure definition
sahilmgandhi 18:6a4db94011d3 254 */
sahilmgandhi 18:6a4db94011d3 255 typedef struct
sahilmgandhi 18:6a4db94011d3 256 {
sahilmgandhi 18:6a4db94011d3 257 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
sahilmgandhi 18:6a4db94011d3 258 This parameter can be a value of @ref FMC_SDRAM_Bank */
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
sahilmgandhi 18:6a4db94011d3 261 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
sahilmgandhi 18:6a4db94011d3 264 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
sahilmgandhi 18:6a4db94011d3 267 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
sahilmgandhi 18:6a4db94011d3 270 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
sahilmgandhi 18:6a4db94011d3 273 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
sahilmgandhi 18:6a4db94011d3 276 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
sahilmgandhi 18:6a4db94011d3 279 to disable the clock before changing frequency.
sahilmgandhi 18:6a4db94011d3 280 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
sahilmgandhi 18:6a4db94011d3 283 commands during the CAS latency and stores data in the Read FIFO.
sahilmgandhi 18:6a4db94011d3 284 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
sahilmgandhi 18:6a4db94011d3 287 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
sahilmgandhi 18:6a4db94011d3 288 }FMC_SDRAM_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /**
sahilmgandhi 18:6a4db94011d3 291 * @brief FMC SDRAM Timing parameters structure definition
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293 typedef struct
sahilmgandhi 18:6a4db94011d3 294 {
sahilmgandhi 18:6a4db94011d3 295 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
sahilmgandhi 18:6a4db94011d3 296 an active or Refresh command in number of memory clock cycles.
sahilmgandhi 18:6a4db94011d3 297 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
sahilmgandhi 18:6a4db94011d3 300 issuing the Activate command in number of memory clock cycles.
sahilmgandhi 18:6a4db94011d3 301 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
sahilmgandhi 18:6a4db94011d3 304 cycles.
sahilmgandhi 18:6a4db94011d3 305 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
sahilmgandhi 18:6a4db94011d3 308 and the delay between two consecutive Refresh commands in number of
sahilmgandhi 18:6a4db94011d3 309 memory clock cycles.
sahilmgandhi 18:6a4db94011d3 310 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
sahilmgandhi 18:6a4db94011d3 313 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
sahilmgandhi 18:6a4db94011d3 316 in number of memory clock cycles.
sahilmgandhi 18:6a4db94011d3 317 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
sahilmgandhi 18:6a4db94011d3 320 command in number of memory clock cycles.
sahilmgandhi 18:6a4db94011d3 321 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 322 }FMC_SDRAM_TimingTypeDef;
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /**
sahilmgandhi 18:6a4db94011d3 325 * @brief SDRAM command parameters structure definition
sahilmgandhi 18:6a4db94011d3 326 */
sahilmgandhi 18:6a4db94011d3 327 typedef struct
sahilmgandhi 18:6a4db94011d3 328 {
sahilmgandhi 18:6a4db94011d3 329 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
sahilmgandhi 18:6a4db94011d3 330 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
sahilmgandhi 18:6a4db94011d3 333 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
sahilmgandhi 18:6a4db94011d3 336 in auto refresh mode.
sahilmgandhi 18:6a4db94011d3 337 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
sahilmgandhi 18:6a4db94011d3 338 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
sahilmgandhi 18:6a4db94011d3 339 }FMC_SDRAM_CommandTypeDef;
sahilmgandhi 18:6a4db94011d3 340 /**
sahilmgandhi 18:6a4db94011d3 341 * @}
sahilmgandhi 18:6a4db94011d3 342 */
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 345 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
sahilmgandhi 18:6a4db94011d3 346 * @{
sahilmgandhi 18:6a4db94011d3 347 */
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
sahilmgandhi 18:6a4db94011d3 350 * @{
sahilmgandhi 18:6a4db94011d3 351 */
sahilmgandhi 18:6a4db94011d3 352 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
sahilmgandhi 18:6a4db94011d3 353 * @{
sahilmgandhi 18:6a4db94011d3 354 */
sahilmgandhi 18:6a4db94011d3 355 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 356 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 357 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 358 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
sahilmgandhi 18:6a4db94011d3 359 /**
sahilmgandhi 18:6a4db94011d3 360 * @}
sahilmgandhi 18:6a4db94011d3 361 */
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
sahilmgandhi 18:6a4db94011d3 364 * @{
sahilmgandhi 18:6a4db94011d3 365 */
sahilmgandhi 18:6a4db94011d3 366 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 367 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 368 /**
sahilmgandhi 18:6a4db94011d3 369 * @}
sahilmgandhi 18:6a4db94011d3 370 */
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /** @defgroup FMC_Memory_Type FMC Memory Type
sahilmgandhi 18:6a4db94011d3 373 * @{
sahilmgandhi 18:6a4db94011d3 374 */
sahilmgandhi 18:6a4db94011d3 375 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 376 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 377 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 378 /**
sahilmgandhi 18:6a4db94011d3 379 * @}
sahilmgandhi 18:6a4db94011d3 380 */
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
sahilmgandhi 18:6a4db94011d3 383 * @{
sahilmgandhi 18:6a4db94011d3 384 */
sahilmgandhi 18:6a4db94011d3 385 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 386 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 387 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
sahilmgandhi 18:6a4db94011d3 388 /**
sahilmgandhi 18:6a4db94011d3 389 * @}
sahilmgandhi 18:6a4db94011d3 390 */
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
sahilmgandhi 18:6a4db94011d3 393 * @{
sahilmgandhi 18:6a4db94011d3 394 */
sahilmgandhi 18:6a4db94011d3 395 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 396 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 397 /**
sahilmgandhi 18:6a4db94011d3 398 * @}
sahilmgandhi 18:6a4db94011d3 399 */
sahilmgandhi 18:6a4db94011d3 400
sahilmgandhi 18:6a4db94011d3 401 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
sahilmgandhi 18:6a4db94011d3 402 * @{
sahilmgandhi 18:6a4db94011d3 403 */
sahilmgandhi 18:6a4db94011d3 404 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 405 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 406 /**
sahilmgandhi 18:6a4db94011d3 407 * @}
sahilmgandhi 18:6a4db94011d3 408 */
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
sahilmgandhi 18:6a4db94011d3 411 * @{
sahilmgandhi 18:6a4db94011d3 412 */
sahilmgandhi 18:6a4db94011d3 413 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 414 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
sahilmgandhi 18:6a4db94011d3 415 /**
sahilmgandhi 18:6a4db94011d3 416 * @}
sahilmgandhi 18:6a4db94011d3 417 */
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
sahilmgandhi 18:6a4db94011d3 420 * @{
sahilmgandhi 18:6a4db94011d3 421 */
sahilmgandhi 18:6a4db94011d3 422 /** @note This mode is not available for the STM32F446/469/479xx devices
sahilmgandhi 18:6a4db94011d3 423 */
sahilmgandhi 18:6a4db94011d3 424 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 425 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
sahilmgandhi 18:6a4db94011d3 426 /**
sahilmgandhi 18:6a4db94011d3 427 * @}
sahilmgandhi 18:6a4db94011d3 428 */
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 /** @defgroup FMC_Wait_Timing FMC Wait Timing
sahilmgandhi 18:6a4db94011d3 431 * @{
sahilmgandhi 18:6a4db94011d3 432 */
sahilmgandhi 18:6a4db94011d3 433 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 434 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
sahilmgandhi 18:6a4db94011d3 435 /**
sahilmgandhi 18:6a4db94011d3 436 * @}
sahilmgandhi 18:6a4db94011d3 437 */
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 /** @defgroup FMC_Write_Operation FMC Write Operation
sahilmgandhi 18:6a4db94011d3 440 * @{
sahilmgandhi 18:6a4db94011d3 441 */
sahilmgandhi 18:6a4db94011d3 442 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 443 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
sahilmgandhi 18:6a4db94011d3 444 /**
sahilmgandhi 18:6a4db94011d3 445 * @}
sahilmgandhi 18:6a4db94011d3 446 */
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /** @defgroup FMC_Wait_Signal FMC Wait Signal
sahilmgandhi 18:6a4db94011d3 449 * @{
sahilmgandhi 18:6a4db94011d3 450 */
sahilmgandhi 18:6a4db94011d3 451 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 452 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
sahilmgandhi 18:6a4db94011d3 453 /**
sahilmgandhi 18:6a4db94011d3 454 * @}
sahilmgandhi 18:6a4db94011d3 455 */
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 /** @defgroup FMC_Extended_Mode FMC Extended Mode
sahilmgandhi 18:6a4db94011d3 458 * @{
sahilmgandhi 18:6a4db94011d3 459 */
sahilmgandhi 18:6a4db94011d3 460 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 461 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
sahilmgandhi 18:6a4db94011d3 462 /**
sahilmgandhi 18:6a4db94011d3 463 * @}
sahilmgandhi 18:6a4db94011d3 464 */
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
sahilmgandhi 18:6a4db94011d3 467 * @{
sahilmgandhi 18:6a4db94011d3 468 */
sahilmgandhi 18:6a4db94011d3 469 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 470 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
sahilmgandhi 18:6a4db94011d3 471 /**
sahilmgandhi 18:6a4db94011d3 472 * @}
sahilmgandhi 18:6a4db94011d3 473 */
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /** @defgroup FMC_Page_Size FMC Page Size
sahilmgandhi 18:6a4db94011d3 476 * @{
sahilmgandhi 18:6a4db94011d3 477 */
sahilmgandhi 18:6a4db94011d3 478 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 479 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
sahilmgandhi 18:6a4db94011d3 480 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
sahilmgandhi 18:6a4db94011d3 481 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
sahilmgandhi 18:6a4db94011d3 482 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
sahilmgandhi 18:6a4db94011d3 483 /**
sahilmgandhi 18:6a4db94011d3 484 * @}
sahilmgandhi 18:6a4db94011d3 485 */
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /** @defgroup FMC_Write_FIFO FMC Write FIFO
sahilmgandhi 18:6a4db94011d3 488 * @note These values are available only for the STM32F446/469/479xx devices.
sahilmgandhi 18:6a4db94011d3 489 * @{
sahilmgandhi 18:6a4db94011d3 490 */
sahilmgandhi 18:6a4db94011d3 491 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
sahilmgandhi 18:6a4db94011d3 492 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 493 /**
sahilmgandhi 18:6a4db94011d3 494 * @}
sahilmgandhi 18:6a4db94011d3 495 */
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /** @defgroup FMC_Write_Burst FMC Write Burst
sahilmgandhi 18:6a4db94011d3 498 * @{
sahilmgandhi 18:6a4db94011d3 499 */
sahilmgandhi 18:6a4db94011d3 500 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 501 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
sahilmgandhi 18:6a4db94011d3 502 /**
sahilmgandhi 18:6a4db94011d3 503 * @}
sahilmgandhi 18:6a4db94011d3 504 */
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
sahilmgandhi 18:6a4db94011d3 507 * @{
sahilmgandhi 18:6a4db94011d3 508 */
sahilmgandhi 18:6a4db94011d3 509 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 510 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
sahilmgandhi 18:6a4db94011d3 511 /**
sahilmgandhi 18:6a4db94011d3 512 * @}
sahilmgandhi 18:6a4db94011d3 513 */
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 /** @defgroup FMC_Access_Mode FMC Access Mode
sahilmgandhi 18:6a4db94011d3 516 * @{
sahilmgandhi 18:6a4db94011d3 517 */
sahilmgandhi 18:6a4db94011d3 518 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 519 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
sahilmgandhi 18:6a4db94011d3 520 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
sahilmgandhi 18:6a4db94011d3 521 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
sahilmgandhi 18:6a4db94011d3 522 /**
sahilmgandhi 18:6a4db94011d3 523 * @}
sahilmgandhi 18:6a4db94011d3 524 */
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 /**
sahilmgandhi 18:6a4db94011d3 527 * @}
sahilmgandhi 18:6a4db94011d3 528 */
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
sahilmgandhi 18:6a4db94011d3 531 * @{
sahilmgandhi 18:6a4db94011d3 532 */
sahilmgandhi 18:6a4db94011d3 533 /** @defgroup FMC_NAND_Bank FMC NAND Bank
sahilmgandhi 18:6a4db94011d3 534 * @{
sahilmgandhi 18:6a4db94011d3 535 */
sahilmgandhi 18:6a4db94011d3 536 #define FMC_NAND_BANK2 ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 537 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 538 /**
sahilmgandhi 18:6a4db94011d3 539 * @}
sahilmgandhi 18:6a4db94011d3 540 */
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 /** @defgroup FMC_Wait_feature FMC Wait feature
sahilmgandhi 18:6a4db94011d3 543 * @{
sahilmgandhi 18:6a4db94011d3 544 */
sahilmgandhi 18:6a4db94011d3 545 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 546 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 547 /**
sahilmgandhi 18:6a4db94011d3 548 * @}
sahilmgandhi 18:6a4db94011d3 549 */
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
sahilmgandhi 18:6a4db94011d3 552 * @{
sahilmgandhi 18:6a4db94011d3 553 */
sahilmgandhi 18:6a4db94011d3 554 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 555 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 556 /**
sahilmgandhi 18:6a4db94011d3 557 * @}
sahilmgandhi 18:6a4db94011d3 558 */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
sahilmgandhi 18:6a4db94011d3 561 * @{
sahilmgandhi 18:6a4db94011d3 562 */
sahilmgandhi 18:6a4db94011d3 563 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 564 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * @}
sahilmgandhi 18:6a4db94011d3 567 */
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /** @defgroup FMC_ECC FMC ECC
sahilmgandhi 18:6a4db94011d3 570 * @{
sahilmgandhi 18:6a4db94011d3 571 */
sahilmgandhi 18:6a4db94011d3 572 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 573 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 574 /**
sahilmgandhi 18:6a4db94011d3 575 * @}
sahilmgandhi 18:6a4db94011d3 576 */
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
sahilmgandhi 18:6a4db94011d3 579 * @{
sahilmgandhi 18:6a4db94011d3 580 */
sahilmgandhi 18:6a4db94011d3 581 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 582 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
sahilmgandhi 18:6a4db94011d3 583 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
sahilmgandhi 18:6a4db94011d3 584 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
sahilmgandhi 18:6a4db94011d3 585 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
sahilmgandhi 18:6a4db94011d3 586 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
sahilmgandhi 18:6a4db94011d3 587 /**
sahilmgandhi 18:6a4db94011d3 588 * @}
sahilmgandhi 18:6a4db94011d3 589 */
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /**
sahilmgandhi 18:6a4db94011d3 592 * @}
sahilmgandhi 18:6a4db94011d3 593 */
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
sahilmgandhi 18:6a4db94011d3 596 * @{
sahilmgandhi 18:6a4db94011d3 597 */
sahilmgandhi 18:6a4db94011d3 598 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
sahilmgandhi 18:6a4db94011d3 599 * @{
sahilmgandhi 18:6a4db94011d3 600 */
sahilmgandhi 18:6a4db94011d3 601 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 602 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 603 /**
sahilmgandhi 18:6a4db94011d3 604 * @}
sahilmgandhi 18:6a4db94011d3 605 */
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
sahilmgandhi 18:6a4db94011d3 608 * @{
sahilmgandhi 18:6a4db94011d3 609 */
sahilmgandhi 18:6a4db94011d3 610 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 611 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 612 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 613 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
sahilmgandhi 18:6a4db94011d3 614 /**
sahilmgandhi 18:6a4db94011d3 615 * @}
sahilmgandhi 18:6a4db94011d3 616 */
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
sahilmgandhi 18:6a4db94011d3 619 * @{
sahilmgandhi 18:6a4db94011d3 620 */
sahilmgandhi 18:6a4db94011d3 621 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 622 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 623 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 624 /**
sahilmgandhi 18:6a4db94011d3 625 * @}
sahilmgandhi 18:6a4db94011d3 626 */
sahilmgandhi 18:6a4db94011d3 627
sahilmgandhi 18:6a4db94011d3 628 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
sahilmgandhi 18:6a4db94011d3 629 * @{
sahilmgandhi 18:6a4db94011d3 630 */
sahilmgandhi 18:6a4db94011d3 631 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 632 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 633 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
sahilmgandhi 18:6a4db94011d3 634 /**
sahilmgandhi 18:6a4db94011d3 635 * @}
sahilmgandhi 18:6a4db94011d3 636 */
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
sahilmgandhi 18:6a4db94011d3 639 * @{
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 642 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 643 /**
sahilmgandhi 18:6a4db94011d3 644 * @}
sahilmgandhi 18:6a4db94011d3 645 */
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
sahilmgandhi 18:6a4db94011d3 648 * @{
sahilmgandhi 18:6a4db94011d3 649 */
sahilmgandhi 18:6a4db94011d3 650 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
sahilmgandhi 18:6a4db94011d3 651 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 652 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
sahilmgandhi 18:6a4db94011d3 653 /**
sahilmgandhi 18:6a4db94011d3 654 * @}
sahilmgandhi 18:6a4db94011d3 655 */
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
sahilmgandhi 18:6a4db94011d3 658 * @{
sahilmgandhi 18:6a4db94011d3 659 */
sahilmgandhi 18:6a4db94011d3 660 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 661 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 /**
sahilmgandhi 18:6a4db94011d3 664 * @}
sahilmgandhi 18:6a4db94011d3 665 */
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
sahilmgandhi 18:6a4db94011d3 668 * @{
sahilmgandhi 18:6a4db94011d3 669 */
sahilmgandhi 18:6a4db94011d3 670 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 671 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
sahilmgandhi 18:6a4db94011d3 672 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
sahilmgandhi 18:6a4db94011d3 673 /**
sahilmgandhi 18:6a4db94011d3 674 * @}
sahilmgandhi 18:6a4db94011d3 675 */
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
sahilmgandhi 18:6a4db94011d3 678 * @{
sahilmgandhi 18:6a4db94011d3 679 */
sahilmgandhi 18:6a4db94011d3 680 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 681 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
sahilmgandhi 18:6a4db94011d3 682 /**
sahilmgandhi 18:6a4db94011d3 683 * @}
sahilmgandhi 18:6a4db94011d3 684 */
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
sahilmgandhi 18:6a4db94011d3 687 * @{
sahilmgandhi 18:6a4db94011d3 688 */
sahilmgandhi 18:6a4db94011d3 689 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 690 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
sahilmgandhi 18:6a4db94011d3 691 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
sahilmgandhi 18:6a4db94011d3 692 /**
sahilmgandhi 18:6a4db94011d3 693 * @}
sahilmgandhi 18:6a4db94011d3 694 */
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
sahilmgandhi 18:6a4db94011d3 697 * @{
sahilmgandhi 18:6a4db94011d3 698 */
sahilmgandhi 18:6a4db94011d3 699 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 700 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 701 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 702 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
sahilmgandhi 18:6a4db94011d3 703 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 704 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
sahilmgandhi 18:6a4db94011d3 705 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
sahilmgandhi 18:6a4db94011d3 706 /**
sahilmgandhi 18:6a4db94011d3 707 * @}
sahilmgandhi 18:6a4db94011d3 708 */
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
sahilmgandhi 18:6a4db94011d3 711 * @{
sahilmgandhi 18:6a4db94011d3 712 */
sahilmgandhi 18:6a4db94011d3 713 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
sahilmgandhi 18:6a4db94011d3 714 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
sahilmgandhi 18:6a4db94011d3 715 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
sahilmgandhi 18:6a4db94011d3 716 /**
sahilmgandhi 18:6a4db94011d3 717 * @}
sahilmgandhi 18:6a4db94011d3 718 */
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
sahilmgandhi 18:6a4db94011d3 721 * @{
sahilmgandhi 18:6a4db94011d3 722 */
sahilmgandhi 18:6a4db94011d3 723 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 724 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
sahilmgandhi 18:6a4db94011d3 725 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
sahilmgandhi 18:6a4db94011d3 726 /**
sahilmgandhi 18:6a4db94011d3 727 * @}
sahilmgandhi 18:6a4db94011d3 728 */
sahilmgandhi 18:6a4db94011d3 729
sahilmgandhi 18:6a4db94011d3 730 /**
sahilmgandhi 18:6a4db94011d3 731 * @}
sahilmgandhi 18:6a4db94011d3 732 */
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
sahilmgandhi 18:6a4db94011d3 735 * @{
sahilmgandhi 18:6a4db94011d3 736 */
sahilmgandhi 18:6a4db94011d3 737 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 738 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 739 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
sahilmgandhi 18:6a4db94011d3 740 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
sahilmgandhi 18:6a4db94011d3 741 /**
sahilmgandhi 18:6a4db94011d3 742 * @}
sahilmgandhi 18:6a4db94011d3 743 */
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
sahilmgandhi 18:6a4db94011d3 746 * @{
sahilmgandhi 18:6a4db94011d3 747 */
sahilmgandhi 18:6a4db94011d3 748 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 749 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 750 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 751 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 752 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
sahilmgandhi 18:6a4db94011d3 753 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
sahilmgandhi 18:6a4db94011d3 754 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
sahilmgandhi 18:6a4db94011d3 755 /**
sahilmgandhi 18:6a4db94011d3 756 * @}
sahilmgandhi 18:6a4db94011d3 757 */
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
sahilmgandhi 18:6a4db94011d3 760 * @{
sahilmgandhi 18:6a4db94011d3 761 */
sahilmgandhi 18:6a4db94011d3 762 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 763 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
sahilmgandhi 18:6a4db94011d3 764 #else
sahilmgandhi 18:6a4db94011d3 765 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
sahilmgandhi 18:6a4db94011d3 766 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
sahilmgandhi 18:6a4db94011d3 767 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 768 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
sahilmgandhi 18:6a4db94011d3 769 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
sahilmgandhi 18:6a4db94011d3 770 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
sahilmgandhi 18:6a4db94011d3 771
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 774 #define FMC_NAND_DEVICE FMC_Bank3
sahilmgandhi 18:6a4db94011d3 775 #else
sahilmgandhi 18:6a4db94011d3 776 #define FMC_NAND_DEVICE FMC_Bank2_3
sahilmgandhi 18:6a4db94011d3 777 #define FMC_PCCARD_DEVICE FMC_Bank4
sahilmgandhi 18:6a4db94011d3 778 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 779 #define FMC_NORSRAM_DEVICE FMC_Bank1
sahilmgandhi 18:6a4db94011d3 780 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
sahilmgandhi 18:6a4db94011d3 781 #define FMC_SDRAM_DEVICE FMC_Bank5_6
sahilmgandhi 18:6a4db94011d3 782 /**
sahilmgandhi 18:6a4db94011d3 783 * @}
sahilmgandhi 18:6a4db94011d3 784 */
sahilmgandhi 18:6a4db94011d3 785
sahilmgandhi 18:6a4db94011d3 786 /**
sahilmgandhi 18:6a4db94011d3 787 * @}
sahilmgandhi 18:6a4db94011d3 788 */
sahilmgandhi 18:6a4db94011d3 789
sahilmgandhi 18:6a4db94011d3 790 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 791 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
sahilmgandhi 18:6a4db94011d3 792 * @{
sahilmgandhi 18:6a4db94011d3 793 */
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
sahilmgandhi 18:6a4db94011d3 796 * @brief macros to handle NOR device enable/disable and read/write operations
sahilmgandhi 18:6a4db94011d3 797 * @{
sahilmgandhi 18:6a4db94011d3 798 */
sahilmgandhi 18:6a4db94011d3 799 /**
sahilmgandhi 18:6a4db94011d3 800 * @brief Enable the NORSRAM device access.
sahilmgandhi 18:6a4db94011d3 801 * @param __INSTANCE__: FMC_NORSRAM Instance
sahilmgandhi 18:6a4db94011d3 802 * @param __BANK__: FMC_NORSRAM Bank
sahilmgandhi 18:6a4db94011d3 803 * @retval None
sahilmgandhi 18:6a4db94011d3 804 */
sahilmgandhi 18:6a4db94011d3 805 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
sahilmgandhi 18:6a4db94011d3 806
sahilmgandhi 18:6a4db94011d3 807 /**
sahilmgandhi 18:6a4db94011d3 808 * @brief Disable the NORSRAM device access.
sahilmgandhi 18:6a4db94011d3 809 * @param __INSTANCE__: FMC_NORSRAM Instance
sahilmgandhi 18:6a4db94011d3 810 * @param __BANK__: FMC_NORSRAM Bank
sahilmgandhi 18:6a4db94011d3 811 * @retval None
sahilmgandhi 18:6a4db94011d3 812 */
sahilmgandhi 18:6a4db94011d3 813 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
sahilmgandhi 18:6a4db94011d3 814 /**
sahilmgandhi 18:6a4db94011d3 815 * @}
sahilmgandhi 18:6a4db94011d3 816 */
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
sahilmgandhi 18:6a4db94011d3 819 * @brief macros to handle NAND device enable/disable
sahilmgandhi 18:6a4db94011d3 820 * @{
sahilmgandhi 18:6a4db94011d3 821 */
sahilmgandhi 18:6a4db94011d3 822 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 823 /**
sahilmgandhi 18:6a4db94011d3 824 * @brief Enable the NAND device access.
sahilmgandhi 18:6a4db94011d3 825 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 826 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 827 * @retval None
sahilmgandhi 18:6a4db94011d3 828 */
sahilmgandhi 18:6a4db94011d3 829 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 /**
sahilmgandhi 18:6a4db94011d3 832 * @brief Disable the NAND device access.
sahilmgandhi 18:6a4db94011d3 833 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 834 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 835 * @retval None
sahilmgandhi 18:6a4db94011d3 836 */
sahilmgandhi 18:6a4db94011d3 837 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
sahilmgandhi 18:6a4db94011d3 838 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
sahilmgandhi 18:6a4db94011d3 839 /**
sahilmgandhi 18:6a4db94011d3 840 * @brief Enable the NAND device access.
sahilmgandhi 18:6a4db94011d3 841 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 842 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 843 * @retval None
sahilmgandhi 18:6a4db94011d3 844 */
sahilmgandhi 18:6a4db94011d3 845 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
sahilmgandhi 18:6a4db94011d3 846 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /**
sahilmgandhi 18:6a4db94011d3 849 * @brief Disable the NAND device access.
sahilmgandhi 18:6a4db94011d3 850 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 851 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 852 * @retval None
sahilmgandhi 18:6a4db94011d3 853 */
sahilmgandhi 18:6a4db94011d3 854 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
sahilmgandhi 18:6a4db94011d3 855 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
sahilmgandhi 18:6a4db94011d3 856
sahilmgandhi 18:6a4db94011d3 857 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
sahilmgandhi 18:6a4db94011d3 858 /**
sahilmgandhi 18:6a4db94011d3 859 * @}
sahilmgandhi 18:6a4db94011d3 860 */
sahilmgandhi 18:6a4db94011d3 861 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
sahilmgandhi 18:6a4db94011d3 862 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
sahilmgandhi 18:6a4db94011d3 863 * @brief macros to handle SRAM read/write operations
sahilmgandhi 18:6a4db94011d3 864 * @{
sahilmgandhi 18:6a4db94011d3 865 */
sahilmgandhi 18:6a4db94011d3 866 /**
sahilmgandhi 18:6a4db94011d3 867 * @brief Enable the PCCARD device access.
sahilmgandhi 18:6a4db94011d3 868 * @param __INSTANCE__: FMC_PCCARD Instance
sahilmgandhi 18:6a4db94011d3 869 * @retval None
sahilmgandhi 18:6a4db94011d3 870 */
sahilmgandhi 18:6a4db94011d3 871 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873 /**
sahilmgandhi 18:6a4db94011d3 874 * @brief Disable the PCCARD device access.
sahilmgandhi 18:6a4db94011d3 875 * @param __INSTANCE__: FMC_PCCARD Instance
sahilmgandhi 18:6a4db94011d3 876 * @retval None
sahilmgandhi 18:6a4db94011d3 877 */
sahilmgandhi 18:6a4db94011d3 878 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
sahilmgandhi 18:6a4db94011d3 879 /**
sahilmgandhi 18:6a4db94011d3 880 * @}
sahilmgandhi 18:6a4db94011d3 881 */
sahilmgandhi 18:6a4db94011d3 882 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
sahilmgandhi 18:6a4db94011d3 885 * @brief macros to handle FMC flags and interrupts
sahilmgandhi 18:6a4db94011d3 886 * @{
sahilmgandhi 18:6a4db94011d3 887 */
sahilmgandhi 18:6a4db94011d3 888 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 889 /**
sahilmgandhi 18:6a4db94011d3 890 * @brief Enable the NAND device interrupt.
sahilmgandhi 18:6a4db94011d3 891 * @param __INSTANCE__: FMC_NAND instance
sahilmgandhi 18:6a4db94011d3 892 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 893 * @param __INTERRUPT__: FMC_NAND interrupt
sahilmgandhi 18:6a4db94011d3 894 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 895 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
sahilmgandhi 18:6a4db94011d3 896 * @arg FMC_IT_LEVEL: Interrupt level.
sahilmgandhi 18:6a4db94011d3 897 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
sahilmgandhi 18:6a4db94011d3 898 * @retval None
sahilmgandhi 18:6a4db94011d3 899 */
sahilmgandhi 18:6a4db94011d3 900 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902 /**
sahilmgandhi 18:6a4db94011d3 903 * @brief Disable the NAND device interrupt.
sahilmgandhi 18:6a4db94011d3 904 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 905 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 906 * @param __INTERRUPT__: FMC_NAND interrupt
sahilmgandhi 18:6a4db94011d3 907 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 908 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
sahilmgandhi 18:6a4db94011d3 909 * @arg FMC_IT_LEVEL: Interrupt level.
sahilmgandhi 18:6a4db94011d3 910 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
sahilmgandhi 18:6a4db94011d3 911 * @retval None
sahilmgandhi 18:6a4db94011d3 912 */
sahilmgandhi 18:6a4db94011d3 913 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 914
sahilmgandhi 18:6a4db94011d3 915 /**
sahilmgandhi 18:6a4db94011d3 916 * @brief Get flag status of the NAND device.
sahilmgandhi 18:6a4db94011d3 917 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 918 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 919 * @param __FLAG__: FMC_NAND flag
sahilmgandhi 18:6a4db94011d3 920 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 921 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
sahilmgandhi 18:6a4db94011d3 922 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
sahilmgandhi 18:6a4db94011d3 923 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
sahilmgandhi 18:6a4db94011d3 924 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 925 * @retval The state of FLAG (SET or RESET).
sahilmgandhi 18:6a4db94011d3 926 */
sahilmgandhi 18:6a4db94011d3 927 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 928 /**
sahilmgandhi 18:6a4db94011d3 929 * @brief Clear flag status of the NAND device.
sahilmgandhi 18:6a4db94011d3 930 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 931 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 932 * @param __FLAG__: FMC_NAND flag
sahilmgandhi 18:6a4db94011d3 933 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 934 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
sahilmgandhi 18:6a4db94011d3 935 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
sahilmgandhi 18:6a4db94011d3 936 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
sahilmgandhi 18:6a4db94011d3 937 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 938 * @retval None
sahilmgandhi 18:6a4db94011d3 939 */
sahilmgandhi 18:6a4db94011d3 940 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
sahilmgandhi 18:6a4db94011d3 941 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
sahilmgandhi 18:6a4db94011d3 942 /**
sahilmgandhi 18:6a4db94011d3 943 * @brief Enable the NAND device interrupt.
sahilmgandhi 18:6a4db94011d3 944 * @param __INSTANCE__: FMC_NAND instance
sahilmgandhi 18:6a4db94011d3 945 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 946 * @param __INTERRUPT__: FMC_NAND interrupt
sahilmgandhi 18:6a4db94011d3 947 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 948 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
sahilmgandhi 18:6a4db94011d3 949 * @arg FMC_IT_LEVEL: Interrupt level.
sahilmgandhi 18:6a4db94011d3 950 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
sahilmgandhi 18:6a4db94011d3 951 * @retval None
sahilmgandhi 18:6a4db94011d3 952 */
sahilmgandhi 18:6a4db94011d3 953 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
sahilmgandhi 18:6a4db94011d3 954 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 955
sahilmgandhi 18:6a4db94011d3 956 /**
sahilmgandhi 18:6a4db94011d3 957 * @brief Disable the NAND device interrupt.
sahilmgandhi 18:6a4db94011d3 958 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 959 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 960 * @param __INTERRUPT__: FMC_NAND interrupt
sahilmgandhi 18:6a4db94011d3 961 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 962 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
sahilmgandhi 18:6a4db94011d3 963 * @arg FMC_IT_LEVEL: Interrupt level.
sahilmgandhi 18:6a4db94011d3 964 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
sahilmgandhi 18:6a4db94011d3 965 * @retval None
sahilmgandhi 18:6a4db94011d3 966 */
sahilmgandhi 18:6a4db94011d3 967 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
sahilmgandhi 18:6a4db94011d3 968 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 /**
sahilmgandhi 18:6a4db94011d3 971 * @brief Get flag status of the NAND device.
sahilmgandhi 18:6a4db94011d3 972 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 973 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 974 * @param __FLAG__: FMC_NAND flag
sahilmgandhi 18:6a4db94011d3 975 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 976 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
sahilmgandhi 18:6a4db94011d3 977 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
sahilmgandhi 18:6a4db94011d3 978 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
sahilmgandhi 18:6a4db94011d3 979 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 980 * @retval The state of FLAG (SET or RESET).
sahilmgandhi 18:6a4db94011d3 981 */
sahilmgandhi 18:6a4db94011d3 982 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
sahilmgandhi 18:6a4db94011d3 983 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
sahilmgandhi 18:6a4db94011d3 984 /**
sahilmgandhi 18:6a4db94011d3 985 * @brief Clear flag status of the NAND device.
sahilmgandhi 18:6a4db94011d3 986 * @param __INSTANCE__: FMC_NAND Instance
sahilmgandhi 18:6a4db94011d3 987 * @param __BANK__: FMC_NAND Bank
sahilmgandhi 18:6a4db94011d3 988 * @param __FLAG__: FMC_NAND flag
sahilmgandhi 18:6a4db94011d3 989 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 990 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
sahilmgandhi 18:6a4db94011d3 991 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
sahilmgandhi 18:6a4db94011d3 992 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
sahilmgandhi 18:6a4db94011d3 993 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 994 * @retval None
sahilmgandhi 18:6a4db94011d3 995 */
sahilmgandhi 18:6a4db94011d3 996 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
sahilmgandhi 18:6a4db94011d3 997 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
sahilmgandhi 18:6a4db94011d3 998 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
sahilmgandhi 18:6a4db94011d3 1001 /**
sahilmgandhi 18:6a4db94011d3 1002 * @brief Enable the PCCARD device interrupt.
sahilmgandhi 18:6a4db94011d3 1003 * @param __INSTANCE__: FMC_PCCARD instance
sahilmgandhi 18:6a4db94011d3 1004 * @param __INTERRUPT__: FMC_PCCARD interrupt
sahilmgandhi 18:6a4db94011d3 1005 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1006 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
sahilmgandhi 18:6a4db94011d3 1007 * @arg FMC_IT_LEVEL: Interrupt level.
sahilmgandhi 18:6a4db94011d3 1008 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
sahilmgandhi 18:6a4db94011d3 1009 * @retval None
sahilmgandhi 18:6a4db94011d3 1010 */
sahilmgandhi 18:6a4db94011d3 1011 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /**
sahilmgandhi 18:6a4db94011d3 1014 * @brief Disable the PCCARD device interrupt.
sahilmgandhi 18:6a4db94011d3 1015 * @param __INSTANCE__: FMC_PCCARD instance
sahilmgandhi 18:6a4db94011d3 1016 * @param __INTERRUPT__: FMC_PCCARD interrupt
sahilmgandhi 18:6a4db94011d3 1017 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1018 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
sahilmgandhi 18:6a4db94011d3 1019 * @arg FMC_IT_LEVEL: Interrupt level.
sahilmgandhi 18:6a4db94011d3 1020 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
sahilmgandhi 18:6a4db94011d3 1021 * @retval None
sahilmgandhi 18:6a4db94011d3 1022 */
sahilmgandhi 18:6a4db94011d3 1023 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1024
sahilmgandhi 18:6a4db94011d3 1025 /**
sahilmgandhi 18:6a4db94011d3 1026 * @brief Get flag status of the PCCARD device.
sahilmgandhi 18:6a4db94011d3 1027 * @param __INSTANCE__: FMC_PCCARD instance
sahilmgandhi 18:6a4db94011d3 1028 * @param __FLAG__: FMC_PCCARD flag
sahilmgandhi 18:6a4db94011d3 1029 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1030 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
sahilmgandhi 18:6a4db94011d3 1031 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
sahilmgandhi 18:6a4db94011d3 1032 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
sahilmgandhi 18:6a4db94011d3 1033 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 1034 * @retval The state of FLAG (SET or RESET).
sahilmgandhi 18:6a4db94011d3 1035 */
sahilmgandhi 18:6a4db94011d3 1036 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 1037
sahilmgandhi 18:6a4db94011d3 1038 /**
sahilmgandhi 18:6a4db94011d3 1039 * @brief Clear flag status of the PCCARD device.
sahilmgandhi 18:6a4db94011d3 1040 * @param __INSTANCE__: FMC_PCCARD instance
sahilmgandhi 18:6a4db94011d3 1041 * @param __FLAG__: FMC_PCCARD flag
sahilmgandhi 18:6a4db94011d3 1042 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1043 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
sahilmgandhi 18:6a4db94011d3 1044 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
sahilmgandhi 18:6a4db94011d3 1045 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
sahilmgandhi 18:6a4db94011d3 1046 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 1047 * @retval None
sahilmgandhi 18:6a4db94011d3 1048 */
sahilmgandhi 18:6a4db94011d3 1049 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
sahilmgandhi 18:6a4db94011d3 1050 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 /**
sahilmgandhi 18:6a4db94011d3 1053 * @brief Enable the SDRAM device interrupt.
sahilmgandhi 18:6a4db94011d3 1054 * @param __INSTANCE__: FMC_SDRAM instance
sahilmgandhi 18:6a4db94011d3 1055 * @param __INTERRUPT__: FMC_SDRAM interrupt
sahilmgandhi 18:6a4db94011d3 1056 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1057 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
sahilmgandhi 18:6a4db94011d3 1058 * @retval None
sahilmgandhi 18:6a4db94011d3 1059 */
sahilmgandhi 18:6a4db94011d3 1060 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /**
sahilmgandhi 18:6a4db94011d3 1063 * @brief Disable the SDRAM device interrupt.
sahilmgandhi 18:6a4db94011d3 1064 * @param __INSTANCE__: FMC_SDRAM instance
sahilmgandhi 18:6a4db94011d3 1065 * @param __INTERRUPT__: FMC_SDRAM interrupt
sahilmgandhi 18:6a4db94011d3 1066 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1067 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
sahilmgandhi 18:6a4db94011d3 1068 * @retval None
sahilmgandhi 18:6a4db94011d3 1069 */
sahilmgandhi 18:6a4db94011d3 1070 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /**
sahilmgandhi 18:6a4db94011d3 1073 * @brief Get flag status of the SDRAM device.
sahilmgandhi 18:6a4db94011d3 1074 * @param __INSTANCE__: FMC_SDRAM instance
sahilmgandhi 18:6a4db94011d3 1075 * @param __FLAG__: FMC_SDRAM flag
sahilmgandhi 18:6a4db94011d3 1076 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1077 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
sahilmgandhi 18:6a4db94011d3 1078 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
sahilmgandhi 18:6a4db94011d3 1079 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
sahilmgandhi 18:6a4db94011d3 1080 * @retval The state of FLAG (SET or RESET).
sahilmgandhi 18:6a4db94011d3 1081 */
sahilmgandhi 18:6a4db94011d3 1082 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 1083
sahilmgandhi 18:6a4db94011d3 1084 /**
sahilmgandhi 18:6a4db94011d3 1085 * @brief Clear flag status of the SDRAM device.
sahilmgandhi 18:6a4db94011d3 1086 * @param __INSTANCE__: FMC_SDRAM instance
sahilmgandhi 18:6a4db94011d3 1087 * @param __FLAG__: FMC_SDRAM flag
sahilmgandhi 18:6a4db94011d3 1088 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1089 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
sahilmgandhi 18:6a4db94011d3 1090 * @retval None
sahilmgandhi 18:6a4db94011d3 1091 */
sahilmgandhi 18:6a4db94011d3 1092 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
sahilmgandhi 18:6a4db94011d3 1093 /**
sahilmgandhi 18:6a4db94011d3 1094 * @}
sahilmgandhi 18:6a4db94011d3 1095 */
sahilmgandhi 18:6a4db94011d3 1096
sahilmgandhi 18:6a4db94011d3 1097 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
sahilmgandhi 18:6a4db94011d3 1098 * @{
sahilmgandhi 18:6a4db94011d3 1099 */
sahilmgandhi 18:6a4db94011d3 1100 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
sahilmgandhi 18:6a4db94011d3 1101 ((BANK) == FMC_NORSRAM_BANK2) || \
sahilmgandhi 18:6a4db94011d3 1102 ((BANK) == FMC_NORSRAM_BANK3) || \
sahilmgandhi 18:6a4db94011d3 1103 ((BANK) == FMC_NORSRAM_BANK4))
sahilmgandhi 18:6a4db94011d3 1104
sahilmgandhi 18:6a4db94011d3 1105 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1106 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
sahilmgandhi 18:6a4db94011d3 1109 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
sahilmgandhi 18:6a4db94011d3 1110 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
sahilmgandhi 18:6a4db94011d3 1111
sahilmgandhi 18:6a4db94011d3 1112 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
sahilmgandhi 18:6a4db94011d3 1113 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
sahilmgandhi 18:6a4db94011d3 1114 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
sahilmgandhi 18:6a4db94011d3 1115
sahilmgandhi 18:6a4db94011d3 1116 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
sahilmgandhi 18:6a4db94011d3 1117 ((__MODE__) == FMC_ACCESS_MODE_B) || \
sahilmgandhi 18:6a4db94011d3 1118 ((__MODE__) == FMC_ACCESS_MODE_C) || \
sahilmgandhi 18:6a4db94011d3 1119 ((__MODE__) == FMC_ACCESS_MODE_D))
sahilmgandhi 18:6a4db94011d3 1120
sahilmgandhi 18:6a4db94011d3 1121 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
sahilmgandhi 18:6a4db94011d3 1122 ((BANK) == FMC_NAND_BANK3))
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1125 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
sahilmgandhi 18:6a4db94011d3 1126
sahilmgandhi 18:6a4db94011d3 1127 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
sahilmgandhi 18:6a4db94011d3 1128 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
sahilmgandhi 18:6a4db94011d3 1129
sahilmgandhi 18:6a4db94011d3 1130 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1131 ((STATE) == FMC_NAND_ECC_ENABLE))
sahilmgandhi 18:6a4db94011d3 1132
sahilmgandhi 18:6a4db94011d3 1133 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
sahilmgandhi 18:6a4db94011d3 1134 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
sahilmgandhi 18:6a4db94011d3 1135 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
sahilmgandhi 18:6a4db94011d3 1136 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
sahilmgandhi 18:6a4db94011d3 1137 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
sahilmgandhi 18:6a4db94011d3 1138 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
sahilmgandhi 18:6a4db94011d3 1141
sahilmgandhi 18:6a4db94011d3 1142 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
sahilmgandhi 18:6a4db94011d3 1143
sahilmgandhi 18:6a4db94011d3 1144 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
sahilmgandhi 18:6a4db94011d3 1147
sahilmgandhi 18:6a4db94011d3 1148 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
sahilmgandhi 18:6a4db94011d3 1153
sahilmgandhi 18:6a4db94011d3 1154 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
sahilmgandhi 18:6a4db94011d3 1155
sahilmgandhi 18:6a4db94011d3 1156 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
sahilmgandhi 18:6a4db94011d3 1159
sahilmgandhi 18:6a4db94011d3 1160 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1161 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
sahilmgandhi 18:6a4db94011d3 1164 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
sahilmgandhi 18:6a4db94011d3 1165
sahilmgandhi 18:6a4db94011d3 1166 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
sahilmgandhi 18:6a4db94011d3 1167 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1168 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
sahilmgandhi 18:6a4db94011d3 1169 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
sahilmgandhi 18:6a4db94011d3 1170
sahilmgandhi 18:6a4db94011d3 1171 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
sahilmgandhi 18:6a4db94011d3 1172 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
sahilmgandhi 18:6a4db94011d3 1173
sahilmgandhi 18:6a4db94011d3 1174 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1175 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
sahilmgandhi 18:6a4db94011d3 1176
sahilmgandhi 18:6a4db94011d3 1177 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1178 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1181 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
sahilmgandhi 18:6a4db94011d3 1182
sahilmgandhi 18:6a4db94011d3 1183 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1184 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
sahilmgandhi 18:6a4db94011d3 1185
sahilmgandhi 18:6a4db94011d3 1186 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1187 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
sahilmgandhi 18:6a4db94011d3 1188
sahilmgandhi 18:6a4db94011d3 1189 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
sahilmgandhi 18:6a4db94011d3 1190 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
sahilmgandhi 18:6a4db94011d3 1191
sahilmgandhi 18:6a4db94011d3 1192 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
sahilmgandhi 18:6a4db94011d3 1195
sahilmgandhi 18:6a4db94011d3 1196 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
sahilmgandhi 18:6a4db94011d3 1199
sahilmgandhi 18:6a4db94011d3 1200 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
sahilmgandhi 18:6a4db94011d3 1201
sahilmgandhi 18:6a4db94011d3 1202 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
sahilmgandhi 18:6a4db94011d3 1205 ((BANK) == FMC_SDRAM_BANK2))
sahilmgandhi 18:6a4db94011d3 1206
sahilmgandhi 18:6a4db94011d3 1207 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
sahilmgandhi 18:6a4db94011d3 1208 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
sahilmgandhi 18:6a4db94011d3 1209 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
sahilmgandhi 18:6a4db94011d3 1210 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
sahilmgandhi 18:6a4db94011d3 1213 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
sahilmgandhi 18:6a4db94011d3 1214 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
sahilmgandhi 18:6a4db94011d3 1215
sahilmgandhi 18:6a4db94011d3 1216 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
sahilmgandhi 18:6a4db94011d3 1217 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
sahilmgandhi 18:6a4db94011d3 1218 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
sahilmgandhi 18:6a4db94011d3 1219
sahilmgandhi 18:6a4db94011d3 1220 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
sahilmgandhi 18:6a4db94011d3 1221 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
sahilmgandhi 18:6a4db94011d3 1222
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
sahilmgandhi 18:6a4db94011d3 1225 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
sahilmgandhi 18:6a4db94011d3 1226 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
sahilmgandhi 18:6a4db94011d3 1227
sahilmgandhi 18:6a4db94011d3 1228 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1229 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
sahilmgandhi 18:6a4db94011d3 1230 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
sahilmgandhi 18:6a4db94011d3 1231
sahilmgandhi 18:6a4db94011d3 1232 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1233 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
sahilmgandhi 18:6a4db94011d3 1234
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
sahilmgandhi 18:6a4db94011d3 1237 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
sahilmgandhi 18:6a4db94011d3 1238 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
sahilmgandhi 18:6a4db94011d3 1239
sahilmgandhi 18:6a4db94011d3 1240 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
sahilmgandhi 18:6a4db94011d3 1241
sahilmgandhi 18:6a4db94011d3 1242 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
sahilmgandhi 18:6a4db94011d3 1245
sahilmgandhi 18:6a4db94011d3 1246 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
sahilmgandhi 18:6a4db94011d3 1247
sahilmgandhi 18:6a4db94011d3 1248 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
sahilmgandhi 18:6a4db94011d3 1249
sahilmgandhi 18:6a4db94011d3 1250 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
sahilmgandhi 18:6a4db94011d3 1253
sahilmgandhi 18:6a4db94011d3 1254 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
sahilmgandhi 18:6a4db94011d3 1255 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
sahilmgandhi 18:6a4db94011d3 1256 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
sahilmgandhi 18:6a4db94011d3 1257 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
sahilmgandhi 18:6a4db94011d3 1258 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
sahilmgandhi 18:6a4db94011d3 1259 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
sahilmgandhi 18:6a4db94011d3 1260 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
sahilmgandhi 18:6a4db94011d3 1261
sahilmgandhi 18:6a4db94011d3 1262 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
sahilmgandhi 18:6a4db94011d3 1263 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
sahilmgandhi 18:6a4db94011d3 1264 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
sahilmgandhi 18:6a4db94011d3 1265
sahilmgandhi 18:6a4db94011d3 1266 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
sahilmgandhi 18:6a4db94011d3 1267
sahilmgandhi 18:6a4db94011d3 1268 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
sahilmgandhi 18:6a4db94011d3 1269
sahilmgandhi 18:6a4db94011d3 1270 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
sahilmgandhi 18:6a4db94011d3 1271
sahilmgandhi 18:6a4db94011d3 1272 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
sahilmgandhi 18:6a4db94011d3 1273
sahilmgandhi 18:6a4db94011d3 1274 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1275 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
sahilmgandhi 18:6a4db94011d3 1276
sahilmgandhi 18:6a4db94011d3 1277 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
sahilmgandhi 18:6a4db94011d3 1278 ((SIZE) == FMC_PAGE_SIZE_128) || \
sahilmgandhi 18:6a4db94011d3 1279 ((SIZE) == FMC_PAGE_SIZE_256) || \
sahilmgandhi 18:6a4db94011d3 1280 ((SIZE) == FMC_PAGE_SIZE_512) || \
sahilmgandhi 18:6a4db94011d3 1281 ((SIZE) == FMC_PAGE_SIZE_1024))
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 1284 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 1285 ((FIFO) == FMC_WRITE_FIFO_ENABLE))
sahilmgandhi 18:6a4db94011d3 1286 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 1287
sahilmgandhi 18:6a4db94011d3 1288 /**
sahilmgandhi 18:6a4db94011d3 1289 * @}
sahilmgandhi 18:6a4db94011d3 1290 */
sahilmgandhi 18:6a4db94011d3 1291
sahilmgandhi 18:6a4db94011d3 1292 /**
sahilmgandhi 18:6a4db94011d3 1293 * @}
sahilmgandhi 18:6a4db94011d3 1294 */
sahilmgandhi 18:6a4db94011d3 1295
sahilmgandhi 18:6a4db94011d3 1296 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1297 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
sahilmgandhi 18:6a4db94011d3 1298 * @{
sahilmgandhi 18:6a4db94011d3 1299 */
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301 /** @defgroup FMC_LL_NORSRAM NOR SRAM
sahilmgandhi 18:6a4db94011d3 1302 * @{
sahilmgandhi 18:6a4db94011d3 1303 */
sahilmgandhi 18:6a4db94011d3 1304 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 1305 * @{
sahilmgandhi 18:6a4db94011d3 1306 */
sahilmgandhi 18:6a4db94011d3 1307 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
sahilmgandhi 18:6a4db94011d3 1308 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1309 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
sahilmgandhi 18:6a4db94011d3 1310 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1311 /**
sahilmgandhi 18:6a4db94011d3 1312 * @}
sahilmgandhi 18:6a4db94011d3 1313 */
sahilmgandhi 18:6a4db94011d3 1314
sahilmgandhi 18:6a4db94011d3 1315 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
sahilmgandhi 18:6a4db94011d3 1316 * @{
sahilmgandhi 18:6a4db94011d3 1317 */
sahilmgandhi 18:6a4db94011d3 1318 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1319 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1320 /**
sahilmgandhi 18:6a4db94011d3 1321 * @}
sahilmgandhi 18:6a4db94011d3 1322 */
sahilmgandhi 18:6a4db94011d3 1323 /**
sahilmgandhi 18:6a4db94011d3 1324 * @}
sahilmgandhi 18:6a4db94011d3 1325 */
sahilmgandhi 18:6a4db94011d3 1326
sahilmgandhi 18:6a4db94011d3 1327 /** @defgroup FMC_LL_NAND NAND
sahilmgandhi 18:6a4db94011d3 1328 * @{
sahilmgandhi 18:6a4db94011d3 1329 */
sahilmgandhi 18:6a4db94011d3 1330 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 1331 * @{
sahilmgandhi 18:6a4db94011d3 1332 */
sahilmgandhi 18:6a4db94011d3 1333 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
sahilmgandhi 18:6a4db94011d3 1334 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1335 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1336 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1337 /**
sahilmgandhi 18:6a4db94011d3 1338 * @}
sahilmgandhi 18:6a4db94011d3 1339 */
sahilmgandhi 18:6a4db94011d3 1340
sahilmgandhi 18:6a4db94011d3 1341 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
sahilmgandhi 18:6a4db94011d3 1342 * @{
sahilmgandhi 18:6a4db94011d3 1343 */
sahilmgandhi 18:6a4db94011d3 1344 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1345 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1346 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 1347
sahilmgandhi 18:6a4db94011d3 1348 /**
sahilmgandhi 18:6a4db94011d3 1349 * @}
sahilmgandhi 18:6a4db94011d3 1350 */
sahilmgandhi 18:6a4db94011d3 1351 /**
sahilmgandhi 18:6a4db94011d3 1352 * @}
sahilmgandhi 18:6a4db94011d3 1353 */
sahilmgandhi 18:6a4db94011d3 1354 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
sahilmgandhi 18:6a4db94011d3 1355 /** @defgroup FMC_LL_PCCARD PCCARD
sahilmgandhi 18:6a4db94011d3 1356 * @{
sahilmgandhi 18:6a4db94011d3 1357 */
sahilmgandhi 18:6a4db94011d3 1358 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 1359 * @{
sahilmgandhi 18:6a4db94011d3 1360 */
sahilmgandhi 18:6a4db94011d3 1361 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
sahilmgandhi 18:6a4db94011d3 1362 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
sahilmgandhi 18:6a4db94011d3 1363 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
sahilmgandhi 18:6a4db94011d3 1364 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
sahilmgandhi 18:6a4db94011d3 1365 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
sahilmgandhi 18:6a4db94011d3 1366 /**
sahilmgandhi 18:6a4db94011d3 1367 * @}
sahilmgandhi 18:6a4db94011d3 1368 */
sahilmgandhi 18:6a4db94011d3 1369 /**
sahilmgandhi 18:6a4db94011d3 1370 * @}
sahilmgandhi 18:6a4db94011d3 1371 */
sahilmgandhi 18:6a4db94011d3 1372 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
sahilmgandhi 18:6a4db94011d3 1373
sahilmgandhi 18:6a4db94011d3 1374 /** @defgroup FMC_LL_SDRAM SDRAM
sahilmgandhi 18:6a4db94011d3 1375 * @{
sahilmgandhi 18:6a4db94011d3 1376 */
sahilmgandhi 18:6a4db94011d3 1377 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 1378 * @{
sahilmgandhi 18:6a4db94011d3 1379 */
sahilmgandhi 18:6a4db94011d3 1380 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
sahilmgandhi 18:6a4db94011d3 1381 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1382 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1383 /**
sahilmgandhi 18:6a4db94011d3 1384 * @}
sahilmgandhi 18:6a4db94011d3 1385 */
sahilmgandhi 18:6a4db94011d3 1386
sahilmgandhi 18:6a4db94011d3 1387 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
sahilmgandhi 18:6a4db94011d3 1388 * @{
sahilmgandhi 18:6a4db94011d3 1389 */
sahilmgandhi 18:6a4db94011d3 1390 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1391 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1392 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 1393 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
sahilmgandhi 18:6a4db94011d3 1394 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
sahilmgandhi 18:6a4db94011d3 1395 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
sahilmgandhi 18:6a4db94011d3 1396 /**
sahilmgandhi 18:6a4db94011d3 1397 * @}
sahilmgandhi 18:6a4db94011d3 1398 */
sahilmgandhi 18:6a4db94011d3 1399 /**
sahilmgandhi 18:6a4db94011d3 1400 * @}
sahilmgandhi 18:6a4db94011d3 1401 */
sahilmgandhi 18:6a4db94011d3 1402
sahilmgandhi 18:6a4db94011d3 1403 /**
sahilmgandhi 18:6a4db94011d3 1404 * @}
sahilmgandhi 18:6a4db94011d3 1405 */
sahilmgandhi 18:6a4db94011d3 1406
sahilmgandhi 18:6a4db94011d3 1407 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 1408 /**
sahilmgandhi 18:6a4db94011d3 1409 * @}
sahilmgandhi 18:6a4db94011d3 1410 */
sahilmgandhi 18:6a4db94011d3 1411
sahilmgandhi 18:6a4db94011d3 1412 /**
sahilmgandhi 18:6a4db94011d3 1413 * @}
sahilmgandhi 18:6a4db94011d3 1414 */
sahilmgandhi 18:6a4db94011d3 1415 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1416 }
sahilmgandhi 18:6a4db94011d3 1417 #endif
sahilmgandhi 18:6a4db94011d3 1418
sahilmgandhi 18:6a4db94011d3 1419 #endif /* __STM32F4xx_LL_FMC_H */
sahilmgandhi 18:6a4db94011d3 1420
sahilmgandhi 18:6a4db94011d3 1421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/