Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file stm32f4xx_hal_sdram.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.5.0 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 06-May-2016 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief SDRAM HAL module driver. |
sahilmgandhi | 18:6a4db94011d3 | 8 | * This file provides a generic firmware to drive SDRAM memories mounted |
sahilmgandhi | 18:6a4db94011d3 | 9 | * as external device. |
sahilmgandhi | 18:6a4db94011d3 | 10 | * |
sahilmgandhi | 18:6a4db94011d3 | 11 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 12 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 13 | ##### How to use this driver ##### |
sahilmgandhi | 18:6a4db94011d3 | 14 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 15 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 16 | This driver is a generic layered driver which contains a set of APIs used to |
sahilmgandhi | 18:6a4db94011d3 | 17 | control SDRAM memories. It uses the FMC layer functions to interface |
sahilmgandhi | 18:6a4db94011d3 | 18 | with SDRAM devices. |
sahilmgandhi | 18:6a4db94011d3 | 19 | The following sequence should be followed to configure the FMC to interface |
sahilmgandhi | 18:6a4db94011d3 | 20 | with SDRAM memories: |
sahilmgandhi | 18:6a4db94011d3 | 21 | |
sahilmgandhi | 18:6a4db94011d3 | 22 | (#) Declare a SDRAM_HandleTypeDef handle structure, for example: |
sahilmgandhi | 18:6a4db94011d3 | 23 | SDRAM_HandleTypeDef hdsram |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed |
sahilmgandhi | 18:6a4db94011d3 | 26 | values of the structure member. |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined |
sahilmgandhi | 18:6a4db94011d3 | 29 | base register instance for NOR or SDRAM device |
sahilmgandhi | 18:6a4db94011d3 | 30 | |
sahilmgandhi | 18:6a4db94011d3 | 31 | (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: |
sahilmgandhi | 18:6a4db94011d3 | 32 | FMC_SDRAM_TimingTypeDef Timing; |
sahilmgandhi | 18:6a4db94011d3 | 33 | and fill its fields with the allowed values of the structure member. |
sahilmgandhi | 18:6a4db94011d3 | 34 | |
sahilmgandhi | 18:6a4db94011d3 | 35 | (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function |
sahilmgandhi | 18:6a4db94011d3 | 36 | performs the following sequence: |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() |
sahilmgandhi | 18:6a4db94011d3 | 39 | (##) Control register configuration using the FMC SDRAM interface function |
sahilmgandhi | 18:6a4db94011d3 | 40 | FMC_SDRAM_Init() |
sahilmgandhi | 18:6a4db94011d3 | 41 | (##) Timing register configuration using the FMC SDRAM interface function |
sahilmgandhi | 18:6a4db94011d3 | 42 | FMC_SDRAM_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 43 | (##) Program the SDRAM external device by applying its initialization sequence |
sahilmgandhi | 18:6a4db94011d3 | 44 | according to the device plugged in your hardware. This step is mandatory |
sahilmgandhi | 18:6a4db94011d3 | 45 | for accessing the SDRAM device. |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | (#) At this stage you can perform read/write accesses from/to the memory connected |
sahilmgandhi | 18:6a4db94011d3 | 48 | to the SDRAM Bank. You can perform either polling or DMA transfer using the |
sahilmgandhi | 18:6a4db94011d3 | 49 | following APIs: |
sahilmgandhi | 18:6a4db94011d3 | 50 | (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access |
sahilmgandhi | 18:6a4db94011d3 | 51 | (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer |
sahilmgandhi | 18:6a4db94011d3 | 52 | |
sahilmgandhi | 18:6a4db94011d3 | 53 | (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ |
sahilmgandhi | 18:6a4db94011d3 | 54 | HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or |
sahilmgandhi | 18:6a4db94011d3 | 55 | the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM |
sahilmgandhi | 18:6a4db94011d3 | 56 | device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 57 | structure. |
sahilmgandhi | 18:6a4db94011d3 | 58 | |
sahilmgandhi | 18:6a4db94011d3 | 59 | (#) You can continuously monitor the SDRAM device HAL state by calling the function |
sahilmgandhi | 18:6a4db94011d3 | 60 | HAL_SDRAM_GetState() |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 63 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 64 | * @attention |
sahilmgandhi | 18:6a4db94011d3 | 65 | * |
sahilmgandhi | 18:6a4db94011d3 | 66 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
sahilmgandhi | 18:6a4db94011d3 | 67 | * |
sahilmgandhi | 18:6a4db94011d3 | 68 | * Redistribution and use in source and binary forms, with or without modification, |
sahilmgandhi | 18:6a4db94011d3 | 69 | * are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 70 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 71 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 72 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 73 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 74 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 75 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 76 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 77 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 78 | * |
sahilmgandhi | 18:6a4db94011d3 | 79 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 80 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 81 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 82 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 83 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 84 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 85 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 86 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 87 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 88 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 89 | * |
sahilmgandhi | 18:6a4db94011d3 | 90 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 91 | */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | |
sahilmgandhi | 18:6a4db94011d3 | 93 | /* Includes ------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 94 | #include "stm32f4xx_hal.h" |
sahilmgandhi | 18:6a4db94011d3 | 95 | |
sahilmgandhi | 18:6a4db94011d3 | 96 | /** @addtogroup STM32F4xx_HAL_Driver |
sahilmgandhi | 18:6a4db94011d3 | 97 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 98 | */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | |
sahilmgandhi | 18:6a4db94011d3 | 100 | /** @defgroup SDRAM SDRAM |
sahilmgandhi | 18:6a4db94011d3 | 101 | * @brief SDRAM driver modules |
sahilmgandhi | 18:6a4db94011d3 | 102 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 103 | */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | #ifdef HAL_SDRAM_MODULE_ENABLED |
sahilmgandhi | 18:6a4db94011d3 | 105 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
sahilmgandhi | 18:6a4db94011d3 | 106 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
sahilmgandhi | 18:6a4db94011d3 | 107 | |
sahilmgandhi | 18:6a4db94011d3 | 108 | /* Private typedef -----------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 109 | /* Private define ------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 110 | /* Private macro -------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 111 | /* Private variables ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 112 | /* Private functions ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 113 | /* Exported functions --------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 114 | /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions |
sahilmgandhi | 18:6a4db94011d3 | 115 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 116 | */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | |
sahilmgandhi | 18:6a4db94011d3 | 118 | /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
sahilmgandhi | 18:6a4db94011d3 | 119 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 120 | * |
sahilmgandhi | 18:6a4db94011d3 | 121 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 122 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 123 | ##### SDRAM Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 124 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 125 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 126 | This section provides functions allowing to initialize/de-initialize |
sahilmgandhi | 18:6a4db94011d3 | 127 | the SDRAM memory |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 130 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 131 | */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | /** |
sahilmgandhi | 18:6a4db94011d3 | 134 | * @brief Performs the SDRAM device initialization sequence. |
sahilmgandhi | 18:6a4db94011d3 | 135 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 136 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 137 | * @param Timing: Pointer to SDRAM control timing structure |
sahilmgandhi | 18:6a4db94011d3 | 138 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 139 | */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) |
sahilmgandhi | 18:6a4db94011d3 | 141 | { |
sahilmgandhi | 18:6a4db94011d3 | 142 | /* Check the SDRAM handle parameter */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | if(hsdram == NULL) |
sahilmgandhi | 18:6a4db94011d3 | 144 | { |
sahilmgandhi | 18:6a4db94011d3 | 145 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 146 | } |
sahilmgandhi | 18:6a4db94011d3 | 147 | |
sahilmgandhi | 18:6a4db94011d3 | 148 | if(hsdram->State == HAL_SDRAM_STATE_RESET) |
sahilmgandhi | 18:6a4db94011d3 | 149 | { |
sahilmgandhi | 18:6a4db94011d3 | 150 | /* Allocate lock resource and initialize it */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | hsdram->Lock = HAL_UNLOCKED; |
sahilmgandhi | 18:6a4db94011d3 | 152 | /* Initialize the low level hardware (MSP) */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | HAL_SDRAM_MspInit(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 154 | } |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | /* Initialize the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 157 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 158 | |
sahilmgandhi | 18:6a4db94011d3 | 159 | /* Initialize SDRAM control Interface */ |
sahilmgandhi | 18:6a4db94011d3 | 160 | FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); |
sahilmgandhi | 18:6a4db94011d3 | 161 | |
sahilmgandhi | 18:6a4db94011d3 | 162 | /* Initialize SDRAM timing Interface */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); |
sahilmgandhi | 18:6a4db94011d3 | 164 | |
sahilmgandhi | 18:6a4db94011d3 | 165 | /* Update the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | hsdram->State = HAL_SDRAM_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 167 | |
sahilmgandhi | 18:6a4db94011d3 | 168 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 169 | } |
sahilmgandhi | 18:6a4db94011d3 | 170 | |
sahilmgandhi | 18:6a4db94011d3 | 171 | /** |
sahilmgandhi | 18:6a4db94011d3 | 172 | * @brief Perform the SDRAM device initialization sequence. |
sahilmgandhi | 18:6a4db94011d3 | 173 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 174 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 175 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 176 | */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 178 | { |
sahilmgandhi | 18:6a4db94011d3 | 179 | /* Initialize the low level hardware (MSP) */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | HAL_SDRAM_MspDeInit(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | /* Configure the SDRAM registers with their reset values */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); |
sahilmgandhi | 18:6a4db94011d3 | 184 | |
sahilmgandhi | 18:6a4db94011d3 | 185 | /* Reset the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | hsdram->State = HAL_SDRAM_STATE_RESET; |
sahilmgandhi | 18:6a4db94011d3 | 187 | |
sahilmgandhi | 18:6a4db94011d3 | 188 | /* Release Lock */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 190 | |
sahilmgandhi | 18:6a4db94011d3 | 191 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 192 | } |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | /** |
sahilmgandhi | 18:6a4db94011d3 | 195 | * @brief SDRAM MSP Init. |
sahilmgandhi | 18:6a4db94011d3 | 196 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 197 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 198 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 199 | */ |
sahilmgandhi | 18:6a4db94011d3 | 200 | __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 201 | { |
sahilmgandhi | 18:6a4db94011d3 | 202 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 203 | UNUSED(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 204 | /* NOTE: This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 205 | the HAL_SDRAM_MspInit could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 206 | */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | } |
sahilmgandhi | 18:6a4db94011d3 | 208 | |
sahilmgandhi | 18:6a4db94011d3 | 209 | /** |
sahilmgandhi | 18:6a4db94011d3 | 210 | * @brief SDRAM MSP DeInit. |
sahilmgandhi | 18:6a4db94011d3 | 211 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 212 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 213 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 214 | */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 216 | { |
sahilmgandhi | 18:6a4db94011d3 | 217 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 218 | UNUSED(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 219 | /* NOTE: This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 220 | the HAL_SDRAM_MspDeInit could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 221 | */ |
sahilmgandhi | 18:6a4db94011d3 | 222 | } |
sahilmgandhi | 18:6a4db94011d3 | 223 | |
sahilmgandhi | 18:6a4db94011d3 | 224 | /** |
sahilmgandhi | 18:6a4db94011d3 | 225 | * @brief This function handles SDRAM refresh error interrupt request. |
sahilmgandhi | 18:6a4db94011d3 | 226 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 227 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 228 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 229 | */ |
sahilmgandhi | 18:6a4db94011d3 | 230 | void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 231 | { |
sahilmgandhi | 18:6a4db94011d3 | 232 | /* Check SDRAM interrupt Rising edge flag */ |
sahilmgandhi | 18:6a4db94011d3 | 233 | if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) |
sahilmgandhi | 18:6a4db94011d3 | 234 | { |
sahilmgandhi | 18:6a4db94011d3 | 235 | /* SDRAM refresh error interrupt callback */ |
sahilmgandhi | 18:6a4db94011d3 | 236 | HAL_SDRAM_RefreshErrorCallback(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 237 | |
sahilmgandhi | 18:6a4db94011d3 | 238 | /* Clear SDRAM refresh error interrupt pending bit */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); |
sahilmgandhi | 18:6a4db94011d3 | 240 | } |
sahilmgandhi | 18:6a4db94011d3 | 241 | } |
sahilmgandhi | 18:6a4db94011d3 | 242 | |
sahilmgandhi | 18:6a4db94011d3 | 243 | /** |
sahilmgandhi | 18:6a4db94011d3 | 244 | * @brief SDRAM Refresh error callback. |
sahilmgandhi | 18:6a4db94011d3 | 245 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 246 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 247 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 248 | */ |
sahilmgandhi | 18:6a4db94011d3 | 249 | __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 250 | { |
sahilmgandhi | 18:6a4db94011d3 | 251 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 252 | UNUSED(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 253 | /* NOTE: This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 254 | the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 255 | */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | } |
sahilmgandhi | 18:6a4db94011d3 | 257 | |
sahilmgandhi | 18:6a4db94011d3 | 258 | /** |
sahilmgandhi | 18:6a4db94011d3 | 259 | * @brief DMA transfer complete callback. |
sahilmgandhi | 18:6a4db94011d3 | 260 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 261 | * the configuration information for the specified DMA module. |
sahilmgandhi | 18:6a4db94011d3 | 262 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 263 | */ |
sahilmgandhi | 18:6a4db94011d3 | 264 | __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) |
sahilmgandhi | 18:6a4db94011d3 | 265 | { |
sahilmgandhi | 18:6a4db94011d3 | 266 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 267 | UNUSED(hdma); |
sahilmgandhi | 18:6a4db94011d3 | 268 | /* NOTE: This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 269 | the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 270 | */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | } |
sahilmgandhi | 18:6a4db94011d3 | 272 | |
sahilmgandhi | 18:6a4db94011d3 | 273 | /** |
sahilmgandhi | 18:6a4db94011d3 | 274 | * @brief DMA transfer complete error callback. |
sahilmgandhi | 18:6a4db94011d3 | 275 | * @param hdma: DMA handle |
sahilmgandhi | 18:6a4db94011d3 | 276 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 277 | */ |
sahilmgandhi | 18:6a4db94011d3 | 278 | __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) |
sahilmgandhi | 18:6a4db94011d3 | 279 | { |
sahilmgandhi | 18:6a4db94011d3 | 280 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | UNUSED(hdma); |
sahilmgandhi | 18:6a4db94011d3 | 282 | /* NOTE: This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 283 | the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 284 | */ |
sahilmgandhi | 18:6a4db94011d3 | 285 | } |
sahilmgandhi | 18:6a4db94011d3 | 286 | /** |
sahilmgandhi | 18:6a4db94011d3 | 287 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 288 | */ |
sahilmgandhi | 18:6a4db94011d3 | 289 | |
sahilmgandhi | 18:6a4db94011d3 | 290 | /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions |
sahilmgandhi | 18:6a4db94011d3 | 291 | * @brief Input Output and memory control functions |
sahilmgandhi | 18:6a4db94011d3 | 292 | * |
sahilmgandhi | 18:6a4db94011d3 | 293 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 294 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 295 | ##### SDRAM Input and Output functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 296 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 297 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 298 | This section provides functions allowing to use and control the SDRAM memory |
sahilmgandhi | 18:6a4db94011d3 | 299 | |
sahilmgandhi | 18:6a4db94011d3 | 300 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 301 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 302 | */ |
sahilmgandhi | 18:6a4db94011d3 | 303 | |
sahilmgandhi | 18:6a4db94011d3 | 304 | /** |
sahilmgandhi | 18:6a4db94011d3 | 305 | * @brief Reads 8-bit data buffer from the SDRAM memory. |
sahilmgandhi | 18:6a4db94011d3 | 306 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 307 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 308 | * @param pAddress: Pointer to read start address |
sahilmgandhi | 18:6a4db94011d3 | 309 | * @param pDstBuffer: Pointer to destination buffer |
sahilmgandhi | 18:6a4db94011d3 | 310 | * @param BufferSize: Size of the buffer to read from memory |
sahilmgandhi | 18:6a4db94011d3 | 311 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 312 | */ |
sahilmgandhi | 18:6a4db94011d3 | 313 | HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 314 | { |
sahilmgandhi | 18:6a4db94011d3 | 315 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 316 | |
sahilmgandhi | 18:6a4db94011d3 | 317 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 319 | |
sahilmgandhi | 18:6a4db94011d3 | 320 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 321 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 322 | { |
sahilmgandhi | 18:6a4db94011d3 | 323 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 324 | } |
sahilmgandhi | 18:6a4db94011d3 | 325 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
sahilmgandhi | 18:6a4db94011d3 | 326 | { |
sahilmgandhi | 18:6a4db94011d3 | 327 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 328 | } |
sahilmgandhi | 18:6a4db94011d3 | 329 | |
sahilmgandhi | 18:6a4db94011d3 | 330 | /* Read data from source */ |
sahilmgandhi | 18:6a4db94011d3 | 331 | for(; BufferSize != 0U; BufferSize--) |
sahilmgandhi | 18:6a4db94011d3 | 332 | { |
sahilmgandhi | 18:6a4db94011d3 | 333 | *pDstBuffer = *(__IO uint8_t *)pSdramAddress; |
sahilmgandhi | 18:6a4db94011d3 | 334 | pDstBuffer++; |
sahilmgandhi | 18:6a4db94011d3 | 335 | pSdramAddress++; |
sahilmgandhi | 18:6a4db94011d3 | 336 | } |
sahilmgandhi | 18:6a4db94011d3 | 337 | |
sahilmgandhi | 18:6a4db94011d3 | 338 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 340 | |
sahilmgandhi | 18:6a4db94011d3 | 341 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 342 | } |
sahilmgandhi | 18:6a4db94011d3 | 343 | |
sahilmgandhi | 18:6a4db94011d3 | 344 | /** |
sahilmgandhi | 18:6a4db94011d3 | 345 | * @brief Writes 8-bit data buffer to SDRAM memory. |
sahilmgandhi | 18:6a4db94011d3 | 346 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 347 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 348 | * @param pAddress: Pointer to write start address |
sahilmgandhi | 18:6a4db94011d3 | 349 | * @param pSrcBuffer: Pointer to source buffer to write |
sahilmgandhi | 18:6a4db94011d3 | 350 | * @param BufferSize: Size of the buffer to write to memory |
sahilmgandhi | 18:6a4db94011d3 | 351 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 352 | */ |
sahilmgandhi | 18:6a4db94011d3 | 353 | HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 354 | { |
sahilmgandhi | 18:6a4db94011d3 | 355 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 356 | uint32_t tmp = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 357 | |
sahilmgandhi | 18:6a4db94011d3 | 358 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 359 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 360 | |
sahilmgandhi | 18:6a4db94011d3 | 361 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 362 | tmp = hsdram->State; |
sahilmgandhi | 18:6a4db94011d3 | 363 | |
sahilmgandhi | 18:6a4db94011d3 | 364 | if(tmp == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 365 | { |
sahilmgandhi | 18:6a4db94011d3 | 366 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 367 | } |
sahilmgandhi | 18:6a4db94011d3 | 368 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
sahilmgandhi | 18:6a4db94011d3 | 369 | { |
sahilmgandhi | 18:6a4db94011d3 | 370 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 371 | } |
sahilmgandhi | 18:6a4db94011d3 | 372 | |
sahilmgandhi | 18:6a4db94011d3 | 373 | /* Write data to memory */ |
sahilmgandhi | 18:6a4db94011d3 | 374 | for(; BufferSize != 0U; BufferSize--) |
sahilmgandhi | 18:6a4db94011d3 | 375 | { |
sahilmgandhi | 18:6a4db94011d3 | 376 | *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; |
sahilmgandhi | 18:6a4db94011d3 | 377 | pSrcBuffer++; |
sahilmgandhi | 18:6a4db94011d3 | 378 | pSdramAddress++; |
sahilmgandhi | 18:6a4db94011d3 | 379 | } |
sahilmgandhi | 18:6a4db94011d3 | 380 | |
sahilmgandhi | 18:6a4db94011d3 | 381 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 382 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 383 | |
sahilmgandhi | 18:6a4db94011d3 | 384 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 385 | } |
sahilmgandhi | 18:6a4db94011d3 | 386 | |
sahilmgandhi | 18:6a4db94011d3 | 387 | /** |
sahilmgandhi | 18:6a4db94011d3 | 388 | * @brief Reads 16-bit data buffer from the SDRAM memory. |
sahilmgandhi | 18:6a4db94011d3 | 389 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 390 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 391 | * @param pAddress: Pointer to read start address |
sahilmgandhi | 18:6a4db94011d3 | 392 | * @param pDstBuffer: Pointer to destination buffer |
sahilmgandhi | 18:6a4db94011d3 | 393 | * @param BufferSize: Size of the buffer to read from memory |
sahilmgandhi | 18:6a4db94011d3 | 394 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 395 | */ |
sahilmgandhi | 18:6a4db94011d3 | 396 | HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 397 | { |
sahilmgandhi | 18:6a4db94011d3 | 398 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 399 | |
sahilmgandhi | 18:6a4db94011d3 | 400 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 401 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 402 | |
sahilmgandhi | 18:6a4db94011d3 | 403 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 404 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 405 | { |
sahilmgandhi | 18:6a4db94011d3 | 406 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 407 | } |
sahilmgandhi | 18:6a4db94011d3 | 408 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
sahilmgandhi | 18:6a4db94011d3 | 409 | { |
sahilmgandhi | 18:6a4db94011d3 | 410 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 411 | } |
sahilmgandhi | 18:6a4db94011d3 | 412 | |
sahilmgandhi | 18:6a4db94011d3 | 413 | /* Read data from source */ |
sahilmgandhi | 18:6a4db94011d3 | 414 | for(; BufferSize != 0U; BufferSize--) |
sahilmgandhi | 18:6a4db94011d3 | 415 | { |
sahilmgandhi | 18:6a4db94011d3 | 416 | *pDstBuffer = *(__IO uint16_t *)pSdramAddress; |
sahilmgandhi | 18:6a4db94011d3 | 417 | pDstBuffer++; |
sahilmgandhi | 18:6a4db94011d3 | 418 | pSdramAddress++; |
sahilmgandhi | 18:6a4db94011d3 | 419 | } |
sahilmgandhi | 18:6a4db94011d3 | 420 | |
sahilmgandhi | 18:6a4db94011d3 | 421 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 422 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 423 | |
sahilmgandhi | 18:6a4db94011d3 | 424 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 425 | } |
sahilmgandhi | 18:6a4db94011d3 | 426 | |
sahilmgandhi | 18:6a4db94011d3 | 427 | /** |
sahilmgandhi | 18:6a4db94011d3 | 428 | * @brief Writes 16-bit data buffer to SDRAM memory. |
sahilmgandhi | 18:6a4db94011d3 | 429 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 430 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 431 | * @param pAddress: Pointer to write start address |
sahilmgandhi | 18:6a4db94011d3 | 432 | * @param pSrcBuffer: Pointer to source buffer to write |
sahilmgandhi | 18:6a4db94011d3 | 433 | * @param BufferSize: Size of the buffer to write to memory |
sahilmgandhi | 18:6a4db94011d3 | 434 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 435 | */ |
sahilmgandhi | 18:6a4db94011d3 | 436 | HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 437 | { |
sahilmgandhi | 18:6a4db94011d3 | 438 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 439 | uint32_t tmp = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 440 | |
sahilmgandhi | 18:6a4db94011d3 | 441 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 442 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 443 | |
sahilmgandhi | 18:6a4db94011d3 | 444 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 445 | tmp = hsdram->State; |
sahilmgandhi | 18:6a4db94011d3 | 446 | |
sahilmgandhi | 18:6a4db94011d3 | 447 | if(tmp == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 448 | { |
sahilmgandhi | 18:6a4db94011d3 | 449 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 450 | } |
sahilmgandhi | 18:6a4db94011d3 | 451 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
sahilmgandhi | 18:6a4db94011d3 | 452 | { |
sahilmgandhi | 18:6a4db94011d3 | 453 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 454 | } |
sahilmgandhi | 18:6a4db94011d3 | 455 | |
sahilmgandhi | 18:6a4db94011d3 | 456 | /* Write data to memory */ |
sahilmgandhi | 18:6a4db94011d3 | 457 | for(; BufferSize != 0U; BufferSize--) |
sahilmgandhi | 18:6a4db94011d3 | 458 | { |
sahilmgandhi | 18:6a4db94011d3 | 459 | *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; |
sahilmgandhi | 18:6a4db94011d3 | 460 | pSrcBuffer++; |
sahilmgandhi | 18:6a4db94011d3 | 461 | pSdramAddress++; |
sahilmgandhi | 18:6a4db94011d3 | 462 | } |
sahilmgandhi | 18:6a4db94011d3 | 463 | |
sahilmgandhi | 18:6a4db94011d3 | 464 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 465 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 466 | |
sahilmgandhi | 18:6a4db94011d3 | 467 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 468 | } |
sahilmgandhi | 18:6a4db94011d3 | 469 | |
sahilmgandhi | 18:6a4db94011d3 | 470 | /** |
sahilmgandhi | 18:6a4db94011d3 | 471 | * @brief Reads 32-bit data buffer from the SDRAM memory. |
sahilmgandhi | 18:6a4db94011d3 | 472 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 473 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 474 | * @param pAddress: Pointer to read start address |
sahilmgandhi | 18:6a4db94011d3 | 475 | * @param pDstBuffer: Pointer to destination buffer |
sahilmgandhi | 18:6a4db94011d3 | 476 | * @param BufferSize: Size of the buffer to read from memory |
sahilmgandhi | 18:6a4db94011d3 | 477 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 478 | */ |
sahilmgandhi | 18:6a4db94011d3 | 479 | HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 480 | { |
sahilmgandhi | 18:6a4db94011d3 | 481 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 482 | |
sahilmgandhi | 18:6a4db94011d3 | 483 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 484 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 485 | |
sahilmgandhi | 18:6a4db94011d3 | 486 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 487 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 488 | { |
sahilmgandhi | 18:6a4db94011d3 | 489 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 490 | } |
sahilmgandhi | 18:6a4db94011d3 | 491 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
sahilmgandhi | 18:6a4db94011d3 | 492 | { |
sahilmgandhi | 18:6a4db94011d3 | 493 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 494 | } |
sahilmgandhi | 18:6a4db94011d3 | 495 | |
sahilmgandhi | 18:6a4db94011d3 | 496 | /* Read data from source */ |
sahilmgandhi | 18:6a4db94011d3 | 497 | for(; BufferSize != 0U; BufferSize--) |
sahilmgandhi | 18:6a4db94011d3 | 498 | { |
sahilmgandhi | 18:6a4db94011d3 | 499 | *pDstBuffer = *(__IO uint32_t *)pSdramAddress; |
sahilmgandhi | 18:6a4db94011d3 | 500 | pDstBuffer++; |
sahilmgandhi | 18:6a4db94011d3 | 501 | pSdramAddress++; |
sahilmgandhi | 18:6a4db94011d3 | 502 | } |
sahilmgandhi | 18:6a4db94011d3 | 503 | |
sahilmgandhi | 18:6a4db94011d3 | 504 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 505 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 506 | |
sahilmgandhi | 18:6a4db94011d3 | 507 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 508 | } |
sahilmgandhi | 18:6a4db94011d3 | 509 | |
sahilmgandhi | 18:6a4db94011d3 | 510 | /** |
sahilmgandhi | 18:6a4db94011d3 | 511 | * @brief Writes 32-bit data buffer to SDRAM memory. |
sahilmgandhi | 18:6a4db94011d3 | 512 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 513 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 514 | * @param pAddress: Pointer to write start address |
sahilmgandhi | 18:6a4db94011d3 | 515 | * @param pSrcBuffer: Pointer to source buffer to write |
sahilmgandhi | 18:6a4db94011d3 | 516 | * @param BufferSize: Size of the buffer to write to memory |
sahilmgandhi | 18:6a4db94011d3 | 517 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 518 | */ |
sahilmgandhi | 18:6a4db94011d3 | 519 | HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 520 | { |
sahilmgandhi | 18:6a4db94011d3 | 521 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 522 | uint32_t tmp = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 523 | |
sahilmgandhi | 18:6a4db94011d3 | 524 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 525 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 526 | |
sahilmgandhi | 18:6a4db94011d3 | 527 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | tmp = hsdram->State; |
sahilmgandhi | 18:6a4db94011d3 | 529 | |
sahilmgandhi | 18:6a4db94011d3 | 530 | if(tmp == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 531 | { |
sahilmgandhi | 18:6a4db94011d3 | 532 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 533 | } |
sahilmgandhi | 18:6a4db94011d3 | 534 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
sahilmgandhi | 18:6a4db94011d3 | 535 | { |
sahilmgandhi | 18:6a4db94011d3 | 536 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 537 | } |
sahilmgandhi | 18:6a4db94011d3 | 538 | |
sahilmgandhi | 18:6a4db94011d3 | 539 | /* Write data to memory */ |
sahilmgandhi | 18:6a4db94011d3 | 540 | for(; BufferSize != 0U; BufferSize--) |
sahilmgandhi | 18:6a4db94011d3 | 541 | { |
sahilmgandhi | 18:6a4db94011d3 | 542 | *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; |
sahilmgandhi | 18:6a4db94011d3 | 543 | pSrcBuffer++; |
sahilmgandhi | 18:6a4db94011d3 | 544 | pSdramAddress++; |
sahilmgandhi | 18:6a4db94011d3 | 545 | } |
sahilmgandhi | 18:6a4db94011d3 | 546 | |
sahilmgandhi | 18:6a4db94011d3 | 547 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 548 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 549 | |
sahilmgandhi | 18:6a4db94011d3 | 550 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 551 | } |
sahilmgandhi | 18:6a4db94011d3 | 552 | |
sahilmgandhi | 18:6a4db94011d3 | 553 | /** |
sahilmgandhi | 18:6a4db94011d3 | 554 | * @brief Reads a Words data from the SDRAM memory using DMA transfer. |
sahilmgandhi | 18:6a4db94011d3 | 555 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 556 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 557 | * @param pAddress: Pointer to read start address |
sahilmgandhi | 18:6a4db94011d3 | 558 | * @param pDstBuffer: Pointer to destination buffer |
sahilmgandhi | 18:6a4db94011d3 | 559 | * @param BufferSize: Size of the buffer to read from memory |
sahilmgandhi | 18:6a4db94011d3 | 560 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 561 | */ |
sahilmgandhi | 18:6a4db94011d3 | 562 | HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 563 | { |
sahilmgandhi | 18:6a4db94011d3 | 564 | uint32_t tmp = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 565 | |
sahilmgandhi | 18:6a4db94011d3 | 566 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 567 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 568 | |
sahilmgandhi | 18:6a4db94011d3 | 569 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 570 | tmp = hsdram->State; |
sahilmgandhi | 18:6a4db94011d3 | 571 | |
sahilmgandhi | 18:6a4db94011d3 | 572 | if(tmp == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 573 | { |
sahilmgandhi | 18:6a4db94011d3 | 574 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 575 | } |
sahilmgandhi | 18:6a4db94011d3 | 576 | else if(tmp == HAL_SDRAM_STATE_PRECHARGED) |
sahilmgandhi | 18:6a4db94011d3 | 577 | { |
sahilmgandhi | 18:6a4db94011d3 | 578 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 579 | } |
sahilmgandhi | 18:6a4db94011d3 | 580 | |
sahilmgandhi | 18:6a4db94011d3 | 581 | /* Configure DMA user callbacks */ |
sahilmgandhi | 18:6a4db94011d3 | 582 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
sahilmgandhi | 18:6a4db94011d3 | 583 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
sahilmgandhi | 18:6a4db94011d3 | 584 | |
sahilmgandhi | 18:6a4db94011d3 | 585 | /* Enable the DMA Stream */ |
sahilmgandhi | 18:6a4db94011d3 | 586 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); |
sahilmgandhi | 18:6a4db94011d3 | 587 | |
sahilmgandhi | 18:6a4db94011d3 | 588 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 589 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 590 | |
sahilmgandhi | 18:6a4db94011d3 | 591 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 592 | } |
sahilmgandhi | 18:6a4db94011d3 | 593 | |
sahilmgandhi | 18:6a4db94011d3 | 594 | /** |
sahilmgandhi | 18:6a4db94011d3 | 595 | * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. |
sahilmgandhi | 18:6a4db94011d3 | 596 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 597 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 598 | * @param pAddress: Pointer to write start address |
sahilmgandhi | 18:6a4db94011d3 | 599 | * @param pSrcBuffer: Pointer to source buffer to write |
sahilmgandhi | 18:6a4db94011d3 | 600 | * @param BufferSize: Size of the buffer to write to memory |
sahilmgandhi | 18:6a4db94011d3 | 601 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 602 | */ |
sahilmgandhi | 18:6a4db94011d3 | 603 | HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 604 | { |
sahilmgandhi | 18:6a4db94011d3 | 605 | uint32_t tmp = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 606 | |
sahilmgandhi | 18:6a4db94011d3 | 607 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 608 | __HAL_LOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 609 | |
sahilmgandhi | 18:6a4db94011d3 | 610 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 611 | tmp = hsdram->State; |
sahilmgandhi | 18:6a4db94011d3 | 612 | |
sahilmgandhi | 18:6a4db94011d3 | 613 | if(tmp == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 614 | { |
sahilmgandhi | 18:6a4db94011d3 | 615 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 616 | } |
sahilmgandhi | 18:6a4db94011d3 | 617 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
sahilmgandhi | 18:6a4db94011d3 | 618 | { |
sahilmgandhi | 18:6a4db94011d3 | 619 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 620 | } |
sahilmgandhi | 18:6a4db94011d3 | 621 | |
sahilmgandhi | 18:6a4db94011d3 | 622 | /* Configure DMA user callbacks */ |
sahilmgandhi | 18:6a4db94011d3 | 623 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
sahilmgandhi | 18:6a4db94011d3 | 624 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
sahilmgandhi | 18:6a4db94011d3 | 625 | |
sahilmgandhi | 18:6a4db94011d3 | 626 | /* Enable the DMA Stream */ |
sahilmgandhi | 18:6a4db94011d3 | 627 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); |
sahilmgandhi | 18:6a4db94011d3 | 628 | |
sahilmgandhi | 18:6a4db94011d3 | 629 | /* Process Unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 630 | __HAL_UNLOCK(hsdram); |
sahilmgandhi | 18:6a4db94011d3 | 631 | |
sahilmgandhi | 18:6a4db94011d3 | 632 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 633 | } |
sahilmgandhi | 18:6a4db94011d3 | 634 | /** |
sahilmgandhi | 18:6a4db94011d3 | 635 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 636 | */ |
sahilmgandhi | 18:6a4db94011d3 | 637 | |
sahilmgandhi | 18:6a4db94011d3 | 638 | /** @defgroup SDRAM_Exported_Functions_Group3 Control functions |
sahilmgandhi | 18:6a4db94011d3 | 639 | * @brief management functions |
sahilmgandhi | 18:6a4db94011d3 | 640 | * |
sahilmgandhi | 18:6a4db94011d3 | 641 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 642 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 643 | ##### SDRAM Control functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 644 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 645 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 646 | This subsection provides a set of functions allowing to control dynamically |
sahilmgandhi | 18:6a4db94011d3 | 647 | the SDRAM interface. |
sahilmgandhi | 18:6a4db94011d3 | 648 | |
sahilmgandhi | 18:6a4db94011d3 | 649 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 650 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 651 | */ |
sahilmgandhi | 18:6a4db94011d3 | 652 | |
sahilmgandhi | 18:6a4db94011d3 | 653 | /** |
sahilmgandhi | 18:6a4db94011d3 | 654 | * @brief Enables dynamically SDRAM write protection. |
sahilmgandhi | 18:6a4db94011d3 | 655 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 656 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 657 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 658 | */ |
sahilmgandhi | 18:6a4db94011d3 | 659 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 660 | { |
sahilmgandhi | 18:6a4db94011d3 | 661 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 662 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 663 | { |
sahilmgandhi | 18:6a4db94011d3 | 664 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 665 | } |
sahilmgandhi | 18:6a4db94011d3 | 666 | |
sahilmgandhi | 18:6a4db94011d3 | 667 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 668 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 669 | |
sahilmgandhi | 18:6a4db94011d3 | 670 | /* Enable write protection */ |
sahilmgandhi | 18:6a4db94011d3 | 671 | FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); |
sahilmgandhi | 18:6a4db94011d3 | 672 | |
sahilmgandhi | 18:6a4db94011d3 | 673 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 674 | hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; |
sahilmgandhi | 18:6a4db94011d3 | 675 | |
sahilmgandhi | 18:6a4db94011d3 | 676 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 677 | } |
sahilmgandhi | 18:6a4db94011d3 | 678 | |
sahilmgandhi | 18:6a4db94011d3 | 679 | /** |
sahilmgandhi | 18:6a4db94011d3 | 680 | * @brief Disables dynamically SDRAM write protection. |
sahilmgandhi | 18:6a4db94011d3 | 681 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 682 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 683 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 684 | */ |
sahilmgandhi | 18:6a4db94011d3 | 685 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 686 | { |
sahilmgandhi | 18:6a4db94011d3 | 687 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 688 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 689 | { |
sahilmgandhi | 18:6a4db94011d3 | 690 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 691 | } |
sahilmgandhi | 18:6a4db94011d3 | 692 | |
sahilmgandhi | 18:6a4db94011d3 | 693 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 694 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 695 | |
sahilmgandhi | 18:6a4db94011d3 | 696 | /* Disable write protection */ |
sahilmgandhi | 18:6a4db94011d3 | 697 | FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); |
sahilmgandhi | 18:6a4db94011d3 | 698 | |
sahilmgandhi | 18:6a4db94011d3 | 699 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 700 | hsdram->State = HAL_SDRAM_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 701 | |
sahilmgandhi | 18:6a4db94011d3 | 702 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 703 | } |
sahilmgandhi | 18:6a4db94011d3 | 704 | |
sahilmgandhi | 18:6a4db94011d3 | 705 | /** |
sahilmgandhi | 18:6a4db94011d3 | 706 | * @brief Sends Command to the SDRAM bank. |
sahilmgandhi | 18:6a4db94011d3 | 707 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 708 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 709 | * @param Command: SDRAM command structure |
sahilmgandhi | 18:6a4db94011d3 | 710 | * @param Timeout: Timeout duration |
sahilmgandhi | 18:6a4db94011d3 | 711 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 712 | */ |
sahilmgandhi | 18:6a4db94011d3 | 713 | HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
sahilmgandhi | 18:6a4db94011d3 | 714 | { |
sahilmgandhi | 18:6a4db94011d3 | 715 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 716 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 717 | { |
sahilmgandhi | 18:6a4db94011d3 | 718 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 719 | } |
sahilmgandhi | 18:6a4db94011d3 | 720 | |
sahilmgandhi | 18:6a4db94011d3 | 721 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 722 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 723 | |
sahilmgandhi | 18:6a4db94011d3 | 724 | /* Send SDRAM command */ |
sahilmgandhi | 18:6a4db94011d3 | 725 | FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); |
sahilmgandhi | 18:6a4db94011d3 | 726 | |
sahilmgandhi | 18:6a4db94011d3 | 727 | /* Update the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 728 | if(Command->CommandMode == FMC_SDRAM_CMD_PALL) |
sahilmgandhi | 18:6a4db94011d3 | 729 | { |
sahilmgandhi | 18:6a4db94011d3 | 730 | hsdram->State = HAL_SDRAM_STATE_PRECHARGED; |
sahilmgandhi | 18:6a4db94011d3 | 731 | } |
sahilmgandhi | 18:6a4db94011d3 | 732 | else |
sahilmgandhi | 18:6a4db94011d3 | 733 | { |
sahilmgandhi | 18:6a4db94011d3 | 734 | hsdram->State = HAL_SDRAM_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 735 | } |
sahilmgandhi | 18:6a4db94011d3 | 736 | |
sahilmgandhi | 18:6a4db94011d3 | 737 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 738 | } |
sahilmgandhi | 18:6a4db94011d3 | 739 | |
sahilmgandhi | 18:6a4db94011d3 | 740 | /** |
sahilmgandhi | 18:6a4db94011d3 | 741 | * @brief Programs the SDRAM Memory Refresh rate. |
sahilmgandhi | 18:6a4db94011d3 | 742 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 743 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 744 | * @param RefreshRate: The SDRAM refresh rate value |
sahilmgandhi | 18:6a4db94011d3 | 745 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 746 | */ |
sahilmgandhi | 18:6a4db94011d3 | 747 | HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) |
sahilmgandhi | 18:6a4db94011d3 | 748 | { |
sahilmgandhi | 18:6a4db94011d3 | 749 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 750 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 751 | { |
sahilmgandhi | 18:6a4db94011d3 | 752 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 753 | } |
sahilmgandhi | 18:6a4db94011d3 | 754 | |
sahilmgandhi | 18:6a4db94011d3 | 755 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 756 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 757 | |
sahilmgandhi | 18:6a4db94011d3 | 758 | /* Program the refresh rate */ |
sahilmgandhi | 18:6a4db94011d3 | 759 | FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); |
sahilmgandhi | 18:6a4db94011d3 | 760 | |
sahilmgandhi | 18:6a4db94011d3 | 761 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 762 | hsdram->State = HAL_SDRAM_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 763 | |
sahilmgandhi | 18:6a4db94011d3 | 764 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 765 | } |
sahilmgandhi | 18:6a4db94011d3 | 766 | |
sahilmgandhi | 18:6a4db94011d3 | 767 | /** |
sahilmgandhi | 18:6a4db94011d3 | 768 | * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. |
sahilmgandhi | 18:6a4db94011d3 | 769 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 770 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 771 | * @param AutoRefreshNumber: The SDRAM auto Refresh number |
sahilmgandhi | 18:6a4db94011d3 | 772 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 773 | */ |
sahilmgandhi | 18:6a4db94011d3 | 774 | HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) |
sahilmgandhi | 18:6a4db94011d3 | 775 | { |
sahilmgandhi | 18:6a4db94011d3 | 776 | /* Check the SDRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 777 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 778 | { |
sahilmgandhi | 18:6a4db94011d3 | 779 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 780 | } |
sahilmgandhi | 18:6a4db94011d3 | 781 | |
sahilmgandhi | 18:6a4db94011d3 | 782 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 783 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 784 | |
sahilmgandhi | 18:6a4db94011d3 | 785 | /* Set the Auto-Refresh number */ |
sahilmgandhi | 18:6a4db94011d3 | 786 | FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); |
sahilmgandhi | 18:6a4db94011d3 | 787 | |
sahilmgandhi | 18:6a4db94011d3 | 788 | /* Update the SDRAM state */ |
sahilmgandhi | 18:6a4db94011d3 | 789 | hsdram->State = HAL_SDRAM_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 790 | |
sahilmgandhi | 18:6a4db94011d3 | 791 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 792 | } |
sahilmgandhi | 18:6a4db94011d3 | 793 | |
sahilmgandhi | 18:6a4db94011d3 | 794 | /** |
sahilmgandhi | 18:6a4db94011d3 | 795 | * @brief Returns the SDRAM memory current mode. |
sahilmgandhi | 18:6a4db94011d3 | 796 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 797 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 798 | * @retval The SDRAM memory mode. |
sahilmgandhi | 18:6a4db94011d3 | 799 | */ |
sahilmgandhi | 18:6a4db94011d3 | 800 | uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 801 | { |
sahilmgandhi | 18:6a4db94011d3 | 802 | /* Return the SDRAM memory current mode */ |
sahilmgandhi | 18:6a4db94011d3 | 803 | return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); |
sahilmgandhi | 18:6a4db94011d3 | 804 | } |
sahilmgandhi | 18:6a4db94011d3 | 805 | |
sahilmgandhi | 18:6a4db94011d3 | 806 | /** |
sahilmgandhi | 18:6a4db94011d3 | 807 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 808 | */ |
sahilmgandhi | 18:6a4db94011d3 | 809 | |
sahilmgandhi | 18:6a4db94011d3 | 810 | /** @defgroup SDRAM_Exported_Functions_Group4 State functions |
sahilmgandhi | 18:6a4db94011d3 | 811 | * @brief Peripheral State functions |
sahilmgandhi | 18:6a4db94011d3 | 812 | * |
sahilmgandhi | 18:6a4db94011d3 | 813 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 814 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 815 | ##### SDRAM State functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 816 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 817 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 818 | This subsection permits to get in run-time the status of the SDRAM controller |
sahilmgandhi | 18:6a4db94011d3 | 819 | and the data flow. |
sahilmgandhi | 18:6a4db94011d3 | 820 | |
sahilmgandhi | 18:6a4db94011d3 | 821 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 822 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 823 | */ |
sahilmgandhi | 18:6a4db94011d3 | 824 | |
sahilmgandhi | 18:6a4db94011d3 | 825 | /** |
sahilmgandhi | 18:6a4db94011d3 | 826 | * @brief Returns the SDRAM state. |
sahilmgandhi | 18:6a4db94011d3 | 827 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 828 | * the configuration information for SDRAM module. |
sahilmgandhi | 18:6a4db94011d3 | 829 | * @retval HAL state |
sahilmgandhi | 18:6a4db94011d3 | 830 | */ |
sahilmgandhi | 18:6a4db94011d3 | 831 | HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) |
sahilmgandhi | 18:6a4db94011d3 | 832 | { |
sahilmgandhi | 18:6a4db94011d3 | 833 | return hsdram->State; |
sahilmgandhi | 18:6a4db94011d3 | 834 | } |
sahilmgandhi | 18:6a4db94011d3 | 835 | |
sahilmgandhi | 18:6a4db94011d3 | 836 | /** |
sahilmgandhi | 18:6a4db94011d3 | 837 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 838 | */ |
sahilmgandhi | 18:6a4db94011d3 | 839 | |
sahilmgandhi | 18:6a4db94011d3 | 840 | /** |
sahilmgandhi | 18:6a4db94011d3 | 841 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 842 | */ |
sahilmgandhi | 18:6a4db94011d3 | 843 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
sahilmgandhi | 18:6a4db94011d3 | 844 | #endif /* HAL_SDRAM_MODULE_ENABLED */ |
sahilmgandhi | 18:6a4db94011d3 | 845 | /** |
sahilmgandhi | 18:6a4db94011d3 | 846 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 847 | */ |
sahilmgandhi | 18:6a4db94011d3 | 848 | |
sahilmgandhi | 18:6a4db94011d3 | 849 | /** |
sahilmgandhi | 18:6a4db94011d3 | 850 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 851 | */ |
sahilmgandhi | 18:6a4db94011d3 | 852 | |
sahilmgandhi | 18:6a4db94011d3 | 853 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |