Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file startup_stm32f439xx.s
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.3.0
sahilmgandhi 18:6a4db94011d3 6 * @date 02-March-2015
sahilmgandhi 18:6a4db94011d3 7 * @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain.
sahilmgandhi 18:6a4db94011d3 8 * This module performs:
sahilmgandhi 18:6a4db94011d3 9 * - Set the initial SP
sahilmgandhi 18:6a4db94011d3 10 * - Set the initial PC == Reset_Handler,
sahilmgandhi 18:6a4db94011d3 11 * - Set the vector table entries with the exceptions ISR address
sahilmgandhi 18:6a4db94011d3 12 * - Branches to main in the C library (which eventually
sahilmgandhi 18:6a4db94011d3 13 * calls main()).
sahilmgandhi 18:6a4db94011d3 14 * After Reset the Cortex-M4 processor is in Thread mode,
sahilmgandhi 18:6a4db94011d3 15 * priority is Privileged, and the Stack is set to Main.
sahilmgandhi 18:6a4db94011d3 16 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 17 * @attention
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 22 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 23 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 26 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 27 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 29 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 30 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 44 */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 .syntax unified
sahilmgandhi 18:6a4db94011d3 47 .cpu cortex-m4
sahilmgandhi 18:6a4db94011d3 48 .fpu softvfp
sahilmgandhi 18:6a4db94011d3 49 .thumb
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 .global g_pfnVectors
sahilmgandhi 18:6a4db94011d3 52 .global Default_Handler
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /* start address for the initialization values of the .data section.
sahilmgandhi 18:6a4db94011d3 55 defined in linker script */
sahilmgandhi 18:6a4db94011d3 56 .word _sidata
sahilmgandhi 18:6a4db94011d3 57 /* start address for the .data section. defined in linker script */
sahilmgandhi 18:6a4db94011d3 58 .word _sdata
sahilmgandhi 18:6a4db94011d3 59 /* end address for the .data section. defined in linker script */
sahilmgandhi 18:6a4db94011d3 60 .word _edata
sahilmgandhi 18:6a4db94011d3 61 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /**
sahilmgandhi 18:6a4db94011d3 64 * @brief This is the code that gets called when the processor first
sahilmgandhi 18:6a4db94011d3 65 * starts execution following a reset event. Only the absolutely
sahilmgandhi 18:6a4db94011d3 66 * necessary set is performed, after which the application
sahilmgandhi 18:6a4db94011d3 67 * supplied main() routine is called.
sahilmgandhi 18:6a4db94011d3 68 * @param None
sahilmgandhi 18:6a4db94011d3 69 * @retval : None
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 .section .text.Reset_Handler
sahilmgandhi 18:6a4db94011d3 73 .weak Reset_Handler
sahilmgandhi 18:6a4db94011d3 74 .type Reset_Handler, %function
sahilmgandhi 18:6a4db94011d3 75 Reset_Handler:
sahilmgandhi 18:6a4db94011d3 76 ldr sp, =_estack /* set stack pointer */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /* Copy the data segment initializers from flash to SRAM */
sahilmgandhi 18:6a4db94011d3 79 movs r1, #0
sahilmgandhi 18:6a4db94011d3 80 b LoopCopyDataInit
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 CopyDataInit:
sahilmgandhi 18:6a4db94011d3 83 ldr r3, =_sidata
sahilmgandhi 18:6a4db94011d3 84 ldr r3, [r3, r1]
sahilmgandhi 18:6a4db94011d3 85 str r3, [r0, r1]
sahilmgandhi 18:6a4db94011d3 86 adds r1, r1, #4
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 LoopCopyDataInit:
sahilmgandhi 18:6a4db94011d3 89 ldr r0, =_sdata
sahilmgandhi 18:6a4db94011d3 90 ldr r3, =_edata
sahilmgandhi 18:6a4db94011d3 91 adds r2, r0, r1
sahilmgandhi 18:6a4db94011d3 92 cmp r2, r3
sahilmgandhi 18:6a4db94011d3 93 bcc CopyDataInit
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /* Call the clock system intitialization function.*/
sahilmgandhi 18:6a4db94011d3 96 bl SystemInit
sahilmgandhi 18:6a4db94011d3 97 /* Call static constructors */
sahilmgandhi 18:6a4db94011d3 98 //bl __libc_init_array
sahilmgandhi 18:6a4db94011d3 99 /* Call the application's entry point.*/
sahilmgandhi 18:6a4db94011d3 100 //bl main
sahilmgandhi 18:6a4db94011d3 101 // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
sahilmgandhi 18:6a4db94011d3 102 // and when existing hardware_init_hook() and software_init_hook() before
sahilmgandhi 18:6a4db94011d3 103 // starting main(). software_init_hook() is available and has to be called due
sahilmgandhi 18:6a4db94011d3 104 // to initializsation when using rtos.
sahilmgandhi 18:6a4db94011d3 105 bl _start
sahilmgandhi 18:6a4db94011d3 106 bx lr
sahilmgandhi 18:6a4db94011d3 107 .size Reset_Handler, .-Reset_Handler
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /**
sahilmgandhi 18:6a4db94011d3 110 * @brief This is the code that gets called when the processor receives an
sahilmgandhi 18:6a4db94011d3 111 * unexpected interrupt. This simply enters an infinite loop, preserving
sahilmgandhi 18:6a4db94011d3 112 * the system state for examination by a debugger.
sahilmgandhi 18:6a4db94011d3 113 * @param None
sahilmgandhi 18:6a4db94011d3 114 * @retval None
sahilmgandhi 18:6a4db94011d3 115 */
sahilmgandhi 18:6a4db94011d3 116 .section .text.Default_Handler,"ax",%progbits
sahilmgandhi 18:6a4db94011d3 117 Default_Handler:
sahilmgandhi 18:6a4db94011d3 118 Infinite_Loop:
sahilmgandhi 18:6a4db94011d3 119 b Infinite_Loop
sahilmgandhi 18:6a4db94011d3 120 .size Default_Handler, .-Default_Handler
sahilmgandhi 18:6a4db94011d3 121 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 122 *
sahilmgandhi 18:6a4db94011d3 123 * The minimal vector table for a Cortex M3. Note that the proper constructs
sahilmgandhi 18:6a4db94011d3 124 * must be placed on this to ensure that it ends up at physical address
sahilmgandhi 18:6a4db94011d3 125 * 0x0000.0000.
sahilmgandhi 18:6a4db94011d3 126 *
sahilmgandhi 18:6a4db94011d3 127 *******************************************************************************/
sahilmgandhi 18:6a4db94011d3 128 .section .isr_vector,"a",%progbits
sahilmgandhi 18:6a4db94011d3 129 .type g_pfnVectors, %object
sahilmgandhi 18:6a4db94011d3 130 .size g_pfnVectors, .-g_pfnVectors
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 g_pfnVectors:
sahilmgandhi 18:6a4db94011d3 133 .word _estack
sahilmgandhi 18:6a4db94011d3 134 .word Reset_Handler
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 .word NMI_Handler
sahilmgandhi 18:6a4db94011d3 137 .word HardFault_Handler
sahilmgandhi 18:6a4db94011d3 138 .word MemManage_Handler
sahilmgandhi 18:6a4db94011d3 139 .word BusFault_Handler
sahilmgandhi 18:6a4db94011d3 140 .word UsageFault_Handler
sahilmgandhi 18:6a4db94011d3 141 .word 0
sahilmgandhi 18:6a4db94011d3 142 .word 0
sahilmgandhi 18:6a4db94011d3 143 .word 0
sahilmgandhi 18:6a4db94011d3 144 .word 0
sahilmgandhi 18:6a4db94011d3 145 .word SVC_Handler
sahilmgandhi 18:6a4db94011d3 146 .word DebugMon_Handler
sahilmgandhi 18:6a4db94011d3 147 .word 0
sahilmgandhi 18:6a4db94011d3 148 .word PendSV_Handler
sahilmgandhi 18:6a4db94011d3 149 .word SysTick_Handler
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* External Interrupts */
sahilmgandhi 18:6a4db94011d3 152 .word WWDG_IRQHandler /* Window WatchDog */
sahilmgandhi 18:6a4db94011d3 153 .word PVD_IRQHandler /* PVD through EXTI Line detection */
sahilmgandhi 18:6a4db94011d3 154 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
sahilmgandhi 18:6a4db94011d3 155 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
sahilmgandhi 18:6a4db94011d3 156 .word FLASH_IRQHandler /* FLASH */
sahilmgandhi 18:6a4db94011d3 157 .word RCC_IRQHandler /* RCC */
sahilmgandhi 18:6a4db94011d3 158 .word EXTI0_IRQHandler /* EXTI Line0 */
sahilmgandhi 18:6a4db94011d3 159 .word EXTI1_IRQHandler /* EXTI Line1 */
sahilmgandhi 18:6a4db94011d3 160 .word EXTI2_IRQHandler /* EXTI Line2 */
sahilmgandhi 18:6a4db94011d3 161 .word EXTI3_IRQHandler /* EXTI Line3 */
sahilmgandhi 18:6a4db94011d3 162 .word EXTI4_IRQHandler /* EXTI Line4 */
sahilmgandhi 18:6a4db94011d3 163 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
sahilmgandhi 18:6a4db94011d3 164 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
sahilmgandhi 18:6a4db94011d3 165 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
sahilmgandhi 18:6a4db94011d3 166 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
sahilmgandhi 18:6a4db94011d3 167 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
sahilmgandhi 18:6a4db94011d3 168 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
sahilmgandhi 18:6a4db94011d3 169 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
sahilmgandhi 18:6a4db94011d3 170 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
sahilmgandhi 18:6a4db94011d3 171 .word CAN1_TX_IRQHandler /* CAN1 TX */
sahilmgandhi 18:6a4db94011d3 172 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
sahilmgandhi 18:6a4db94011d3 173 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
sahilmgandhi 18:6a4db94011d3 174 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
sahilmgandhi 18:6a4db94011d3 175 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
sahilmgandhi 18:6a4db94011d3 176 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
sahilmgandhi 18:6a4db94011d3 177 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
sahilmgandhi 18:6a4db94011d3 178 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
sahilmgandhi 18:6a4db94011d3 179 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
sahilmgandhi 18:6a4db94011d3 180 .word TIM2_IRQHandler /* TIM2 */
sahilmgandhi 18:6a4db94011d3 181 .word TIM3_IRQHandler /* TIM3 */
sahilmgandhi 18:6a4db94011d3 182 .word TIM4_IRQHandler /* TIM4 */
sahilmgandhi 18:6a4db94011d3 183 .word I2C1_EV_IRQHandler /* I2C1 Event */
sahilmgandhi 18:6a4db94011d3 184 .word I2C1_ER_IRQHandler /* I2C1 Error */
sahilmgandhi 18:6a4db94011d3 185 .word I2C2_EV_IRQHandler /* I2C2 Event */
sahilmgandhi 18:6a4db94011d3 186 .word I2C2_ER_IRQHandler /* I2C2 Error */
sahilmgandhi 18:6a4db94011d3 187 .word SPI1_IRQHandler /* SPI1 */
sahilmgandhi 18:6a4db94011d3 188 .word SPI2_IRQHandler /* SPI2 */
sahilmgandhi 18:6a4db94011d3 189 .word USART1_IRQHandler /* USART1 */
sahilmgandhi 18:6a4db94011d3 190 .word USART2_IRQHandler /* USART2 */
sahilmgandhi 18:6a4db94011d3 191 .word USART3_IRQHandler /* USART3 */
sahilmgandhi 18:6a4db94011d3 192 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
sahilmgandhi 18:6a4db94011d3 193 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
sahilmgandhi 18:6a4db94011d3 194 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
sahilmgandhi 18:6a4db94011d3 195 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
sahilmgandhi 18:6a4db94011d3 196 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
sahilmgandhi 18:6a4db94011d3 197 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
sahilmgandhi 18:6a4db94011d3 198 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
sahilmgandhi 18:6a4db94011d3 199 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
sahilmgandhi 18:6a4db94011d3 200 .word FMC_IRQHandler /* FMC */
sahilmgandhi 18:6a4db94011d3 201 .word SDIO_IRQHandler /* SDIO */
sahilmgandhi 18:6a4db94011d3 202 .word TIM5_IRQHandler /* TIM5 */
sahilmgandhi 18:6a4db94011d3 203 .word SPI3_IRQHandler /* SPI3 */
sahilmgandhi 18:6a4db94011d3 204 .word UART4_IRQHandler /* UART4 */
sahilmgandhi 18:6a4db94011d3 205 .word UART5_IRQHandler /* UART5 */
sahilmgandhi 18:6a4db94011d3 206 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
sahilmgandhi 18:6a4db94011d3 207 .word TIM7_IRQHandler /* TIM7 */
sahilmgandhi 18:6a4db94011d3 208 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
sahilmgandhi 18:6a4db94011d3 209 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
sahilmgandhi 18:6a4db94011d3 210 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
sahilmgandhi 18:6a4db94011d3 211 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
sahilmgandhi 18:6a4db94011d3 212 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
sahilmgandhi 18:6a4db94011d3 213 .word ETH_IRQHandler /* Ethernet */
sahilmgandhi 18:6a4db94011d3 214 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
sahilmgandhi 18:6a4db94011d3 215 .word CAN2_TX_IRQHandler /* CAN2 TX */
sahilmgandhi 18:6a4db94011d3 216 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
sahilmgandhi 18:6a4db94011d3 217 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
sahilmgandhi 18:6a4db94011d3 218 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
sahilmgandhi 18:6a4db94011d3 219 .word OTG_FS_IRQHandler /* USB OTG FS */
sahilmgandhi 18:6a4db94011d3 220 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
sahilmgandhi 18:6a4db94011d3 221 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
sahilmgandhi 18:6a4db94011d3 222 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
sahilmgandhi 18:6a4db94011d3 223 .word USART6_IRQHandler /* USART6 */
sahilmgandhi 18:6a4db94011d3 224 .word I2C3_EV_IRQHandler /* I2C3 event */
sahilmgandhi 18:6a4db94011d3 225 .word I2C3_ER_IRQHandler /* I2C3 error */
sahilmgandhi 18:6a4db94011d3 226 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
sahilmgandhi 18:6a4db94011d3 227 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
sahilmgandhi 18:6a4db94011d3 228 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
sahilmgandhi 18:6a4db94011d3 229 .word OTG_HS_IRQHandler /* USB OTG HS */
sahilmgandhi 18:6a4db94011d3 230 .word DCMI_IRQHandler /* DCMI */
sahilmgandhi 18:6a4db94011d3 231 .word CRYP_IRQHandler /* CRYP crypto */
sahilmgandhi 18:6a4db94011d3 232 .word HASH_RNG_IRQHandler /* Hash and Rng */
sahilmgandhi 18:6a4db94011d3 233 .word FPU_IRQHandler /* FPU */
sahilmgandhi 18:6a4db94011d3 234 .word UART7_IRQHandler /* UART7 */
sahilmgandhi 18:6a4db94011d3 235 .word UART8_IRQHandler /* UART8 */
sahilmgandhi 18:6a4db94011d3 236 .word SPI4_IRQHandler /* SPI4 */
sahilmgandhi 18:6a4db94011d3 237 .word SPI5_IRQHandler /* SPI5 */
sahilmgandhi 18:6a4db94011d3 238 .word SPI6_IRQHandler /* SPI6 */
sahilmgandhi 18:6a4db94011d3 239 .word SAI1_IRQHandler /* SAI1 */
sahilmgandhi 18:6a4db94011d3 240 .word LTDC_IRQHandler /* LTDC */
sahilmgandhi 18:6a4db94011d3 241 .word LTDC_ER_IRQHandler /* LTDC error */
sahilmgandhi 18:6a4db94011d3 242 .word DMA2D_IRQHandler /* DMA2D */
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 247 *
sahilmgandhi 18:6a4db94011d3 248 * Provide weak aliases for each Exception handler to the Default_Handler.
sahilmgandhi 18:6a4db94011d3 249 * As they are weak aliases, any function with the same name will override
sahilmgandhi 18:6a4db94011d3 250 * this definition.
sahilmgandhi 18:6a4db94011d3 251 *
sahilmgandhi 18:6a4db94011d3 252 *******************************************************************************/
sahilmgandhi 18:6a4db94011d3 253 .weak NMI_Handler
sahilmgandhi 18:6a4db94011d3 254 .thumb_set NMI_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 .weak HardFault_Handler
sahilmgandhi 18:6a4db94011d3 257 .thumb_set HardFault_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 .weak MemManage_Handler
sahilmgandhi 18:6a4db94011d3 260 .thumb_set MemManage_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 .weak BusFault_Handler
sahilmgandhi 18:6a4db94011d3 263 .thumb_set BusFault_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 .weak UsageFault_Handler
sahilmgandhi 18:6a4db94011d3 266 .thumb_set UsageFault_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 .weak SVC_Handler
sahilmgandhi 18:6a4db94011d3 269 .thumb_set SVC_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 .weak DebugMon_Handler
sahilmgandhi 18:6a4db94011d3 272 .thumb_set DebugMon_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 .weak PendSV_Handler
sahilmgandhi 18:6a4db94011d3 275 .thumb_set PendSV_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 .weak SysTick_Handler
sahilmgandhi 18:6a4db94011d3 278 .thumb_set SysTick_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 .weak WWDG_IRQHandler
sahilmgandhi 18:6a4db94011d3 281 .thumb_set WWDG_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 .weak PVD_IRQHandler
sahilmgandhi 18:6a4db94011d3 284 .thumb_set PVD_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 .weak TAMP_STAMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 287 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 .weak RTC_WKUP_IRQHandler
sahilmgandhi 18:6a4db94011d3 290 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 .weak FLASH_IRQHandler
sahilmgandhi 18:6a4db94011d3 293 .thumb_set FLASH_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 .weak RCC_IRQHandler
sahilmgandhi 18:6a4db94011d3 296 .thumb_set RCC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 .weak EXTI0_IRQHandler
sahilmgandhi 18:6a4db94011d3 299 .thumb_set EXTI0_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 .weak EXTI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 302 .thumb_set EXTI1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 .weak EXTI2_IRQHandler
sahilmgandhi 18:6a4db94011d3 305 .thumb_set EXTI2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 .weak EXTI3_IRQHandler
sahilmgandhi 18:6a4db94011d3 308 .thumb_set EXTI3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 .weak EXTI4_IRQHandler
sahilmgandhi 18:6a4db94011d3 311 .thumb_set EXTI4_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 .weak DMA1_Stream0_IRQHandler
sahilmgandhi 18:6a4db94011d3 314 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 .weak DMA1_Stream1_IRQHandler
sahilmgandhi 18:6a4db94011d3 317 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 .weak DMA1_Stream2_IRQHandler
sahilmgandhi 18:6a4db94011d3 320 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 .weak DMA1_Stream3_IRQHandler
sahilmgandhi 18:6a4db94011d3 323 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 .weak DMA1_Stream4_IRQHandler
sahilmgandhi 18:6a4db94011d3 326 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 .weak DMA1_Stream5_IRQHandler
sahilmgandhi 18:6a4db94011d3 329 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 .weak DMA1_Stream6_IRQHandler
sahilmgandhi 18:6a4db94011d3 332 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 .weak ADC_IRQHandler
sahilmgandhi 18:6a4db94011d3 335 .thumb_set ADC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 .weak CAN1_TX_IRQHandler
sahilmgandhi 18:6a4db94011d3 338 .thumb_set CAN1_TX_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 .weak CAN1_RX0_IRQHandler
sahilmgandhi 18:6a4db94011d3 341 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 .weak CAN1_RX1_IRQHandler
sahilmgandhi 18:6a4db94011d3 344 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 .weak CAN1_SCE_IRQHandler
sahilmgandhi 18:6a4db94011d3 347 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 .weak EXTI9_5_IRQHandler
sahilmgandhi 18:6a4db94011d3 350 .thumb_set EXTI9_5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 .weak TIM1_BRK_TIM9_IRQHandler
sahilmgandhi 18:6a4db94011d3 353 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 .weak TIM1_UP_TIM10_IRQHandler
sahilmgandhi 18:6a4db94011d3 356 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 .weak TIM1_TRG_COM_TIM11_IRQHandler
sahilmgandhi 18:6a4db94011d3 359 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 .weak TIM1_CC_IRQHandler
sahilmgandhi 18:6a4db94011d3 362 .thumb_set TIM1_CC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 .weak TIM2_IRQHandler
sahilmgandhi 18:6a4db94011d3 365 .thumb_set TIM2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 .weak TIM3_IRQHandler
sahilmgandhi 18:6a4db94011d3 368 .thumb_set TIM3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 .weak TIM4_IRQHandler
sahilmgandhi 18:6a4db94011d3 371 .thumb_set TIM4_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 .weak I2C1_EV_IRQHandler
sahilmgandhi 18:6a4db94011d3 374 .thumb_set I2C1_EV_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 .weak I2C1_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 377 .thumb_set I2C1_ER_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 .weak I2C2_EV_IRQHandler
sahilmgandhi 18:6a4db94011d3 380 .thumb_set I2C2_EV_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 .weak I2C2_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 383 .thumb_set I2C2_ER_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 .weak SPI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 386 .thumb_set SPI1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 .weak SPI2_IRQHandler
sahilmgandhi 18:6a4db94011d3 389 .thumb_set SPI2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 .weak USART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 392 .thumb_set USART1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 .weak USART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 395 .thumb_set USART2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 .weak USART3_IRQHandler
sahilmgandhi 18:6a4db94011d3 398 .thumb_set USART3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 .weak EXTI15_10_IRQHandler
sahilmgandhi 18:6a4db94011d3 401 .thumb_set EXTI15_10_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 .weak RTC_Alarm_IRQHandler
sahilmgandhi 18:6a4db94011d3 404 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 .weak OTG_FS_WKUP_IRQHandler
sahilmgandhi 18:6a4db94011d3 407 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 .weak TIM8_BRK_TIM12_IRQHandler
sahilmgandhi 18:6a4db94011d3 410 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 .weak TIM8_UP_TIM13_IRQHandler
sahilmgandhi 18:6a4db94011d3 413 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 .weak TIM8_TRG_COM_TIM14_IRQHandler
sahilmgandhi 18:6a4db94011d3 416 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 .weak TIM8_CC_IRQHandler
sahilmgandhi 18:6a4db94011d3 419 .thumb_set TIM8_CC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 .weak DMA1_Stream7_IRQHandler
sahilmgandhi 18:6a4db94011d3 422 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 .weak FMC_IRQHandler
sahilmgandhi 18:6a4db94011d3 425 .thumb_set FMC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 .weak SDIO_IRQHandler
sahilmgandhi 18:6a4db94011d3 428 .thumb_set SDIO_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 .weak TIM5_IRQHandler
sahilmgandhi 18:6a4db94011d3 431 .thumb_set TIM5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 .weak SPI3_IRQHandler
sahilmgandhi 18:6a4db94011d3 434 .thumb_set SPI3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 .weak UART4_IRQHandler
sahilmgandhi 18:6a4db94011d3 437 .thumb_set UART4_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 .weak UART5_IRQHandler
sahilmgandhi 18:6a4db94011d3 440 .thumb_set UART5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 .weak TIM6_DAC_IRQHandler
sahilmgandhi 18:6a4db94011d3 443 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 .weak TIM7_IRQHandler
sahilmgandhi 18:6a4db94011d3 446 .thumb_set TIM7_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 .weak DMA2_Stream0_IRQHandler
sahilmgandhi 18:6a4db94011d3 449 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 .weak DMA2_Stream1_IRQHandler
sahilmgandhi 18:6a4db94011d3 452 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 .weak DMA2_Stream2_IRQHandler
sahilmgandhi 18:6a4db94011d3 455 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 .weak DMA2_Stream3_IRQHandler
sahilmgandhi 18:6a4db94011d3 458 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 .weak DMA2_Stream4_IRQHandler
sahilmgandhi 18:6a4db94011d3 461 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 .weak ETH_IRQHandler
sahilmgandhi 18:6a4db94011d3 464 .thumb_set ETH_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 .weak ETH_WKUP_IRQHandler
sahilmgandhi 18:6a4db94011d3 467 .thumb_set ETH_WKUP_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 .weak CAN2_TX_IRQHandler
sahilmgandhi 18:6a4db94011d3 470 .thumb_set CAN2_TX_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 .weak CAN2_RX0_IRQHandler
sahilmgandhi 18:6a4db94011d3 473 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 .weak CAN2_RX1_IRQHandler
sahilmgandhi 18:6a4db94011d3 476 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 .weak CAN2_SCE_IRQHandler
sahilmgandhi 18:6a4db94011d3 479 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 .weak OTG_FS_IRQHandler
sahilmgandhi 18:6a4db94011d3 482 .thumb_set OTG_FS_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 .weak DMA2_Stream5_IRQHandler
sahilmgandhi 18:6a4db94011d3 485 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 .weak DMA2_Stream6_IRQHandler
sahilmgandhi 18:6a4db94011d3 488 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 .weak DMA2_Stream7_IRQHandler
sahilmgandhi 18:6a4db94011d3 491 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 .weak USART6_IRQHandler
sahilmgandhi 18:6a4db94011d3 494 .thumb_set USART6_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 .weak I2C3_EV_IRQHandler
sahilmgandhi 18:6a4db94011d3 497 .thumb_set I2C3_EV_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 .weak I2C3_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 500 .thumb_set I2C3_ER_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 .weak OTG_HS_EP1_OUT_IRQHandler
sahilmgandhi 18:6a4db94011d3 503 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 .weak OTG_HS_EP1_IN_IRQHandler
sahilmgandhi 18:6a4db94011d3 506 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 .weak OTG_HS_WKUP_IRQHandler
sahilmgandhi 18:6a4db94011d3 509 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 510
sahilmgandhi 18:6a4db94011d3 511 .weak OTG_HS_IRQHandler
sahilmgandhi 18:6a4db94011d3 512 .thumb_set OTG_HS_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 .weak DCMI_IRQHandler
sahilmgandhi 18:6a4db94011d3 515 .thumb_set DCMI_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 .weak CRYP_IRQHandler
sahilmgandhi 18:6a4db94011d3 518 .thumb_set CRYP_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 .weak HASH_RNG_IRQHandler
sahilmgandhi 18:6a4db94011d3 521 .thumb_set HASH_RNG_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 .weak FPU_IRQHandler
sahilmgandhi 18:6a4db94011d3 524 .thumb_set FPU_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 .weak UART7_IRQHandler
sahilmgandhi 18:6a4db94011d3 527 .thumb_set UART7_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 .weak UART8_IRQHandler
sahilmgandhi 18:6a4db94011d3 530 .thumb_set UART8_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 .weak SPI4_IRQHandler
sahilmgandhi 18:6a4db94011d3 533 .thumb_set SPI4_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 .weak SPI5_IRQHandler
sahilmgandhi 18:6a4db94011d3 536 .thumb_set SPI5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 .weak SPI6_IRQHandler
sahilmgandhi 18:6a4db94011d3 539 .thumb_set SPI6_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 .weak SAI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 542 .thumb_set SAI1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 .weak LTDC_IRQHandler
sahilmgandhi 18:6a4db94011d3 545 .thumb_set LTDC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 .weak LTDC_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 548 .thumb_set LTDC_ER_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 .weak DMA2D_IRQHandler
sahilmgandhi 18:6a4db94011d3 551 .thumb_set DMA2D_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560