MacroRat
Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_stm32f4xx.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 3 | * @file system_stm32f4xx.c |
| sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
| sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V2.5.0 |
| sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 22-April-2016 |
| sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| sahilmgandhi | 18:6a4db94011d3 | 8 | * |
| sahilmgandhi | 18:6a4db94011d3 | 9 | * This file provides two functions and one global variable to be called from |
| sahilmgandhi | 18:6a4db94011d3 | 10 | * user application: |
| sahilmgandhi | 18:6a4db94011d3 | 11 | * - SystemInit(): This function is called at startup just after reset and |
| sahilmgandhi | 18:6a4db94011d3 | 12 | * before branch to main program. This call is made inside |
| sahilmgandhi | 18:6a4db94011d3 | 13 | * the "startup_stm32f4xx.s" file. |
| sahilmgandhi | 18:6a4db94011d3 | 14 | * |
| sahilmgandhi | 18:6a4db94011d3 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| sahilmgandhi | 18:6a4db94011d3 | 16 | * by the user application to setup the SysTick |
| sahilmgandhi | 18:6a4db94011d3 | 17 | * timer or configure other parameters. |
| sahilmgandhi | 18:6a4db94011d3 | 18 | * |
| sahilmgandhi | 18:6a4db94011d3 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| sahilmgandhi | 18:6a4db94011d3 | 20 | * be called whenever the core clock is changed |
| sahilmgandhi | 18:6a4db94011d3 | 21 | * during program execution. |
| sahilmgandhi | 18:6a4db94011d3 | 22 | * |
| sahilmgandhi | 18:6a4db94011d3 | 23 | * This file configures the system clock as follows: |
| sahilmgandhi | 18:6a4db94011d3 | 24 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 25 | * System clock source | 1- PLL_HSE_XTAL | 3- PLL_HSI |
| sahilmgandhi | 18:6a4db94011d3 | 26 | * | (external 16 MHz xtal) | (internal 16 MHz) |
| sahilmgandhi | 18:6a4db94011d3 | 27 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 28 | * SYSCLK(MHz) | 180 | 180 |
| sahilmgandhi | 18:6a4db94011d3 | 29 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 30 | * AHBCLK (MHz) | 180 | 180 |
| sahilmgandhi | 18:6a4db94011d3 | 31 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 32 | * APB1CLK (MHz) | 45 | 45 |
| sahilmgandhi | 18:6a4db94011d3 | 33 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 34 | * APB2CLK (MHz) | 90 | 90 |
| sahilmgandhi | 18:6a4db94011d3 | 35 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 36 | * USB capable (48 MHz precise clock) | YES | NO |
| sahilmgandhi | 18:6a4db94011d3 | 37 | *----------------------------------------------------------------------------- |
| sahilmgandhi | 18:6a4db94011d3 | 38 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 39 | * @attention |
| sahilmgandhi | 18:6a4db94011d3 | 40 | * |
| sahilmgandhi | 18:6a4db94011d3 | 41 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| sahilmgandhi | 18:6a4db94011d3 | 42 | * |
| sahilmgandhi | 18:6a4db94011d3 | 43 | * Redistribution and use in source and binary forms, with or without modification, |
| sahilmgandhi | 18:6a4db94011d3 | 44 | * are permitted provided that the following conditions are met: |
| sahilmgandhi | 18:6a4db94011d3 | 45 | * 1. Redistributions of source code must retain the above copyright notice, |
| sahilmgandhi | 18:6a4db94011d3 | 46 | * this list of conditions and the following disclaimer. |
| sahilmgandhi | 18:6a4db94011d3 | 47 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| sahilmgandhi | 18:6a4db94011d3 | 48 | * this list of conditions and the following disclaimer in the documentation |
| sahilmgandhi | 18:6a4db94011d3 | 49 | * and/or other materials provided with the distribution. |
| sahilmgandhi | 18:6a4db94011d3 | 50 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| sahilmgandhi | 18:6a4db94011d3 | 51 | * may be used to endorse or promote products derived from this software |
| sahilmgandhi | 18:6a4db94011d3 | 52 | * without specific prior written permission. |
| sahilmgandhi | 18:6a4db94011d3 | 53 | * |
| sahilmgandhi | 18:6a4db94011d3 | 54 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| sahilmgandhi | 18:6a4db94011d3 | 55 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| sahilmgandhi | 18:6a4db94011d3 | 56 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| sahilmgandhi | 18:6a4db94011d3 | 57 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| sahilmgandhi | 18:6a4db94011d3 | 58 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| sahilmgandhi | 18:6a4db94011d3 | 59 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| sahilmgandhi | 18:6a4db94011d3 | 60 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| sahilmgandhi | 18:6a4db94011d3 | 61 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| sahilmgandhi | 18:6a4db94011d3 | 62 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| sahilmgandhi | 18:6a4db94011d3 | 63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| sahilmgandhi | 18:6a4db94011d3 | 64 | * |
| sahilmgandhi | 18:6a4db94011d3 | 65 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 66 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 67 | |
| sahilmgandhi | 18:6a4db94011d3 | 68 | /** @addtogroup CMSIS |
| sahilmgandhi | 18:6a4db94011d3 | 69 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 70 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 71 | |
| sahilmgandhi | 18:6a4db94011d3 | 72 | /** @addtogroup stm32f4xx_system |
| sahilmgandhi | 18:6a4db94011d3 | 73 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 74 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 75 | |
| sahilmgandhi | 18:6a4db94011d3 | 76 | /** @addtogroup STM32F4xx_System_Private_Includes |
| sahilmgandhi | 18:6a4db94011d3 | 77 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 78 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 79 | |
| sahilmgandhi | 18:6a4db94011d3 | 80 | #include "stm32f4xx.h" |
| sahilmgandhi | 18:6a4db94011d3 | 81 | #include "hal_tick.h" |
| sahilmgandhi | 18:6a4db94011d3 | 82 | |
| sahilmgandhi | 18:6a4db94011d3 | 83 | #if !defined (HSE_VALUE) |
| sahilmgandhi | 18:6a4db94011d3 | 84 | #define HSE_VALUE ((uint32_t)16000000) /*!< Default value of the External oscillator in Hz */ |
| sahilmgandhi | 18:6a4db94011d3 | 85 | #endif /* HSE_VALUE */ |
| sahilmgandhi | 18:6a4db94011d3 | 86 | |
| sahilmgandhi | 18:6a4db94011d3 | 87 | #if !defined (HSI_VALUE) |
| sahilmgandhi | 18:6a4db94011d3 | 88 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| sahilmgandhi | 18:6a4db94011d3 | 89 | #endif /* HSI_VALUE */ |
| sahilmgandhi | 18:6a4db94011d3 | 90 | |
| sahilmgandhi | 18:6a4db94011d3 | 91 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 92 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 93 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 94 | |
| sahilmgandhi | 18:6a4db94011d3 | 95 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| sahilmgandhi | 18:6a4db94011d3 | 96 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 97 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 98 | |
| sahilmgandhi | 18:6a4db94011d3 | 99 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 100 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 101 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 102 | |
| sahilmgandhi | 18:6a4db94011d3 | 103 | /** @addtogroup STM32F4xx_System_Private_Defines |
| sahilmgandhi | 18:6a4db94011d3 | 104 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 105 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 106 | |
| sahilmgandhi | 18:6a4db94011d3 | 107 | /************************* Miscellaneous Configuration ************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 108 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ |
| sahilmgandhi | 18:6a4db94011d3 | 109 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 110 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 111 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| sahilmgandhi | 18:6a4db94011d3 | 112 | /* #define DATA_IN_ExtSRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 113 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ |
| sahilmgandhi | 18:6a4db94011d3 | 114 | STM32F412Zx || STM32F412Vx */ |
| sahilmgandhi | 18:6a4db94011d3 | 115 | |
| sahilmgandhi | 18:6a4db94011d3 | 116 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 117 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| sahilmgandhi | 18:6a4db94011d3 | 118 | /* #define DATA_IN_ExtSDRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 119 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
| sahilmgandhi | 18:6a4db94011d3 | 120 | STM32F479xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 121 | |
| sahilmgandhi | 18:6a4db94011d3 | 122 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| sahilmgandhi | 18:6a4db94011d3 | 123 | Internal SRAM. */ |
| sahilmgandhi | 18:6a4db94011d3 | 124 | /* #define VECT_TAB_SRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 125 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| sahilmgandhi | 18:6a4db94011d3 | 126 | This value must be a multiple of 0x200. */ |
| sahilmgandhi | 18:6a4db94011d3 | 127 | /******************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 128 | |
| sahilmgandhi | 18:6a4db94011d3 | 129 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 130 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 131 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 132 | |
| sahilmgandhi | 18:6a4db94011d3 | 133 | /** @addtogroup STM32F4xx_System_Private_Macros |
| sahilmgandhi | 18:6a4db94011d3 | 134 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 135 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 136 | |
| sahilmgandhi | 18:6a4db94011d3 | 137 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| sahilmgandhi | 18:6a4db94011d3 | 138 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 139 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| sahilmgandhi | 18:6a4db94011d3 | 140 | |
| sahilmgandhi | 18:6a4db94011d3 | 141 | #define DEBUG_MCO (0) // 0=OFF |
| sahilmgandhi | 18:6a4db94011d3 | 142 | // 1=Output the MCO1 on PA8 |
| sahilmgandhi | 18:6a4db94011d3 | 143 | // 2=Output the MCO2 on PC9 |
| sahilmgandhi | 18:6a4db94011d3 | 144 | |
| sahilmgandhi | 18:6a4db94011d3 | 145 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 146 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 147 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 148 | |
| sahilmgandhi | 18:6a4db94011d3 | 149 | /** @addtogroup STM32F4xx_System_Private_Variables |
| sahilmgandhi | 18:6a4db94011d3 | 150 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 151 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 152 | /* This variable is updated in three ways: |
| sahilmgandhi | 18:6a4db94011d3 | 153 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| sahilmgandhi | 18:6a4db94011d3 | 154 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| sahilmgandhi | 18:6a4db94011d3 | 155 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| sahilmgandhi | 18:6a4db94011d3 | 156 | Note: If you use this function to configure the system clock; then there |
| sahilmgandhi | 18:6a4db94011d3 | 157 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| sahilmgandhi | 18:6a4db94011d3 | 158 | variable is updated automatically. |
| sahilmgandhi | 18:6a4db94011d3 | 159 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 160 | uint32_t SystemCoreClock = 16000000; |
| sahilmgandhi | 18:6a4db94011d3 | 161 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| sahilmgandhi | 18:6a4db94011d3 | 162 | |
| sahilmgandhi | 18:6a4db94011d3 | 163 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 164 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 165 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 166 | |
| sahilmgandhi | 18:6a4db94011d3 | 167 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| sahilmgandhi | 18:6a4db94011d3 | 168 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 169 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 170 | |
| sahilmgandhi | 18:6a4db94011d3 | 171 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 172 | static void SystemInit_ExtMemCtl(void); |
| sahilmgandhi | 18:6a4db94011d3 | 173 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 174 | |
| sahilmgandhi | 18:6a4db94011d3 | 175 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| sahilmgandhi | 18:6a4db94011d3 | 176 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| sahilmgandhi | 18:6a4db94011d3 | 177 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 178 | |
| sahilmgandhi | 18:6a4db94011d3 | 179 | uint8_t SetSysClock_PLL_HSI(void); |
| sahilmgandhi | 18:6a4db94011d3 | 180 | |
| sahilmgandhi | 18:6a4db94011d3 | 181 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 182 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 183 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 184 | |
| sahilmgandhi | 18:6a4db94011d3 | 185 | /** @addtogroup STM32F4xx_System_Private_Functions |
| sahilmgandhi | 18:6a4db94011d3 | 186 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 187 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 188 | |
| sahilmgandhi | 18:6a4db94011d3 | 189 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 190 | * @brief Setup the microcontroller system |
| sahilmgandhi | 18:6a4db94011d3 | 191 | * Initialize the FPU setting, vector table location and External memory |
| sahilmgandhi | 18:6a4db94011d3 | 192 | * configuration. |
| sahilmgandhi | 18:6a4db94011d3 | 193 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 194 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 195 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 196 | void SystemInit(void) |
| sahilmgandhi | 18:6a4db94011d3 | 197 | { |
| sahilmgandhi | 18:6a4db94011d3 | 198 | /* FPU settings ------------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 199 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| sahilmgandhi | 18:6a4db94011d3 | 200 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| sahilmgandhi | 18:6a4db94011d3 | 201 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 202 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 203 | /* Set HSION bit */ |
| sahilmgandhi | 18:6a4db94011d3 | 204 | RCC->CR |= (uint32_t)0x00000001; |
| sahilmgandhi | 18:6a4db94011d3 | 205 | |
| sahilmgandhi | 18:6a4db94011d3 | 206 | /* Reset CFGR register */ |
| sahilmgandhi | 18:6a4db94011d3 | 207 | RCC->CFGR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 208 | |
| sahilmgandhi | 18:6a4db94011d3 | 209 | /* Reset HSEON, CSSON and PLLON bits */ |
| sahilmgandhi | 18:6a4db94011d3 | 210 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 211 | |
| sahilmgandhi | 18:6a4db94011d3 | 212 | /* Reset PLLCFGR register */ |
| sahilmgandhi | 18:6a4db94011d3 | 213 | RCC->PLLCFGR = 0x24003010; |
| sahilmgandhi | 18:6a4db94011d3 | 214 | |
| sahilmgandhi | 18:6a4db94011d3 | 215 | /* Reset HSEBYP bit */ |
| sahilmgandhi | 18:6a4db94011d3 | 216 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 217 | |
| sahilmgandhi | 18:6a4db94011d3 | 218 | /* Disable all interrupts */ |
| sahilmgandhi | 18:6a4db94011d3 | 219 | RCC->CIR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 220 | |
| sahilmgandhi | 18:6a4db94011d3 | 221 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 222 | SystemInit_ExtMemCtl(); |
| sahilmgandhi | 18:6a4db94011d3 | 223 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 224 | |
| sahilmgandhi | 18:6a4db94011d3 | 225 | /* Configure the Vector Table location add offset address ------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 226 | #ifdef VECT_TAB_SRAM |
| sahilmgandhi | 18:6a4db94011d3 | 227 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 228 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 229 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| sahilmgandhi | 18:6a4db94011d3 | 230 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 231 | |
| sahilmgandhi | 18:6a4db94011d3 | 232 | /* Configure the Cube driver */ |
| sahilmgandhi | 18:6a4db94011d3 | 233 | SystemCoreClock = 18000000; // At this stage the HSI is used as system clock |
| sahilmgandhi | 18:6a4db94011d3 | 234 | HAL_Init(); |
| sahilmgandhi | 18:6a4db94011d3 | 235 | |
| sahilmgandhi | 18:6a4db94011d3 | 236 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| sahilmgandhi | 18:6a4db94011d3 | 237 | AHB/APBx prescalers and Flash settings */ |
| sahilmgandhi | 18:6a4db94011d3 | 238 | SetSysClock(); |
| sahilmgandhi | 18:6a4db94011d3 | 239 | |
| sahilmgandhi | 18:6a4db94011d3 | 240 | /* Reset the timer to avoid issues after the RAM initialization */ |
| sahilmgandhi | 18:6a4db94011d3 | 241 | TIM_MST_RESET_ON; |
| sahilmgandhi | 18:6a4db94011d3 | 242 | TIM_MST_RESET_OFF; |
| sahilmgandhi | 18:6a4db94011d3 | 243 | } |
| sahilmgandhi | 18:6a4db94011d3 | 244 | |
| sahilmgandhi | 18:6a4db94011d3 | 245 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 246 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| sahilmgandhi | 18:6a4db94011d3 | 247 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| sahilmgandhi | 18:6a4db94011d3 | 248 | * be used by the user application to setup the SysTick timer or configure |
| sahilmgandhi | 18:6a4db94011d3 | 249 | * other parameters. |
| sahilmgandhi | 18:6a4db94011d3 | 250 | * |
| sahilmgandhi | 18:6a4db94011d3 | 251 | * @note Each time the core clock (HCLK) changes, this function must be called |
| sahilmgandhi | 18:6a4db94011d3 | 252 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| sahilmgandhi | 18:6a4db94011d3 | 253 | * based on this variable will be incorrect. |
| sahilmgandhi | 18:6a4db94011d3 | 254 | * |
| sahilmgandhi | 18:6a4db94011d3 | 255 | * @note - The system frequency computed by this function is not the real |
| sahilmgandhi | 18:6a4db94011d3 | 256 | * frequency in the chip. It is calculated based on the predefined |
| sahilmgandhi | 18:6a4db94011d3 | 257 | * constant and the selected clock source: |
| sahilmgandhi | 18:6a4db94011d3 | 258 | * |
| sahilmgandhi | 18:6a4db94011d3 | 259 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| sahilmgandhi | 18:6a4db94011d3 | 260 | * |
| sahilmgandhi | 18:6a4db94011d3 | 261 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| sahilmgandhi | 18:6a4db94011d3 | 262 | * |
| sahilmgandhi | 18:6a4db94011d3 | 263 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| sahilmgandhi | 18:6a4db94011d3 | 264 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| sahilmgandhi | 18:6a4db94011d3 | 265 | * |
| sahilmgandhi | 18:6a4db94011d3 | 266 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| sahilmgandhi | 18:6a4db94011d3 | 267 | * 16 MHz) but the real value may vary depending on the variations |
| sahilmgandhi | 18:6a4db94011d3 | 268 | * in voltage and temperature. |
| sahilmgandhi | 18:6a4db94011d3 | 269 | * |
| sahilmgandhi | 18:6a4db94011d3 | 270 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| sahilmgandhi | 18:6a4db94011d3 | 271 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| sahilmgandhi | 18:6a4db94011d3 | 272 | * is same as the real frequency of the crystal used. Otherwise, this function |
| sahilmgandhi | 18:6a4db94011d3 | 273 | * may have wrong result. |
| sahilmgandhi | 18:6a4db94011d3 | 274 | * |
| sahilmgandhi | 18:6a4db94011d3 | 275 | * - The result of this function could be not correct when using fractional |
| sahilmgandhi | 18:6a4db94011d3 | 276 | * value for HSE crystal. |
| sahilmgandhi | 18:6a4db94011d3 | 277 | * |
| sahilmgandhi | 18:6a4db94011d3 | 278 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 279 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 280 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 281 | void SystemCoreClockUpdate(void) |
| sahilmgandhi | 18:6a4db94011d3 | 282 | { |
| sahilmgandhi | 18:6a4db94011d3 | 283 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| sahilmgandhi | 18:6a4db94011d3 | 284 | |
| sahilmgandhi | 18:6a4db94011d3 | 285 | /* Get SYSCLK source -------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 286 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| sahilmgandhi | 18:6a4db94011d3 | 287 | |
| sahilmgandhi | 18:6a4db94011d3 | 288 | switch (tmp) |
| sahilmgandhi | 18:6a4db94011d3 | 289 | { |
| sahilmgandhi | 18:6a4db94011d3 | 290 | case 0x00: /* HSI used as system clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 291 | SystemCoreClock = HSI_VALUE; |
| sahilmgandhi | 18:6a4db94011d3 | 292 | break; |
| sahilmgandhi | 18:6a4db94011d3 | 293 | case 0x04: /* HSE used as system clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 294 | SystemCoreClock = HSE_VALUE; |
| sahilmgandhi | 18:6a4db94011d3 | 295 | break; |
| sahilmgandhi | 18:6a4db94011d3 | 296 | case 0x08: /* PLL used as system clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 297 | |
| sahilmgandhi | 18:6a4db94011d3 | 298 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| sahilmgandhi | 18:6a4db94011d3 | 299 | SYSCLK = PLL_VCO / PLL_P |
| sahilmgandhi | 18:6a4db94011d3 | 300 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 301 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| sahilmgandhi | 18:6a4db94011d3 | 302 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| sahilmgandhi | 18:6a4db94011d3 | 303 | |
| sahilmgandhi | 18:6a4db94011d3 | 304 | if (pllsource != 0) |
| sahilmgandhi | 18:6a4db94011d3 | 305 | { |
| sahilmgandhi | 18:6a4db94011d3 | 306 | /* HSE used as PLL clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 307 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| sahilmgandhi | 18:6a4db94011d3 | 308 | } |
| sahilmgandhi | 18:6a4db94011d3 | 309 | else |
| sahilmgandhi | 18:6a4db94011d3 | 310 | { |
| sahilmgandhi | 18:6a4db94011d3 | 311 | /* HSI used as PLL clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 312 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| sahilmgandhi | 18:6a4db94011d3 | 313 | } |
| sahilmgandhi | 18:6a4db94011d3 | 314 | |
| sahilmgandhi | 18:6a4db94011d3 | 315 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| sahilmgandhi | 18:6a4db94011d3 | 316 | SystemCoreClock = pllvco/pllp; |
| sahilmgandhi | 18:6a4db94011d3 | 317 | break; |
| sahilmgandhi | 18:6a4db94011d3 | 318 | default: |
| sahilmgandhi | 18:6a4db94011d3 | 319 | SystemCoreClock = HSI_VALUE; |
| sahilmgandhi | 18:6a4db94011d3 | 320 | break; |
| sahilmgandhi | 18:6a4db94011d3 | 321 | } |
| sahilmgandhi | 18:6a4db94011d3 | 322 | /* Compute HCLK frequency --------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 323 | /* Get HCLK prescaler */ |
| sahilmgandhi | 18:6a4db94011d3 | 324 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| sahilmgandhi | 18:6a4db94011d3 | 325 | /* HCLK frequency */ |
| sahilmgandhi | 18:6a4db94011d3 | 326 | SystemCoreClock >>= tmp; |
| sahilmgandhi | 18:6a4db94011d3 | 327 | } |
| sahilmgandhi | 18:6a4db94011d3 | 328 | |
| sahilmgandhi | 18:6a4db94011d3 | 329 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 330 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| sahilmgandhi | 18:6a4db94011d3 | 331 | defined(STM32F469xx) || defined(STM32F479xx) |
| sahilmgandhi | 18:6a4db94011d3 | 332 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 333 | * @brief Setup the external memory controller. |
| sahilmgandhi | 18:6a4db94011d3 | 334 | * Called in startup_stm32f4xx.s before jump to main. |
| sahilmgandhi | 18:6a4db94011d3 | 335 | * This function configures the external memories (SRAM/SDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 336 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| sahilmgandhi | 18:6a4db94011d3 | 337 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 338 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 339 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 340 | void SystemInit_ExtMemCtl(void) |
| sahilmgandhi | 18:6a4db94011d3 | 341 | { |
| sahilmgandhi | 18:6a4db94011d3 | 342 | __IO uint32_t tmp = 0x00; |
| sahilmgandhi | 18:6a4db94011d3 | 343 | |
| sahilmgandhi | 18:6a4db94011d3 | 344 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 345 | register __IO uint32_t index; |
| sahilmgandhi | 18:6a4db94011d3 | 346 | |
| sahilmgandhi | 18:6a4db94011d3 | 347 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 348 | RCC->AHB1ENR |= 0x000001F8; |
| sahilmgandhi | 18:6a4db94011d3 | 349 | |
| sahilmgandhi | 18:6a4db94011d3 | 350 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 351 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 352 | |
| sahilmgandhi | 18:6a4db94011d3 | 353 | /* Connect PDx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 354 | GPIOD->AFR[0] = 0x00CCC0CC; |
| sahilmgandhi | 18:6a4db94011d3 | 355 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 356 | /* Configure PDx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 357 | GPIOD->MODER = 0xAAAA0A8A; |
| sahilmgandhi | 18:6a4db94011d3 | 358 | /* Configure PDx pins speed to 100 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 359 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| sahilmgandhi | 18:6a4db94011d3 | 360 | /* Configure PDx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 361 | GPIOD->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 362 | /* No pull-up, pull-down for PDx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 363 | GPIOD->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 364 | |
| sahilmgandhi | 18:6a4db94011d3 | 365 | /* Connect PEx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 366 | GPIOE->AFR[0] = 0xC00CC0CC; |
| sahilmgandhi | 18:6a4db94011d3 | 367 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 368 | /* Configure PEx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 369 | GPIOE->MODER = 0xAAAA828A; |
| sahilmgandhi | 18:6a4db94011d3 | 370 | /* Configure PEx pins speed to 100 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 371 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| sahilmgandhi | 18:6a4db94011d3 | 372 | /* Configure PEx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 373 | GPIOE->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 374 | /* No pull-up, pull-down for PEx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 375 | GPIOE->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 376 | |
| sahilmgandhi | 18:6a4db94011d3 | 377 | /* Connect PFx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 378 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 379 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 380 | /* Configure PFx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 381 | GPIOF->MODER = 0xAA800AAA; |
| sahilmgandhi | 18:6a4db94011d3 | 382 | /* Configure PFx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 383 | GPIOF->OSPEEDR = 0xAA800AAA; |
| sahilmgandhi | 18:6a4db94011d3 | 384 | /* Configure PFx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 385 | GPIOF->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 386 | /* No pull-up, pull-down for PFx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 387 | GPIOF->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 388 | |
| sahilmgandhi | 18:6a4db94011d3 | 389 | /* Connect PGx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 390 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 391 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 392 | /* Configure PGx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 393 | GPIOG->MODER = 0xAAAAAAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 394 | /* Configure PGx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 395 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 396 | /* Configure PGx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 397 | GPIOG->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 398 | /* No pull-up, pull-down for PGx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 399 | GPIOG->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 400 | |
| sahilmgandhi | 18:6a4db94011d3 | 401 | /* Connect PHx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 402 | GPIOH->AFR[0] = 0x00C0CC00; |
| sahilmgandhi | 18:6a4db94011d3 | 403 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 404 | /* Configure PHx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 405 | GPIOH->MODER = 0xAAAA08A0; |
| sahilmgandhi | 18:6a4db94011d3 | 406 | /* Configure PHx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 407 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| sahilmgandhi | 18:6a4db94011d3 | 408 | /* Configure PHx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 409 | GPIOH->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 410 | /* No pull-up, pull-down for PHx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 411 | GPIOH->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 412 | |
| sahilmgandhi | 18:6a4db94011d3 | 413 | /* Connect PIx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 414 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 415 | GPIOI->AFR[1] = 0x00000CC0; |
| sahilmgandhi | 18:6a4db94011d3 | 416 | /* Configure PIx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 417 | GPIOI->MODER = 0x0028AAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 418 | /* Configure PIx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 419 | GPIOI->OSPEEDR = 0x0028AAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 420 | /* Configure PIx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 421 | GPIOI->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 422 | /* No pull-up, pull-down for PIx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 423 | GPIOI->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 424 | |
| sahilmgandhi | 18:6a4db94011d3 | 425 | /*-- FMC Configuration -------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 426 | /* Enable the FMC interface clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 427 | RCC->AHB3ENR |= 0x00000001; |
| sahilmgandhi | 18:6a4db94011d3 | 428 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 429 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 430 | |
| sahilmgandhi | 18:6a4db94011d3 | 431 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| sahilmgandhi | 18:6a4db94011d3 | 432 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| sahilmgandhi | 18:6a4db94011d3 | 433 | |
| sahilmgandhi | 18:6a4db94011d3 | 434 | /* SDRAM initialization sequence */ |
| sahilmgandhi | 18:6a4db94011d3 | 435 | /* Clock enable command */ |
| sahilmgandhi | 18:6a4db94011d3 | 436 | FMC_Bank5_6->SDCMR = 0x00000011; |
| sahilmgandhi | 18:6a4db94011d3 | 437 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 438 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 439 | { |
| sahilmgandhi | 18:6a4db94011d3 | 440 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 441 | } |
| sahilmgandhi | 18:6a4db94011d3 | 442 | |
| sahilmgandhi | 18:6a4db94011d3 | 443 | /* Delay */ |
| sahilmgandhi | 18:6a4db94011d3 | 444 | for (index = 0; index<1000; index++); |
| sahilmgandhi | 18:6a4db94011d3 | 445 | |
| sahilmgandhi | 18:6a4db94011d3 | 446 | /* PALL command */ |
| sahilmgandhi | 18:6a4db94011d3 | 447 | FMC_Bank5_6->SDCMR = 0x00000012; |
| sahilmgandhi | 18:6a4db94011d3 | 448 | timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 449 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 450 | { |
| sahilmgandhi | 18:6a4db94011d3 | 451 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 452 | } |
| sahilmgandhi | 18:6a4db94011d3 | 453 | |
| sahilmgandhi | 18:6a4db94011d3 | 454 | /* Auto refresh command */ |
| sahilmgandhi | 18:6a4db94011d3 | 455 | FMC_Bank5_6->SDCMR = 0x00000073; |
| sahilmgandhi | 18:6a4db94011d3 | 456 | timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 457 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 458 | { |
| sahilmgandhi | 18:6a4db94011d3 | 459 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 460 | } |
| sahilmgandhi | 18:6a4db94011d3 | 461 | |
| sahilmgandhi | 18:6a4db94011d3 | 462 | /* MRD register program */ |
| sahilmgandhi | 18:6a4db94011d3 | 463 | FMC_Bank5_6->SDCMR = 0x00046014; |
| sahilmgandhi | 18:6a4db94011d3 | 464 | timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 465 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 466 | { |
| sahilmgandhi | 18:6a4db94011d3 | 467 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 468 | } |
| sahilmgandhi | 18:6a4db94011d3 | 469 | |
| sahilmgandhi | 18:6a4db94011d3 | 470 | /* Set refresh count */ |
| sahilmgandhi | 18:6a4db94011d3 | 471 | tmpreg = FMC_Bank5_6->SDRTR; |
| sahilmgandhi | 18:6a4db94011d3 | 472 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| sahilmgandhi | 18:6a4db94011d3 | 473 | |
| sahilmgandhi | 18:6a4db94011d3 | 474 | /* Disable write protection */ |
| sahilmgandhi | 18:6a4db94011d3 | 475 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| sahilmgandhi | 18:6a4db94011d3 | 476 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| sahilmgandhi | 18:6a4db94011d3 | 477 | |
| sahilmgandhi | 18:6a4db94011d3 | 478 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| sahilmgandhi | 18:6a4db94011d3 | 479 | /* Configure and enable Bank1_SRAM2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 480 | FMC_Bank1->BTCR[2] = 0x00001011; |
| sahilmgandhi | 18:6a4db94011d3 | 481 | FMC_Bank1->BTCR[3] = 0x00000201; |
| sahilmgandhi | 18:6a4db94011d3 | 482 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| sahilmgandhi | 18:6a4db94011d3 | 483 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 484 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| sahilmgandhi | 18:6a4db94011d3 | 485 | /* Configure and enable Bank1_SRAM2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 486 | FMC_Bank1->BTCR[2] = 0x00001091; |
| sahilmgandhi | 18:6a4db94011d3 | 487 | FMC_Bank1->BTCR[3] = 0x00110212; |
| sahilmgandhi | 18:6a4db94011d3 | 488 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| sahilmgandhi | 18:6a4db94011d3 | 489 | #endif /* STM32F469xx || STM32F479xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 490 | |
| sahilmgandhi | 18:6a4db94011d3 | 491 | (void)(tmp); |
| sahilmgandhi | 18:6a4db94011d3 | 492 | } |
| sahilmgandhi | 18:6a4db94011d3 | 493 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 494 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 495 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 496 | * @brief Setup the external memory controller. |
| sahilmgandhi | 18:6a4db94011d3 | 497 | * Called in startup_stm32f4xx.s before jump to main. |
| sahilmgandhi | 18:6a4db94011d3 | 498 | * This function configures the external memories (SRAM/SDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 499 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| sahilmgandhi | 18:6a4db94011d3 | 500 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 501 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 502 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 503 | void SystemInit_ExtMemCtl(void) |
| sahilmgandhi | 18:6a4db94011d3 | 504 | { |
| sahilmgandhi | 18:6a4db94011d3 | 505 | __IO uint32_t tmp = 0x00; |
| sahilmgandhi | 18:6a4db94011d3 | 506 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 507 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| sahilmgandhi | 18:6a4db94011d3 | 508 | #if defined (DATA_IN_ExtSDRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 509 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 510 | register __IO uint32_t index; |
| sahilmgandhi | 18:6a4db94011d3 | 511 | |
| sahilmgandhi | 18:6a4db94011d3 | 512 | #if defined(STM32F446xx) |
| sahilmgandhi | 18:6a4db94011d3 | 513 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface |
| sahilmgandhi | 18:6a4db94011d3 | 514 | clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 515 | RCC->AHB1ENR |= 0x0000007D; |
| sahilmgandhi | 18:6a4db94011d3 | 516 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 517 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| sahilmgandhi | 18:6a4db94011d3 | 518 | clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 519 | RCC->AHB1ENR |= 0x000001F8; |
| sahilmgandhi | 18:6a4db94011d3 | 520 | #endif /* STM32F446xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 521 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 522 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 523 | |
| sahilmgandhi | 18:6a4db94011d3 | 524 | #if defined(STM32F446xx) |
| sahilmgandhi | 18:6a4db94011d3 | 525 | /* Connect PAx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 526 | GPIOA->AFR[0] |= 0xC0000000; |
| sahilmgandhi | 18:6a4db94011d3 | 527 | GPIOA->AFR[1] |= 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 528 | /* Configure PDx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 529 | GPIOA->MODER |= 0x00008000; |
| sahilmgandhi | 18:6a4db94011d3 | 530 | /* Configure PDx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 531 | GPIOA->OSPEEDR |= 0x00008000; |
| sahilmgandhi | 18:6a4db94011d3 | 532 | /* Configure PDx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 533 | GPIOA->OTYPER |= 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 534 | /* No pull-up, pull-down for PDx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 535 | GPIOA->PUPDR |= 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 536 | |
| sahilmgandhi | 18:6a4db94011d3 | 537 | /* Connect PCx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 538 | GPIOC->AFR[0] |= 0x00CC0000; |
| sahilmgandhi | 18:6a4db94011d3 | 539 | GPIOC->AFR[1] |= 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 540 | /* Configure PDx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 541 | GPIOC->MODER |= 0x00000A00; |
| sahilmgandhi | 18:6a4db94011d3 | 542 | /* Configure PDx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 543 | GPIOC->OSPEEDR |= 0x00000A00; |
| sahilmgandhi | 18:6a4db94011d3 | 544 | /* Configure PDx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 545 | GPIOC->OTYPER |= 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 546 | /* No pull-up, pull-down for PDx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 547 | GPIOC->PUPDR |= 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 548 | #endif /* STM32F446xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 549 | |
| sahilmgandhi | 18:6a4db94011d3 | 550 | /* Connect PDx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 551 | GPIOD->AFR[0] = 0x000000CC; |
| sahilmgandhi | 18:6a4db94011d3 | 552 | GPIOD->AFR[1] = 0xCC000CCC; |
| sahilmgandhi | 18:6a4db94011d3 | 553 | /* Configure PDx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 554 | GPIOD->MODER = 0xA02A000A; |
| sahilmgandhi | 18:6a4db94011d3 | 555 | /* Configure PDx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 556 | GPIOD->OSPEEDR = 0xA02A000A; |
| sahilmgandhi | 18:6a4db94011d3 | 557 | /* Configure PDx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 558 | GPIOD->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 559 | /* No pull-up, pull-down for PDx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 560 | GPIOD->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 561 | |
| sahilmgandhi | 18:6a4db94011d3 | 562 | /* Connect PEx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 563 | GPIOE->AFR[0] = 0xC00000CC; |
| sahilmgandhi | 18:6a4db94011d3 | 564 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 565 | /* Configure PEx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 566 | GPIOE->MODER = 0xAAAA800A; |
| sahilmgandhi | 18:6a4db94011d3 | 567 | /* Configure PEx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 568 | GPIOE->OSPEEDR = 0xAAAA800A; |
| sahilmgandhi | 18:6a4db94011d3 | 569 | /* Configure PEx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 570 | GPIOE->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 571 | /* No pull-up, pull-down for PEx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 572 | GPIOE->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 573 | |
| sahilmgandhi | 18:6a4db94011d3 | 574 | /* Connect PFx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 575 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 576 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 577 | /* Configure PFx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 578 | GPIOF->MODER = 0xAA800AAA; |
| sahilmgandhi | 18:6a4db94011d3 | 579 | /* Configure PFx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 580 | GPIOF->OSPEEDR = 0xAA800AAA; |
| sahilmgandhi | 18:6a4db94011d3 | 581 | /* Configure PFx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 582 | GPIOF->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 583 | /* No pull-up, pull-down for PFx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 584 | GPIOF->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 585 | |
| sahilmgandhi | 18:6a4db94011d3 | 586 | /* Connect PGx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 587 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 588 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 589 | /* Configure PGx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 590 | GPIOG->MODER = 0xAAAAAAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 591 | /* Configure PGx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 592 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 593 | /* Configure PGx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 594 | GPIOG->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 595 | /* No pull-up, pull-down for PGx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 596 | GPIOG->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 597 | |
| sahilmgandhi | 18:6a4db94011d3 | 598 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 599 | || defined(STM32F469xx) || defined(STM32F479xx) |
| sahilmgandhi | 18:6a4db94011d3 | 600 | /* Connect PHx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 601 | GPIOH->AFR[0] = 0x00C0CC00; |
| sahilmgandhi | 18:6a4db94011d3 | 602 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 603 | /* Configure PHx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 604 | GPIOH->MODER = 0xAAAA08A0; |
| sahilmgandhi | 18:6a4db94011d3 | 605 | /* Configure PHx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 606 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| sahilmgandhi | 18:6a4db94011d3 | 607 | /* Configure PHx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 608 | GPIOH->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 609 | /* No pull-up, pull-down for PHx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 610 | GPIOH->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 611 | |
| sahilmgandhi | 18:6a4db94011d3 | 612 | /* Connect PIx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 613 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 614 | GPIOI->AFR[1] = 0x00000CC0; |
| sahilmgandhi | 18:6a4db94011d3 | 615 | /* Configure PIx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 616 | GPIOI->MODER = 0x0028AAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 617 | /* Configure PIx pins speed to 50 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 618 | GPIOI->OSPEEDR = 0x0028AAAA; |
| sahilmgandhi | 18:6a4db94011d3 | 619 | /* Configure PIx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 620 | GPIOI->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 621 | /* No pull-up, pull-down for PIx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 622 | GPIOI->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 623 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 624 | |
| sahilmgandhi | 18:6a4db94011d3 | 625 | /*-- FMC Configuration -------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 626 | /* Enable the FMC interface clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 627 | RCC->AHB3ENR |= 0x00000001; |
| sahilmgandhi | 18:6a4db94011d3 | 628 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 629 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 630 | |
| sahilmgandhi | 18:6a4db94011d3 | 631 | /* Configure and enable SDRAM bank1 */ |
| sahilmgandhi | 18:6a4db94011d3 | 632 | #if defined(STM32F446xx) |
| sahilmgandhi | 18:6a4db94011d3 | 633 | FMC_Bank5_6->SDCR[0] = 0x00001954; |
| sahilmgandhi | 18:6a4db94011d3 | 634 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 635 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| sahilmgandhi | 18:6a4db94011d3 | 636 | #endif /* STM32F446xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 637 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| sahilmgandhi | 18:6a4db94011d3 | 638 | |
| sahilmgandhi | 18:6a4db94011d3 | 639 | /* SDRAM initialization sequence */ |
| sahilmgandhi | 18:6a4db94011d3 | 640 | /* Clock enable command */ |
| sahilmgandhi | 18:6a4db94011d3 | 641 | FMC_Bank5_6->SDCMR = 0x00000011; |
| sahilmgandhi | 18:6a4db94011d3 | 642 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 643 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 644 | { |
| sahilmgandhi | 18:6a4db94011d3 | 645 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 646 | } |
| sahilmgandhi | 18:6a4db94011d3 | 647 | |
| sahilmgandhi | 18:6a4db94011d3 | 648 | /* Delay */ |
| sahilmgandhi | 18:6a4db94011d3 | 649 | for (index = 0; index<1000; index++); |
| sahilmgandhi | 18:6a4db94011d3 | 650 | |
| sahilmgandhi | 18:6a4db94011d3 | 651 | /* PALL command */ |
| sahilmgandhi | 18:6a4db94011d3 | 652 | FMC_Bank5_6->SDCMR = 0x00000012; |
| sahilmgandhi | 18:6a4db94011d3 | 653 | timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 654 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 655 | { |
| sahilmgandhi | 18:6a4db94011d3 | 656 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 657 | } |
| sahilmgandhi | 18:6a4db94011d3 | 658 | |
| sahilmgandhi | 18:6a4db94011d3 | 659 | /* Auto refresh command */ |
| sahilmgandhi | 18:6a4db94011d3 | 660 | #if defined(STM32F446xx) |
| sahilmgandhi | 18:6a4db94011d3 | 661 | FMC_Bank5_6->SDCMR = 0x000000F3; |
| sahilmgandhi | 18:6a4db94011d3 | 662 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 663 | FMC_Bank5_6->SDCMR = 0x00000073; |
| sahilmgandhi | 18:6a4db94011d3 | 664 | #endif /* STM32F446xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 665 | timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 666 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 667 | { |
| sahilmgandhi | 18:6a4db94011d3 | 668 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 669 | } |
| sahilmgandhi | 18:6a4db94011d3 | 670 | |
| sahilmgandhi | 18:6a4db94011d3 | 671 | /* MRD register program */ |
| sahilmgandhi | 18:6a4db94011d3 | 672 | #if defined(STM32F446xx) |
| sahilmgandhi | 18:6a4db94011d3 | 673 | FMC_Bank5_6->SDCMR = 0x00044014; |
| sahilmgandhi | 18:6a4db94011d3 | 674 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 675 | FMC_Bank5_6->SDCMR = 0x00046014; |
| sahilmgandhi | 18:6a4db94011d3 | 676 | #endif /* STM32F446xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 677 | timeout = 0xFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 678 | while((tmpreg != 0) && (timeout-- > 0)) |
| sahilmgandhi | 18:6a4db94011d3 | 679 | { |
| sahilmgandhi | 18:6a4db94011d3 | 680 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| sahilmgandhi | 18:6a4db94011d3 | 681 | } |
| sahilmgandhi | 18:6a4db94011d3 | 682 | |
| sahilmgandhi | 18:6a4db94011d3 | 683 | /* Set refresh count */ |
| sahilmgandhi | 18:6a4db94011d3 | 684 | tmpreg = FMC_Bank5_6->SDRTR; |
| sahilmgandhi | 18:6a4db94011d3 | 685 | #if defined(STM32F446xx) |
| sahilmgandhi | 18:6a4db94011d3 | 686 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); |
| sahilmgandhi | 18:6a4db94011d3 | 687 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 688 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| sahilmgandhi | 18:6a4db94011d3 | 689 | #endif /* STM32F446xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 690 | |
| sahilmgandhi | 18:6a4db94011d3 | 691 | /* Disable write protection */ |
| sahilmgandhi | 18:6a4db94011d3 | 692 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| sahilmgandhi | 18:6a4db94011d3 | 693 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| sahilmgandhi | 18:6a4db94011d3 | 694 | #endif /* DATA_IN_ExtSDRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 695 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 696 | |
| sahilmgandhi | 18:6a4db94011d3 | 697 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 698 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 699 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| sahilmgandhi | 18:6a4db94011d3 | 700 | |
| sahilmgandhi | 18:6a4db94011d3 | 701 | #if defined(DATA_IN_ExtSRAM) |
| sahilmgandhi | 18:6a4db94011d3 | 702 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 703 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 704 | RCC->AHB1ENR |= 0x00000078; |
| sahilmgandhi | 18:6a4db94011d3 | 705 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 706 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); |
| sahilmgandhi | 18:6a4db94011d3 | 707 | |
| sahilmgandhi | 18:6a4db94011d3 | 708 | /* Connect PDx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 709 | GPIOD->AFR[0] = 0x00CCC0CC; |
| sahilmgandhi | 18:6a4db94011d3 | 710 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 711 | /* Configure PDx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 712 | GPIOD->MODER = 0xAAAA0A8A; |
| sahilmgandhi | 18:6a4db94011d3 | 713 | /* Configure PDx pins speed to 100 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 714 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| sahilmgandhi | 18:6a4db94011d3 | 715 | /* Configure PDx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 716 | GPIOD->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 717 | /* No pull-up, pull-down for PDx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 718 | GPIOD->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 719 | |
| sahilmgandhi | 18:6a4db94011d3 | 720 | /* Connect PEx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 721 | GPIOE->AFR[0] = 0xC00CC0CC; |
| sahilmgandhi | 18:6a4db94011d3 | 722 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 723 | /* Configure PEx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 724 | GPIOE->MODER = 0xAAAA828A; |
| sahilmgandhi | 18:6a4db94011d3 | 725 | /* Configure PEx pins speed to 100 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 726 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| sahilmgandhi | 18:6a4db94011d3 | 727 | /* Configure PEx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 728 | GPIOE->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 729 | /* No pull-up, pull-down for PEx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 730 | GPIOE->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 731 | |
| sahilmgandhi | 18:6a4db94011d3 | 732 | /* Connect PFx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 733 | GPIOF->AFR[0] = 0x00CCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 734 | GPIOF->AFR[1] = 0xCCCC0000; |
| sahilmgandhi | 18:6a4db94011d3 | 735 | /* Configure PFx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 736 | GPIOF->MODER = 0xAA000AAA; |
| sahilmgandhi | 18:6a4db94011d3 | 737 | /* Configure PFx pins speed to 100 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 738 | GPIOF->OSPEEDR = 0xFF000FFF; |
| sahilmgandhi | 18:6a4db94011d3 | 739 | /* Configure PFx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 740 | GPIOF->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 741 | /* No pull-up, pull-down for PFx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 742 | GPIOF->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 743 | |
| sahilmgandhi | 18:6a4db94011d3 | 744 | /* Connect PGx pins to FMC Alternate function */ |
| sahilmgandhi | 18:6a4db94011d3 | 745 | GPIOG->AFR[0] = 0x00CCCCCC; |
| sahilmgandhi | 18:6a4db94011d3 | 746 | GPIOG->AFR[1] = 0x000000C0; |
| sahilmgandhi | 18:6a4db94011d3 | 747 | /* Configure PGx pins in Alternate function mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 748 | GPIOG->MODER = 0x00085AAA; |
| sahilmgandhi | 18:6a4db94011d3 | 749 | /* Configure PGx pins speed to 100 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 750 | GPIOG->OSPEEDR = 0x000CAFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 751 | /* Configure PGx pins Output type to push-pull */ |
| sahilmgandhi | 18:6a4db94011d3 | 752 | GPIOG->OTYPER = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 753 | /* No pull-up, pull-down for PGx pins */ |
| sahilmgandhi | 18:6a4db94011d3 | 754 | GPIOG->PUPDR = 0x00000000; |
| sahilmgandhi | 18:6a4db94011d3 | 755 | |
| sahilmgandhi | 18:6a4db94011d3 | 756 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 757 | /* Enable the FMC/FSMC interface clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 758 | RCC->AHB3ENR |= 0x00000001; |
| sahilmgandhi | 18:6a4db94011d3 | 759 | |
| sahilmgandhi | 18:6a4db94011d3 | 760 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| sahilmgandhi | 18:6a4db94011d3 | 761 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 762 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 763 | /* Configure and enable Bank1_SRAM2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 764 | FMC_Bank1->BTCR[2] = 0x00001011; |
| sahilmgandhi | 18:6a4db94011d3 | 765 | FMC_Bank1->BTCR[3] = 0x00000201; |
| sahilmgandhi | 18:6a4db94011d3 | 766 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| sahilmgandhi | 18:6a4db94011d3 | 767 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 768 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| sahilmgandhi | 18:6a4db94011d3 | 769 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 770 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 771 | /* Configure and enable Bank1_SRAM2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 772 | FMC_Bank1->BTCR[2] = 0x00001091; |
| sahilmgandhi | 18:6a4db94011d3 | 773 | FMC_Bank1->BTCR[3] = 0x00110212; |
| sahilmgandhi | 18:6a4db94011d3 | 774 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| sahilmgandhi | 18:6a4db94011d3 | 775 | #endif /* STM32F469xx || STM32F479xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 776 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ |
| sahilmgandhi | 18:6a4db94011d3 | 777 | || defined(STM32F412Zx) || defined(STM32F412Vx) |
| sahilmgandhi | 18:6a4db94011d3 | 778 | /* Delay after an RCC peripheral clock enabling */ |
| sahilmgandhi | 18:6a4db94011d3 | 779 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); |
| sahilmgandhi | 18:6a4db94011d3 | 780 | /* Configure and enable Bank1_SRAM2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 781 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| sahilmgandhi | 18:6a4db94011d3 | 782 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| sahilmgandhi | 18:6a4db94011d3 | 783 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| sahilmgandhi | 18:6a4db94011d3 | 784 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ |
| sahilmgandhi | 18:6a4db94011d3 | 785 | |
| sahilmgandhi | 18:6a4db94011d3 | 786 | #endif /* DATA_IN_ExtSRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 787 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
| sahilmgandhi | 18:6a4db94011d3 | 788 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ |
| sahilmgandhi | 18:6a4db94011d3 | 789 | (void)(tmp); |
| sahilmgandhi | 18:6a4db94011d3 | 790 | } |
| sahilmgandhi | 18:6a4db94011d3 | 791 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| sahilmgandhi | 18:6a4db94011d3 | 792 | |
| sahilmgandhi | 18:6a4db94011d3 | 793 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 794 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| sahilmgandhi | 18:6a4db94011d3 | 795 | * AHB/APBx prescalers and Flash settings |
| sahilmgandhi | 18:6a4db94011d3 | 796 | * @note This function should be called only once the RCC clock configuration |
| sahilmgandhi | 18:6a4db94011d3 | 797 | * is reset to the default reset state (done in SystemInit() function). |
| sahilmgandhi | 18:6a4db94011d3 | 798 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 799 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 800 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 801 | void SetSysClock(void) |
| sahilmgandhi | 18:6a4db94011d3 | 802 | { |
| sahilmgandhi | 18:6a4db94011d3 | 803 | /* 1- Try to start with HSE and external clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 804 | #if USE_PLL_HSE_EXTC != 0 |
| sahilmgandhi | 18:6a4db94011d3 | 805 | if (SetSysClock_PLL_HSE(1) == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 806 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 807 | { |
| sahilmgandhi | 18:6a4db94011d3 | 808 | /* 2- If fail try to start with HSE and external xtal */ |
| sahilmgandhi | 18:6a4db94011d3 | 809 | #if USE_PLL_HSE_XTAL != 0 |
| sahilmgandhi | 18:6a4db94011d3 | 810 | if (SetSysClock_PLL_HSE(0) == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 811 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 812 | { |
| sahilmgandhi | 18:6a4db94011d3 | 813 | /* 3- If fail start with HSI clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 814 | if (SetSysClock_PLL_HSI() == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 815 | { |
| sahilmgandhi | 18:6a4db94011d3 | 816 | while(1) |
| sahilmgandhi | 18:6a4db94011d3 | 817 | { |
| sahilmgandhi | 18:6a4db94011d3 | 818 | // [TODO] Put something here to tell the user that a problem occured... |
| sahilmgandhi | 18:6a4db94011d3 | 819 | } |
| sahilmgandhi | 18:6a4db94011d3 | 820 | } |
| sahilmgandhi | 18:6a4db94011d3 | 821 | } |
| sahilmgandhi | 18:6a4db94011d3 | 822 | } |
| sahilmgandhi | 18:6a4db94011d3 | 823 | |
| sahilmgandhi | 18:6a4db94011d3 | 824 | // Output clock on MCO2 pin(PC9) for debugging purpose |
| sahilmgandhi | 18:6a4db94011d3 | 825 | #if DEBUG_MCO == 2 |
| sahilmgandhi | 18:6a4db94011d3 | 826 | HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 180/4 = 45 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 827 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 828 | } |
| sahilmgandhi | 18:6a4db94011d3 | 829 | |
| sahilmgandhi | 18:6a4db94011d3 | 830 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| sahilmgandhi | 18:6a4db94011d3 | 831 | /******************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 832 | /* PLL (clocked by HSE) used as System clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 833 | /******************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 834 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| sahilmgandhi | 18:6a4db94011d3 | 835 | { |
| sahilmgandhi | 18:6a4db94011d3 | 836 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| sahilmgandhi | 18:6a4db94011d3 | 837 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| sahilmgandhi | 18:6a4db94011d3 | 838 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; |
| sahilmgandhi | 18:6a4db94011d3 | 839 | |
| sahilmgandhi | 18:6a4db94011d3 | 840 | /* The voltage scaling allows optimizing the power consumption when the device is |
| sahilmgandhi | 18:6a4db94011d3 | 841 | clocked below the maximum system frequency, to update the voltage scaling value |
| sahilmgandhi | 18:6a4db94011d3 | 842 | regarding system frequency refer to product datasheet. */ |
| sahilmgandhi | 18:6a4db94011d3 | 843 | __HAL_RCC_PWR_CLK_ENABLE(); |
| sahilmgandhi | 18:6a4db94011d3 | 844 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| sahilmgandhi | 18:6a4db94011d3 | 845 | |
| sahilmgandhi | 18:6a4db94011d3 | 846 | // Enable HSE oscillator and activate PLL with HSE as source |
| sahilmgandhi | 18:6a4db94011d3 | 847 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| sahilmgandhi | 18:6a4db94011d3 | 848 | if (bypass == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 849 | { |
| sahilmgandhi | 18:6a4db94011d3 | 850 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
| sahilmgandhi | 18:6a4db94011d3 | 851 | } |
| sahilmgandhi | 18:6a4db94011d3 | 852 | else |
| sahilmgandhi | 18:6a4db94011d3 | 853 | { |
| sahilmgandhi | 18:6a4db94011d3 | 854 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN |
| sahilmgandhi | 18:6a4db94011d3 | 855 | } |
| sahilmgandhi | 18:6a4db94011d3 | 856 | |
| sahilmgandhi | 18:6a4db94011d3 | 857 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| sahilmgandhi | 18:6a4db94011d3 | 858 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| sahilmgandhi | 18:6a4db94011d3 | 859 | RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) |
| sahilmgandhi | 18:6a4db94011d3 | 860 | RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360) |
| sahilmgandhi | 18:6a4db94011d3 | 861 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2) |
| sahilmgandhi | 18:6a4db94011d3 | 862 | RCC_OscInitStruct.PLL.PLLQ = 7; // |
| sahilmgandhi | 18:6a4db94011d3 | 863 | RCC_OscInitStruct.PLL.PLLR = 6; // |
| sahilmgandhi | 18:6a4db94011d3 | 864 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| sahilmgandhi | 18:6a4db94011d3 | 865 | { |
| sahilmgandhi | 18:6a4db94011d3 | 866 | return 0; // FAIL |
| sahilmgandhi | 18:6a4db94011d3 | 867 | } |
| sahilmgandhi | 18:6a4db94011d3 | 868 | |
| sahilmgandhi | 18:6a4db94011d3 | 869 | // Activate the OverDrive to reach the 180 MHz Frequency |
| sahilmgandhi | 18:6a4db94011d3 | 870 | if (HAL_PWREx_ActivateOverDrive() != HAL_OK) |
| sahilmgandhi | 18:6a4db94011d3 | 871 | { |
| sahilmgandhi | 18:6a4db94011d3 | 872 | return 0; // FAIL |
| sahilmgandhi | 18:6a4db94011d3 | 873 | } |
| sahilmgandhi | 18:6a4db94011d3 | 874 | |
| sahilmgandhi | 18:6a4db94011d3 | 875 | // Select PLLSAI output as USB clock source |
| sahilmgandhi | 18:6a4db94011d3 | 876 | PeriphClkInitStruct.PLLSAI.PLLSAIM = 8; |
| sahilmgandhi | 18:6a4db94011d3 | 877 | PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; |
| sahilmgandhi | 18:6a4db94011d3 | 878 | PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8; |
| sahilmgandhi | 18:6a4db94011d3 | 879 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48; |
| sahilmgandhi | 18:6a4db94011d3 | 880 | PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLSAIP; |
| sahilmgandhi | 18:6a4db94011d3 | 881 | HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
| sahilmgandhi | 18:6a4db94011d3 | 882 | |
| sahilmgandhi | 18:6a4db94011d3 | 883 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
| sahilmgandhi | 18:6a4db94011d3 | 884 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
| sahilmgandhi | 18:6a4db94011d3 | 885 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| sahilmgandhi | 18:6a4db94011d3 | 886 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 887 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 888 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 889 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) |
| sahilmgandhi | 18:6a4db94011d3 | 890 | { |
| sahilmgandhi | 18:6a4db94011d3 | 891 | return 0; // FAIL |
| sahilmgandhi | 18:6a4db94011d3 | 892 | } |
| sahilmgandhi | 18:6a4db94011d3 | 893 | |
| sahilmgandhi | 18:6a4db94011d3 | 894 | // Output clock on MCO1 pin(PA8) for debugging purpose |
| sahilmgandhi | 18:6a4db94011d3 | 895 | #if DEBUG_MCO == 1 |
| sahilmgandhi | 18:6a4db94011d3 | 896 | if (bypass == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 897 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 16 MHz with xtal |
| sahilmgandhi | 18:6a4db94011d3 | 898 | else |
| sahilmgandhi | 18:6a4db94011d3 | 899 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz with external clock (MCO) |
| sahilmgandhi | 18:6a4db94011d3 | 900 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 901 | |
| sahilmgandhi | 18:6a4db94011d3 | 902 | return 1; // OK |
| sahilmgandhi | 18:6a4db94011d3 | 903 | } |
| sahilmgandhi | 18:6a4db94011d3 | 904 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 905 | |
| sahilmgandhi | 18:6a4db94011d3 | 906 | /******************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 907 | /* PLL (clocked by HSI) used as System clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 908 | /******************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 909 | uint8_t SetSysClock_PLL_HSI(void) |
| sahilmgandhi | 18:6a4db94011d3 | 910 | { |
| sahilmgandhi | 18:6a4db94011d3 | 911 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| sahilmgandhi | 18:6a4db94011d3 | 912 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| sahilmgandhi | 18:6a4db94011d3 | 913 | |
| sahilmgandhi | 18:6a4db94011d3 | 914 | /* The voltage scaling allows optimizing the power consumption when the device is |
| sahilmgandhi | 18:6a4db94011d3 | 915 | clocked below the maximum system frequency, to update the voltage scaling value |
| sahilmgandhi | 18:6a4db94011d3 | 916 | regarding system frequency refer to product datasheet. */ |
| sahilmgandhi | 18:6a4db94011d3 | 917 | __HAL_RCC_PWR_CLK_ENABLE(); |
| sahilmgandhi | 18:6a4db94011d3 | 918 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| sahilmgandhi | 18:6a4db94011d3 | 919 | |
| sahilmgandhi | 18:6a4db94011d3 | 920 | // Enable HSI oscillator and activate PLL with HSI as source |
| sahilmgandhi | 18:6a4db94011d3 | 921 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| sahilmgandhi | 18:6a4db94011d3 | 922 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| sahilmgandhi | 18:6a4db94011d3 | 923 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| sahilmgandhi | 18:6a4db94011d3 | 924 | RCC_OscInitStruct.HSICalibrationValue = 16; |
| sahilmgandhi | 18:6a4db94011d3 | 925 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| sahilmgandhi | 18:6a4db94011d3 | 926 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
| sahilmgandhi | 18:6a4db94011d3 | 927 | RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) |
| sahilmgandhi | 18:6a4db94011d3 | 928 | RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360) |
| sahilmgandhi | 18:6a4db94011d3 | 929 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2) |
| sahilmgandhi | 18:6a4db94011d3 | 930 | RCC_OscInitStruct.PLL.PLLQ = 7; // |
| sahilmgandhi | 18:6a4db94011d3 | 931 | RCC_OscInitStruct.PLL.PLLQ = 6; // |
| sahilmgandhi | 18:6a4db94011d3 | 932 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| sahilmgandhi | 18:6a4db94011d3 | 933 | { |
| sahilmgandhi | 18:6a4db94011d3 | 934 | return 0; // FAIL |
| sahilmgandhi | 18:6a4db94011d3 | 935 | } |
| sahilmgandhi | 18:6a4db94011d3 | 936 | |
| sahilmgandhi | 18:6a4db94011d3 | 937 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| sahilmgandhi | 18:6a4db94011d3 | 938 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| sahilmgandhi | 18:6a4db94011d3 | 939 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 940 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 941 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 942 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 943 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) |
| sahilmgandhi | 18:6a4db94011d3 | 944 | { |
| sahilmgandhi | 18:6a4db94011d3 | 945 | return 0; // FAIL |
| sahilmgandhi | 18:6a4db94011d3 | 946 | } |
| sahilmgandhi | 18:6a4db94011d3 | 947 | |
| sahilmgandhi | 18:6a4db94011d3 | 948 | // Output clock on MCO1 pin(PA8) for debugging purpose |
| sahilmgandhi | 18:6a4db94011d3 | 949 | #if DEBUG_MCO == 1 |
| sahilmgandhi | 18:6a4db94011d3 | 950 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
| sahilmgandhi | 18:6a4db94011d3 | 951 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 952 | |
| sahilmgandhi | 18:6a4db94011d3 | 953 | return 1; // OK |
| sahilmgandhi | 18:6a4db94011d3 | 954 | } |
| sahilmgandhi | 18:6a4db94011d3 | 955 | |
| sahilmgandhi | 18:6a4db94011d3 | 956 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 957 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 958 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 959 | |
| sahilmgandhi | 18:6a4db94011d3 | 960 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 961 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 962 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 963 | |
| sahilmgandhi | 18:6a4db94011d3 | 964 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 965 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 966 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 967 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |