MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f401xc.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f401xc.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 22-April-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file contains:
sahilmgandhi 18:6a4db94011d3 10 * - Data structures and the address mapping for all peripherals
sahilmgandhi 18:6a4db94011d3 11 * - peripherals registers declarations and bits definition
sahilmgandhi 18:6a4db94011d3 12 * - Macros to access peripheral's registers hardware
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 15 * @attention
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 20 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 21 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 22 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 25 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 27 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 28 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 29 *
sahilmgandhi 18:6a4db94011d3 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 40 *
sahilmgandhi 18:6a4db94011d3 41 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /** @addtogroup CMSIS
sahilmgandhi 18:6a4db94011d3 45 * @{
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /** @addtogroup stm32f401xc
sahilmgandhi 18:6a4db94011d3 49 * @{
sahilmgandhi 18:6a4db94011d3 50 */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #ifndef __STM32F401xC_H
sahilmgandhi 18:6a4db94011d3 53 #define __STM32F401xC_H
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 56 extern "C" {
sahilmgandhi 18:6a4db94011d3 57 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /** @addtogroup Configuration_section_for_CMSIS
sahilmgandhi 18:6a4db94011d3 61 * @{
sahilmgandhi 18:6a4db94011d3 62 */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**
sahilmgandhi 18:6a4db94011d3 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
sahilmgandhi 18:6a4db94011d3 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
sahilmgandhi 18:6a4db94011d3 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
sahilmgandhi 18:6a4db94011d3 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 71 #ifndef __FPU_PRESENT
sahilmgandhi 18:6a4db94011d3 72 #define __FPU_PRESENT 1U /*!< FPU present */
sahilmgandhi 18:6a4db94011d3 73 #endif /* __FPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /**
sahilmgandhi 18:6a4db94011d3 76 * @}
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /** @addtogroup Peripheral_interrupt_number_definition
sahilmgandhi 18:6a4db94011d3 80 * @{
sahilmgandhi 18:6a4db94011d3 81 */
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 /**
sahilmgandhi 18:6a4db94011d3 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
sahilmgandhi 18:6a4db94011d3 85 * in @ref Library_configuration_section
sahilmgandhi 18:6a4db94011d3 86 */
sahilmgandhi 18:6a4db94011d3 87 typedef enum
sahilmgandhi 18:6a4db94011d3 88 {
sahilmgandhi 18:6a4db94011d3 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
sahilmgandhi 18:6a4db94011d3 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
sahilmgandhi 18:6a4db94011d3 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
sahilmgandhi 18:6a4db94011d3 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
sahilmgandhi 18:6a4db94011d3 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
sahilmgandhi 18:6a4db94011d3 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
sahilmgandhi 18:6a4db94011d3 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
sahilmgandhi 18:6a4db94011d3 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
sahilmgandhi 18:6a4db94011d3 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
sahilmgandhi 18:6a4db94011d3 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
sahilmgandhi 18:6a4db94011d3 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
sahilmgandhi 18:6a4db94011d3 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
sahilmgandhi 18:6a4db94011d3 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
sahilmgandhi 18:6a4db94011d3 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
sahilmgandhi 18:6a4db94011d3 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
sahilmgandhi 18:6a4db94011d3 117 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
sahilmgandhi 18:6a4db94011d3 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
sahilmgandhi 18:6a4db94011d3 119 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
sahilmgandhi 18:6a4db94011d3 120 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
sahilmgandhi 18:6a4db94011d3 121 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
sahilmgandhi 18:6a4db94011d3 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
sahilmgandhi 18:6a4db94011d3 123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
sahilmgandhi 18:6a4db94011d3 128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
sahilmgandhi 18:6a4db94011d3 130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
sahilmgandhi 18:6a4db94011d3 135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
sahilmgandhi 18:6a4db94011d3 136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
sahilmgandhi 18:6a4db94011d3 137 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
sahilmgandhi 18:6a4db94011d3 138 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
sahilmgandhi 18:6a4db94011d3 139 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 140 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 141 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
sahilmgandhi 18:6a4db94011d3 142 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 143 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 144 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 145 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
sahilmgandhi 18:6a4db94011d3 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
sahilmgandhi 18:6a4db94011d3 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
sahilmgandhi 18:6a4db94011d3 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
sahilmgandhi 18:6a4db94011d3 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
sahilmgandhi 18:6a4db94011d3 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
sahilmgandhi 18:6a4db94011d3 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
sahilmgandhi 18:6a4db94011d3 153 FPU_IRQn = 81, /*!< FPU global interrupt */
sahilmgandhi 18:6a4db94011d3 154 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 155 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /**
sahilmgandhi 18:6a4db94011d3 158 * @}
sahilmgandhi 18:6a4db94011d3 159 */
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 162 #include "system_stm32f4xx.h"
sahilmgandhi 18:6a4db94011d3 163 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /** @addtogroup Peripheral_registers_structures
sahilmgandhi 18:6a4db94011d3 166 * @{
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 /**
sahilmgandhi 18:6a4db94011d3 170 * @brief Analog to Digital Converter
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 typedef struct
sahilmgandhi 18:6a4db94011d3 174 {
sahilmgandhi 18:6a4db94011d3 175 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 176 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 177 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 179 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 180 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 181 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 182 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 183 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 184 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 185 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 186 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 187 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 188 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 189 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
sahilmgandhi 18:6a4db94011d3 190 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 191 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 192 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 193 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 194 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 195 } ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 typedef struct
sahilmgandhi 18:6a4db94011d3 198 {
sahilmgandhi 18:6a4db94011d3 199 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
sahilmgandhi 18:6a4db94011d3 200 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
sahilmgandhi 18:6a4db94011d3 201 __IO uint32_t CDR; /*!< ADC common regular data register for dual
sahilmgandhi 18:6a4db94011d3 202 AND triple modes, Address offset: ADC1 base address + 0x308 */
sahilmgandhi 18:6a4db94011d3 203 } ADC_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /**
sahilmgandhi 18:6a4db94011d3 206 * @brief CRC calculation unit
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 typedef struct
sahilmgandhi 18:6a4db94011d3 210 {
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 212 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 213 uint8_t RESERVED0; /*!< Reserved, 0x05 */
sahilmgandhi 18:6a4db94011d3 214 uint16_t RESERVED1; /*!< Reserved, 0x06 */
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 216 } CRC_TypeDef;
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /**
sahilmgandhi 18:6a4db94011d3 219 * @brief Debug MCU
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 typedef struct
sahilmgandhi 18:6a4db94011d3 223 {
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 226 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 228 }DBGMCU_TypeDef;
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /**
sahilmgandhi 18:6a4db94011d3 232 * @brief DMA Controller
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 typedef struct
sahilmgandhi 18:6a4db94011d3 236 {
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t CR; /*!< DMA stream x configuration register */
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
sahilmgandhi 18:6a4db94011d3 240 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
sahilmgandhi 18:6a4db94011d3 241 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
sahilmgandhi 18:6a4db94011d3 242 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
sahilmgandhi 18:6a4db94011d3 243 } DMA_Stream_TypeDef;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 typedef struct
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 248 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 250 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 251 } DMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /**
sahilmgandhi 18:6a4db94011d3 255 * @brief External Interrupt/Event Controller
sahilmgandhi 18:6a4db94011d3 256 */
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 typedef struct
sahilmgandhi 18:6a4db94011d3 259 {
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 262 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 264 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 265 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 266 } EXTI_TypeDef;
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /**
sahilmgandhi 18:6a4db94011d3 269 * @brief FLASH Registers
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 typedef struct
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 276 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 281 } FLASH_TypeDef;
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /**
sahilmgandhi 18:6a4db94011d3 284 * @brief General Purpose I/O
sahilmgandhi 18:6a4db94011d3 285 */
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 typedef struct
sahilmgandhi 18:6a4db94011d3 288 {
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 290 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 292 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 293 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 295 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 296 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 297 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
sahilmgandhi 18:6a4db94011d3 298 } GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /**
sahilmgandhi 18:6a4db94011d3 301 * @brief System configuration controller
sahilmgandhi 18:6a4db94011d3 302 */
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 typedef struct
sahilmgandhi 18:6a4db94011d3 305 {
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 307 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
sahilmgandhi 18:6a4db94011d3 309 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
sahilmgandhi 18:6a4db94011d3 310 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 311 } SYSCFG_TypeDef;
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /**
sahilmgandhi 18:6a4db94011d3 314 * @brief Inter-integrated Circuit Interface
sahilmgandhi 18:6a4db94011d3 315 */
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 typedef struct
sahilmgandhi 18:6a4db94011d3 318 {
sahilmgandhi 18:6a4db94011d3 319 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 320 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 321 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 322 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 323 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 325 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 327 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 328 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 329 } I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /**
sahilmgandhi 18:6a4db94011d3 332 * @brief Independent WATCHDOG
sahilmgandhi 18:6a4db94011d3 333 */
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 typedef struct
sahilmgandhi 18:6a4db94011d3 336 {
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 338 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 339 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 340 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 341 } IWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /**
sahilmgandhi 18:6a4db94011d3 344 * @brief Power Control
sahilmgandhi 18:6a4db94011d3 345 */
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 typedef struct
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 350 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 351 } PWR_TypeDef;
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 /**
sahilmgandhi 18:6a4db94011d3 354 * @brief Reset and Clock Control
sahilmgandhi 18:6a4db94011d3 355 */
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 typedef struct
sahilmgandhi 18:6a4db94011d3 358 {
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 366 uint32_t RESERVED0; /*!< Reserved, 0x1C */
sahilmgandhi 18:6a4db94011d3 367 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 369 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
sahilmgandhi 18:6a4db94011d3 370 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 371 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 373 uint32_t RESERVED2; /*!< Reserved, 0x3C */
sahilmgandhi 18:6a4db94011d3 374 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 376 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 380 uint32_t RESERVED4; /*!< Reserved, 0x5C */
sahilmgandhi 18:6a4db94011d3 381 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 382 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 383 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 386 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
sahilmgandhi 18:6a4db94011d3 387 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 388 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 389 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 391 } RCC_TypeDef;
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 /**
sahilmgandhi 18:6a4db94011d3 394 * @brief Real-Time Clock
sahilmgandhi 18:6a4db94011d3 395 */
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 typedef struct
sahilmgandhi 18:6a4db94011d3 398 {
sahilmgandhi 18:6a4db94011d3 399 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 400 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 401 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 402 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 403 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 404 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 407 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 409 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 410 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 412 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 416 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 418 uint32_t RESERVED7; /*!< Reserved, 0x4C */
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 421 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 422 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 424 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 426 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 427 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 428 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 429 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
sahilmgandhi 18:6a4db94011d3 430 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
sahilmgandhi 18:6a4db94011d3 431 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 432 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 433 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 435 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 436 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 437 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
sahilmgandhi 18:6a4db94011d3 438 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
sahilmgandhi 18:6a4db94011d3 439 } RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /**
sahilmgandhi 18:6a4db94011d3 443 * @brief SD host Interface
sahilmgandhi 18:6a4db94011d3 444 */
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 typedef struct
sahilmgandhi 18:6a4db94011d3 447 {
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 450 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 452 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 453 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 454 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 455 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 456 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 459 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 460 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 461 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 462 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 463 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 464 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
sahilmgandhi 18:6a4db94011d3 465 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 466 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 468 } SDIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 /**
sahilmgandhi 18:6a4db94011d3 471 * @brief Serial Peripheral Interface
sahilmgandhi 18:6a4db94011d3 472 */
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 typedef struct
sahilmgandhi 18:6a4db94011d3 475 {
sahilmgandhi 18:6a4db94011d3 476 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 477 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 478 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 480 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 485 } SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /**
sahilmgandhi 18:6a4db94011d3 488 * @brief TIM
sahilmgandhi 18:6a4db94011d3 489 */
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 typedef struct
sahilmgandhi 18:6a4db94011d3 492 {
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 495 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 496 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 498 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 499 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 500 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 510 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 512 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 513 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 514 } TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 /**
sahilmgandhi 18:6a4db94011d3 517 * @brief Universal Synchronous Asynchronous Receiver Transmitter
sahilmgandhi 18:6a4db94011d3 518 */
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 typedef struct
sahilmgandhi 18:6a4db94011d3 521 {
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 526 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 527 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 528 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 529 } USART_TypeDef;
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 /**
sahilmgandhi 18:6a4db94011d3 532 * @brief Window WATCHDOG
sahilmgandhi 18:6a4db94011d3 533 */
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 typedef struct
sahilmgandhi 18:6a4db94011d3 536 {
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 538 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 539 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 540 } WWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 /**
sahilmgandhi 18:6a4db94011d3 543 * @brief __USB_OTG_Core_register
sahilmgandhi 18:6a4db94011d3 544 */
sahilmgandhi 18:6a4db94011d3 545 typedef struct
sahilmgandhi 18:6a4db94011d3 546 {
sahilmgandhi 18:6a4db94011d3 547 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
sahilmgandhi 18:6a4db94011d3 554 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
sahilmgandhi 18:6a4db94011d3 555 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
sahilmgandhi 18:6a4db94011d3 558 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
sahilmgandhi 18:6a4db94011d3 559 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
sahilmgandhi 18:6a4db94011d3 560 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
sahilmgandhi 18:6a4db94011d3 561 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
sahilmgandhi 18:6a4db94011d3 562 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
sahilmgandhi 18:6a4db94011d3 563 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
sahilmgandhi 18:6a4db94011d3 564 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
sahilmgandhi 18:6a4db94011d3 565 }
sahilmgandhi 18:6a4db94011d3 566 USB_OTG_GlobalTypeDef;
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /**
sahilmgandhi 18:6a4db94011d3 571 * @brief __device_Registers
sahilmgandhi 18:6a4db94011d3 572 */
sahilmgandhi 18:6a4db94011d3 573 typedef struct
sahilmgandhi 18:6a4db94011d3 574 {
sahilmgandhi 18:6a4db94011d3 575 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
sahilmgandhi 18:6a4db94011d3 577 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
sahilmgandhi 18:6a4db94011d3 578 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
sahilmgandhi 18:6a4db94011d3 581 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
sahilmgandhi 18:6a4db94011d3 583 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
sahilmgandhi 18:6a4db94011d3 584 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
sahilmgandhi 18:6a4db94011d3 589 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
sahilmgandhi 18:6a4db94011d3 591 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
sahilmgandhi 18:6a4db94011d3 592 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
sahilmgandhi 18:6a4db94011d3 593 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
sahilmgandhi 18:6a4db94011d3 594 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
sahilmgandhi 18:6a4db94011d3 595 }
sahilmgandhi 18:6a4db94011d3 596 USB_OTG_DeviceTypeDef;
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 /**
sahilmgandhi 18:6a4db94011d3 600 * @brief __IN_Endpoint-Specific_Register
sahilmgandhi 18:6a4db94011d3 601 */
sahilmgandhi 18:6a4db94011d3 602 typedef struct
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
sahilmgandhi 18:6a4db94011d3 605 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
sahilmgandhi 18:6a4db94011d3 607 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
sahilmgandhi 18:6a4db94011d3 608 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
sahilmgandhi 18:6a4db94011d3 611 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
sahilmgandhi 18:6a4db94011d3 612 }
sahilmgandhi 18:6a4db94011d3 613 USB_OTG_INEndpointTypeDef;
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 /**
sahilmgandhi 18:6a4db94011d3 617 * @brief __OUT_Endpoint-Specific_Registers
sahilmgandhi 18:6a4db94011d3 618 */
sahilmgandhi 18:6a4db94011d3 619 typedef struct
sahilmgandhi 18:6a4db94011d3 620 {
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
sahilmgandhi 18:6a4db94011d3 622 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
sahilmgandhi 18:6a4db94011d3 623 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
sahilmgandhi 18:6a4db94011d3 624 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
sahilmgandhi 18:6a4db94011d3 625 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
sahilmgandhi 18:6a4db94011d3 627 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629 USB_OTG_OUTEndpointTypeDef;
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632 /**
sahilmgandhi 18:6a4db94011d3 633 * @brief __Host_Mode_Register_Structures
sahilmgandhi 18:6a4db94011d3 634 */
sahilmgandhi 18:6a4db94011d3 635 typedef struct
sahilmgandhi 18:6a4db94011d3 636 {
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
sahilmgandhi 18:6a4db94011d3 639 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
sahilmgandhi 18:6a4db94011d3 640 uint32_t Reserved40C; /* Reserved 40Ch*/
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
sahilmgandhi 18:6a4db94011d3 644 }
sahilmgandhi 18:6a4db94011d3 645 USB_OTG_HostTypeDef;
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647
sahilmgandhi 18:6a4db94011d3 648 /**
sahilmgandhi 18:6a4db94011d3 649 * @brief __Host_Channel_Specific_Registers
sahilmgandhi 18:6a4db94011d3 650 */
sahilmgandhi 18:6a4db94011d3 651 typedef struct
sahilmgandhi 18:6a4db94011d3 652 {
sahilmgandhi 18:6a4db94011d3 653 __IO uint32_t HCCHAR;
sahilmgandhi 18:6a4db94011d3 654 __IO uint32_t HCSPLT;
sahilmgandhi 18:6a4db94011d3 655 __IO uint32_t HCINT;
sahilmgandhi 18:6a4db94011d3 656 __IO uint32_t HCINTMSK;
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t HCTSIZ;
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t HCDMA;
sahilmgandhi 18:6a4db94011d3 659 uint32_t Reserved[2];
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661 USB_OTG_HostChannelTypeDef;
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /**
sahilmgandhi 18:6a4db94011d3 665 * @brief Peripheral_memory_map
sahilmgandhi 18:6a4db94011d3 666 */
sahilmgandhi 18:6a4db94011d3 667 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 668 #define SRAM1_BASE 0x20000000U /*!< SRAM1(64 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 669 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
sahilmgandhi 18:6a4db94011d3 670 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 671 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 672 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 673 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 674 #define FLASH_END 0x0803FFFFU /*!< FLASH end address */
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 677 #define SRAM_BASE SRAM1_BASE
sahilmgandhi 18:6a4db94011d3 678 #define SRAM_BB_BASE SRAM1_BB_BASE
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 /*!< Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 682 #define APB1PERIPH_BASE PERIPH_BASE
sahilmgandhi 18:6a4db94011d3 683 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
sahilmgandhi 18:6a4db94011d3 684 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
sahilmgandhi 18:6a4db94011d3 685 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 /*!< APB1 peripherals */
sahilmgandhi 18:6a4db94011d3 688 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 689 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 690 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
sahilmgandhi 18:6a4db94011d3 691 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
sahilmgandhi 18:6a4db94011d3 692 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
sahilmgandhi 18:6a4db94011d3 693 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
sahilmgandhi 18:6a4db94011d3 694 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 695 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
sahilmgandhi 18:6a4db94011d3 696 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 697 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 698 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
sahilmgandhi 18:6a4db94011d3 699 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
sahilmgandhi 18:6a4db94011d3 700 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
sahilmgandhi 18:6a4db94011d3 701 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
sahilmgandhi 18:6a4db94011d3 702 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
sahilmgandhi 18:6a4db94011d3 703 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
sahilmgandhi 18:6a4db94011d3 704
sahilmgandhi 18:6a4db94011d3 705 /*!< APB2 peripherals */
sahilmgandhi 18:6a4db94011d3 706 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 707 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 708 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 709 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 710 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
sahilmgandhi 18:6a4db94011d3 711 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
sahilmgandhi 18:6a4db94011d3 712 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 713 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
sahilmgandhi 18:6a4db94011d3 714 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 715 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 716 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
sahilmgandhi 18:6a4db94011d3 717 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
sahilmgandhi 18:6a4db94011d3 718 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /*!< AHB1 peripherals */
sahilmgandhi 18:6a4db94011d3 721 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 722 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 723 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
sahilmgandhi 18:6a4db94011d3 724 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
sahilmgandhi 18:6a4db94011d3 725 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 726 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
sahilmgandhi 18:6a4db94011d3 727 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 728 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 729 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 730 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
sahilmgandhi 18:6a4db94011d3 731 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
sahilmgandhi 18:6a4db94011d3 732 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
sahilmgandhi 18:6a4db94011d3 733 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
sahilmgandhi 18:6a4db94011d3 734 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
sahilmgandhi 18:6a4db94011d3 735 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
sahilmgandhi 18:6a4db94011d3 736 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
sahilmgandhi 18:6a4db94011d3 737 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
sahilmgandhi 18:6a4db94011d3 738 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
sahilmgandhi 18:6a4db94011d3 739 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
sahilmgandhi 18:6a4db94011d3 740 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
sahilmgandhi 18:6a4db94011d3 741 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
sahilmgandhi 18:6a4db94011d3 742 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
sahilmgandhi 18:6a4db94011d3 743 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
sahilmgandhi 18:6a4db94011d3 744 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
sahilmgandhi 18:6a4db94011d3 745 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
sahilmgandhi 18:6a4db94011d3 746 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
sahilmgandhi 18:6a4db94011d3 747 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 /* Debug MCU registers base address */
sahilmgandhi 18:6a4db94011d3 750 #define DBGMCU_BASE 0xE0042000U
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 /*!< USB registers base address */
sahilmgandhi 18:6a4db94011d3 753 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 #define USB_OTG_GLOBAL_BASE 0x000U
sahilmgandhi 18:6a4db94011d3 756 #define USB_OTG_DEVICE_BASE 0x800U
sahilmgandhi 18:6a4db94011d3 757 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
sahilmgandhi 18:6a4db94011d3 758 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
sahilmgandhi 18:6a4db94011d3 759 #define USB_OTG_EP_REG_SIZE 0x20U
sahilmgandhi 18:6a4db94011d3 760 #define USB_OTG_HOST_BASE 0x400U
sahilmgandhi 18:6a4db94011d3 761 #define USB_OTG_HOST_PORT_BASE 0x440U
sahilmgandhi 18:6a4db94011d3 762 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
sahilmgandhi 18:6a4db94011d3 763 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
sahilmgandhi 18:6a4db94011d3 764 #define USB_OTG_PCGCCTL_BASE 0xE00U
sahilmgandhi 18:6a4db94011d3 765 #define USB_OTG_FIFO_BASE 0x1000U
sahilmgandhi 18:6a4db94011d3 766 #define USB_OTG_FIFO_SIZE 0x1000U
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 /**
sahilmgandhi 18:6a4db94011d3 769 * @}
sahilmgandhi 18:6a4db94011d3 770 */
sahilmgandhi 18:6a4db94011d3 771
sahilmgandhi 18:6a4db94011d3 772 /** @addtogroup Peripheral_declaration
sahilmgandhi 18:6a4db94011d3 773 * @{
sahilmgandhi 18:6a4db94011d3 774 */
sahilmgandhi 18:6a4db94011d3 775 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 776 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 777 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
sahilmgandhi 18:6a4db94011d3 778 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
sahilmgandhi 18:6a4db94011d3 779 #define RTC ((RTC_TypeDef *) RTC_BASE)
sahilmgandhi 18:6a4db94011d3 780 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
sahilmgandhi 18:6a4db94011d3 781 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
sahilmgandhi 18:6a4db94011d3 782 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
sahilmgandhi 18:6a4db94011d3 783 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 784 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
sahilmgandhi 18:6a4db94011d3 785 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
sahilmgandhi 18:6a4db94011d3 786 #define USART2 ((USART_TypeDef *) USART2_BASE)
sahilmgandhi 18:6a4db94011d3 787 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 788 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 789 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
sahilmgandhi 18:6a4db94011d3 790 #define PWR ((PWR_TypeDef *) PWR_BASE)
sahilmgandhi 18:6a4db94011d3 791 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
sahilmgandhi 18:6a4db94011d3 792 #define USART1 ((USART_TypeDef *) USART1_BASE)
sahilmgandhi 18:6a4db94011d3 793 #define USART6 ((USART_TypeDef *) USART6_BASE)
sahilmgandhi 18:6a4db94011d3 794 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
sahilmgandhi 18:6a4db94011d3 795 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 796 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
sahilmgandhi 18:6a4db94011d3 797 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 798 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
sahilmgandhi 18:6a4db94011d3 799 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
sahilmgandhi 18:6a4db94011d3 800 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
sahilmgandhi 18:6a4db94011d3 801 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
sahilmgandhi 18:6a4db94011d3 802 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
sahilmgandhi 18:6a4db94011d3 803 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
sahilmgandhi 18:6a4db94011d3 804 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
sahilmgandhi 18:6a4db94011d3 805 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
sahilmgandhi 18:6a4db94011d3 806 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 807 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
sahilmgandhi 18:6a4db94011d3 808 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
sahilmgandhi 18:6a4db94011d3 809 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
sahilmgandhi 18:6a4db94011d3 810 #define CRC ((CRC_TypeDef *) CRC_BASE)
sahilmgandhi 18:6a4db94011d3 811 #define RCC ((RCC_TypeDef *) RCC_BASE)
sahilmgandhi 18:6a4db94011d3 812 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
sahilmgandhi 18:6a4db94011d3 813 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
sahilmgandhi 18:6a4db94011d3 814 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
sahilmgandhi 18:6a4db94011d3 815 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
sahilmgandhi 18:6a4db94011d3 816 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
sahilmgandhi 18:6a4db94011d3 817 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
sahilmgandhi 18:6a4db94011d3 818 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
sahilmgandhi 18:6a4db94011d3 819 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
sahilmgandhi 18:6a4db94011d3 820 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
sahilmgandhi 18:6a4db94011d3 821 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
sahilmgandhi 18:6a4db94011d3 822 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
sahilmgandhi 18:6a4db94011d3 823 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
sahilmgandhi 18:6a4db94011d3 824 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
sahilmgandhi 18:6a4db94011d3 825 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
sahilmgandhi 18:6a4db94011d3 826 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
sahilmgandhi 18:6a4db94011d3 827 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
sahilmgandhi 18:6a4db94011d3 828 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
sahilmgandhi 18:6a4db94011d3 829 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
sahilmgandhi 18:6a4db94011d3 830 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 835
sahilmgandhi 18:6a4db94011d3 836 /**
sahilmgandhi 18:6a4db94011d3 837 * @}
sahilmgandhi 18:6a4db94011d3 838 */
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 /** @addtogroup Exported_constants
sahilmgandhi 18:6a4db94011d3 841 * @{
sahilmgandhi 18:6a4db94011d3 842 */
sahilmgandhi 18:6a4db94011d3 843
sahilmgandhi 18:6a4db94011d3 844 /** @addtogroup Peripheral_Registers_Bits_Definition
sahilmgandhi 18:6a4db94011d3 845 * @{
sahilmgandhi 18:6a4db94011d3 846 */
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 849 /* Peripheral Registers_Bits_Definition */
sahilmgandhi 18:6a4db94011d3 850 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 853 /* */
sahilmgandhi 18:6a4db94011d3 854 /* Analog to Digital Converter */
sahilmgandhi 18:6a4db94011d3 855 /* */
sahilmgandhi 18:6a4db94011d3 856 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 857 /******************** Bit definition for ADC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 858 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 859 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
sahilmgandhi 18:6a4db94011d3 860 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 861 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 862 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 863 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
sahilmgandhi 18:6a4db94011d3 864
sahilmgandhi 18:6a4db94011d3 865 /******************* Bit definition for ADC_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 866 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
sahilmgandhi 18:6a4db94011d3 867 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 868 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 869 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 870 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 871 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 872 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
sahilmgandhi 18:6a4db94011d3 873 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
sahilmgandhi 18:6a4db94011d3 874 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
sahilmgandhi 18:6a4db94011d3 875 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
sahilmgandhi 18:6a4db94011d3 876 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
sahilmgandhi 18:6a4db94011d3 877 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
sahilmgandhi 18:6a4db94011d3 878 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
sahilmgandhi 18:6a4db94011d3 879 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
sahilmgandhi 18:6a4db94011d3 880 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
sahilmgandhi 18:6a4db94011d3 881 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 882 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 883 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 884 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
sahilmgandhi 18:6a4db94011d3 885 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
sahilmgandhi 18:6a4db94011d3 886 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
sahilmgandhi 18:6a4db94011d3 887 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 888 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 889 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 890
sahilmgandhi 18:6a4db94011d3 891 /******************* Bit definition for ADC_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 892 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
sahilmgandhi 18:6a4db94011d3 893 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
sahilmgandhi 18:6a4db94011d3 894 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
sahilmgandhi 18:6a4db94011d3 895 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
sahilmgandhi 18:6a4db94011d3 896 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
sahilmgandhi 18:6a4db94011d3 897 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
sahilmgandhi 18:6a4db94011d3 898 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
sahilmgandhi 18:6a4db94011d3 899 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 900 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 901 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 902 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 903 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
sahilmgandhi 18:6a4db94011d3 904 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 905 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 906 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
sahilmgandhi 18:6a4db94011d3 907 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
sahilmgandhi 18:6a4db94011d3 908 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 909 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 910 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 911 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 912 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
sahilmgandhi 18:6a4db94011d3 913 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 914 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 915 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 /****************** Bit definition for ADC_SMPR1 register *******************/
sahilmgandhi 18:6a4db94011d3 918 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 919 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 920 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 921 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 922 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 923 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 924 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 925 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 926 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 927 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 928 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 929 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 930 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 931 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 932 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 933 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 934 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 935 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 936 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 937 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 938 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 939 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 940 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 941 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 942 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 943 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 944 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 945 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 946 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 947 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 948 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 949 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 950 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 951 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 952 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 953 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 /****************** Bit definition for ADC_SMPR2 register *******************/
sahilmgandhi 18:6a4db94011d3 956 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 957 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 958 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 959 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 960 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 961 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 962 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 963 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 964 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 965 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 966 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 967 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 968 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 969 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 970 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 971 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 972 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 973 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 974 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 975 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 976 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 977 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 978 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 979 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 980 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 981 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 982 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 983 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 984 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 985 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 986 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 987 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 988 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 989 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 990 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 991 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 992 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 993 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 994 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 995 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997 /****************** Bit definition for ADC_JOFR1 register *******************/
sahilmgandhi 18:6a4db94011d3 998 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /****************** Bit definition for ADC_JOFR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1001 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 /****************** Bit definition for ADC_JOFR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1004 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
sahilmgandhi 18:6a4db94011d3 1005
sahilmgandhi 18:6a4db94011d3 1006 /****************** Bit definition for ADC_JOFR4 register *******************/
sahilmgandhi 18:6a4db94011d3 1007 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 /******************* Bit definition for ADC_HTR register ********************/
sahilmgandhi 18:6a4db94011d3 1010 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 /******************* Bit definition for ADC_LTR register ********************/
sahilmgandhi 18:6a4db94011d3 1013 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
sahilmgandhi 18:6a4db94011d3 1014
sahilmgandhi 18:6a4db94011d3 1015 /******************* Bit definition for ADC_SQR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1016 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1017 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1018 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1019 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1020 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1021 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1022 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1023 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1024 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1025 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1026 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1027 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1028 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1029 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1030 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1031 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1032 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1033 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1034 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1035 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1036 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1037 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1038 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1039 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1040 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
sahilmgandhi 18:6a4db94011d3 1041 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1042 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1043 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1044 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1045
sahilmgandhi 18:6a4db94011d3 1046 /******************* Bit definition for ADC_SQR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1047 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1048 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1049 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1050 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1051 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1052 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1053 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1054 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1055 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1056 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1057 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1058 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1059 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1060 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1061 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1062 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1063 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1064 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1065 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1066 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1067 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1068 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1069 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1070 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1071 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1072 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1073 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1074 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1075 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1076 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1077 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1078 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1079 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1080 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1081 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1082 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1083
sahilmgandhi 18:6a4db94011d3 1084 /******************* Bit definition for ADC_SQR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1085 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1086 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1087 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1088 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1089 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1090 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1091 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1092 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1093 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1094 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1095 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1096 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1097 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1098 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1099 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1100 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1101 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1102 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1103 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1104 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1105 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1106 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1107 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1108 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1109 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1110 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1111 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1112 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1113 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1114 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1115 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1116 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1117 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1118 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1119 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1120 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122 /******************* Bit definition for ADC_JSQR register *******************/
sahilmgandhi 18:6a4db94011d3 1123 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1124 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1125 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1126 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1127 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1128 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1129 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1130 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1131 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1132 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1133 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1134 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1135 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1136 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1137 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1138 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1139 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1140 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1141 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1142 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1143 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1144 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1145 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1146 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1147 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
sahilmgandhi 18:6a4db94011d3 1148 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1149 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1150
sahilmgandhi 18:6a4db94011d3 1151 /******************* Bit definition for ADC_JDR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1152 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1153
sahilmgandhi 18:6a4db94011d3 1154 /******************* Bit definition for ADC_JDR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1155 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1156
sahilmgandhi 18:6a4db94011d3 1157 /******************* Bit definition for ADC_JDR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1158 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1159
sahilmgandhi 18:6a4db94011d3 1160 /******************* Bit definition for ADC_JDR4 register *******************/
sahilmgandhi 18:6a4db94011d3 1161 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163 /******************** Bit definition for ADC_DR register ********************/
sahilmgandhi 18:6a4db94011d3 1164 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
sahilmgandhi 18:6a4db94011d3 1165 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
sahilmgandhi 18:6a4db94011d3 1166
sahilmgandhi 18:6a4db94011d3 1167 /******************* Bit definition for ADC_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 1168 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1169 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
sahilmgandhi 18:6a4db94011d3 1170 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1171 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1172 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1173 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1174 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1175 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
sahilmgandhi 18:6a4db94011d3 1176 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1177 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1178 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1179 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1180 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1181 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
sahilmgandhi 18:6a4db94011d3 1182 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1183 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1184 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1185 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1186
sahilmgandhi 18:6a4db94011d3 1187 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 1188 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
sahilmgandhi 18:6a4db94011d3 1189 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
sahilmgandhi 18:6a4db94011d3 1190 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
sahilmgandhi 18:6a4db94011d3 1191
sahilmgandhi 18:6a4db94011d3 1192 /******************* Bit definition for ADC_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 1193 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
sahilmgandhi 18:6a4db94011d3 1194 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1195 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1196 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1197 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1198 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1199 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
sahilmgandhi 18:6a4db94011d3 1200 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1201 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1202 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1203 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1204 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
sahilmgandhi 18:6a4db94011d3 1205 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
sahilmgandhi 18:6a4db94011d3 1206 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1207 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1208 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
sahilmgandhi 18:6a4db94011d3 1209 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1210 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1211 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
sahilmgandhi 18:6a4db94011d3 1212 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
sahilmgandhi 18:6a4db94011d3 1213
sahilmgandhi 18:6a4db94011d3 1214 /******************* Bit definition for ADC_CDR register ********************/
sahilmgandhi 18:6a4db94011d3 1215 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
sahilmgandhi 18:6a4db94011d3 1216 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
sahilmgandhi 18:6a4db94011d3 1217
sahilmgandhi 18:6a4db94011d3 1218 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1219 /* */
sahilmgandhi 18:6a4db94011d3 1220 /* CRC calculation unit */
sahilmgandhi 18:6a4db94011d3 1221 /* */
sahilmgandhi 18:6a4db94011d3 1222 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1223 /******************* Bit definition for CRC_DR register *********************/
sahilmgandhi 18:6a4db94011d3 1224 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
sahilmgandhi 18:6a4db94011d3 1225
sahilmgandhi 18:6a4db94011d3 1226
sahilmgandhi 18:6a4db94011d3 1227 /******************* Bit definition for CRC_IDR register ********************/
sahilmgandhi 18:6a4db94011d3 1228 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
sahilmgandhi 18:6a4db94011d3 1229
sahilmgandhi 18:6a4db94011d3 1230
sahilmgandhi 18:6a4db94011d3 1231 /******************** Bit definition for CRC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 1232 #define CRC_CR_RESET 0x01U /*!< RESET bit */
sahilmgandhi 18:6a4db94011d3 1233
sahilmgandhi 18:6a4db94011d3 1234 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1235 /* */
sahilmgandhi 18:6a4db94011d3 1236 /* Debug MCU */
sahilmgandhi 18:6a4db94011d3 1237 /* */
sahilmgandhi 18:6a4db94011d3 1238 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1239
sahilmgandhi 18:6a4db94011d3 1240 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1241 /* */
sahilmgandhi 18:6a4db94011d3 1242 /* DMA Controller */
sahilmgandhi 18:6a4db94011d3 1243 /* */
sahilmgandhi 18:6a4db94011d3 1244 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1245 /******************** Bits definition for DMA_SxCR register *****************/
sahilmgandhi 18:6a4db94011d3 1246 #define DMA_SxCR_CHSEL 0x0E000000U
sahilmgandhi 18:6a4db94011d3 1247 #define DMA_SxCR_CHSEL_0 0x02000000U
sahilmgandhi 18:6a4db94011d3 1248 #define DMA_SxCR_CHSEL_1 0x04000000U
sahilmgandhi 18:6a4db94011d3 1249 #define DMA_SxCR_CHSEL_2 0x08000000U
sahilmgandhi 18:6a4db94011d3 1250 #define DMA_SxCR_MBURST 0x01800000U
sahilmgandhi 18:6a4db94011d3 1251 #define DMA_SxCR_MBURST_0 0x00800000U
sahilmgandhi 18:6a4db94011d3 1252 #define DMA_SxCR_MBURST_1 0x01000000U
sahilmgandhi 18:6a4db94011d3 1253 #define DMA_SxCR_PBURST 0x00600000U
sahilmgandhi 18:6a4db94011d3 1254 #define DMA_SxCR_PBURST_0 0x00200000U
sahilmgandhi 18:6a4db94011d3 1255 #define DMA_SxCR_PBURST_1 0x00400000U
sahilmgandhi 18:6a4db94011d3 1256 #define DMA_SxCR_CT 0x00080000U
sahilmgandhi 18:6a4db94011d3 1257 #define DMA_SxCR_DBM 0x00040000U
sahilmgandhi 18:6a4db94011d3 1258 #define DMA_SxCR_PL 0x00030000U
sahilmgandhi 18:6a4db94011d3 1259 #define DMA_SxCR_PL_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1260 #define DMA_SxCR_PL_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1261 #define DMA_SxCR_PINCOS 0x00008000U
sahilmgandhi 18:6a4db94011d3 1262 #define DMA_SxCR_MSIZE 0x00006000U
sahilmgandhi 18:6a4db94011d3 1263 #define DMA_SxCR_MSIZE_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 1264 #define DMA_SxCR_MSIZE_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 1265 #define DMA_SxCR_PSIZE 0x00001800U
sahilmgandhi 18:6a4db94011d3 1266 #define DMA_SxCR_PSIZE_0 0x00000800U
sahilmgandhi 18:6a4db94011d3 1267 #define DMA_SxCR_PSIZE_1 0x00001000U
sahilmgandhi 18:6a4db94011d3 1268 #define DMA_SxCR_MINC 0x00000400U
sahilmgandhi 18:6a4db94011d3 1269 #define DMA_SxCR_PINC 0x00000200U
sahilmgandhi 18:6a4db94011d3 1270 #define DMA_SxCR_CIRC 0x00000100U
sahilmgandhi 18:6a4db94011d3 1271 #define DMA_SxCR_DIR 0x000000C0U
sahilmgandhi 18:6a4db94011d3 1272 #define DMA_SxCR_DIR_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 1273 #define DMA_SxCR_DIR_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 1274 #define DMA_SxCR_PFCTRL 0x00000020U
sahilmgandhi 18:6a4db94011d3 1275 #define DMA_SxCR_TCIE 0x00000010U
sahilmgandhi 18:6a4db94011d3 1276 #define DMA_SxCR_HTIE 0x00000008U
sahilmgandhi 18:6a4db94011d3 1277 #define DMA_SxCR_TEIE 0x00000004U
sahilmgandhi 18:6a4db94011d3 1278 #define DMA_SxCR_DMEIE 0x00000002U
sahilmgandhi 18:6a4db94011d3 1279 #define DMA_SxCR_EN 0x00000001U
sahilmgandhi 18:6a4db94011d3 1280
sahilmgandhi 18:6a4db94011d3 1281 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 1282 #define DMA_SxCR_ACK 0x00100000U
sahilmgandhi 18:6a4db94011d3 1283
sahilmgandhi 18:6a4db94011d3 1284 /******************** Bits definition for DMA_SxCNDTR register **************/
sahilmgandhi 18:6a4db94011d3 1285 #define DMA_SxNDT 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 1286 #define DMA_SxNDT_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1287 #define DMA_SxNDT_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1288 #define DMA_SxNDT_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 1289 #define DMA_SxNDT_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 1290 #define DMA_SxNDT_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1291 #define DMA_SxNDT_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 1292 #define DMA_SxNDT_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 1293 #define DMA_SxNDT_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 1294 #define DMA_SxNDT_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 1295 #define DMA_SxNDT_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 1296 #define DMA_SxNDT_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 1297 #define DMA_SxNDT_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 1298 #define DMA_SxNDT_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 1299 #define DMA_SxNDT_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 1300 #define DMA_SxNDT_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 1301 #define DMA_SxNDT_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 1302
sahilmgandhi 18:6a4db94011d3 1303 /******************** Bits definition for DMA_SxFCR register ****************/
sahilmgandhi 18:6a4db94011d3 1304 #define DMA_SxFCR_FEIE 0x00000080U
sahilmgandhi 18:6a4db94011d3 1305 #define DMA_SxFCR_FS 0x00000038U
sahilmgandhi 18:6a4db94011d3 1306 #define DMA_SxFCR_FS_0 0x00000008U
sahilmgandhi 18:6a4db94011d3 1307 #define DMA_SxFCR_FS_1 0x00000010U
sahilmgandhi 18:6a4db94011d3 1308 #define DMA_SxFCR_FS_2 0x00000020U
sahilmgandhi 18:6a4db94011d3 1309 #define DMA_SxFCR_DMDIS 0x00000004U
sahilmgandhi 18:6a4db94011d3 1310 #define DMA_SxFCR_FTH 0x00000003U
sahilmgandhi 18:6a4db94011d3 1311 #define DMA_SxFCR_FTH_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1312 #define DMA_SxFCR_FTH_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1313
sahilmgandhi 18:6a4db94011d3 1314 /******************** Bits definition for DMA_LISR register *****************/
sahilmgandhi 18:6a4db94011d3 1315 #define DMA_LISR_TCIF3 0x08000000U
sahilmgandhi 18:6a4db94011d3 1316 #define DMA_LISR_HTIF3 0x04000000U
sahilmgandhi 18:6a4db94011d3 1317 #define DMA_LISR_TEIF3 0x02000000U
sahilmgandhi 18:6a4db94011d3 1318 #define DMA_LISR_DMEIF3 0x01000000U
sahilmgandhi 18:6a4db94011d3 1319 #define DMA_LISR_FEIF3 0x00400000U
sahilmgandhi 18:6a4db94011d3 1320 #define DMA_LISR_TCIF2 0x00200000U
sahilmgandhi 18:6a4db94011d3 1321 #define DMA_LISR_HTIF2 0x00100000U
sahilmgandhi 18:6a4db94011d3 1322 #define DMA_LISR_TEIF2 0x00080000U
sahilmgandhi 18:6a4db94011d3 1323 #define DMA_LISR_DMEIF2 0x00040000U
sahilmgandhi 18:6a4db94011d3 1324 #define DMA_LISR_FEIF2 0x00010000U
sahilmgandhi 18:6a4db94011d3 1325 #define DMA_LISR_TCIF1 0x00000800U
sahilmgandhi 18:6a4db94011d3 1326 #define DMA_LISR_HTIF1 0x00000400U
sahilmgandhi 18:6a4db94011d3 1327 #define DMA_LISR_TEIF1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1328 #define DMA_LISR_DMEIF1 0x00000100U
sahilmgandhi 18:6a4db94011d3 1329 #define DMA_LISR_FEIF1 0x00000040U
sahilmgandhi 18:6a4db94011d3 1330 #define DMA_LISR_TCIF0 0x00000020U
sahilmgandhi 18:6a4db94011d3 1331 #define DMA_LISR_HTIF0 0x00000010U
sahilmgandhi 18:6a4db94011d3 1332 #define DMA_LISR_TEIF0 0x00000008U
sahilmgandhi 18:6a4db94011d3 1333 #define DMA_LISR_DMEIF0 0x00000004U
sahilmgandhi 18:6a4db94011d3 1334 #define DMA_LISR_FEIF0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1335
sahilmgandhi 18:6a4db94011d3 1336 /******************** Bits definition for DMA_HISR register *****************/
sahilmgandhi 18:6a4db94011d3 1337 #define DMA_HISR_TCIF7 0x08000000U
sahilmgandhi 18:6a4db94011d3 1338 #define DMA_HISR_HTIF7 0x04000000U
sahilmgandhi 18:6a4db94011d3 1339 #define DMA_HISR_TEIF7 0x02000000U
sahilmgandhi 18:6a4db94011d3 1340 #define DMA_HISR_DMEIF7 0x01000000U
sahilmgandhi 18:6a4db94011d3 1341 #define DMA_HISR_FEIF7 0x00400000U
sahilmgandhi 18:6a4db94011d3 1342 #define DMA_HISR_TCIF6 0x00200000U
sahilmgandhi 18:6a4db94011d3 1343 #define DMA_HISR_HTIF6 0x00100000U
sahilmgandhi 18:6a4db94011d3 1344 #define DMA_HISR_TEIF6 0x00080000U
sahilmgandhi 18:6a4db94011d3 1345 #define DMA_HISR_DMEIF6 0x00040000U
sahilmgandhi 18:6a4db94011d3 1346 #define DMA_HISR_FEIF6 0x00010000U
sahilmgandhi 18:6a4db94011d3 1347 #define DMA_HISR_TCIF5 0x00000800U
sahilmgandhi 18:6a4db94011d3 1348 #define DMA_HISR_HTIF5 0x00000400U
sahilmgandhi 18:6a4db94011d3 1349 #define DMA_HISR_TEIF5 0x00000200U
sahilmgandhi 18:6a4db94011d3 1350 #define DMA_HISR_DMEIF5 0x00000100U
sahilmgandhi 18:6a4db94011d3 1351 #define DMA_HISR_FEIF5 0x00000040U
sahilmgandhi 18:6a4db94011d3 1352 #define DMA_HISR_TCIF4 0x00000020U
sahilmgandhi 18:6a4db94011d3 1353 #define DMA_HISR_HTIF4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1354 #define DMA_HISR_TEIF4 0x00000008U
sahilmgandhi 18:6a4db94011d3 1355 #define DMA_HISR_DMEIF4 0x00000004U
sahilmgandhi 18:6a4db94011d3 1356 #define DMA_HISR_FEIF4 0x00000001U
sahilmgandhi 18:6a4db94011d3 1357
sahilmgandhi 18:6a4db94011d3 1358 /******************** Bits definition for DMA_LIFCR register ****************/
sahilmgandhi 18:6a4db94011d3 1359 #define DMA_LIFCR_CTCIF3 0x08000000U
sahilmgandhi 18:6a4db94011d3 1360 #define DMA_LIFCR_CHTIF3 0x04000000U
sahilmgandhi 18:6a4db94011d3 1361 #define DMA_LIFCR_CTEIF3 0x02000000U
sahilmgandhi 18:6a4db94011d3 1362 #define DMA_LIFCR_CDMEIF3 0x01000000U
sahilmgandhi 18:6a4db94011d3 1363 #define DMA_LIFCR_CFEIF3 0x00400000U
sahilmgandhi 18:6a4db94011d3 1364 #define DMA_LIFCR_CTCIF2 0x00200000U
sahilmgandhi 18:6a4db94011d3 1365 #define DMA_LIFCR_CHTIF2 0x00100000U
sahilmgandhi 18:6a4db94011d3 1366 #define DMA_LIFCR_CTEIF2 0x00080000U
sahilmgandhi 18:6a4db94011d3 1367 #define DMA_LIFCR_CDMEIF2 0x00040000U
sahilmgandhi 18:6a4db94011d3 1368 #define DMA_LIFCR_CFEIF2 0x00010000U
sahilmgandhi 18:6a4db94011d3 1369 #define DMA_LIFCR_CTCIF1 0x00000800U
sahilmgandhi 18:6a4db94011d3 1370 #define DMA_LIFCR_CHTIF1 0x00000400U
sahilmgandhi 18:6a4db94011d3 1371 #define DMA_LIFCR_CTEIF1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1372 #define DMA_LIFCR_CDMEIF1 0x00000100U
sahilmgandhi 18:6a4db94011d3 1373 #define DMA_LIFCR_CFEIF1 0x00000040U
sahilmgandhi 18:6a4db94011d3 1374 #define DMA_LIFCR_CTCIF0 0x00000020U
sahilmgandhi 18:6a4db94011d3 1375 #define DMA_LIFCR_CHTIF0 0x00000010U
sahilmgandhi 18:6a4db94011d3 1376 #define DMA_LIFCR_CTEIF0 0x00000008U
sahilmgandhi 18:6a4db94011d3 1377 #define DMA_LIFCR_CDMEIF0 0x00000004U
sahilmgandhi 18:6a4db94011d3 1378 #define DMA_LIFCR_CFEIF0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1379
sahilmgandhi 18:6a4db94011d3 1380 /******************** Bits definition for DMA_HIFCR register ****************/
sahilmgandhi 18:6a4db94011d3 1381 #define DMA_HIFCR_CTCIF7 0x08000000U
sahilmgandhi 18:6a4db94011d3 1382 #define DMA_HIFCR_CHTIF7 0x04000000U
sahilmgandhi 18:6a4db94011d3 1383 #define DMA_HIFCR_CTEIF7 0x02000000U
sahilmgandhi 18:6a4db94011d3 1384 #define DMA_HIFCR_CDMEIF7 0x01000000U
sahilmgandhi 18:6a4db94011d3 1385 #define DMA_HIFCR_CFEIF7 0x00400000U
sahilmgandhi 18:6a4db94011d3 1386 #define DMA_HIFCR_CTCIF6 0x00200000U
sahilmgandhi 18:6a4db94011d3 1387 #define DMA_HIFCR_CHTIF6 0x00100000U
sahilmgandhi 18:6a4db94011d3 1388 #define DMA_HIFCR_CTEIF6 0x00080000U
sahilmgandhi 18:6a4db94011d3 1389 #define DMA_HIFCR_CDMEIF6 0x00040000U
sahilmgandhi 18:6a4db94011d3 1390 #define DMA_HIFCR_CFEIF6 0x00010000U
sahilmgandhi 18:6a4db94011d3 1391 #define DMA_HIFCR_CTCIF5 0x00000800U
sahilmgandhi 18:6a4db94011d3 1392 #define DMA_HIFCR_CHTIF5 0x00000400U
sahilmgandhi 18:6a4db94011d3 1393 #define DMA_HIFCR_CTEIF5 0x00000200U
sahilmgandhi 18:6a4db94011d3 1394 #define DMA_HIFCR_CDMEIF5 0x00000100U
sahilmgandhi 18:6a4db94011d3 1395 #define DMA_HIFCR_CFEIF5 0x00000040U
sahilmgandhi 18:6a4db94011d3 1396 #define DMA_HIFCR_CTCIF4 0x00000020U
sahilmgandhi 18:6a4db94011d3 1397 #define DMA_HIFCR_CHTIF4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1398 #define DMA_HIFCR_CTEIF4 0x00000008U
sahilmgandhi 18:6a4db94011d3 1399 #define DMA_HIFCR_CDMEIF4 0x00000004U
sahilmgandhi 18:6a4db94011d3 1400 #define DMA_HIFCR_CFEIF4 0x00000001U
sahilmgandhi 18:6a4db94011d3 1401
sahilmgandhi 18:6a4db94011d3 1402
sahilmgandhi 18:6a4db94011d3 1403 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1404 /* */
sahilmgandhi 18:6a4db94011d3 1405 /* External Interrupt/Event Controller */
sahilmgandhi 18:6a4db94011d3 1406 /* */
sahilmgandhi 18:6a4db94011d3 1407 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1408 /******************* Bit definition for EXTI_IMR register *******************/
sahilmgandhi 18:6a4db94011d3 1409 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 1410 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 1411 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 1412 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 1413 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 1414 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 1415 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 1416 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 1417 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 1418 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 1419 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 1420 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 1421 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 1422 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 1423 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 1424 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 1425 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 1426 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 1427 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 1428 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 1429 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 1430 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 1431 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 /******************* Bit definition for EXTI_EMR register *******************/
sahilmgandhi 18:6a4db94011d3 1434 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 1435 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 1436 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 1437 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 1438 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 1439 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 1440 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 1441 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 1442 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 1443 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 1444 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 1445 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 1446 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 1447 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 1448 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 1449 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 1450 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 1451 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 1452 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 1453 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 1454 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 1455 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 1456 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 1457
sahilmgandhi 18:6a4db94011d3 1458 /****************** Bit definition for EXTI_RTSR register *******************/
sahilmgandhi 18:6a4db94011d3 1459 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 1460 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 1461 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 1462 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 1463 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 1464 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 1465 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 1466 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 1467 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 1468 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 1469 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 1470 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 1471 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 1472 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 1473 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 1474 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 1475 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 1476 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 1477 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
sahilmgandhi 18:6a4db94011d3 1478 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 1479 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 1480 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 1481 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 1482
sahilmgandhi 18:6a4db94011d3 1483 /****************** Bit definition for EXTI_FTSR register *******************/
sahilmgandhi 18:6a4db94011d3 1484 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 1485 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 1486 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 1487 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 1488 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 1489 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 1490 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 1491 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 1492 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 1493 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 1494 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 1495 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 1496 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 1497 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 1498 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 1499 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 1500 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 1501 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 1502 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
sahilmgandhi 18:6a4db94011d3 1503 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 1504 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 1505 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 1506 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 1507
sahilmgandhi 18:6a4db94011d3 1508 /****************** Bit definition for EXTI_SWIER register ******************/
sahilmgandhi 18:6a4db94011d3 1509 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
sahilmgandhi 18:6a4db94011d3 1510 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
sahilmgandhi 18:6a4db94011d3 1511 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
sahilmgandhi 18:6a4db94011d3 1512 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
sahilmgandhi 18:6a4db94011d3 1513 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
sahilmgandhi 18:6a4db94011d3 1514 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
sahilmgandhi 18:6a4db94011d3 1515 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
sahilmgandhi 18:6a4db94011d3 1516 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
sahilmgandhi 18:6a4db94011d3 1517 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
sahilmgandhi 18:6a4db94011d3 1518 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
sahilmgandhi 18:6a4db94011d3 1519 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
sahilmgandhi 18:6a4db94011d3 1520 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
sahilmgandhi 18:6a4db94011d3 1521 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
sahilmgandhi 18:6a4db94011d3 1522 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
sahilmgandhi 18:6a4db94011d3 1523 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
sahilmgandhi 18:6a4db94011d3 1524 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
sahilmgandhi 18:6a4db94011d3 1525 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
sahilmgandhi 18:6a4db94011d3 1526 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
sahilmgandhi 18:6a4db94011d3 1527 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
sahilmgandhi 18:6a4db94011d3 1528 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
sahilmgandhi 18:6a4db94011d3 1529 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
sahilmgandhi 18:6a4db94011d3 1530 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
sahilmgandhi 18:6a4db94011d3 1531 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
sahilmgandhi 18:6a4db94011d3 1532
sahilmgandhi 18:6a4db94011d3 1533 /******************* Bit definition for EXTI_PR register ********************/
sahilmgandhi 18:6a4db94011d3 1534 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
sahilmgandhi 18:6a4db94011d3 1535 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
sahilmgandhi 18:6a4db94011d3 1536 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
sahilmgandhi 18:6a4db94011d3 1537 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
sahilmgandhi 18:6a4db94011d3 1538 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
sahilmgandhi 18:6a4db94011d3 1539 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
sahilmgandhi 18:6a4db94011d3 1540 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
sahilmgandhi 18:6a4db94011d3 1541 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
sahilmgandhi 18:6a4db94011d3 1542 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
sahilmgandhi 18:6a4db94011d3 1543 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
sahilmgandhi 18:6a4db94011d3 1544 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
sahilmgandhi 18:6a4db94011d3 1545 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
sahilmgandhi 18:6a4db94011d3 1546 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
sahilmgandhi 18:6a4db94011d3 1547 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
sahilmgandhi 18:6a4db94011d3 1548 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
sahilmgandhi 18:6a4db94011d3 1549 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
sahilmgandhi 18:6a4db94011d3 1550 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
sahilmgandhi 18:6a4db94011d3 1551 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
sahilmgandhi 18:6a4db94011d3 1552 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
sahilmgandhi 18:6a4db94011d3 1553 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
sahilmgandhi 18:6a4db94011d3 1554 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
sahilmgandhi 18:6a4db94011d3 1555 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
sahilmgandhi 18:6a4db94011d3 1556 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
sahilmgandhi 18:6a4db94011d3 1557
sahilmgandhi 18:6a4db94011d3 1558 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1559 /* */
sahilmgandhi 18:6a4db94011d3 1560 /* FLASH */
sahilmgandhi 18:6a4db94011d3 1561 /* */
sahilmgandhi 18:6a4db94011d3 1562 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1563 /******************* Bits definition for FLASH_ACR register *****************/
sahilmgandhi 18:6a4db94011d3 1564 #define FLASH_ACR_LATENCY 0x0000000FU
sahilmgandhi 18:6a4db94011d3 1565 #define FLASH_ACR_LATENCY_0WS 0x00000000U
sahilmgandhi 18:6a4db94011d3 1566 #define FLASH_ACR_LATENCY_1WS 0x00000001U
sahilmgandhi 18:6a4db94011d3 1567 #define FLASH_ACR_LATENCY_2WS 0x00000002U
sahilmgandhi 18:6a4db94011d3 1568 #define FLASH_ACR_LATENCY_3WS 0x00000003U
sahilmgandhi 18:6a4db94011d3 1569 #define FLASH_ACR_LATENCY_4WS 0x00000004U
sahilmgandhi 18:6a4db94011d3 1570 #define FLASH_ACR_LATENCY_5WS 0x00000005U
sahilmgandhi 18:6a4db94011d3 1571 #define FLASH_ACR_LATENCY_6WS 0x00000006U
sahilmgandhi 18:6a4db94011d3 1572 #define FLASH_ACR_LATENCY_7WS 0x00000007U
sahilmgandhi 18:6a4db94011d3 1573
sahilmgandhi 18:6a4db94011d3 1574 #define FLASH_ACR_PRFTEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 1575 #define FLASH_ACR_ICEN 0x00000200U
sahilmgandhi 18:6a4db94011d3 1576 #define FLASH_ACR_DCEN 0x00000400U
sahilmgandhi 18:6a4db94011d3 1577 #define FLASH_ACR_ICRST 0x00000800U
sahilmgandhi 18:6a4db94011d3 1578 #define FLASH_ACR_DCRST 0x00001000U
sahilmgandhi 18:6a4db94011d3 1579 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
sahilmgandhi 18:6a4db94011d3 1580 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
sahilmgandhi 18:6a4db94011d3 1581
sahilmgandhi 18:6a4db94011d3 1582 /******************* Bits definition for FLASH_SR register ******************/
sahilmgandhi 18:6a4db94011d3 1583 #define FLASH_SR_EOP 0x00000001U
sahilmgandhi 18:6a4db94011d3 1584 #define FLASH_SR_SOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 1585 #define FLASH_SR_WRPERR 0x00000010U
sahilmgandhi 18:6a4db94011d3 1586 #define FLASH_SR_PGAERR 0x00000020U
sahilmgandhi 18:6a4db94011d3 1587 #define FLASH_SR_PGPERR 0x00000040U
sahilmgandhi 18:6a4db94011d3 1588 #define FLASH_SR_PGSERR 0x00000080U
sahilmgandhi 18:6a4db94011d3 1589 #define FLASH_SR_BSY 0x00010000U
sahilmgandhi 18:6a4db94011d3 1590
sahilmgandhi 18:6a4db94011d3 1591 /******************* Bits definition for FLASH_CR register ******************/
sahilmgandhi 18:6a4db94011d3 1592 #define FLASH_CR_PG 0x00000001U
sahilmgandhi 18:6a4db94011d3 1593 #define FLASH_CR_SER 0x00000002U
sahilmgandhi 18:6a4db94011d3 1594 #define FLASH_CR_MER 0x00000004U
sahilmgandhi 18:6a4db94011d3 1595 #define FLASH_CR_SNB 0x000000F8U
sahilmgandhi 18:6a4db94011d3 1596 #define FLASH_CR_SNB_0 0x00000008U
sahilmgandhi 18:6a4db94011d3 1597 #define FLASH_CR_SNB_1 0x00000010U
sahilmgandhi 18:6a4db94011d3 1598 #define FLASH_CR_SNB_2 0x00000020U
sahilmgandhi 18:6a4db94011d3 1599 #define FLASH_CR_SNB_3 0x00000040U
sahilmgandhi 18:6a4db94011d3 1600 #define FLASH_CR_SNB_4 0x00000080U
sahilmgandhi 18:6a4db94011d3 1601 #define FLASH_CR_PSIZE 0x00000300U
sahilmgandhi 18:6a4db94011d3 1602 #define FLASH_CR_PSIZE_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 1603 #define FLASH_CR_PSIZE_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1604 #define FLASH_CR_STRT 0x00010000U
sahilmgandhi 18:6a4db94011d3 1605 #define FLASH_CR_EOPIE 0x01000000U
sahilmgandhi 18:6a4db94011d3 1606 #define FLASH_CR_LOCK 0x80000000U
sahilmgandhi 18:6a4db94011d3 1607
sahilmgandhi 18:6a4db94011d3 1608 /******************* Bits definition for FLASH_OPTCR register ***************/
sahilmgandhi 18:6a4db94011d3 1609 #define FLASH_OPTCR_OPTLOCK 0x00000001U
sahilmgandhi 18:6a4db94011d3 1610 #define FLASH_OPTCR_OPTSTRT 0x00000002U
sahilmgandhi 18:6a4db94011d3 1611 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 1612 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 1613 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
sahilmgandhi 18:6a4db94011d3 1614
sahilmgandhi 18:6a4db94011d3 1615 #define FLASH_OPTCR_WDG_SW 0x00000020U
sahilmgandhi 18:6a4db94011d3 1616 #define FLASH_OPTCR_nRST_STOP 0x00000040U
sahilmgandhi 18:6a4db94011d3 1617 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
sahilmgandhi 18:6a4db94011d3 1618 #define FLASH_OPTCR_RDP 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 1619 #define FLASH_OPTCR_RDP_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 1620 #define FLASH_OPTCR_RDP_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1621 #define FLASH_OPTCR_RDP_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 1622 #define FLASH_OPTCR_RDP_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 1623 #define FLASH_OPTCR_RDP_4 0x00001000U
sahilmgandhi 18:6a4db94011d3 1624 #define FLASH_OPTCR_RDP_5 0x00002000U
sahilmgandhi 18:6a4db94011d3 1625 #define FLASH_OPTCR_RDP_6 0x00004000U
sahilmgandhi 18:6a4db94011d3 1626 #define FLASH_OPTCR_RDP_7 0x00008000U
sahilmgandhi 18:6a4db94011d3 1627 #define FLASH_OPTCR_nWRP 0x0FFF0000U
sahilmgandhi 18:6a4db94011d3 1628 #define FLASH_OPTCR_nWRP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1629 #define FLASH_OPTCR_nWRP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1630 #define FLASH_OPTCR_nWRP_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 1631 #define FLASH_OPTCR_nWRP_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 1632 #define FLASH_OPTCR_nWRP_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 1633 #define FLASH_OPTCR_nWRP_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 1634 #define FLASH_OPTCR_nWRP_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 1635 #define FLASH_OPTCR_nWRP_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 1636 #define FLASH_OPTCR_nWRP_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 1637 #define FLASH_OPTCR_nWRP_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 1638 #define FLASH_OPTCR_nWRP_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 1639 #define FLASH_OPTCR_nWRP_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 1640
sahilmgandhi 18:6a4db94011d3 1641 /****************** Bits definition for FLASH_OPTCR1 register ***************/
sahilmgandhi 18:6a4db94011d3 1642 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
sahilmgandhi 18:6a4db94011d3 1643 #define FLASH_OPTCR1_nWRP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1644 #define FLASH_OPTCR1_nWRP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1645 #define FLASH_OPTCR1_nWRP_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 1646 #define FLASH_OPTCR1_nWRP_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 1647 #define FLASH_OPTCR1_nWRP_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 1648 #define FLASH_OPTCR1_nWRP_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 1649 #define FLASH_OPTCR1_nWRP_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 1650 #define FLASH_OPTCR1_nWRP_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 1651 #define FLASH_OPTCR1_nWRP_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 1652 #define FLASH_OPTCR1_nWRP_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 1653 #define FLASH_OPTCR1_nWRP_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 1654 #define FLASH_OPTCR1_nWRP_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 1655
sahilmgandhi 18:6a4db94011d3 1656 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1657 /* */
sahilmgandhi 18:6a4db94011d3 1658 /* General Purpose I/O */
sahilmgandhi 18:6a4db94011d3 1659 /* */
sahilmgandhi 18:6a4db94011d3 1660 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1661 /****************** Bits definition for GPIO_MODER register *****************/
sahilmgandhi 18:6a4db94011d3 1662 #define GPIO_MODER_MODER0 0x00000003U
sahilmgandhi 18:6a4db94011d3 1663 #define GPIO_MODER_MODER0_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1664 #define GPIO_MODER_MODER0_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1665
sahilmgandhi 18:6a4db94011d3 1666 #define GPIO_MODER_MODER1 0x0000000CU
sahilmgandhi 18:6a4db94011d3 1667 #define GPIO_MODER_MODER1_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 1668 #define GPIO_MODER_MODER1_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 1669
sahilmgandhi 18:6a4db94011d3 1670 #define GPIO_MODER_MODER2 0x00000030U
sahilmgandhi 18:6a4db94011d3 1671 #define GPIO_MODER_MODER2_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 1672 #define GPIO_MODER_MODER2_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 1673
sahilmgandhi 18:6a4db94011d3 1674 #define GPIO_MODER_MODER3 0x000000C0U
sahilmgandhi 18:6a4db94011d3 1675 #define GPIO_MODER_MODER3_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 1676 #define GPIO_MODER_MODER3_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 1677
sahilmgandhi 18:6a4db94011d3 1678 #define GPIO_MODER_MODER4 0x00000300U
sahilmgandhi 18:6a4db94011d3 1679 #define GPIO_MODER_MODER4_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 1680 #define GPIO_MODER_MODER4_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1681
sahilmgandhi 18:6a4db94011d3 1682 #define GPIO_MODER_MODER5 0x00000C00U
sahilmgandhi 18:6a4db94011d3 1683 #define GPIO_MODER_MODER5_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 1684 #define GPIO_MODER_MODER5_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 1685
sahilmgandhi 18:6a4db94011d3 1686 #define GPIO_MODER_MODER6 0x00003000U
sahilmgandhi 18:6a4db94011d3 1687 #define GPIO_MODER_MODER6_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 1688 #define GPIO_MODER_MODER6_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 1689
sahilmgandhi 18:6a4db94011d3 1690 #define GPIO_MODER_MODER7 0x0000C000U
sahilmgandhi 18:6a4db94011d3 1691 #define GPIO_MODER_MODER7_0 0x00004000U
sahilmgandhi 18:6a4db94011d3 1692 #define GPIO_MODER_MODER7_1 0x00008000U
sahilmgandhi 18:6a4db94011d3 1693
sahilmgandhi 18:6a4db94011d3 1694 #define GPIO_MODER_MODER8 0x00030000U
sahilmgandhi 18:6a4db94011d3 1695 #define GPIO_MODER_MODER8_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1696 #define GPIO_MODER_MODER8_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1697
sahilmgandhi 18:6a4db94011d3 1698 #define GPIO_MODER_MODER9 0x000C0000U
sahilmgandhi 18:6a4db94011d3 1699 #define GPIO_MODER_MODER9_0 0x00040000U
sahilmgandhi 18:6a4db94011d3 1700 #define GPIO_MODER_MODER9_1 0x00080000U
sahilmgandhi 18:6a4db94011d3 1701
sahilmgandhi 18:6a4db94011d3 1702 #define GPIO_MODER_MODER10 0x00300000U
sahilmgandhi 18:6a4db94011d3 1703 #define GPIO_MODER_MODER10_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 1704 #define GPIO_MODER_MODER10_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 1705
sahilmgandhi 18:6a4db94011d3 1706 #define GPIO_MODER_MODER11 0x00C00000U
sahilmgandhi 18:6a4db94011d3 1707 #define GPIO_MODER_MODER11_0 0x00400000U
sahilmgandhi 18:6a4db94011d3 1708 #define GPIO_MODER_MODER11_1 0x00800000U
sahilmgandhi 18:6a4db94011d3 1709
sahilmgandhi 18:6a4db94011d3 1710 #define GPIO_MODER_MODER12 0x03000000U
sahilmgandhi 18:6a4db94011d3 1711 #define GPIO_MODER_MODER12_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 1712 #define GPIO_MODER_MODER12_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 1713
sahilmgandhi 18:6a4db94011d3 1714 #define GPIO_MODER_MODER13 0x0C000000U
sahilmgandhi 18:6a4db94011d3 1715 #define GPIO_MODER_MODER13_0 0x04000000U
sahilmgandhi 18:6a4db94011d3 1716 #define GPIO_MODER_MODER13_1 0x08000000U
sahilmgandhi 18:6a4db94011d3 1717
sahilmgandhi 18:6a4db94011d3 1718 #define GPIO_MODER_MODER14 0x30000000U
sahilmgandhi 18:6a4db94011d3 1719 #define GPIO_MODER_MODER14_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 1720 #define GPIO_MODER_MODER14_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 1721
sahilmgandhi 18:6a4db94011d3 1722 #define GPIO_MODER_MODER15 0xC0000000U
sahilmgandhi 18:6a4db94011d3 1723 #define GPIO_MODER_MODER15_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 1724 #define GPIO_MODER_MODER15_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 1725
sahilmgandhi 18:6a4db94011d3 1726 /****************** Bits definition for GPIO_OTYPER register ****************/
sahilmgandhi 18:6a4db94011d3 1727 #define GPIO_OTYPER_OT_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1728 #define GPIO_OTYPER_OT_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1729 #define GPIO_OTYPER_OT_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 1730 #define GPIO_OTYPER_OT_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 1731 #define GPIO_OTYPER_OT_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1732 #define GPIO_OTYPER_OT_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 1733 #define GPIO_OTYPER_OT_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 1734 #define GPIO_OTYPER_OT_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 1735 #define GPIO_OTYPER_OT_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 1736 #define GPIO_OTYPER_OT_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 1737 #define GPIO_OTYPER_OT_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 1738 #define GPIO_OTYPER_OT_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 1739 #define GPIO_OTYPER_OT_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 1740 #define GPIO_OTYPER_OT_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 1741 #define GPIO_OTYPER_OT_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 1742 #define GPIO_OTYPER_OT_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 1743
sahilmgandhi 18:6a4db94011d3 1744 /****************** Bits definition for GPIO_OSPEEDR register ***************/
sahilmgandhi 18:6a4db94011d3 1745 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
sahilmgandhi 18:6a4db94011d3 1746 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1747 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1748
sahilmgandhi 18:6a4db94011d3 1749 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
sahilmgandhi 18:6a4db94011d3 1750 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 1751 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 1752
sahilmgandhi 18:6a4db94011d3 1753 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
sahilmgandhi 18:6a4db94011d3 1754 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 1755 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 1756
sahilmgandhi 18:6a4db94011d3 1757 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
sahilmgandhi 18:6a4db94011d3 1758 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 1759 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 1760
sahilmgandhi 18:6a4db94011d3 1761 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
sahilmgandhi 18:6a4db94011d3 1762 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 1763 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1764
sahilmgandhi 18:6a4db94011d3 1765 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
sahilmgandhi 18:6a4db94011d3 1766 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 1767 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 1768
sahilmgandhi 18:6a4db94011d3 1769 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
sahilmgandhi 18:6a4db94011d3 1770 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 1771 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 1772
sahilmgandhi 18:6a4db94011d3 1773 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
sahilmgandhi 18:6a4db94011d3 1774 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
sahilmgandhi 18:6a4db94011d3 1775 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
sahilmgandhi 18:6a4db94011d3 1776
sahilmgandhi 18:6a4db94011d3 1777 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
sahilmgandhi 18:6a4db94011d3 1778 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1779 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1780
sahilmgandhi 18:6a4db94011d3 1781 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
sahilmgandhi 18:6a4db94011d3 1782 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
sahilmgandhi 18:6a4db94011d3 1783 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
sahilmgandhi 18:6a4db94011d3 1784
sahilmgandhi 18:6a4db94011d3 1785 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
sahilmgandhi 18:6a4db94011d3 1786 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 1787 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 1788
sahilmgandhi 18:6a4db94011d3 1789 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
sahilmgandhi 18:6a4db94011d3 1790 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
sahilmgandhi 18:6a4db94011d3 1791 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
sahilmgandhi 18:6a4db94011d3 1792
sahilmgandhi 18:6a4db94011d3 1793 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
sahilmgandhi 18:6a4db94011d3 1794 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 1795 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 1796
sahilmgandhi 18:6a4db94011d3 1797 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
sahilmgandhi 18:6a4db94011d3 1798 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
sahilmgandhi 18:6a4db94011d3 1799 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
sahilmgandhi 18:6a4db94011d3 1800
sahilmgandhi 18:6a4db94011d3 1801 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
sahilmgandhi 18:6a4db94011d3 1802 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 1803 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 1804
sahilmgandhi 18:6a4db94011d3 1805 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
sahilmgandhi 18:6a4db94011d3 1806 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 1807 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 1808
sahilmgandhi 18:6a4db94011d3 1809 /****************** Bits definition for GPIO_PUPDR register *****************/
sahilmgandhi 18:6a4db94011d3 1810 #define GPIO_PUPDR_PUPDR0 0x00000003U
sahilmgandhi 18:6a4db94011d3 1811 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1812 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1813
sahilmgandhi 18:6a4db94011d3 1814 #define GPIO_PUPDR_PUPDR1 0x0000000CU
sahilmgandhi 18:6a4db94011d3 1815 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 1816 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 1817
sahilmgandhi 18:6a4db94011d3 1818 #define GPIO_PUPDR_PUPDR2 0x00000030U
sahilmgandhi 18:6a4db94011d3 1819 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 1820 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 1821
sahilmgandhi 18:6a4db94011d3 1822 #define GPIO_PUPDR_PUPDR3 0x000000C0U
sahilmgandhi 18:6a4db94011d3 1823 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 1824 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 1825
sahilmgandhi 18:6a4db94011d3 1826 #define GPIO_PUPDR_PUPDR4 0x00000300U
sahilmgandhi 18:6a4db94011d3 1827 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 1828 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 1829
sahilmgandhi 18:6a4db94011d3 1830 #define GPIO_PUPDR_PUPDR5 0x00000C00U
sahilmgandhi 18:6a4db94011d3 1831 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 1832 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 1833
sahilmgandhi 18:6a4db94011d3 1834 #define GPIO_PUPDR_PUPDR6 0x00003000U
sahilmgandhi 18:6a4db94011d3 1835 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 1836 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 1837
sahilmgandhi 18:6a4db94011d3 1838 #define GPIO_PUPDR_PUPDR7 0x0000C000U
sahilmgandhi 18:6a4db94011d3 1839 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
sahilmgandhi 18:6a4db94011d3 1840 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
sahilmgandhi 18:6a4db94011d3 1841
sahilmgandhi 18:6a4db94011d3 1842 #define GPIO_PUPDR_PUPDR8 0x00030000U
sahilmgandhi 18:6a4db94011d3 1843 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1844 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1845
sahilmgandhi 18:6a4db94011d3 1846 #define GPIO_PUPDR_PUPDR9 0x000C0000U
sahilmgandhi 18:6a4db94011d3 1847 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
sahilmgandhi 18:6a4db94011d3 1848 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
sahilmgandhi 18:6a4db94011d3 1849
sahilmgandhi 18:6a4db94011d3 1850 #define GPIO_PUPDR_PUPDR10 0x00300000U
sahilmgandhi 18:6a4db94011d3 1851 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 1852 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 1853
sahilmgandhi 18:6a4db94011d3 1854 #define GPIO_PUPDR_PUPDR11 0x00C00000U
sahilmgandhi 18:6a4db94011d3 1855 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
sahilmgandhi 18:6a4db94011d3 1856 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
sahilmgandhi 18:6a4db94011d3 1857
sahilmgandhi 18:6a4db94011d3 1858 #define GPIO_PUPDR_PUPDR12 0x03000000U
sahilmgandhi 18:6a4db94011d3 1859 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 1860 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 1861
sahilmgandhi 18:6a4db94011d3 1862 #define GPIO_PUPDR_PUPDR13 0x0C000000U
sahilmgandhi 18:6a4db94011d3 1863 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
sahilmgandhi 18:6a4db94011d3 1864 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
sahilmgandhi 18:6a4db94011d3 1865
sahilmgandhi 18:6a4db94011d3 1866 #define GPIO_PUPDR_PUPDR14 0x30000000U
sahilmgandhi 18:6a4db94011d3 1867 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 1868 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 1869
sahilmgandhi 18:6a4db94011d3 1870 #define GPIO_PUPDR_PUPDR15 0xC0000000U
sahilmgandhi 18:6a4db94011d3 1871 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 1872 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 1873
sahilmgandhi 18:6a4db94011d3 1874 /****************** Bits definition for GPIO_IDR register *******************/
sahilmgandhi 18:6a4db94011d3 1875 #define GPIO_IDR_IDR_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1876 #define GPIO_IDR_IDR_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1877 #define GPIO_IDR_IDR_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 1878 #define GPIO_IDR_IDR_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 1879 #define GPIO_IDR_IDR_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1880 #define GPIO_IDR_IDR_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 1881 #define GPIO_IDR_IDR_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 1882 #define GPIO_IDR_IDR_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 1883 #define GPIO_IDR_IDR_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 1884 #define GPIO_IDR_IDR_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 1885 #define GPIO_IDR_IDR_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 1886 #define GPIO_IDR_IDR_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 1887 #define GPIO_IDR_IDR_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 1888 #define GPIO_IDR_IDR_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 1889 #define GPIO_IDR_IDR_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 1890 #define GPIO_IDR_IDR_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 1891 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 1892 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
sahilmgandhi 18:6a4db94011d3 1893 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
sahilmgandhi 18:6a4db94011d3 1894 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
sahilmgandhi 18:6a4db94011d3 1895 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
sahilmgandhi 18:6a4db94011d3 1896 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
sahilmgandhi 18:6a4db94011d3 1897 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
sahilmgandhi 18:6a4db94011d3 1898 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
sahilmgandhi 18:6a4db94011d3 1899 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
sahilmgandhi 18:6a4db94011d3 1900 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
sahilmgandhi 18:6a4db94011d3 1901 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
sahilmgandhi 18:6a4db94011d3 1902 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
sahilmgandhi 18:6a4db94011d3 1903 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
sahilmgandhi 18:6a4db94011d3 1904 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
sahilmgandhi 18:6a4db94011d3 1905 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
sahilmgandhi 18:6a4db94011d3 1906 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
sahilmgandhi 18:6a4db94011d3 1907 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
sahilmgandhi 18:6a4db94011d3 1908
sahilmgandhi 18:6a4db94011d3 1909 /****************** Bits definition for GPIO_ODR register *******************/
sahilmgandhi 18:6a4db94011d3 1910 #define GPIO_ODR_ODR_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1911 #define GPIO_ODR_ODR_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1912 #define GPIO_ODR_ODR_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 1913 #define GPIO_ODR_ODR_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 1914 #define GPIO_ODR_ODR_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1915 #define GPIO_ODR_ODR_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 1916 #define GPIO_ODR_ODR_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 1917 #define GPIO_ODR_ODR_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 1918 #define GPIO_ODR_ODR_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 1919 #define GPIO_ODR_ODR_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 1920 #define GPIO_ODR_ODR_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 1921 #define GPIO_ODR_ODR_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 1922 #define GPIO_ODR_ODR_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 1923 #define GPIO_ODR_ODR_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 1924 #define GPIO_ODR_ODR_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 1925 #define GPIO_ODR_ODR_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 1926 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 1927 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
sahilmgandhi 18:6a4db94011d3 1928 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
sahilmgandhi 18:6a4db94011d3 1929 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
sahilmgandhi 18:6a4db94011d3 1930 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
sahilmgandhi 18:6a4db94011d3 1931 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
sahilmgandhi 18:6a4db94011d3 1932 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
sahilmgandhi 18:6a4db94011d3 1933 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
sahilmgandhi 18:6a4db94011d3 1934 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
sahilmgandhi 18:6a4db94011d3 1935 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
sahilmgandhi 18:6a4db94011d3 1936 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
sahilmgandhi 18:6a4db94011d3 1937 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
sahilmgandhi 18:6a4db94011d3 1938 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
sahilmgandhi 18:6a4db94011d3 1939 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
sahilmgandhi 18:6a4db94011d3 1940 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
sahilmgandhi 18:6a4db94011d3 1941 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
sahilmgandhi 18:6a4db94011d3 1942 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
sahilmgandhi 18:6a4db94011d3 1943
sahilmgandhi 18:6a4db94011d3 1944 /****************** Bits definition for GPIO_BSRR register ******************/
sahilmgandhi 18:6a4db94011d3 1945 #define GPIO_BSRR_BS_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1946 #define GPIO_BSRR_BS_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1947 #define GPIO_BSRR_BS_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 1948 #define GPIO_BSRR_BS_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 1949 #define GPIO_BSRR_BS_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1950 #define GPIO_BSRR_BS_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 1951 #define GPIO_BSRR_BS_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 1952 #define GPIO_BSRR_BS_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 1953 #define GPIO_BSRR_BS_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 1954 #define GPIO_BSRR_BS_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 1955 #define GPIO_BSRR_BS_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 1956 #define GPIO_BSRR_BS_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 1957 #define GPIO_BSRR_BS_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 1958 #define GPIO_BSRR_BS_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 1959 #define GPIO_BSRR_BS_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 1960 #define GPIO_BSRR_BS_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 1961 #define GPIO_BSRR_BR_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 1962 #define GPIO_BSRR_BR_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 1963 #define GPIO_BSRR_BR_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 1964 #define GPIO_BSRR_BR_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 1965 #define GPIO_BSRR_BR_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 1966 #define GPIO_BSRR_BR_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 1967 #define GPIO_BSRR_BR_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 1968 #define GPIO_BSRR_BR_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 1969 #define GPIO_BSRR_BR_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 1970 #define GPIO_BSRR_BR_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 1971 #define GPIO_BSRR_BR_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 1972 #define GPIO_BSRR_BR_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 1973 #define GPIO_BSRR_BR_12 0x10000000U
sahilmgandhi 18:6a4db94011d3 1974 #define GPIO_BSRR_BR_13 0x20000000U
sahilmgandhi 18:6a4db94011d3 1975 #define GPIO_BSRR_BR_14 0x40000000U
sahilmgandhi 18:6a4db94011d3 1976 #define GPIO_BSRR_BR_15 0x80000000U
sahilmgandhi 18:6a4db94011d3 1977
sahilmgandhi 18:6a4db94011d3 1978 /****************** Bit definition for GPIO_LCKR register *********************/
sahilmgandhi 18:6a4db94011d3 1979 #define GPIO_LCKR_LCK0 0x00000001U
sahilmgandhi 18:6a4db94011d3 1980 #define GPIO_LCKR_LCK1 0x00000002U
sahilmgandhi 18:6a4db94011d3 1981 #define GPIO_LCKR_LCK2 0x00000004U
sahilmgandhi 18:6a4db94011d3 1982 #define GPIO_LCKR_LCK3 0x00000008U
sahilmgandhi 18:6a4db94011d3 1983 #define GPIO_LCKR_LCK4 0x00000010U
sahilmgandhi 18:6a4db94011d3 1984 #define GPIO_LCKR_LCK5 0x00000020U
sahilmgandhi 18:6a4db94011d3 1985 #define GPIO_LCKR_LCK6 0x00000040U
sahilmgandhi 18:6a4db94011d3 1986 #define GPIO_LCKR_LCK7 0x00000080U
sahilmgandhi 18:6a4db94011d3 1987 #define GPIO_LCKR_LCK8 0x00000100U
sahilmgandhi 18:6a4db94011d3 1988 #define GPIO_LCKR_LCK9 0x00000200U
sahilmgandhi 18:6a4db94011d3 1989 #define GPIO_LCKR_LCK10 0x00000400U
sahilmgandhi 18:6a4db94011d3 1990 #define GPIO_LCKR_LCK11 0x00000800U
sahilmgandhi 18:6a4db94011d3 1991 #define GPIO_LCKR_LCK12 0x00001000U
sahilmgandhi 18:6a4db94011d3 1992 #define GPIO_LCKR_LCK13 0x00002000U
sahilmgandhi 18:6a4db94011d3 1993 #define GPIO_LCKR_LCK14 0x00004000U
sahilmgandhi 18:6a4db94011d3 1994 #define GPIO_LCKR_LCK15 0x00008000U
sahilmgandhi 18:6a4db94011d3 1995 #define GPIO_LCKR_LCKK 0x00010000U
sahilmgandhi 18:6a4db94011d3 1996
sahilmgandhi 18:6a4db94011d3 1997 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1998 /* */
sahilmgandhi 18:6a4db94011d3 1999 /* Inter-integrated Circuit Interface */
sahilmgandhi 18:6a4db94011d3 2000 /* */
sahilmgandhi 18:6a4db94011d3 2001 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2002 /******************* Bit definition for I2C_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 2003 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
sahilmgandhi 18:6a4db94011d3 2004 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
sahilmgandhi 18:6a4db94011d3 2005 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
sahilmgandhi 18:6a4db94011d3 2006 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
sahilmgandhi 18:6a4db94011d3 2007 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
sahilmgandhi 18:6a4db94011d3 2008 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
sahilmgandhi 18:6a4db94011d3 2009 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2010 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
sahilmgandhi 18:6a4db94011d3 2011 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
sahilmgandhi 18:6a4db94011d3 2012 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
sahilmgandhi 18:6a4db94011d3 2013 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
sahilmgandhi 18:6a4db94011d3 2014 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
sahilmgandhi 18:6a4db94011d3 2015 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
sahilmgandhi 18:6a4db94011d3 2016 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
sahilmgandhi 18:6a4db94011d3 2017
sahilmgandhi 18:6a4db94011d3 2018 /******************* Bit definition for I2C_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 2019 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
sahilmgandhi 18:6a4db94011d3 2020 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2021 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2022 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2023 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2024 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 2025 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 2026
sahilmgandhi 18:6a4db94011d3 2027 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2028 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2029 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2030 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
sahilmgandhi 18:6a4db94011d3 2031 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
sahilmgandhi 18:6a4db94011d3 2032
sahilmgandhi 18:6a4db94011d3 2033 /******************* Bit definition for I2C_OAR1 register *******************/
sahilmgandhi 18:6a4db94011d3 2034 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
sahilmgandhi 18:6a4db94011d3 2035 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
sahilmgandhi 18:6a4db94011d3 2036
sahilmgandhi 18:6a4db94011d3 2037 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2038 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2039 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2040 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2041 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 2042 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 2043 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 2044 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 2045 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 2046 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
sahilmgandhi 18:6a4db94011d3 2047
sahilmgandhi 18:6a4db94011d3 2048 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2049
sahilmgandhi 18:6a4db94011d3 2050 /******************* Bit definition for I2C_OAR2 register *******************/
sahilmgandhi 18:6a4db94011d3 2051 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
sahilmgandhi 18:6a4db94011d3 2052 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
sahilmgandhi 18:6a4db94011d3 2053
sahilmgandhi 18:6a4db94011d3 2054 /******************** Bit definition for I2C_DR register ********************/
sahilmgandhi 18:6a4db94011d3 2055 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
sahilmgandhi 18:6a4db94011d3 2056
sahilmgandhi 18:6a4db94011d3 2057 /******************* Bit definition for I2C_SR1 register ********************/
sahilmgandhi 18:6a4db94011d3 2058 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
sahilmgandhi 18:6a4db94011d3 2059 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
sahilmgandhi 18:6a4db94011d3 2060 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
sahilmgandhi 18:6a4db94011d3 2061 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
sahilmgandhi 18:6a4db94011d3 2062 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2063 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
sahilmgandhi 18:6a4db94011d3 2064 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
sahilmgandhi 18:6a4db94011d3 2065 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
sahilmgandhi 18:6a4db94011d3 2066 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
sahilmgandhi 18:6a4db94011d3 2067 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
sahilmgandhi 18:6a4db94011d3 2068 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
sahilmgandhi 18:6a4db94011d3 2069 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
sahilmgandhi 18:6a4db94011d3 2070 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
sahilmgandhi 18:6a4db94011d3 2071 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
sahilmgandhi 18:6a4db94011d3 2072
sahilmgandhi 18:6a4db94011d3 2073 /******************* Bit definition for I2C_SR2 register ********************/
sahilmgandhi 18:6a4db94011d3 2074 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
sahilmgandhi 18:6a4db94011d3 2075 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
sahilmgandhi 18:6a4db94011d3 2076 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
sahilmgandhi 18:6a4db94011d3 2077 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2078 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2079 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2080 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
sahilmgandhi 18:6a4db94011d3 2081 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
sahilmgandhi 18:6a4db94011d3 2082
sahilmgandhi 18:6a4db94011d3 2083 /******************* Bit definition for I2C_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 2084 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
sahilmgandhi 18:6a4db94011d3 2085 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
sahilmgandhi 18:6a4db94011d3 2086 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
sahilmgandhi 18:6a4db94011d3 2087
sahilmgandhi 18:6a4db94011d3 2088 /****************** Bit definition for I2C_TRISE register *******************/
sahilmgandhi 18:6a4db94011d3 2089 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
sahilmgandhi 18:6a4db94011d3 2090
sahilmgandhi 18:6a4db94011d3 2091 /****************** Bit definition for I2C_FLTR register *******************/
sahilmgandhi 18:6a4db94011d3 2092 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
sahilmgandhi 18:6a4db94011d3 2093 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
sahilmgandhi 18:6a4db94011d3 2094
sahilmgandhi 18:6a4db94011d3 2095 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2096 /* */
sahilmgandhi 18:6a4db94011d3 2097 /* Independent WATCHDOG */
sahilmgandhi 18:6a4db94011d3 2098 /* */
sahilmgandhi 18:6a4db94011d3 2099 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2100 /******************* Bit definition for IWDG_KR register ********************/
sahilmgandhi 18:6a4db94011d3 2101 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
sahilmgandhi 18:6a4db94011d3 2102
sahilmgandhi 18:6a4db94011d3 2103 /******************* Bit definition for IWDG_PR register ********************/
sahilmgandhi 18:6a4db94011d3 2104 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
sahilmgandhi 18:6a4db94011d3 2105 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2106 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2107 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2108
sahilmgandhi 18:6a4db94011d3 2109 /******************* Bit definition for IWDG_RLR register *******************/
sahilmgandhi 18:6a4db94011d3 2110 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
sahilmgandhi 18:6a4db94011d3 2111
sahilmgandhi 18:6a4db94011d3 2112 /******************* Bit definition for IWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 2113 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
sahilmgandhi 18:6a4db94011d3 2114 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
sahilmgandhi 18:6a4db94011d3 2115
sahilmgandhi 18:6a4db94011d3 2116
sahilmgandhi 18:6a4db94011d3 2117 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2118 /* */
sahilmgandhi 18:6a4db94011d3 2119 /* Power Control */
sahilmgandhi 18:6a4db94011d3 2120 /* */
sahilmgandhi 18:6a4db94011d3 2121 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2122 /******************** Bit definition for PWR_CR register ********************/
sahilmgandhi 18:6a4db94011d3 2123 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
sahilmgandhi 18:6a4db94011d3 2124 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
sahilmgandhi 18:6a4db94011d3 2125 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 2126 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
sahilmgandhi 18:6a4db94011d3 2127 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
sahilmgandhi 18:6a4db94011d3 2128
sahilmgandhi 18:6a4db94011d3 2129 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
sahilmgandhi 18:6a4db94011d3 2130 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2131 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2132 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 2133
sahilmgandhi 18:6a4db94011d3 2134 /*!< PVD level configuration */
sahilmgandhi 18:6a4db94011d3 2135 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
sahilmgandhi 18:6a4db94011d3 2136 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
sahilmgandhi 18:6a4db94011d3 2137 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
sahilmgandhi 18:6a4db94011d3 2138 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
sahilmgandhi 18:6a4db94011d3 2139 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
sahilmgandhi 18:6a4db94011d3 2140 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
sahilmgandhi 18:6a4db94011d3 2141 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
sahilmgandhi 18:6a4db94011d3 2142 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
sahilmgandhi 18:6a4db94011d3 2143
sahilmgandhi 18:6a4db94011d3 2144 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
sahilmgandhi 18:6a4db94011d3 2145 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
sahilmgandhi 18:6a4db94011d3 2146 #define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
sahilmgandhi 18:6a4db94011d3 2147 #define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
sahilmgandhi 18:6a4db94011d3 2148 #define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 2149 #define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
sahilmgandhi 18:6a4db94011d3 2150 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2151 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2152
sahilmgandhi 18:6a4db94011d3 2153 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 2154 #define PWR_CR_PMODE PWR_CR_VOS
sahilmgandhi 18:6a4db94011d3 2155
sahilmgandhi 18:6a4db94011d3 2156 /******************* Bit definition for PWR_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 2157 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 2158 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
sahilmgandhi 18:6a4db94011d3 2159 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
sahilmgandhi 18:6a4db94011d3 2160 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
sahilmgandhi 18:6a4db94011d3 2161 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
sahilmgandhi 18:6a4db94011d3 2162 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
sahilmgandhi 18:6a4db94011d3 2163 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
sahilmgandhi 18:6a4db94011d3 2164
sahilmgandhi 18:6a4db94011d3 2165 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 2166 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
sahilmgandhi 18:6a4db94011d3 2167
sahilmgandhi 18:6a4db94011d3 2168 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2169 /* */
sahilmgandhi 18:6a4db94011d3 2170 /* Reset and Clock Control */
sahilmgandhi 18:6a4db94011d3 2171 /* */
sahilmgandhi 18:6a4db94011d3 2172 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2173 /******************** Bit definition for RCC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 2174 #define RCC_CR_HSION 0x00000001U
sahilmgandhi 18:6a4db94011d3 2175 #define RCC_CR_HSIRDY 0x00000002U
sahilmgandhi 18:6a4db94011d3 2176
sahilmgandhi 18:6a4db94011d3 2177 #define RCC_CR_HSITRIM 0x000000F8U
sahilmgandhi 18:6a4db94011d3 2178 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2179 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2180 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2181 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2182 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 2183
sahilmgandhi 18:6a4db94011d3 2184 #define RCC_CR_HSICAL 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 2185 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2186 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2187 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2188 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2189 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 2190 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 2191 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 2192 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 2193
sahilmgandhi 18:6a4db94011d3 2194 #define RCC_CR_HSEON 0x00010000U
sahilmgandhi 18:6a4db94011d3 2195 #define RCC_CR_HSERDY 0x00020000U
sahilmgandhi 18:6a4db94011d3 2196 #define RCC_CR_HSEBYP 0x00040000U
sahilmgandhi 18:6a4db94011d3 2197 #define RCC_CR_CSSON 0x00080000U
sahilmgandhi 18:6a4db94011d3 2198 #define RCC_CR_PLLON 0x01000000U
sahilmgandhi 18:6a4db94011d3 2199 #define RCC_CR_PLLRDY 0x02000000U
sahilmgandhi 18:6a4db94011d3 2200 #define RCC_CR_PLLI2SON 0x04000000U
sahilmgandhi 18:6a4db94011d3 2201 #define RCC_CR_PLLI2SRDY 0x08000000U
sahilmgandhi 18:6a4db94011d3 2202
sahilmgandhi 18:6a4db94011d3 2203 /******************** Bit definition for RCC_PLLCFGR register ***************/
sahilmgandhi 18:6a4db94011d3 2204 #define RCC_PLLCFGR_PLLM 0x0000003FU
sahilmgandhi 18:6a4db94011d3 2205 #define RCC_PLLCFGR_PLLM_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2206 #define RCC_PLLCFGR_PLLM_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2207 #define RCC_PLLCFGR_PLLM_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2208 #define RCC_PLLCFGR_PLLM_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2209 #define RCC_PLLCFGR_PLLM_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 2210 #define RCC_PLLCFGR_PLLM_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 2211
sahilmgandhi 18:6a4db94011d3 2212 #define RCC_PLLCFGR_PLLN 0x00007FC0U
sahilmgandhi 18:6a4db94011d3 2213 #define RCC_PLLCFGR_PLLN_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 2214 #define RCC_PLLCFGR_PLLN_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 2215 #define RCC_PLLCFGR_PLLN_2 0x00000100U
sahilmgandhi 18:6a4db94011d3 2216 #define RCC_PLLCFGR_PLLN_3 0x00000200U
sahilmgandhi 18:6a4db94011d3 2217 #define RCC_PLLCFGR_PLLN_4 0x00000400U
sahilmgandhi 18:6a4db94011d3 2218 #define RCC_PLLCFGR_PLLN_5 0x00000800U
sahilmgandhi 18:6a4db94011d3 2219 #define RCC_PLLCFGR_PLLN_6 0x00001000U
sahilmgandhi 18:6a4db94011d3 2220 #define RCC_PLLCFGR_PLLN_7 0x00002000U
sahilmgandhi 18:6a4db94011d3 2221 #define RCC_PLLCFGR_PLLN_8 0x00004000U
sahilmgandhi 18:6a4db94011d3 2222
sahilmgandhi 18:6a4db94011d3 2223 #define RCC_PLLCFGR_PLLP 0x00030000U
sahilmgandhi 18:6a4db94011d3 2224 #define RCC_PLLCFGR_PLLP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2225 #define RCC_PLLCFGR_PLLP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2226
sahilmgandhi 18:6a4db94011d3 2227 #define RCC_PLLCFGR_PLLSRC 0x00400000U
sahilmgandhi 18:6a4db94011d3 2228 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
sahilmgandhi 18:6a4db94011d3 2229 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
sahilmgandhi 18:6a4db94011d3 2230
sahilmgandhi 18:6a4db94011d3 2231 #define RCC_PLLCFGR_PLLQ 0x0F000000U
sahilmgandhi 18:6a4db94011d3 2232 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 2233 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 2234 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 2235 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 2236
sahilmgandhi 18:6a4db94011d3 2237 /******************** Bit definition for RCC_CFGR register ******************/
sahilmgandhi 18:6a4db94011d3 2238 /*!< SW configuration */
sahilmgandhi 18:6a4db94011d3 2239 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
sahilmgandhi 18:6a4db94011d3 2240 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2241 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2242
sahilmgandhi 18:6a4db94011d3 2243 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
sahilmgandhi 18:6a4db94011d3 2244 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
sahilmgandhi 18:6a4db94011d3 2245 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
sahilmgandhi 18:6a4db94011d3 2246
sahilmgandhi 18:6a4db94011d3 2247 /*!< SWS configuration */
sahilmgandhi 18:6a4db94011d3 2248 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
sahilmgandhi 18:6a4db94011d3 2249 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2250 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2251
sahilmgandhi 18:6a4db94011d3 2252 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 2253 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 2254 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 2255
sahilmgandhi 18:6a4db94011d3 2256 /*!< HPRE configuration */
sahilmgandhi 18:6a4db94011d3 2257 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
sahilmgandhi 18:6a4db94011d3 2258 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2259 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2260 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 2261 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
sahilmgandhi 18:6a4db94011d3 2262
sahilmgandhi 18:6a4db94011d3 2263 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
sahilmgandhi 18:6a4db94011d3 2264 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 2265 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 2266 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 2267 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 2268 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
sahilmgandhi 18:6a4db94011d3 2269 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
sahilmgandhi 18:6a4db94011d3 2270 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
sahilmgandhi 18:6a4db94011d3 2271 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
sahilmgandhi 18:6a4db94011d3 2272
sahilmgandhi 18:6a4db94011d3 2273 /*!< PPRE1 configuration */
sahilmgandhi 18:6a4db94011d3 2274 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
sahilmgandhi 18:6a4db94011d3 2275 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2276 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2277 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 2278
sahilmgandhi 18:6a4db94011d3 2279 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 2280 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 2281 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 2282 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 2283 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 2284
sahilmgandhi 18:6a4db94011d3 2285 /*!< PPRE2 configuration */
sahilmgandhi 18:6a4db94011d3 2286 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
sahilmgandhi 18:6a4db94011d3 2287 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2288 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2289 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 2290
sahilmgandhi 18:6a4db94011d3 2291 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 2292 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 2293 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 2294 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 2295 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 2296
sahilmgandhi 18:6a4db94011d3 2297 /*!< RTCPRE configuration */
sahilmgandhi 18:6a4db94011d3 2298 #define RCC_CFGR_RTCPRE 0x001F0000U
sahilmgandhi 18:6a4db94011d3 2299 #define RCC_CFGR_RTCPRE_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2300 #define RCC_CFGR_RTCPRE_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2301 #define RCC_CFGR_RTCPRE_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 2302 #define RCC_CFGR_RTCPRE_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 2303 #define RCC_CFGR_RTCPRE_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 2304
sahilmgandhi 18:6a4db94011d3 2305 /*!< MCO1 configuration */
sahilmgandhi 18:6a4db94011d3 2306 #define RCC_CFGR_MCO1 0x00600000U
sahilmgandhi 18:6a4db94011d3 2307 #define RCC_CFGR_MCO1_0 0x00200000U
sahilmgandhi 18:6a4db94011d3 2308 #define RCC_CFGR_MCO1_1 0x00400000U
sahilmgandhi 18:6a4db94011d3 2309
sahilmgandhi 18:6a4db94011d3 2310 #define RCC_CFGR_I2SSRC 0x00800000U
sahilmgandhi 18:6a4db94011d3 2311
sahilmgandhi 18:6a4db94011d3 2312 #define RCC_CFGR_MCO1PRE 0x07000000U
sahilmgandhi 18:6a4db94011d3 2313 #define RCC_CFGR_MCO1PRE_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 2314 #define RCC_CFGR_MCO1PRE_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 2315 #define RCC_CFGR_MCO1PRE_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 2316
sahilmgandhi 18:6a4db94011d3 2317 #define RCC_CFGR_MCO2PRE 0x38000000U
sahilmgandhi 18:6a4db94011d3 2318 #define RCC_CFGR_MCO2PRE_0 0x08000000U
sahilmgandhi 18:6a4db94011d3 2319 #define RCC_CFGR_MCO2PRE_1 0x10000000U
sahilmgandhi 18:6a4db94011d3 2320 #define RCC_CFGR_MCO2PRE_2 0x20000000U
sahilmgandhi 18:6a4db94011d3 2321
sahilmgandhi 18:6a4db94011d3 2322 #define RCC_CFGR_MCO2 0xC0000000U
sahilmgandhi 18:6a4db94011d3 2323 #define RCC_CFGR_MCO2_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 2324 #define RCC_CFGR_MCO2_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 2325
sahilmgandhi 18:6a4db94011d3 2326 /******************** Bit definition for RCC_CIR register *******************/
sahilmgandhi 18:6a4db94011d3 2327 #define RCC_CIR_LSIRDYF 0x00000001U
sahilmgandhi 18:6a4db94011d3 2328 #define RCC_CIR_LSERDYF 0x00000002U
sahilmgandhi 18:6a4db94011d3 2329 #define RCC_CIR_HSIRDYF 0x00000004U
sahilmgandhi 18:6a4db94011d3 2330 #define RCC_CIR_HSERDYF 0x00000008U
sahilmgandhi 18:6a4db94011d3 2331 #define RCC_CIR_PLLRDYF 0x00000010U
sahilmgandhi 18:6a4db94011d3 2332 #define RCC_CIR_PLLI2SRDYF 0x00000020U
sahilmgandhi 18:6a4db94011d3 2333
sahilmgandhi 18:6a4db94011d3 2334 #define RCC_CIR_CSSF 0x00000080U
sahilmgandhi 18:6a4db94011d3 2335 #define RCC_CIR_LSIRDYIE 0x00000100U
sahilmgandhi 18:6a4db94011d3 2336 #define RCC_CIR_LSERDYIE 0x00000200U
sahilmgandhi 18:6a4db94011d3 2337 #define RCC_CIR_HSIRDYIE 0x00000400U
sahilmgandhi 18:6a4db94011d3 2338 #define RCC_CIR_HSERDYIE 0x00000800U
sahilmgandhi 18:6a4db94011d3 2339 #define RCC_CIR_PLLRDYIE 0x00001000U
sahilmgandhi 18:6a4db94011d3 2340 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
sahilmgandhi 18:6a4db94011d3 2341
sahilmgandhi 18:6a4db94011d3 2342 #define RCC_CIR_LSIRDYC 0x00010000U
sahilmgandhi 18:6a4db94011d3 2343 #define RCC_CIR_LSERDYC 0x00020000U
sahilmgandhi 18:6a4db94011d3 2344 #define RCC_CIR_HSIRDYC 0x00040000U
sahilmgandhi 18:6a4db94011d3 2345 #define RCC_CIR_HSERDYC 0x00080000U
sahilmgandhi 18:6a4db94011d3 2346 #define RCC_CIR_PLLRDYC 0x00100000U
sahilmgandhi 18:6a4db94011d3 2347 #define RCC_CIR_PLLI2SRDYC 0x00200000U
sahilmgandhi 18:6a4db94011d3 2348
sahilmgandhi 18:6a4db94011d3 2349 #define RCC_CIR_CSSC 0x00800000U
sahilmgandhi 18:6a4db94011d3 2350
sahilmgandhi 18:6a4db94011d3 2351 /******************** Bit definition for RCC_AHB1RSTR register **************/
sahilmgandhi 18:6a4db94011d3 2352 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
sahilmgandhi 18:6a4db94011d3 2353 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
sahilmgandhi 18:6a4db94011d3 2354 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
sahilmgandhi 18:6a4db94011d3 2355 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
sahilmgandhi 18:6a4db94011d3 2356 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
sahilmgandhi 18:6a4db94011d3 2357 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
sahilmgandhi 18:6a4db94011d3 2358 #define RCC_AHB1RSTR_CRCRST 0x00001000U
sahilmgandhi 18:6a4db94011d3 2359 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
sahilmgandhi 18:6a4db94011d3 2360 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
sahilmgandhi 18:6a4db94011d3 2361
sahilmgandhi 18:6a4db94011d3 2362 /******************** Bit definition for RCC_AHB2RSTR register **************/
sahilmgandhi 18:6a4db94011d3 2363 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
sahilmgandhi 18:6a4db94011d3 2364
sahilmgandhi 18:6a4db94011d3 2365 /******************** Bit definition for RCC_AHB3RSTR register **************/
sahilmgandhi 18:6a4db94011d3 2366
sahilmgandhi 18:6a4db94011d3 2367 /******************** Bit definition for RCC_APB1RSTR register **************/
sahilmgandhi 18:6a4db94011d3 2368 #define RCC_APB1RSTR_TIM2RST 0x00000001U
sahilmgandhi 18:6a4db94011d3 2369 #define RCC_APB1RSTR_TIM3RST 0x00000002U
sahilmgandhi 18:6a4db94011d3 2370 #define RCC_APB1RSTR_TIM4RST 0x00000004U
sahilmgandhi 18:6a4db94011d3 2371 #define RCC_APB1RSTR_TIM5RST 0x00000008U
sahilmgandhi 18:6a4db94011d3 2372 #define RCC_APB1RSTR_WWDGRST 0x00000800U
sahilmgandhi 18:6a4db94011d3 2373 #define RCC_APB1RSTR_SPI2RST 0x00004000U
sahilmgandhi 18:6a4db94011d3 2374 #define RCC_APB1RSTR_SPI3RST 0x00008000U
sahilmgandhi 18:6a4db94011d3 2375 #define RCC_APB1RSTR_USART2RST 0x00020000U
sahilmgandhi 18:6a4db94011d3 2376 #define RCC_APB1RSTR_I2C1RST 0x00200000U
sahilmgandhi 18:6a4db94011d3 2377 #define RCC_APB1RSTR_I2C2RST 0x00400000U
sahilmgandhi 18:6a4db94011d3 2378 #define RCC_APB1RSTR_I2C3RST 0x00800000U
sahilmgandhi 18:6a4db94011d3 2379 #define RCC_APB1RSTR_PWRRST 0x10000000U
sahilmgandhi 18:6a4db94011d3 2380
sahilmgandhi 18:6a4db94011d3 2381 /******************** Bit definition for RCC_APB2RSTR register **************/
sahilmgandhi 18:6a4db94011d3 2382 #define RCC_APB2RSTR_TIM1RST 0x00000001U
sahilmgandhi 18:6a4db94011d3 2383 #define RCC_APB2RSTR_USART1RST 0x00000010U
sahilmgandhi 18:6a4db94011d3 2384 #define RCC_APB2RSTR_USART6RST 0x00000020U
sahilmgandhi 18:6a4db94011d3 2385 #define RCC_APB2RSTR_ADCRST 0x00000100U
sahilmgandhi 18:6a4db94011d3 2386 #define RCC_APB2RSTR_SDIORST 0x00000800U
sahilmgandhi 18:6a4db94011d3 2387 #define RCC_APB2RSTR_SPI1RST 0x00001000U
sahilmgandhi 18:6a4db94011d3 2388 #define RCC_APB2RSTR_SPI4RST 0x00002000U
sahilmgandhi 18:6a4db94011d3 2389 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
sahilmgandhi 18:6a4db94011d3 2390 #define RCC_APB2RSTR_TIM9RST 0x00010000U
sahilmgandhi 18:6a4db94011d3 2391 #define RCC_APB2RSTR_TIM10RST 0x00020000U
sahilmgandhi 18:6a4db94011d3 2392 #define RCC_APB2RSTR_TIM11RST 0x00040000U
sahilmgandhi 18:6a4db94011d3 2393
sahilmgandhi 18:6a4db94011d3 2394 /* Old SPI1RST bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 2395 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
sahilmgandhi 18:6a4db94011d3 2396
sahilmgandhi 18:6a4db94011d3 2397 /******************** Bit definition for RCC_AHB1ENR register ***************/
sahilmgandhi 18:6a4db94011d3 2398 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 2399 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 2400 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 2401 #define RCC_AHB1ENR_GPIODEN 0x00000008U
sahilmgandhi 18:6a4db94011d3 2402 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 2403 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 2404 #define RCC_AHB1ENR_CRCEN 0x00001000U
sahilmgandhi 18:6a4db94011d3 2405 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 2406 #define RCC_AHB1ENR_DMA1EN 0x00200000U
sahilmgandhi 18:6a4db94011d3 2407 #define RCC_AHB1ENR_DMA2EN 0x00400000U
sahilmgandhi 18:6a4db94011d3 2408
sahilmgandhi 18:6a4db94011d3 2409 /******************** Bit definition for RCC_AHB2ENR register ***************/
sahilmgandhi 18:6a4db94011d3 2410 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 2411
sahilmgandhi 18:6a4db94011d3 2412 /******************** Bit definition for RCC_AHB3ENR register ***************/
sahilmgandhi 18:6a4db94011d3 2413
sahilmgandhi 18:6a4db94011d3 2414 /******************** Bit definition for RCC_APB1ENR register ***************/
sahilmgandhi 18:6a4db94011d3 2415 #define RCC_APB1ENR_TIM2EN 0x00000001U
sahilmgandhi 18:6a4db94011d3 2416 #define RCC_APB1ENR_TIM3EN 0x00000002U
sahilmgandhi 18:6a4db94011d3 2417 #define RCC_APB1ENR_TIM4EN 0x00000004U
sahilmgandhi 18:6a4db94011d3 2418 #define RCC_APB1ENR_TIM5EN 0x00000008U
sahilmgandhi 18:6a4db94011d3 2419 #define RCC_APB1ENR_WWDGEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 2420 #define RCC_APB1ENR_SPI2EN 0x00004000U
sahilmgandhi 18:6a4db94011d3 2421 #define RCC_APB1ENR_SPI3EN 0x00008000U
sahilmgandhi 18:6a4db94011d3 2422 #define RCC_APB1ENR_USART2EN 0x00020000U
sahilmgandhi 18:6a4db94011d3 2423 #define RCC_APB1ENR_I2C1EN 0x00200000U
sahilmgandhi 18:6a4db94011d3 2424 #define RCC_APB1ENR_I2C2EN 0x00400000U
sahilmgandhi 18:6a4db94011d3 2425 #define RCC_APB1ENR_I2C3EN 0x00800000U
sahilmgandhi 18:6a4db94011d3 2426 #define RCC_APB1ENR_PWREN 0x10000000U
sahilmgandhi 18:6a4db94011d3 2427
sahilmgandhi 18:6a4db94011d3 2428 /******************** Bit definition for RCC_APB2ENR register ***************/
sahilmgandhi 18:6a4db94011d3 2429 #define RCC_APB2ENR_TIM1EN 0x00000001U
sahilmgandhi 18:6a4db94011d3 2430 #define RCC_APB2ENR_USART1EN 0x00000010U
sahilmgandhi 18:6a4db94011d3 2431 #define RCC_APB2ENR_USART6EN 0x00000020U
sahilmgandhi 18:6a4db94011d3 2432 #define RCC_APB2ENR_ADC1EN 0x00000100U
sahilmgandhi 18:6a4db94011d3 2433 #define RCC_APB2ENR_SDIOEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 2434 #define RCC_APB2ENR_SPI1EN 0x00001000U
sahilmgandhi 18:6a4db94011d3 2435 #define RCC_APB2ENR_SPI4EN 0x00002000U
sahilmgandhi 18:6a4db94011d3 2436 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
sahilmgandhi 18:6a4db94011d3 2437 #define RCC_APB2ENR_TIM9EN 0x00010000U
sahilmgandhi 18:6a4db94011d3 2438 #define RCC_APB2ENR_TIM10EN 0x00020000U
sahilmgandhi 18:6a4db94011d3 2439 #define RCC_APB2ENR_TIM11EN 0x00040000U
sahilmgandhi 18:6a4db94011d3 2440
sahilmgandhi 18:6a4db94011d3 2441 /******************** Bit definition for RCC_AHB1LPENR register *************/
sahilmgandhi 18:6a4db94011d3 2442 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 2443 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 2444 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 2445 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
sahilmgandhi 18:6a4db94011d3 2446 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 2447 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 2448 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
sahilmgandhi 18:6a4db94011d3 2449 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
sahilmgandhi 18:6a4db94011d3 2450 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
sahilmgandhi 18:6a4db94011d3 2451 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
sahilmgandhi 18:6a4db94011d3 2452 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 2453 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
sahilmgandhi 18:6a4db94011d3 2454 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
sahilmgandhi 18:6a4db94011d3 2455
sahilmgandhi 18:6a4db94011d3 2456 /******************** Bit definition for RCC_AHB2LPENR register *************/
sahilmgandhi 18:6a4db94011d3 2457 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 2458
sahilmgandhi 18:6a4db94011d3 2459 /******************** Bit definition for RCC_AHB3LPENR register *************/
sahilmgandhi 18:6a4db94011d3 2460
sahilmgandhi 18:6a4db94011d3 2461 /******************** Bit definition for RCC_APB1LPENR register *************/
sahilmgandhi 18:6a4db94011d3 2462 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 2463 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 2464 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 2465 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
sahilmgandhi 18:6a4db94011d3 2466 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 2467 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
sahilmgandhi 18:6a4db94011d3 2468 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
sahilmgandhi 18:6a4db94011d3 2469 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
sahilmgandhi 18:6a4db94011d3 2470 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
sahilmgandhi 18:6a4db94011d3 2471 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
sahilmgandhi 18:6a4db94011d3 2472 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
sahilmgandhi 18:6a4db94011d3 2473 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
sahilmgandhi 18:6a4db94011d3 2474 #define RCC_APB1LPENR_DACLPEN 0x20000000U
sahilmgandhi 18:6a4db94011d3 2475
sahilmgandhi 18:6a4db94011d3 2476 /******************** Bit definition for RCC_APB2LPENR register *************/
sahilmgandhi 18:6a4db94011d3 2477 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 2478 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 2479 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 2480 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 2481 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 2482 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
sahilmgandhi 18:6a4db94011d3 2483 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
sahilmgandhi 18:6a4db94011d3 2484 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
sahilmgandhi 18:6a4db94011d3 2485 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
sahilmgandhi 18:6a4db94011d3 2486 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
sahilmgandhi 18:6a4db94011d3 2487 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 2488
sahilmgandhi 18:6a4db94011d3 2489 /******************** Bit definition for RCC_BDCR register ******************/
sahilmgandhi 18:6a4db94011d3 2490 #define RCC_BDCR_LSEON 0x00000001U
sahilmgandhi 18:6a4db94011d3 2491 #define RCC_BDCR_LSERDY 0x00000002U
sahilmgandhi 18:6a4db94011d3 2492 #define RCC_BDCR_LSEBYP 0x00000004U
sahilmgandhi 18:6a4db94011d3 2493
sahilmgandhi 18:6a4db94011d3 2494 #define RCC_BDCR_RTCSEL 0x00000300U
sahilmgandhi 18:6a4db94011d3 2495 #define RCC_BDCR_RTCSEL_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2496 #define RCC_BDCR_RTCSEL_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2497
sahilmgandhi 18:6a4db94011d3 2498 #define RCC_BDCR_RTCEN 0x00008000U
sahilmgandhi 18:6a4db94011d3 2499 #define RCC_BDCR_BDRST 0x00010000U
sahilmgandhi 18:6a4db94011d3 2500
sahilmgandhi 18:6a4db94011d3 2501 /******************** Bit definition for RCC_CSR register *******************/
sahilmgandhi 18:6a4db94011d3 2502 #define RCC_CSR_LSION 0x00000001U
sahilmgandhi 18:6a4db94011d3 2503 #define RCC_CSR_LSIRDY 0x00000002U
sahilmgandhi 18:6a4db94011d3 2504 #define RCC_CSR_RMVF 0x01000000U
sahilmgandhi 18:6a4db94011d3 2505 #define RCC_CSR_BORRSTF 0x02000000U
sahilmgandhi 18:6a4db94011d3 2506 #define RCC_CSR_PADRSTF 0x04000000U
sahilmgandhi 18:6a4db94011d3 2507 #define RCC_CSR_PORRSTF 0x08000000U
sahilmgandhi 18:6a4db94011d3 2508 #define RCC_CSR_SFTRSTF 0x10000000U
sahilmgandhi 18:6a4db94011d3 2509 #define RCC_CSR_WDGRSTF 0x20000000U
sahilmgandhi 18:6a4db94011d3 2510 #define RCC_CSR_WWDGRSTF 0x40000000U
sahilmgandhi 18:6a4db94011d3 2511 #define RCC_CSR_LPWRRSTF 0x80000000U
sahilmgandhi 18:6a4db94011d3 2512
sahilmgandhi 18:6a4db94011d3 2513 /******************** Bit definition for RCC_SSCGR register *****************/
sahilmgandhi 18:6a4db94011d3 2514 #define RCC_SSCGR_MODPER 0x00001FFFU
sahilmgandhi 18:6a4db94011d3 2515 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
sahilmgandhi 18:6a4db94011d3 2516 #define RCC_SSCGR_SPREADSEL 0x40000000U
sahilmgandhi 18:6a4db94011d3 2517 #define RCC_SSCGR_SSCGEN 0x80000000U
sahilmgandhi 18:6a4db94011d3 2518
sahilmgandhi 18:6a4db94011d3 2519 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
sahilmgandhi 18:6a4db94011d3 2520 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
sahilmgandhi 18:6a4db94011d3 2521 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 2522 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 2523 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
sahilmgandhi 18:6a4db94011d3 2524 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
sahilmgandhi 18:6a4db94011d3 2525 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
sahilmgandhi 18:6a4db94011d3 2526 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
sahilmgandhi 18:6a4db94011d3 2527 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
sahilmgandhi 18:6a4db94011d3 2528 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
sahilmgandhi 18:6a4db94011d3 2529 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
sahilmgandhi 18:6a4db94011d3 2530
sahilmgandhi 18:6a4db94011d3 2531 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
sahilmgandhi 18:6a4db94011d3 2532 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 2533 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 2534 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
sahilmgandhi 18:6a4db94011d3 2535
sahilmgandhi 18:6a4db94011d3 2536 /******************** Bit definition for RCC_DCKCFGR register ***************/
sahilmgandhi 18:6a4db94011d3 2537 #define RCC_DCKCFGR_TIMPRE 0x01000000U
sahilmgandhi 18:6a4db94011d3 2538
sahilmgandhi 18:6a4db94011d3 2539 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2540 /* */
sahilmgandhi 18:6a4db94011d3 2541 /* Real-Time Clock (RTC) */
sahilmgandhi 18:6a4db94011d3 2542 /* */
sahilmgandhi 18:6a4db94011d3 2543 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2544 /******************** Bits definition for RTC_TR register *******************/
sahilmgandhi 18:6a4db94011d3 2545 #define RTC_TR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 2546 #define RTC_TR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 2547 #define RTC_TR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 2548 #define RTC_TR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 2549 #define RTC_TR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 2550 #define RTC_TR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2551 #define RTC_TR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2552 #define RTC_TR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 2553 #define RTC_TR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 2554 #define RTC_TR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 2555 #define RTC_TR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 2556 #define RTC_TR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 2557 #define RTC_TR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 2558 #define RTC_TR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 2559 #define RTC_TR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2560 #define RTC_TR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2561 #define RTC_TR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2562 #define RTC_TR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 2563 #define RTC_TR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 2564 #define RTC_TR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 2565 #define RTC_TR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 2566 #define RTC_TR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 2567 #define RTC_TR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 2568 #define RTC_TR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2569 #define RTC_TR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2570 #define RTC_TR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2571 #define RTC_TR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2572
sahilmgandhi 18:6a4db94011d3 2573 /******************** Bits definition for RTC_DR register *******************/
sahilmgandhi 18:6a4db94011d3 2574 #define RTC_DR_YT 0x00F00000U
sahilmgandhi 18:6a4db94011d3 2575 #define RTC_DR_YT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 2576 #define RTC_DR_YT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 2577 #define RTC_DR_YT_2 0x00400000U
sahilmgandhi 18:6a4db94011d3 2578 #define RTC_DR_YT_3 0x00800000U
sahilmgandhi 18:6a4db94011d3 2579 #define RTC_DR_YU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 2580 #define RTC_DR_YU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2581 #define RTC_DR_YU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2582 #define RTC_DR_YU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 2583 #define RTC_DR_YU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 2584 #define RTC_DR_WDU 0x0000E000U
sahilmgandhi 18:6a4db94011d3 2585 #define RTC_DR_WDU_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 2586 #define RTC_DR_WDU_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 2587 #define RTC_DR_WDU_2 0x00008000U
sahilmgandhi 18:6a4db94011d3 2588 #define RTC_DR_MT 0x00001000U
sahilmgandhi 18:6a4db94011d3 2589 #define RTC_DR_MU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 2590 #define RTC_DR_MU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2591 #define RTC_DR_MU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2592 #define RTC_DR_MU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2593 #define RTC_DR_MU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 2594 #define RTC_DR_DT 0x00000030U
sahilmgandhi 18:6a4db94011d3 2595 #define RTC_DR_DT_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 2596 #define RTC_DR_DT_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 2597 #define RTC_DR_DU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 2598 #define RTC_DR_DU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2599 #define RTC_DR_DU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2600 #define RTC_DR_DU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2601 #define RTC_DR_DU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2602
sahilmgandhi 18:6a4db94011d3 2603 /******************** Bits definition for RTC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 2604 #define RTC_CR_COE 0x00800000U
sahilmgandhi 18:6a4db94011d3 2605 #define RTC_CR_OSEL 0x00600000U
sahilmgandhi 18:6a4db94011d3 2606 #define RTC_CR_OSEL_0 0x00200000U
sahilmgandhi 18:6a4db94011d3 2607 #define RTC_CR_OSEL_1 0x00400000U
sahilmgandhi 18:6a4db94011d3 2608 #define RTC_CR_POL 0x00100000U
sahilmgandhi 18:6a4db94011d3 2609 #define RTC_CR_COSEL 0x00080000U
sahilmgandhi 18:6a4db94011d3 2610 #define RTC_CR_BCK 0x00040000U
sahilmgandhi 18:6a4db94011d3 2611 #define RTC_CR_SUB1H 0x00020000U
sahilmgandhi 18:6a4db94011d3 2612 #define RTC_CR_ADD1H 0x00010000U
sahilmgandhi 18:6a4db94011d3 2613 #define RTC_CR_TSIE 0x00008000U
sahilmgandhi 18:6a4db94011d3 2614 #define RTC_CR_WUTIE 0x00004000U
sahilmgandhi 18:6a4db94011d3 2615 #define RTC_CR_ALRBIE 0x00002000U
sahilmgandhi 18:6a4db94011d3 2616 #define RTC_CR_ALRAIE 0x00001000U
sahilmgandhi 18:6a4db94011d3 2617 #define RTC_CR_TSE 0x00000800U
sahilmgandhi 18:6a4db94011d3 2618 #define RTC_CR_WUTE 0x00000400U
sahilmgandhi 18:6a4db94011d3 2619 #define RTC_CR_ALRBE 0x00000200U
sahilmgandhi 18:6a4db94011d3 2620 #define RTC_CR_ALRAE 0x00000100U
sahilmgandhi 18:6a4db94011d3 2621 #define RTC_CR_DCE 0x00000080U
sahilmgandhi 18:6a4db94011d3 2622 #define RTC_CR_FMT 0x00000040U
sahilmgandhi 18:6a4db94011d3 2623 #define RTC_CR_BYPSHAD 0x00000020U
sahilmgandhi 18:6a4db94011d3 2624 #define RTC_CR_REFCKON 0x00000010U
sahilmgandhi 18:6a4db94011d3 2625 #define RTC_CR_TSEDGE 0x00000008U
sahilmgandhi 18:6a4db94011d3 2626 #define RTC_CR_WUCKSEL 0x00000007U
sahilmgandhi 18:6a4db94011d3 2627 #define RTC_CR_WUCKSEL_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2628 #define RTC_CR_WUCKSEL_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2629 #define RTC_CR_WUCKSEL_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2630
sahilmgandhi 18:6a4db94011d3 2631 /******************** Bits definition for RTC_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 2632 #define RTC_ISR_RECALPF 0x00010000U
sahilmgandhi 18:6a4db94011d3 2633 #define RTC_ISR_TAMP1F 0x00002000U
sahilmgandhi 18:6a4db94011d3 2634 #define RTC_ISR_TAMP2F 0x00004000U
sahilmgandhi 18:6a4db94011d3 2635 #define RTC_ISR_TSOVF 0x00001000U
sahilmgandhi 18:6a4db94011d3 2636 #define RTC_ISR_TSF 0x00000800U
sahilmgandhi 18:6a4db94011d3 2637 #define RTC_ISR_WUTF 0x00000400U
sahilmgandhi 18:6a4db94011d3 2638 #define RTC_ISR_ALRBF 0x00000200U
sahilmgandhi 18:6a4db94011d3 2639 #define RTC_ISR_ALRAF 0x00000100U
sahilmgandhi 18:6a4db94011d3 2640 #define RTC_ISR_INIT 0x00000080U
sahilmgandhi 18:6a4db94011d3 2641 #define RTC_ISR_INITF 0x00000040U
sahilmgandhi 18:6a4db94011d3 2642 #define RTC_ISR_RSF 0x00000020U
sahilmgandhi 18:6a4db94011d3 2643 #define RTC_ISR_INITS 0x00000010U
sahilmgandhi 18:6a4db94011d3 2644 #define RTC_ISR_SHPF 0x00000008U
sahilmgandhi 18:6a4db94011d3 2645 #define RTC_ISR_WUTWF 0x00000004U
sahilmgandhi 18:6a4db94011d3 2646 #define RTC_ISR_ALRBWF 0x00000002U
sahilmgandhi 18:6a4db94011d3 2647 #define RTC_ISR_ALRAWF 0x00000001U
sahilmgandhi 18:6a4db94011d3 2648
sahilmgandhi 18:6a4db94011d3 2649 /******************** Bits definition for RTC_PRER register *****************/
sahilmgandhi 18:6a4db94011d3 2650 #define RTC_PRER_PREDIV_A 0x007F0000U
sahilmgandhi 18:6a4db94011d3 2651 #define RTC_PRER_PREDIV_S 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 2652
sahilmgandhi 18:6a4db94011d3 2653 /******************** Bits definition for RTC_WUTR register *****************/
sahilmgandhi 18:6a4db94011d3 2654 #define RTC_WUTR_WUT 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 2655
sahilmgandhi 18:6a4db94011d3 2656 /******************** Bits definition for RTC_CALIBR register ***************/
sahilmgandhi 18:6a4db94011d3 2657 #define RTC_CALIBR_DCS 0x00000080U
sahilmgandhi 18:6a4db94011d3 2658 #define RTC_CALIBR_DC 0x0000001FU
sahilmgandhi 18:6a4db94011d3 2659
sahilmgandhi 18:6a4db94011d3 2660 /******************** Bits definition for RTC_ALRMAR register ***************/
sahilmgandhi 18:6a4db94011d3 2661 #define RTC_ALRMAR_MSK4 0x80000000U
sahilmgandhi 18:6a4db94011d3 2662 #define RTC_ALRMAR_WDSEL 0x40000000U
sahilmgandhi 18:6a4db94011d3 2663 #define RTC_ALRMAR_DT 0x30000000U
sahilmgandhi 18:6a4db94011d3 2664 #define RTC_ALRMAR_DT_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 2665 #define RTC_ALRMAR_DT_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 2666 #define RTC_ALRMAR_DU 0x0F000000U
sahilmgandhi 18:6a4db94011d3 2667 #define RTC_ALRMAR_DU_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 2668 #define RTC_ALRMAR_DU_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 2669 #define RTC_ALRMAR_DU_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 2670 #define RTC_ALRMAR_DU_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 2671 #define RTC_ALRMAR_MSK3 0x00800000U
sahilmgandhi 18:6a4db94011d3 2672 #define RTC_ALRMAR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 2673 #define RTC_ALRMAR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 2674 #define RTC_ALRMAR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 2675 #define RTC_ALRMAR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 2676 #define RTC_ALRMAR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 2677 #define RTC_ALRMAR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2678 #define RTC_ALRMAR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2679 #define RTC_ALRMAR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 2680 #define RTC_ALRMAR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 2681 #define RTC_ALRMAR_MSK2 0x00008000U
sahilmgandhi 18:6a4db94011d3 2682 #define RTC_ALRMAR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 2683 #define RTC_ALRMAR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 2684 #define RTC_ALRMAR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 2685 #define RTC_ALRMAR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 2686 #define RTC_ALRMAR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 2687 #define RTC_ALRMAR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2688 #define RTC_ALRMAR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2689 #define RTC_ALRMAR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2690 #define RTC_ALRMAR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 2691 #define RTC_ALRMAR_MSK1 0x00000080U
sahilmgandhi 18:6a4db94011d3 2692 #define RTC_ALRMAR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 2693 #define RTC_ALRMAR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 2694 #define RTC_ALRMAR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 2695 #define RTC_ALRMAR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 2696 #define RTC_ALRMAR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 2697 #define RTC_ALRMAR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2698 #define RTC_ALRMAR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2699 #define RTC_ALRMAR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2700 #define RTC_ALRMAR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2701
sahilmgandhi 18:6a4db94011d3 2702 /******************** Bits definition for RTC_ALRMBR register ***************/
sahilmgandhi 18:6a4db94011d3 2703 #define RTC_ALRMBR_MSK4 0x80000000U
sahilmgandhi 18:6a4db94011d3 2704 #define RTC_ALRMBR_WDSEL 0x40000000U
sahilmgandhi 18:6a4db94011d3 2705 #define RTC_ALRMBR_DT 0x30000000U
sahilmgandhi 18:6a4db94011d3 2706 #define RTC_ALRMBR_DT_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 2707 #define RTC_ALRMBR_DT_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 2708 #define RTC_ALRMBR_DU 0x0F000000U
sahilmgandhi 18:6a4db94011d3 2709 #define RTC_ALRMBR_DU_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 2710 #define RTC_ALRMBR_DU_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 2711 #define RTC_ALRMBR_DU_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 2712 #define RTC_ALRMBR_DU_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 2713 #define RTC_ALRMBR_MSK3 0x00800000U
sahilmgandhi 18:6a4db94011d3 2714 #define RTC_ALRMBR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 2715 #define RTC_ALRMBR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 2716 #define RTC_ALRMBR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 2717 #define RTC_ALRMBR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 2718 #define RTC_ALRMBR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 2719 #define RTC_ALRMBR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2720 #define RTC_ALRMBR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2721 #define RTC_ALRMBR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 2722 #define RTC_ALRMBR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 2723 #define RTC_ALRMBR_MSK2 0x00008000U
sahilmgandhi 18:6a4db94011d3 2724 #define RTC_ALRMBR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 2725 #define RTC_ALRMBR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 2726 #define RTC_ALRMBR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 2727 #define RTC_ALRMBR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 2728 #define RTC_ALRMBR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 2729 #define RTC_ALRMBR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2730 #define RTC_ALRMBR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2731 #define RTC_ALRMBR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2732 #define RTC_ALRMBR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 2733 #define RTC_ALRMBR_MSK1 0x00000080U
sahilmgandhi 18:6a4db94011d3 2734 #define RTC_ALRMBR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 2735 #define RTC_ALRMBR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 2736 #define RTC_ALRMBR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 2737 #define RTC_ALRMBR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 2738 #define RTC_ALRMBR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 2739 #define RTC_ALRMBR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2740 #define RTC_ALRMBR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2741 #define RTC_ALRMBR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2742 #define RTC_ALRMBR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2743
sahilmgandhi 18:6a4db94011d3 2744 /******************** Bits definition for RTC_WPR register ******************/
sahilmgandhi 18:6a4db94011d3 2745 #define RTC_WPR_KEY 0x000000FFU
sahilmgandhi 18:6a4db94011d3 2746
sahilmgandhi 18:6a4db94011d3 2747 /******************** Bits definition for RTC_SSR register ******************/
sahilmgandhi 18:6a4db94011d3 2748 #define RTC_SSR_SS 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 2749
sahilmgandhi 18:6a4db94011d3 2750 /******************** Bits definition for RTC_SHIFTR register ***************/
sahilmgandhi 18:6a4db94011d3 2751 #define RTC_SHIFTR_SUBFS 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 2752 #define RTC_SHIFTR_ADD1S 0x80000000U
sahilmgandhi 18:6a4db94011d3 2753
sahilmgandhi 18:6a4db94011d3 2754 /******************** Bits definition for RTC_TSTR register *****************/
sahilmgandhi 18:6a4db94011d3 2755 #define RTC_TSTR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 2756 #define RTC_TSTR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 2757 #define RTC_TSTR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 2758 #define RTC_TSTR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 2759 #define RTC_TSTR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 2760 #define RTC_TSTR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 2761 #define RTC_TSTR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 2762 #define RTC_TSTR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 2763 #define RTC_TSTR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 2764 #define RTC_TSTR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 2765 #define RTC_TSTR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 2766 #define RTC_TSTR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 2767 #define RTC_TSTR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 2768 #define RTC_TSTR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 2769 #define RTC_TSTR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2770 #define RTC_TSTR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2771 #define RTC_TSTR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2772 #define RTC_TSTR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 2773 #define RTC_TSTR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 2774 #define RTC_TSTR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 2775 #define RTC_TSTR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 2776 #define RTC_TSTR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 2777 #define RTC_TSTR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 2778 #define RTC_TSTR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2779 #define RTC_TSTR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2780 #define RTC_TSTR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2781 #define RTC_TSTR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2782
sahilmgandhi 18:6a4db94011d3 2783 /******************** Bits definition for RTC_TSDR register *****************/
sahilmgandhi 18:6a4db94011d3 2784 #define RTC_TSDR_WDU 0x0000E000U
sahilmgandhi 18:6a4db94011d3 2785 #define RTC_TSDR_WDU_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 2786 #define RTC_TSDR_WDU_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 2787 #define RTC_TSDR_WDU_2 0x00008000U
sahilmgandhi 18:6a4db94011d3 2788 #define RTC_TSDR_MT 0x00001000U
sahilmgandhi 18:6a4db94011d3 2789 #define RTC_TSDR_MU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 2790 #define RTC_TSDR_MU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2791 #define RTC_TSDR_MU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2792 #define RTC_TSDR_MU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2793 #define RTC_TSDR_MU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 2794 #define RTC_TSDR_DT 0x00000030U
sahilmgandhi 18:6a4db94011d3 2795 #define RTC_TSDR_DT_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 2796 #define RTC_TSDR_DT_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 2797 #define RTC_TSDR_DU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 2798 #define RTC_TSDR_DU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2799 #define RTC_TSDR_DU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2800 #define RTC_TSDR_DU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2801 #define RTC_TSDR_DU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2802
sahilmgandhi 18:6a4db94011d3 2803 /******************** Bits definition for RTC_TSSSR register ****************/
sahilmgandhi 18:6a4db94011d3 2804 #define RTC_TSSSR_SS 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 2805
sahilmgandhi 18:6a4db94011d3 2806 /******************** Bits definition for RTC_CAL register *****************/
sahilmgandhi 18:6a4db94011d3 2807 #define RTC_CALR_CALP 0x00008000U
sahilmgandhi 18:6a4db94011d3 2808 #define RTC_CALR_CALW8 0x00004000U
sahilmgandhi 18:6a4db94011d3 2809 #define RTC_CALR_CALW16 0x00002000U
sahilmgandhi 18:6a4db94011d3 2810 #define RTC_CALR_CALM 0x000001FFU
sahilmgandhi 18:6a4db94011d3 2811 #define RTC_CALR_CALM_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 2812 #define RTC_CALR_CALM_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 2813 #define RTC_CALR_CALM_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 2814 #define RTC_CALR_CALM_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 2815 #define RTC_CALR_CALM_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 2816 #define RTC_CALR_CALM_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 2817 #define RTC_CALR_CALM_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 2818 #define RTC_CALR_CALM_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 2819 #define RTC_CALR_CALM_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 2820
sahilmgandhi 18:6a4db94011d3 2821 /******************** Bits definition for RTC_TAFCR register ****************/
sahilmgandhi 18:6a4db94011d3 2822 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
sahilmgandhi 18:6a4db94011d3 2823 #define RTC_TAFCR_TSINSEL 0x00020000U
sahilmgandhi 18:6a4db94011d3 2824 #define RTC_TAFCR_TAMPINSEL 0x00010000U
sahilmgandhi 18:6a4db94011d3 2825 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
sahilmgandhi 18:6a4db94011d3 2826 #define RTC_TAFCR_TAMPPRCH 0x00006000U
sahilmgandhi 18:6a4db94011d3 2827 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 2828 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 2829 #define RTC_TAFCR_TAMPFLT 0x00001800U
sahilmgandhi 18:6a4db94011d3 2830 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
sahilmgandhi 18:6a4db94011d3 2831 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
sahilmgandhi 18:6a4db94011d3 2832 #define RTC_TAFCR_TAMPFREQ 0x00000700U
sahilmgandhi 18:6a4db94011d3 2833 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 2834 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 2835 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 2836 #define RTC_TAFCR_TAMPTS 0x00000080U
sahilmgandhi 18:6a4db94011d3 2837 #define RTC_TAFCR_TAMP2TRG 0x00000010U
sahilmgandhi 18:6a4db94011d3 2838 #define RTC_TAFCR_TAMP2E 0x00000008U
sahilmgandhi 18:6a4db94011d3 2839 #define RTC_TAFCR_TAMPIE 0x00000004U
sahilmgandhi 18:6a4db94011d3 2840 #define RTC_TAFCR_TAMP1TRG 0x00000002U
sahilmgandhi 18:6a4db94011d3 2841 #define RTC_TAFCR_TAMP1E 0x00000001U
sahilmgandhi 18:6a4db94011d3 2842
sahilmgandhi 18:6a4db94011d3 2843 /******************** Bits definition for RTC_ALRMASSR register *************/
sahilmgandhi 18:6a4db94011d3 2844 #define RTC_ALRMASSR_MASKSS 0x0F000000U
sahilmgandhi 18:6a4db94011d3 2845 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 2846 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 2847 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 2848 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 2849 #define RTC_ALRMASSR_SS 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 2850
sahilmgandhi 18:6a4db94011d3 2851 /******************** Bits definition for RTC_ALRMBSSR register *************/
sahilmgandhi 18:6a4db94011d3 2852 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
sahilmgandhi 18:6a4db94011d3 2853 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 2854 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 2855 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 2856 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 2857 #define RTC_ALRMBSSR_SS 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 2858
sahilmgandhi 18:6a4db94011d3 2859 /******************** Bits definition for RTC_BKP0R register ****************/
sahilmgandhi 18:6a4db94011d3 2860 #define RTC_BKP0R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2861
sahilmgandhi 18:6a4db94011d3 2862 /******************** Bits definition for RTC_BKP1R register ****************/
sahilmgandhi 18:6a4db94011d3 2863 #define RTC_BKP1R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2864
sahilmgandhi 18:6a4db94011d3 2865 /******************** Bits definition for RTC_BKP2R register ****************/
sahilmgandhi 18:6a4db94011d3 2866 #define RTC_BKP2R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2867
sahilmgandhi 18:6a4db94011d3 2868 /******************** Bits definition for RTC_BKP3R register ****************/
sahilmgandhi 18:6a4db94011d3 2869 #define RTC_BKP3R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2870
sahilmgandhi 18:6a4db94011d3 2871 /******************** Bits definition for RTC_BKP4R register ****************/
sahilmgandhi 18:6a4db94011d3 2872 #define RTC_BKP4R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2873
sahilmgandhi 18:6a4db94011d3 2874 /******************** Bits definition for RTC_BKP5R register ****************/
sahilmgandhi 18:6a4db94011d3 2875 #define RTC_BKP5R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2876
sahilmgandhi 18:6a4db94011d3 2877 /******************** Bits definition for RTC_BKP6R register ****************/
sahilmgandhi 18:6a4db94011d3 2878 #define RTC_BKP6R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2879
sahilmgandhi 18:6a4db94011d3 2880 /******************** Bits definition for RTC_BKP7R register ****************/
sahilmgandhi 18:6a4db94011d3 2881 #define RTC_BKP7R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2882
sahilmgandhi 18:6a4db94011d3 2883 /******************** Bits definition for RTC_BKP8R register ****************/
sahilmgandhi 18:6a4db94011d3 2884 #define RTC_BKP8R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2885
sahilmgandhi 18:6a4db94011d3 2886 /******************** Bits definition for RTC_BKP9R register ****************/
sahilmgandhi 18:6a4db94011d3 2887 #define RTC_BKP9R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2888
sahilmgandhi 18:6a4db94011d3 2889 /******************** Bits definition for RTC_BKP10R register ***************/
sahilmgandhi 18:6a4db94011d3 2890 #define RTC_BKP10R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2891
sahilmgandhi 18:6a4db94011d3 2892 /******************** Bits definition for RTC_BKP11R register ***************/
sahilmgandhi 18:6a4db94011d3 2893 #define RTC_BKP11R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2894
sahilmgandhi 18:6a4db94011d3 2895 /******************** Bits definition for RTC_BKP12R register ***************/
sahilmgandhi 18:6a4db94011d3 2896 #define RTC_BKP12R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2897
sahilmgandhi 18:6a4db94011d3 2898 /******************** Bits definition for RTC_BKP13R register ***************/
sahilmgandhi 18:6a4db94011d3 2899 #define RTC_BKP13R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2900
sahilmgandhi 18:6a4db94011d3 2901 /******************** Bits definition for RTC_BKP14R register ***************/
sahilmgandhi 18:6a4db94011d3 2902 #define RTC_BKP14R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2903
sahilmgandhi 18:6a4db94011d3 2904 /******************** Bits definition for RTC_BKP15R register ***************/
sahilmgandhi 18:6a4db94011d3 2905 #define RTC_BKP15R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2906
sahilmgandhi 18:6a4db94011d3 2907 /******************** Bits definition for RTC_BKP16R register ***************/
sahilmgandhi 18:6a4db94011d3 2908 #define RTC_BKP16R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2909
sahilmgandhi 18:6a4db94011d3 2910 /******************** Bits definition for RTC_BKP17R register ***************/
sahilmgandhi 18:6a4db94011d3 2911 #define RTC_BKP17R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2912
sahilmgandhi 18:6a4db94011d3 2913 /******************** Bits definition for RTC_BKP18R register ***************/
sahilmgandhi 18:6a4db94011d3 2914 #define RTC_BKP18R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2915
sahilmgandhi 18:6a4db94011d3 2916 /******************** Bits definition for RTC_BKP19R register ***************/
sahilmgandhi 18:6a4db94011d3 2917 #define RTC_BKP19R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 2918
sahilmgandhi 18:6a4db94011d3 2919
sahilmgandhi 18:6a4db94011d3 2920
sahilmgandhi 18:6a4db94011d3 2921 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2922 /* */
sahilmgandhi 18:6a4db94011d3 2923 /* SD host Interface */
sahilmgandhi 18:6a4db94011d3 2924 /* */
sahilmgandhi 18:6a4db94011d3 2925 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2926 /****************** Bit definition for SDIO_POWER register ******************/
sahilmgandhi 18:6a4db94011d3 2927 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
sahilmgandhi 18:6a4db94011d3 2928 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2929 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2930
sahilmgandhi 18:6a4db94011d3 2931 /****************** Bit definition for SDIO_CLKCR register ******************/
sahilmgandhi 18:6a4db94011d3 2932 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
sahilmgandhi 18:6a4db94011d3 2933 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
sahilmgandhi 18:6a4db94011d3 2934 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
sahilmgandhi 18:6a4db94011d3 2935 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
sahilmgandhi 18:6a4db94011d3 2936
sahilmgandhi 18:6a4db94011d3 2937 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
sahilmgandhi 18:6a4db94011d3 2938 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2939 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2940
sahilmgandhi 18:6a4db94011d3 2941 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
sahilmgandhi 18:6a4db94011d3 2942 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
sahilmgandhi 18:6a4db94011d3 2943
sahilmgandhi 18:6a4db94011d3 2944 /******************* Bit definition for SDIO_ARG register *******************/
sahilmgandhi 18:6a4db94011d3 2945 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
sahilmgandhi 18:6a4db94011d3 2946
sahilmgandhi 18:6a4db94011d3 2947 /******************* Bit definition for SDIO_CMD register *******************/
sahilmgandhi 18:6a4db94011d3 2948 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
sahilmgandhi 18:6a4db94011d3 2949
sahilmgandhi 18:6a4db94011d3 2950 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
sahilmgandhi 18:6a4db94011d3 2951 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 2952 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 2953
sahilmgandhi 18:6a4db94011d3 2954 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
sahilmgandhi 18:6a4db94011d3 2955 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
sahilmgandhi 18:6a4db94011d3 2956 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
sahilmgandhi 18:6a4db94011d3 2957 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
sahilmgandhi 18:6a4db94011d3 2958 #define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
sahilmgandhi 18:6a4db94011d3 2959 #define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2960 #define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
sahilmgandhi 18:6a4db94011d3 2961
sahilmgandhi 18:6a4db94011d3 2962 /***************** Bit definition for SDIO_RESPCMD register *****************/
sahilmgandhi 18:6a4db94011d3 2963 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
sahilmgandhi 18:6a4db94011d3 2964
sahilmgandhi 18:6a4db94011d3 2965 /****************** Bit definition for SDIO_RESP0 register ******************/
sahilmgandhi 18:6a4db94011d3 2966 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 2967
sahilmgandhi 18:6a4db94011d3 2968 /****************** Bit definition for SDIO_RESP1 register ******************/
sahilmgandhi 18:6a4db94011d3 2969 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 2970
sahilmgandhi 18:6a4db94011d3 2971 /****************** Bit definition for SDIO_RESP2 register ******************/
sahilmgandhi 18:6a4db94011d3 2972 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 2973
sahilmgandhi 18:6a4db94011d3 2974 /****************** Bit definition for SDIO_RESP3 register ******************/
sahilmgandhi 18:6a4db94011d3 2975 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 2976
sahilmgandhi 18:6a4db94011d3 2977 /****************** Bit definition for SDIO_RESP4 register ******************/
sahilmgandhi 18:6a4db94011d3 2978 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 2979
sahilmgandhi 18:6a4db94011d3 2980 /****************** Bit definition for SDIO_DTIMER register *****************/
sahilmgandhi 18:6a4db94011d3 2981 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
sahilmgandhi 18:6a4db94011d3 2982
sahilmgandhi 18:6a4db94011d3 2983 /****************** Bit definition for SDIO_DLEN register *******************/
sahilmgandhi 18:6a4db94011d3 2984 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
sahilmgandhi 18:6a4db94011d3 2985
sahilmgandhi 18:6a4db94011d3 2986 /****************** Bit definition for SDIO_DCTRL register ******************/
sahilmgandhi 18:6a4db94011d3 2987 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
sahilmgandhi 18:6a4db94011d3 2988 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
sahilmgandhi 18:6a4db94011d3 2989 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
sahilmgandhi 18:6a4db94011d3 2990 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
sahilmgandhi 18:6a4db94011d3 2991
sahilmgandhi 18:6a4db94011d3 2992 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
sahilmgandhi 18:6a4db94011d3 2993 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2994 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2995 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2996 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2997
sahilmgandhi 18:6a4db94011d3 2998 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
sahilmgandhi 18:6a4db94011d3 2999 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
sahilmgandhi 18:6a4db94011d3 3000 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
sahilmgandhi 18:6a4db94011d3 3001 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
sahilmgandhi 18:6a4db94011d3 3002
sahilmgandhi 18:6a4db94011d3 3003 /****************** Bit definition for SDIO_DCOUNT register *****************/
sahilmgandhi 18:6a4db94011d3 3004 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
sahilmgandhi 18:6a4db94011d3 3005
sahilmgandhi 18:6a4db94011d3 3006 /****************** Bit definition for SDIO_STA register ********************/
sahilmgandhi 18:6a4db94011d3 3007 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
sahilmgandhi 18:6a4db94011d3 3008 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
sahilmgandhi 18:6a4db94011d3 3009 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
sahilmgandhi 18:6a4db94011d3 3010 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
sahilmgandhi 18:6a4db94011d3 3011 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
sahilmgandhi 18:6a4db94011d3 3012 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
sahilmgandhi 18:6a4db94011d3 3013 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
sahilmgandhi 18:6a4db94011d3 3014 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
sahilmgandhi 18:6a4db94011d3 3015 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
sahilmgandhi 18:6a4db94011d3 3016 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
sahilmgandhi 18:6a4db94011d3 3017 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
sahilmgandhi 18:6a4db94011d3 3018 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
sahilmgandhi 18:6a4db94011d3 3019 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
sahilmgandhi 18:6a4db94011d3 3020 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
sahilmgandhi 18:6a4db94011d3 3021 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
sahilmgandhi 18:6a4db94011d3 3022 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
sahilmgandhi 18:6a4db94011d3 3023 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
sahilmgandhi 18:6a4db94011d3 3024 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
sahilmgandhi 18:6a4db94011d3 3025 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
sahilmgandhi 18:6a4db94011d3 3026 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
sahilmgandhi 18:6a4db94011d3 3027 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
sahilmgandhi 18:6a4db94011d3 3028 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
sahilmgandhi 18:6a4db94011d3 3029 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
sahilmgandhi 18:6a4db94011d3 3030 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
sahilmgandhi 18:6a4db94011d3 3031
sahilmgandhi 18:6a4db94011d3 3032 /******************* Bit definition for SDIO_ICR register *******************/
sahilmgandhi 18:6a4db94011d3 3033 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
sahilmgandhi 18:6a4db94011d3 3034 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
sahilmgandhi 18:6a4db94011d3 3035 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
sahilmgandhi 18:6a4db94011d3 3036 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
sahilmgandhi 18:6a4db94011d3 3037 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 3038 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 3039 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
sahilmgandhi 18:6a4db94011d3 3040 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
sahilmgandhi 18:6a4db94011d3 3041 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 3042 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 3043 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 3044 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
sahilmgandhi 18:6a4db94011d3 3045 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 3046
sahilmgandhi 18:6a4db94011d3 3047 /****************** Bit definition for SDIO_MASK register *******************/
sahilmgandhi 18:6a4db94011d3 3048 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3049 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3050 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3051 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3052 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3053 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3054 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3055 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3056 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3057 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3058 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3059 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3060 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3061 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
sahilmgandhi 18:6a4db94011d3 3062 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3063 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3064 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3065 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3066 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3067 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3068 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3069 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3070 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3071 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3072
sahilmgandhi 18:6a4db94011d3 3073 /***************** Bit definition for SDIO_FIFOCNT register *****************/
sahilmgandhi 18:6a4db94011d3 3074 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
sahilmgandhi 18:6a4db94011d3 3075
sahilmgandhi 18:6a4db94011d3 3076 /****************** Bit definition for SDIO_FIFO register *******************/
sahilmgandhi 18:6a4db94011d3 3077 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
sahilmgandhi 18:6a4db94011d3 3078
sahilmgandhi 18:6a4db94011d3 3079 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3080 /* */
sahilmgandhi 18:6a4db94011d3 3081 /* Serial Peripheral Interface */
sahilmgandhi 18:6a4db94011d3 3082 /* */
sahilmgandhi 18:6a4db94011d3 3083 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3084 /******************* Bit definition for SPI_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 3085 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
sahilmgandhi 18:6a4db94011d3 3086 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
sahilmgandhi 18:6a4db94011d3 3087 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
sahilmgandhi 18:6a4db94011d3 3088
sahilmgandhi 18:6a4db94011d3 3089 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
sahilmgandhi 18:6a4db94011d3 3090 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3091 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3092 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3093
sahilmgandhi 18:6a4db94011d3 3094 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
sahilmgandhi 18:6a4db94011d3 3095 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
sahilmgandhi 18:6a4db94011d3 3096 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
sahilmgandhi 18:6a4db94011d3 3097 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
sahilmgandhi 18:6a4db94011d3 3098 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
sahilmgandhi 18:6a4db94011d3 3099 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
sahilmgandhi 18:6a4db94011d3 3100 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
sahilmgandhi 18:6a4db94011d3 3101 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
sahilmgandhi 18:6a4db94011d3 3102 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
sahilmgandhi 18:6a4db94011d3 3103 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
sahilmgandhi 18:6a4db94011d3 3104
sahilmgandhi 18:6a4db94011d3 3105 /******************* Bit definition for SPI_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 3106 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 3107 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 3108 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
sahilmgandhi 18:6a4db94011d3 3109 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
sahilmgandhi 18:6a4db94011d3 3110 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3111 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3112 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3113
sahilmgandhi 18:6a4db94011d3 3114 /******************** Bit definition for SPI_SR register ********************/
sahilmgandhi 18:6a4db94011d3 3115 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
sahilmgandhi 18:6a4db94011d3 3116 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
sahilmgandhi 18:6a4db94011d3 3117 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
sahilmgandhi 18:6a4db94011d3 3118 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
sahilmgandhi 18:6a4db94011d3 3119 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
sahilmgandhi 18:6a4db94011d3 3120 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
sahilmgandhi 18:6a4db94011d3 3121 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
sahilmgandhi 18:6a4db94011d3 3122 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
sahilmgandhi 18:6a4db94011d3 3123 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
sahilmgandhi 18:6a4db94011d3 3124
sahilmgandhi 18:6a4db94011d3 3125 /******************** Bit definition for SPI_DR register ********************/
sahilmgandhi 18:6a4db94011d3 3126 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
sahilmgandhi 18:6a4db94011d3 3127
sahilmgandhi 18:6a4db94011d3 3128 /******************* Bit definition for SPI_CRCPR register ******************/
sahilmgandhi 18:6a4db94011d3 3129 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
sahilmgandhi 18:6a4db94011d3 3130
sahilmgandhi 18:6a4db94011d3 3131 /****************** Bit definition for SPI_RXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 3132 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
sahilmgandhi 18:6a4db94011d3 3133
sahilmgandhi 18:6a4db94011d3 3134 /****************** Bit definition for SPI_TXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 3135 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
sahilmgandhi 18:6a4db94011d3 3136
sahilmgandhi 18:6a4db94011d3 3137 /****************** Bit definition for SPI_I2SCFGR register *****************/
sahilmgandhi 18:6a4db94011d3 3138 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
sahilmgandhi 18:6a4db94011d3 3139
sahilmgandhi 18:6a4db94011d3 3140 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
sahilmgandhi 18:6a4db94011d3 3141 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3142 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3143
sahilmgandhi 18:6a4db94011d3 3144 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
sahilmgandhi 18:6a4db94011d3 3145
sahilmgandhi 18:6a4db94011d3 3146 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
sahilmgandhi 18:6a4db94011d3 3147 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3148 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3149
sahilmgandhi 18:6a4db94011d3 3150 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
sahilmgandhi 18:6a4db94011d3 3151
sahilmgandhi 18:6a4db94011d3 3152 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
sahilmgandhi 18:6a4db94011d3 3153 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3154 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3155
sahilmgandhi 18:6a4db94011d3 3156 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
sahilmgandhi 18:6a4db94011d3 3157 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
sahilmgandhi 18:6a4db94011d3 3158
sahilmgandhi 18:6a4db94011d3 3159 /****************** Bit definition for SPI_I2SPR register *******************/
sahilmgandhi 18:6a4db94011d3 3160 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
sahilmgandhi 18:6a4db94011d3 3161 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
sahilmgandhi 18:6a4db94011d3 3162 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
sahilmgandhi 18:6a4db94011d3 3163
sahilmgandhi 18:6a4db94011d3 3164 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3165 /* */
sahilmgandhi 18:6a4db94011d3 3166 /* SYSCFG */
sahilmgandhi 18:6a4db94011d3 3167 /* */
sahilmgandhi 18:6a4db94011d3 3168 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3169 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
sahilmgandhi 18:6a4db94011d3 3170 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
sahilmgandhi 18:6a4db94011d3 3171 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 3172 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 3173 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 3174
sahilmgandhi 18:6a4db94011d3 3175 /****************** Bit definition for SYSCFG_PMC register ******************/
sahilmgandhi 18:6a4db94011d3 3176 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 3177
sahilmgandhi 18:6a4db94011d3 3178 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
sahilmgandhi 18:6a4db94011d3 3179 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
sahilmgandhi 18:6a4db94011d3 3180 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
sahilmgandhi 18:6a4db94011d3 3181 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
sahilmgandhi 18:6a4db94011d3 3182 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
sahilmgandhi 18:6a4db94011d3 3183 /**
sahilmgandhi 18:6a4db94011d3 3184 * @brief EXTI0 configuration
sahilmgandhi 18:6a4db94011d3 3185 */
sahilmgandhi 18:6a4db94011d3 3186 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
sahilmgandhi 18:6a4db94011d3 3187 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
sahilmgandhi 18:6a4db94011d3 3188 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
sahilmgandhi 18:6a4db94011d3 3189 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
sahilmgandhi 18:6a4db94011d3 3190 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
sahilmgandhi 18:6a4db94011d3 3191 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
sahilmgandhi 18:6a4db94011d3 3192
sahilmgandhi 18:6a4db94011d3 3193 /**
sahilmgandhi 18:6a4db94011d3 3194 * @brief EXTI1 configuration
sahilmgandhi 18:6a4db94011d3 3195 */
sahilmgandhi 18:6a4db94011d3 3196 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
sahilmgandhi 18:6a4db94011d3 3197 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
sahilmgandhi 18:6a4db94011d3 3198 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
sahilmgandhi 18:6a4db94011d3 3199 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
sahilmgandhi 18:6a4db94011d3 3200 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
sahilmgandhi 18:6a4db94011d3 3201 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
sahilmgandhi 18:6a4db94011d3 3202
sahilmgandhi 18:6a4db94011d3 3203 /**
sahilmgandhi 18:6a4db94011d3 3204 * @brief EXTI2 configuration
sahilmgandhi 18:6a4db94011d3 3205 */
sahilmgandhi 18:6a4db94011d3 3206 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
sahilmgandhi 18:6a4db94011d3 3207 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
sahilmgandhi 18:6a4db94011d3 3208 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
sahilmgandhi 18:6a4db94011d3 3209 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
sahilmgandhi 18:6a4db94011d3 3210 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
sahilmgandhi 18:6a4db94011d3 3211 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
sahilmgandhi 18:6a4db94011d3 3212
sahilmgandhi 18:6a4db94011d3 3213 /**
sahilmgandhi 18:6a4db94011d3 3214 * @brief EXTI3 configuration
sahilmgandhi 18:6a4db94011d3 3215 */
sahilmgandhi 18:6a4db94011d3 3216 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
sahilmgandhi 18:6a4db94011d3 3217 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
sahilmgandhi 18:6a4db94011d3 3218 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
sahilmgandhi 18:6a4db94011d3 3219 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
sahilmgandhi 18:6a4db94011d3 3220 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
sahilmgandhi 18:6a4db94011d3 3221 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
sahilmgandhi 18:6a4db94011d3 3222
sahilmgandhi 18:6a4db94011d3 3223 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
sahilmgandhi 18:6a4db94011d3 3224 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
sahilmgandhi 18:6a4db94011d3 3225 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
sahilmgandhi 18:6a4db94011d3 3226 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
sahilmgandhi 18:6a4db94011d3 3227 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
sahilmgandhi 18:6a4db94011d3 3228 /**
sahilmgandhi 18:6a4db94011d3 3229 * @brief EXTI4 configuration
sahilmgandhi 18:6a4db94011d3 3230 */
sahilmgandhi 18:6a4db94011d3 3231 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
sahilmgandhi 18:6a4db94011d3 3232 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
sahilmgandhi 18:6a4db94011d3 3233 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
sahilmgandhi 18:6a4db94011d3 3234 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
sahilmgandhi 18:6a4db94011d3 3235 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
sahilmgandhi 18:6a4db94011d3 3236 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
sahilmgandhi 18:6a4db94011d3 3237
sahilmgandhi 18:6a4db94011d3 3238 /**
sahilmgandhi 18:6a4db94011d3 3239 * @brief EXTI5 configuration
sahilmgandhi 18:6a4db94011d3 3240 */
sahilmgandhi 18:6a4db94011d3 3241 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
sahilmgandhi 18:6a4db94011d3 3242 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
sahilmgandhi 18:6a4db94011d3 3243 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
sahilmgandhi 18:6a4db94011d3 3244 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
sahilmgandhi 18:6a4db94011d3 3245 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
sahilmgandhi 18:6a4db94011d3 3246 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
sahilmgandhi 18:6a4db94011d3 3247
sahilmgandhi 18:6a4db94011d3 3248 /**
sahilmgandhi 18:6a4db94011d3 3249 * @brief EXTI6 configuration
sahilmgandhi 18:6a4db94011d3 3250 */
sahilmgandhi 18:6a4db94011d3 3251 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
sahilmgandhi 18:6a4db94011d3 3252 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
sahilmgandhi 18:6a4db94011d3 3253 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
sahilmgandhi 18:6a4db94011d3 3254 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
sahilmgandhi 18:6a4db94011d3 3255 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
sahilmgandhi 18:6a4db94011d3 3256 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
sahilmgandhi 18:6a4db94011d3 3257
sahilmgandhi 18:6a4db94011d3 3258 /**
sahilmgandhi 18:6a4db94011d3 3259 * @brief EXTI7 configuration
sahilmgandhi 18:6a4db94011d3 3260 */
sahilmgandhi 18:6a4db94011d3 3261 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
sahilmgandhi 18:6a4db94011d3 3262 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
sahilmgandhi 18:6a4db94011d3 3263 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
sahilmgandhi 18:6a4db94011d3 3264 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
sahilmgandhi 18:6a4db94011d3 3265 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
sahilmgandhi 18:6a4db94011d3 3266 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
sahilmgandhi 18:6a4db94011d3 3267
sahilmgandhi 18:6a4db94011d3 3268
sahilmgandhi 18:6a4db94011d3 3269 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
sahilmgandhi 18:6a4db94011d3 3270 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
sahilmgandhi 18:6a4db94011d3 3271 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
sahilmgandhi 18:6a4db94011d3 3272 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
sahilmgandhi 18:6a4db94011d3 3273 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
sahilmgandhi 18:6a4db94011d3 3274
sahilmgandhi 18:6a4db94011d3 3275 /**
sahilmgandhi 18:6a4db94011d3 3276 * @brief EXTI8 configuration
sahilmgandhi 18:6a4db94011d3 3277 */
sahilmgandhi 18:6a4db94011d3 3278 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
sahilmgandhi 18:6a4db94011d3 3279 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
sahilmgandhi 18:6a4db94011d3 3280 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
sahilmgandhi 18:6a4db94011d3 3281 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
sahilmgandhi 18:6a4db94011d3 3282 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
sahilmgandhi 18:6a4db94011d3 3283 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
sahilmgandhi 18:6a4db94011d3 3284
sahilmgandhi 18:6a4db94011d3 3285 /**
sahilmgandhi 18:6a4db94011d3 3286 * @brief EXTI9 configuration
sahilmgandhi 18:6a4db94011d3 3287 */
sahilmgandhi 18:6a4db94011d3 3288 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
sahilmgandhi 18:6a4db94011d3 3289 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
sahilmgandhi 18:6a4db94011d3 3290 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
sahilmgandhi 18:6a4db94011d3 3291 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
sahilmgandhi 18:6a4db94011d3 3292 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
sahilmgandhi 18:6a4db94011d3 3293 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
sahilmgandhi 18:6a4db94011d3 3294
sahilmgandhi 18:6a4db94011d3 3295 /**
sahilmgandhi 18:6a4db94011d3 3296 * @brief EXTI10 configuration
sahilmgandhi 18:6a4db94011d3 3297 */
sahilmgandhi 18:6a4db94011d3 3298 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
sahilmgandhi 18:6a4db94011d3 3299 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
sahilmgandhi 18:6a4db94011d3 3300 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
sahilmgandhi 18:6a4db94011d3 3301 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
sahilmgandhi 18:6a4db94011d3 3302 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
sahilmgandhi 18:6a4db94011d3 3303 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
sahilmgandhi 18:6a4db94011d3 3304
sahilmgandhi 18:6a4db94011d3 3305 /**
sahilmgandhi 18:6a4db94011d3 3306 * @brief EXTI11 configuration
sahilmgandhi 18:6a4db94011d3 3307 */
sahilmgandhi 18:6a4db94011d3 3308 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
sahilmgandhi 18:6a4db94011d3 3309 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
sahilmgandhi 18:6a4db94011d3 3310 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
sahilmgandhi 18:6a4db94011d3 3311 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
sahilmgandhi 18:6a4db94011d3 3312 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
sahilmgandhi 18:6a4db94011d3 3313 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
sahilmgandhi 18:6a4db94011d3 3314
sahilmgandhi 18:6a4db94011d3 3315 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
sahilmgandhi 18:6a4db94011d3 3316 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
sahilmgandhi 18:6a4db94011d3 3317 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
sahilmgandhi 18:6a4db94011d3 3318 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
sahilmgandhi 18:6a4db94011d3 3319 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
sahilmgandhi 18:6a4db94011d3 3320 /**
sahilmgandhi 18:6a4db94011d3 3321 * @brief EXTI12 configuration
sahilmgandhi 18:6a4db94011d3 3322 */
sahilmgandhi 18:6a4db94011d3 3323 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
sahilmgandhi 18:6a4db94011d3 3324 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
sahilmgandhi 18:6a4db94011d3 3325 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
sahilmgandhi 18:6a4db94011d3 3326 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
sahilmgandhi 18:6a4db94011d3 3327 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
sahilmgandhi 18:6a4db94011d3 3328 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
sahilmgandhi 18:6a4db94011d3 3329
sahilmgandhi 18:6a4db94011d3 3330 /**
sahilmgandhi 18:6a4db94011d3 3331 * @brief EXTI13 configuration
sahilmgandhi 18:6a4db94011d3 3332 */
sahilmgandhi 18:6a4db94011d3 3333 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
sahilmgandhi 18:6a4db94011d3 3334 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
sahilmgandhi 18:6a4db94011d3 3335 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
sahilmgandhi 18:6a4db94011d3 3336 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
sahilmgandhi 18:6a4db94011d3 3337 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
sahilmgandhi 18:6a4db94011d3 3338 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
sahilmgandhi 18:6a4db94011d3 3339
sahilmgandhi 18:6a4db94011d3 3340 /**
sahilmgandhi 18:6a4db94011d3 3341 * @brief EXTI14 configuration
sahilmgandhi 18:6a4db94011d3 3342 */
sahilmgandhi 18:6a4db94011d3 3343 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
sahilmgandhi 18:6a4db94011d3 3344 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
sahilmgandhi 18:6a4db94011d3 3345 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
sahilmgandhi 18:6a4db94011d3 3346 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
sahilmgandhi 18:6a4db94011d3 3347 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
sahilmgandhi 18:6a4db94011d3 3348 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
sahilmgandhi 18:6a4db94011d3 3349
sahilmgandhi 18:6a4db94011d3 3350 /**
sahilmgandhi 18:6a4db94011d3 3351 * @brief EXTI15 configuration
sahilmgandhi 18:6a4db94011d3 3352 */
sahilmgandhi 18:6a4db94011d3 3353 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
sahilmgandhi 18:6a4db94011d3 3354 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
sahilmgandhi 18:6a4db94011d3 3355 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
sahilmgandhi 18:6a4db94011d3 3356 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
sahilmgandhi 18:6a4db94011d3 3357 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
sahilmgandhi 18:6a4db94011d3 3358 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
sahilmgandhi 18:6a4db94011d3 3359
sahilmgandhi 18:6a4db94011d3 3360 /****************** Bit definition for SYSCFG_CMPCR register ****************/
sahilmgandhi 18:6a4db94011d3 3361 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
sahilmgandhi 18:6a4db94011d3 3362 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
sahilmgandhi 18:6a4db94011d3 3363
sahilmgandhi 18:6a4db94011d3 3364 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3365 /* */
sahilmgandhi 18:6a4db94011d3 3366 /* TIM */
sahilmgandhi 18:6a4db94011d3 3367 /* */
sahilmgandhi 18:6a4db94011d3 3368 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3369 /******************* Bit definition for TIM_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 3370 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
sahilmgandhi 18:6a4db94011d3 3371 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
sahilmgandhi 18:6a4db94011d3 3372 #define TIM_CR1_URS 0x0004U /*!<Update request source */
sahilmgandhi 18:6a4db94011d3 3373 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
sahilmgandhi 18:6a4db94011d3 3374 #define TIM_CR1_DIR 0x0010U /*!<Direction */
sahilmgandhi 18:6a4db94011d3 3375
sahilmgandhi 18:6a4db94011d3 3376 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
sahilmgandhi 18:6a4db94011d3 3377 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3378 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3379
sahilmgandhi 18:6a4db94011d3 3380 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
sahilmgandhi 18:6a4db94011d3 3381
sahilmgandhi 18:6a4db94011d3 3382 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
sahilmgandhi 18:6a4db94011d3 3383 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3384 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3385
sahilmgandhi 18:6a4db94011d3 3386 /******************* Bit definition for TIM_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 3387 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
sahilmgandhi 18:6a4db94011d3 3388 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
sahilmgandhi 18:6a4db94011d3 3389 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
sahilmgandhi 18:6a4db94011d3 3390
sahilmgandhi 18:6a4db94011d3 3391 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
sahilmgandhi 18:6a4db94011d3 3392 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3393 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3394 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3395
sahilmgandhi 18:6a4db94011d3 3396 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
sahilmgandhi 18:6a4db94011d3 3397 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
sahilmgandhi 18:6a4db94011d3 3398 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
sahilmgandhi 18:6a4db94011d3 3399 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
sahilmgandhi 18:6a4db94011d3 3400 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
sahilmgandhi 18:6a4db94011d3 3401 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
sahilmgandhi 18:6a4db94011d3 3402 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
sahilmgandhi 18:6a4db94011d3 3403 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
sahilmgandhi 18:6a4db94011d3 3404
sahilmgandhi 18:6a4db94011d3 3405 /******************* Bit definition for TIM_SMCR register *******************/
sahilmgandhi 18:6a4db94011d3 3406 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
sahilmgandhi 18:6a4db94011d3 3407 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3408 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3409 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3410
sahilmgandhi 18:6a4db94011d3 3411 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
sahilmgandhi 18:6a4db94011d3 3412 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3413 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3414 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3415
sahilmgandhi 18:6a4db94011d3 3416 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
sahilmgandhi 18:6a4db94011d3 3417
sahilmgandhi 18:6a4db94011d3 3418 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
sahilmgandhi 18:6a4db94011d3 3419 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3420 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3421 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3422 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3423
sahilmgandhi 18:6a4db94011d3 3424 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
sahilmgandhi 18:6a4db94011d3 3425 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3426 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3427
sahilmgandhi 18:6a4db94011d3 3428 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
sahilmgandhi 18:6a4db94011d3 3429 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
sahilmgandhi 18:6a4db94011d3 3430
sahilmgandhi 18:6a4db94011d3 3431 /******************* Bit definition for TIM_DIER register *******************/
sahilmgandhi 18:6a4db94011d3 3432 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
sahilmgandhi 18:6a4db94011d3 3433 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
sahilmgandhi 18:6a4db94011d3 3434 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
sahilmgandhi 18:6a4db94011d3 3435 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
sahilmgandhi 18:6a4db94011d3 3436 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
sahilmgandhi 18:6a4db94011d3 3437 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
sahilmgandhi 18:6a4db94011d3 3438 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
sahilmgandhi 18:6a4db94011d3 3439 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
sahilmgandhi 18:6a4db94011d3 3440 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
sahilmgandhi 18:6a4db94011d3 3441 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
sahilmgandhi 18:6a4db94011d3 3442 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
sahilmgandhi 18:6a4db94011d3 3443 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
sahilmgandhi 18:6a4db94011d3 3444 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
sahilmgandhi 18:6a4db94011d3 3445 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
sahilmgandhi 18:6a4db94011d3 3446 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
sahilmgandhi 18:6a4db94011d3 3447
sahilmgandhi 18:6a4db94011d3 3448 /******************** Bit definition for TIM_SR register ********************/
sahilmgandhi 18:6a4db94011d3 3449 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3450 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3451 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3452 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3453 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3454 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3455 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3456 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3457 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 3458 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 3459 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 3460 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 3461
sahilmgandhi 18:6a4db94011d3 3462 /******************* Bit definition for TIM_EGR register ********************/
sahilmgandhi 18:6a4db94011d3 3463 #define TIM_EGR_UG 0x01U /*!<Update Generation */
sahilmgandhi 18:6a4db94011d3 3464 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
sahilmgandhi 18:6a4db94011d3 3465 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
sahilmgandhi 18:6a4db94011d3 3466 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
sahilmgandhi 18:6a4db94011d3 3467 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
sahilmgandhi 18:6a4db94011d3 3468 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
sahilmgandhi 18:6a4db94011d3 3469 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
sahilmgandhi 18:6a4db94011d3 3470 #define TIM_EGR_BG 0x80U /*!<Break Generation */
sahilmgandhi 18:6a4db94011d3 3471
sahilmgandhi 18:6a4db94011d3 3472 /****************** Bit definition for TIM_CCMR1 register *******************/
sahilmgandhi 18:6a4db94011d3 3473 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
sahilmgandhi 18:6a4db94011d3 3474 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3475 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3476
sahilmgandhi 18:6a4db94011d3 3477 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
sahilmgandhi 18:6a4db94011d3 3478 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
sahilmgandhi 18:6a4db94011d3 3479
sahilmgandhi 18:6a4db94011d3 3480 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
sahilmgandhi 18:6a4db94011d3 3481 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3482 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3483 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3484
sahilmgandhi 18:6a4db94011d3 3485 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
sahilmgandhi 18:6a4db94011d3 3486
sahilmgandhi 18:6a4db94011d3 3487 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
sahilmgandhi 18:6a4db94011d3 3488 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3489 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3490
sahilmgandhi 18:6a4db94011d3 3491 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
sahilmgandhi 18:6a4db94011d3 3492 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
sahilmgandhi 18:6a4db94011d3 3493
sahilmgandhi 18:6a4db94011d3 3494 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
sahilmgandhi 18:6a4db94011d3 3495 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3496 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3497 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3498
sahilmgandhi 18:6a4db94011d3 3499 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
sahilmgandhi 18:6a4db94011d3 3500
sahilmgandhi 18:6a4db94011d3 3501 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 3502
sahilmgandhi 18:6a4db94011d3 3503 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
sahilmgandhi 18:6a4db94011d3 3504 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3505 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3506
sahilmgandhi 18:6a4db94011d3 3507 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
sahilmgandhi 18:6a4db94011d3 3508 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3509 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3510 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3511 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3512
sahilmgandhi 18:6a4db94011d3 3513 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
sahilmgandhi 18:6a4db94011d3 3514 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3515 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3516
sahilmgandhi 18:6a4db94011d3 3517 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
sahilmgandhi 18:6a4db94011d3 3518 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3519 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3520 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3521 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3522
sahilmgandhi 18:6a4db94011d3 3523 /****************** Bit definition for TIM_CCMR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3524 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
sahilmgandhi 18:6a4db94011d3 3525 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3526 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3527
sahilmgandhi 18:6a4db94011d3 3528 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
sahilmgandhi 18:6a4db94011d3 3529 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
sahilmgandhi 18:6a4db94011d3 3530
sahilmgandhi 18:6a4db94011d3 3531 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
sahilmgandhi 18:6a4db94011d3 3532 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3533 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3534 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3535
sahilmgandhi 18:6a4db94011d3 3536 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
sahilmgandhi 18:6a4db94011d3 3537
sahilmgandhi 18:6a4db94011d3 3538 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
sahilmgandhi 18:6a4db94011d3 3539 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3540 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3541
sahilmgandhi 18:6a4db94011d3 3542 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
sahilmgandhi 18:6a4db94011d3 3543 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
sahilmgandhi 18:6a4db94011d3 3544
sahilmgandhi 18:6a4db94011d3 3545 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
sahilmgandhi 18:6a4db94011d3 3546 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3547 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3548 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3549
sahilmgandhi 18:6a4db94011d3 3550 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
sahilmgandhi 18:6a4db94011d3 3551
sahilmgandhi 18:6a4db94011d3 3552 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 3553
sahilmgandhi 18:6a4db94011d3 3554 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
sahilmgandhi 18:6a4db94011d3 3555 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3556 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3557
sahilmgandhi 18:6a4db94011d3 3558 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
sahilmgandhi 18:6a4db94011d3 3559 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3560 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3561 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3562 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3563
sahilmgandhi 18:6a4db94011d3 3564 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
sahilmgandhi 18:6a4db94011d3 3565 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3566 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3567
sahilmgandhi 18:6a4db94011d3 3568 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
sahilmgandhi 18:6a4db94011d3 3569 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3570 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3571 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3572 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3573
sahilmgandhi 18:6a4db94011d3 3574 /******************* Bit definition for TIM_CCER register *******************/
sahilmgandhi 18:6a4db94011d3 3575 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
sahilmgandhi 18:6a4db94011d3 3576 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
sahilmgandhi 18:6a4db94011d3 3577 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 3578 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 3579 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
sahilmgandhi 18:6a4db94011d3 3580 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
sahilmgandhi 18:6a4db94011d3 3581 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 3582 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 3583 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
sahilmgandhi 18:6a4db94011d3 3584 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
sahilmgandhi 18:6a4db94011d3 3585 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 3586 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 3587 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
sahilmgandhi 18:6a4db94011d3 3588 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
sahilmgandhi 18:6a4db94011d3 3589 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 3590
sahilmgandhi 18:6a4db94011d3 3591 /******************* Bit definition for TIM_CNT register ********************/
sahilmgandhi 18:6a4db94011d3 3592 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
sahilmgandhi 18:6a4db94011d3 3593
sahilmgandhi 18:6a4db94011d3 3594 /******************* Bit definition for TIM_PSC register ********************/
sahilmgandhi 18:6a4db94011d3 3595 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
sahilmgandhi 18:6a4db94011d3 3596
sahilmgandhi 18:6a4db94011d3 3597 /******************* Bit definition for TIM_ARR register ********************/
sahilmgandhi 18:6a4db94011d3 3598 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
sahilmgandhi 18:6a4db94011d3 3599
sahilmgandhi 18:6a4db94011d3 3600 /******************* Bit definition for TIM_RCR register ********************/
sahilmgandhi 18:6a4db94011d3 3601 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
sahilmgandhi 18:6a4db94011d3 3602
sahilmgandhi 18:6a4db94011d3 3603 /******************* Bit definition for TIM_CCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 3604 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
sahilmgandhi 18:6a4db94011d3 3605
sahilmgandhi 18:6a4db94011d3 3606 /******************* Bit definition for TIM_CCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3607 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
sahilmgandhi 18:6a4db94011d3 3608
sahilmgandhi 18:6a4db94011d3 3609 /******************* Bit definition for TIM_CCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 3610 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
sahilmgandhi 18:6a4db94011d3 3611
sahilmgandhi 18:6a4db94011d3 3612 /******************* Bit definition for TIM_CCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 3613 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
sahilmgandhi 18:6a4db94011d3 3614
sahilmgandhi 18:6a4db94011d3 3615 /******************* Bit definition for TIM_BDTR register *******************/
sahilmgandhi 18:6a4db94011d3 3616 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
sahilmgandhi 18:6a4db94011d3 3617 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3618 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3619 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3620 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3621 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3622 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3623 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3624 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3625
sahilmgandhi 18:6a4db94011d3 3626 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
sahilmgandhi 18:6a4db94011d3 3627 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3628 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3629
sahilmgandhi 18:6a4db94011d3 3630 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
sahilmgandhi 18:6a4db94011d3 3631 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
sahilmgandhi 18:6a4db94011d3 3632 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
sahilmgandhi 18:6a4db94011d3 3633 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
sahilmgandhi 18:6a4db94011d3 3634 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
sahilmgandhi 18:6a4db94011d3 3635 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
sahilmgandhi 18:6a4db94011d3 3636
sahilmgandhi 18:6a4db94011d3 3637 /******************* Bit definition for TIM_DCR register ********************/
sahilmgandhi 18:6a4db94011d3 3638 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
sahilmgandhi 18:6a4db94011d3 3639 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3640 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3641 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3642 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3643 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3644
sahilmgandhi 18:6a4db94011d3 3645 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
sahilmgandhi 18:6a4db94011d3 3646 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3647 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3648 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3649 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3650 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3651
sahilmgandhi 18:6a4db94011d3 3652 /******************* Bit definition for TIM_DMAR register *******************/
sahilmgandhi 18:6a4db94011d3 3653 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
sahilmgandhi 18:6a4db94011d3 3654
sahilmgandhi 18:6a4db94011d3 3655 /******************* Bit definition for TIM_OR register *********************/
sahilmgandhi 18:6a4db94011d3 3656 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
sahilmgandhi 18:6a4db94011d3 3657 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3658 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3659 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
sahilmgandhi 18:6a4db94011d3 3660 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3661 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3662
sahilmgandhi 18:6a4db94011d3 3663
sahilmgandhi 18:6a4db94011d3 3664 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3665 /* */
sahilmgandhi 18:6a4db94011d3 3666 /* Universal Synchronous Asynchronous Receiver Transmitter */
sahilmgandhi 18:6a4db94011d3 3667 /* */
sahilmgandhi 18:6a4db94011d3 3668 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3669 /******************* Bit definition for USART_SR register *******************/
sahilmgandhi 18:6a4db94011d3 3670 #define USART_SR_PE 0x0001U /*!<Parity Error */
sahilmgandhi 18:6a4db94011d3 3671 #define USART_SR_FE 0x0002U /*!<Framing Error */
sahilmgandhi 18:6a4db94011d3 3672 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
sahilmgandhi 18:6a4db94011d3 3673 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
sahilmgandhi 18:6a4db94011d3 3674 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
sahilmgandhi 18:6a4db94011d3 3675 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
sahilmgandhi 18:6a4db94011d3 3676 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
sahilmgandhi 18:6a4db94011d3 3677 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
sahilmgandhi 18:6a4db94011d3 3678 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
sahilmgandhi 18:6a4db94011d3 3679 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
sahilmgandhi 18:6a4db94011d3 3680
sahilmgandhi 18:6a4db94011d3 3681 /******************* Bit definition for USART_DR register *******************/
sahilmgandhi 18:6a4db94011d3 3682 #define USART_DR_DR 0x01FFU /*!<Data value */
sahilmgandhi 18:6a4db94011d3 3683
sahilmgandhi 18:6a4db94011d3 3684 /****************** Bit definition for USART_BRR register *******************/
sahilmgandhi 18:6a4db94011d3 3685 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
sahilmgandhi 18:6a4db94011d3 3686 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
sahilmgandhi 18:6a4db94011d3 3687
sahilmgandhi 18:6a4db94011d3 3688 /****************** Bit definition for USART_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 3689 #define USART_CR1_SBK 0x0001U /*!<Send Break */
sahilmgandhi 18:6a4db94011d3 3690 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
sahilmgandhi 18:6a4db94011d3 3691 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
sahilmgandhi 18:6a4db94011d3 3692 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
sahilmgandhi 18:6a4db94011d3 3693 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3694 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3695 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3696 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3697 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3698 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
sahilmgandhi 18:6a4db94011d3 3699 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
sahilmgandhi 18:6a4db94011d3 3700 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
sahilmgandhi 18:6a4db94011d3 3701 #define USART_CR1_M 0x1000U /*!<Word length */
sahilmgandhi 18:6a4db94011d3 3702 #define USART_CR1_UE 0x2000U /*!<USART Enable */
sahilmgandhi 18:6a4db94011d3 3703 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
sahilmgandhi 18:6a4db94011d3 3704
sahilmgandhi 18:6a4db94011d3 3705 /****************** Bit definition for USART_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3706 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
sahilmgandhi 18:6a4db94011d3 3707 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
sahilmgandhi 18:6a4db94011d3 3708 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3709 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
sahilmgandhi 18:6a4db94011d3 3710 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
sahilmgandhi 18:6a4db94011d3 3711 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
sahilmgandhi 18:6a4db94011d3 3712 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
sahilmgandhi 18:6a4db94011d3 3713
sahilmgandhi 18:6a4db94011d3 3714 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
sahilmgandhi 18:6a4db94011d3 3715 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3716 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3717
sahilmgandhi 18:6a4db94011d3 3718 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
sahilmgandhi 18:6a4db94011d3 3719
sahilmgandhi 18:6a4db94011d3 3720 /****************** Bit definition for USART_CR3 register *******************/
sahilmgandhi 18:6a4db94011d3 3721 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3722 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
sahilmgandhi 18:6a4db94011d3 3723 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
sahilmgandhi 18:6a4db94011d3 3724 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
sahilmgandhi 18:6a4db94011d3 3725 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
sahilmgandhi 18:6a4db94011d3 3726 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
sahilmgandhi 18:6a4db94011d3 3727 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
sahilmgandhi 18:6a4db94011d3 3728 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
sahilmgandhi 18:6a4db94011d3 3729 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
sahilmgandhi 18:6a4db94011d3 3730 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
sahilmgandhi 18:6a4db94011d3 3731 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3732 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
sahilmgandhi 18:6a4db94011d3 3733
sahilmgandhi 18:6a4db94011d3 3734 /****************** Bit definition for USART_GTPR register ******************/
sahilmgandhi 18:6a4db94011d3 3735 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
sahilmgandhi 18:6a4db94011d3 3736 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3737 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3738 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3739 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3740 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3741 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3742 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3743 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3744
sahilmgandhi 18:6a4db94011d3 3745 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
sahilmgandhi 18:6a4db94011d3 3746
sahilmgandhi 18:6a4db94011d3 3747 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3748 /* */
sahilmgandhi 18:6a4db94011d3 3749 /* Window WATCHDOG */
sahilmgandhi 18:6a4db94011d3 3750 /* */
sahilmgandhi 18:6a4db94011d3 3751 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3752 /******************* Bit definition for WWDG_CR register ********************/
sahilmgandhi 18:6a4db94011d3 3753 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
sahilmgandhi 18:6a4db94011d3 3754 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3755 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3756 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3757 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3758 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3759 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3760 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3761 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3762 #define WWDG_CR_T0 WWDG_CR_T_0
sahilmgandhi 18:6a4db94011d3 3763 #define WWDG_CR_T1 WWDG_CR_T_1
sahilmgandhi 18:6a4db94011d3 3764 #define WWDG_CR_T2 WWDG_CR_T_2
sahilmgandhi 18:6a4db94011d3 3765 #define WWDG_CR_T3 WWDG_CR_T_3
sahilmgandhi 18:6a4db94011d3 3766 #define WWDG_CR_T4 WWDG_CR_T_4
sahilmgandhi 18:6a4db94011d3 3767 #define WWDG_CR_T5 WWDG_CR_T_5
sahilmgandhi 18:6a4db94011d3 3768 #define WWDG_CR_T6 WWDG_CR_T_6
sahilmgandhi 18:6a4db94011d3 3769
sahilmgandhi 18:6a4db94011d3 3770 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
sahilmgandhi 18:6a4db94011d3 3771
sahilmgandhi 18:6a4db94011d3 3772 /******************* Bit definition for WWDG_CFR register *******************/
sahilmgandhi 18:6a4db94011d3 3773 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
sahilmgandhi 18:6a4db94011d3 3774 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3775 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3776 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3777 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3778 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3779 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3780 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3781 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3782 #define WWDG_CFR_W0 WWDG_CFR_W_0
sahilmgandhi 18:6a4db94011d3 3783 #define WWDG_CFR_W1 WWDG_CFR_W_1
sahilmgandhi 18:6a4db94011d3 3784 #define WWDG_CFR_W2 WWDG_CFR_W_2
sahilmgandhi 18:6a4db94011d3 3785 #define WWDG_CFR_W3 WWDG_CFR_W_3
sahilmgandhi 18:6a4db94011d3 3786 #define WWDG_CFR_W4 WWDG_CFR_W_4
sahilmgandhi 18:6a4db94011d3 3787 #define WWDG_CFR_W5 WWDG_CFR_W_5
sahilmgandhi 18:6a4db94011d3 3788 #define WWDG_CFR_W6 WWDG_CFR_W_6
sahilmgandhi 18:6a4db94011d3 3789
sahilmgandhi 18:6a4db94011d3 3790 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
sahilmgandhi 18:6a4db94011d3 3791 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3792 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3793 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3794 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
sahilmgandhi 18:6a4db94011d3 3795 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
sahilmgandhi 18:6a4db94011d3 3796
sahilmgandhi 18:6a4db94011d3 3797 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 3798
sahilmgandhi 18:6a4db94011d3 3799 /******************* Bit definition for WWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 3800 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 3801
sahilmgandhi 18:6a4db94011d3 3802
sahilmgandhi 18:6a4db94011d3 3803 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3804 /* */
sahilmgandhi 18:6a4db94011d3 3805 /* DBG */
sahilmgandhi 18:6a4db94011d3 3806 /* */
sahilmgandhi 18:6a4db94011d3 3807 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3808 /******************** Bit definition for DBGMCU_IDCODE register *************/
sahilmgandhi 18:6a4db94011d3 3809 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
sahilmgandhi 18:6a4db94011d3 3810 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
sahilmgandhi 18:6a4db94011d3 3811
sahilmgandhi 18:6a4db94011d3 3812 /******************** Bit definition for DBGMCU_CR register *****************/
sahilmgandhi 18:6a4db94011d3 3813 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
sahilmgandhi 18:6a4db94011d3 3814 #define DBGMCU_CR_DBG_STOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 3815 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
sahilmgandhi 18:6a4db94011d3 3816 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 3817
sahilmgandhi 18:6a4db94011d3 3818 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
sahilmgandhi 18:6a4db94011d3 3819 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3820 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3821
sahilmgandhi 18:6a4db94011d3 3822 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
sahilmgandhi 18:6a4db94011d3 3823 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
sahilmgandhi 18:6a4db94011d3 3824 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 3825 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
sahilmgandhi 18:6a4db94011d3 3826 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
sahilmgandhi 18:6a4db94011d3 3827 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
sahilmgandhi 18:6a4db94011d3 3828 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
sahilmgandhi 18:6a4db94011d3 3829 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
sahilmgandhi 18:6a4db94011d3 3830 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
sahilmgandhi 18:6a4db94011d3 3831 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
sahilmgandhi 18:6a4db94011d3 3832 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
sahilmgandhi 18:6a4db94011d3 3833 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
sahilmgandhi 18:6a4db94011d3 3834 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
sahilmgandhi 18:6a4db94011d3 3835 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
sahilmgandhi 18:6a4db94011d3 3836 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
sahilmgandhi 18:6a4db94011d3 3837 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
sahilmgandhi 18:6a4db94011d3 3838 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
sahilmgandhi 18:6a4db94011d3 3839 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
sahilmgandhi 18:6a4db94011d3 3840 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 3841 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
sahilmgandhi 18:6a4db94011d3 3842
sahilmgandhi 18:6a4db94011d3 3843 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
sahilmgandhi 18:6a4db94011d3 3844 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
sahilmgandhi 18:6a4db94011d3 3845 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 3846 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
sahilmgandhi 18:6a4db94011d3 3847 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
sahilmgandhi 18:6a4db94011d3 3848 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
sahilmgandhi 18:6a4db94011d3 3849
sahilmgandhi 18:6a4db94011d3 3850 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3851 /* */
sahilmgandhi 18:6a4db94011d3 3852 /* USB_OTG */
sahilmgandhi 18:6a4db94011d3 3853 /* */
sahilmgandhi 18:6a4db94011d3 3854 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3855 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
sahilmgandhi 18:6a4db94011d3 3856 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
sahilmgandhi 18:6a4db94011d3 3857 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
sahilmgandhi 18:6a4db94011d3 3858 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
sahilmgandhi 18:6a4db94011d3 3859 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
sahilmgandhi 18:6a4db94011d3 3860 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
sahilmgandhi 18:6a4db94011d3 3861 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
sahilmgandhi 18:6a4db94011d3 3862 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
sahilmgandhi 18:6a4db94011d3 3863 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
sahilmgandhi 18:6a4db94011d3 3864 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
sahilmgandhi 18:6a4db94011d3 3865 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
sahilmgandhi 18:6a4db94011d3 3866
sahilmgandhi 18:6a4db94011d3 3867 /******************** Bit definition forUSB_OTG_HCFG register ********************/
sahilmgandhi 18:6a4db94011d3 3868
sahilmgandhi 18:6a4db94011d3 3869 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
sahilmgandhi 18:6a4db94011d3 3870 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3871 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3872 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
sahilmgandhi 18:6a4db94011d3 3873
sahilmgandhi 18:6a4db94011d3 3874 /******************** Bit definition forUSB_OTG_DCFG register ********************/
sahilmgandhi 18:6a4db94011d3 3875
sahilmgandhi 18:6a4db94011d3 3876 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
sahilmgandhi 18:6a4db94011d3 3877 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3878 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3879 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
sahilmgandhi 18:6a4db94011d3 3880
sahilmgandhi 18:6a4db94011d3 3881 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
sahilmgandhi 18:6a4db94011d3 3882 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3883 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3884 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3885 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3886 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3887 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3888 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3889
sahilmgandhi 18:6a4db94011d3 3890 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
sahilmgandhi 18:6a4db94011d3 3891 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3892 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3893
sahilmgandhi 18:6a4db94011d3 3894 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
sahilmgandhi 18:6a4db94011d3 3895 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3896 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3897
sahilmgandhi 18:6a4db94011d3 3898 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
sahilmgandhi 18:6a4db94011d3 3899 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
sahilmgandhi 18:6a4db94011d3 3900 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
sahilmgandhi 18:6a4db94011d3 3901 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
sahilmgandhi 18:6a4db94011d3 3902
sahilmgandhi 18:6a4db94011d3 3903 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
sahilmgandhi 18:6a4db94011d3 3904 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
sahilmgandhi 18:6a4db94011d3 3905 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
sahilmgandhi 18:6a4db94011d3 3906 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
sahilmgandhi 18:6a4db94011d3 3907 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
sahilmgandhi 18:6a4db94011d3 3908 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
sahilmgandhi 18:6a4db94011d3 3909 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
sahilmgandhi 18:6a4db94011d3 3910
sahilmgandhi 18:6a4db94011d3 3911 /******************** Bit definition forUSB_OTG_DCTL register ********************/
sahilmgandhi 18:6a4db94011d3 3912 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
sahilmgandhi 18:6a4db94011d3 3913 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
sahilmgandhi 18:6a4db94011d3 3914 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
sahilmgandhi 18:6a4db94011d3 3915 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
sahilmgandhi 18:6a4db94011d3 3916
sahilmgandhi 18:6a4db94011d3 3917 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
sahilmgandhi 18:6a4db94011d3 3918 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3919 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3920 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3921 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
sahilmgandhi 18:6a4db94011d3 3922 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
sahilmgandhi 18:6a4db94011d3 3923 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
sahilmgandhi 18:6a4db94011d3 3924 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
sahilmgandhi 18:6a4db94011d3 3925 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
sahilmgandhi 18:6a4db94011d3 3926
sahilmgandhi 18:6a4db94011d3 3927 /******************** Bit definition forUSB_OTG_HFIR register ********************/
sahilmgandhi 18:6a4db94011d3 3928 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
sahilmgandhi 18:6a4db94011d3 3929
sahilmgandhi 18:6a4db94011d3 3930 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
sahilmgandhi 18:6a4db94011d3 3931 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 3932 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
sahilmgandhi 18:6a4db94011d3 3933
sahilmgandhi 18:6a4db94011d3 3934 /******************** Bit definition forUSB_OTG_DSTS register ********************/
sahilmgandhi 18:6a4db94011d3 3935 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
sahilmgandhi 18:6a4db94011d3 3936
sahilmgandhi 18:6a4db94011d3 3937 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
sahilmgandhi 18:6a4db94011d3 3938 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3939 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3940 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
sahilmgandhi 18:6a4db94011d3 3941 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
sahilmgandhi 18:6a4db94011d3 3942
sahilmgandhi 18:6a4db94011d3 3943 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
sahilmgandhi 18:6a4db94011d3 3944 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
sahilmgandhi 18:6a4db94011d3 3945
sahilmgandhi 18:6a4db94011d3 3946 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
sahilmgandhi 18:6a4db94011d3 3947 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3948 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3949 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3950 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3951 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
sahilmgandhi 18:6a4db94011d3 3952 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
sahilmgandhi 18:6a4db94011d3 3953 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
sahilmgandhi 18:6a4db94011d3 3954
sahilmgandhi 18:6a4db94011d3 3955 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
sahilmgandhi 18:6a4db94011d3 3956
sahilmgandhi 18:6a4db94011d3 3957 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
sahilmgandhi 18:6a4db94011d3 3958 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3959 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3960 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3961 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
sahilmgandhi 18:6a4db94011d3 3962 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
sahilmgandhi 18:6a4db94011d3 3963 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
sahilmgandhi 18:6a4db94011d3 3964
sahilmgandhi 18:6a4db94011d3 3965 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
sahilmgandhi 18:6a4db94011d3 3966 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3967 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3968 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3969 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3970 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
sahilmgandhi 18:6a4db94011d3 3971 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
sahilmgandhi 18:6a4db94011d3 3972 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
sahilmgandhi 18:6a4db94011d3 3973 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
sahilmgandhi 18:6a4db94011d3 3974 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
sahilmgandhi 18:6a4db94011d3 3975 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
sahilmgandhi 18:6a4db94011d3 3976 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
sahilmgandhi 18:6a4db94011d3 3977 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
sahilmgandhi 18:6a4db94011d3 3978 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
sahilmgandhi 18:6a4db94011d3 3979 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
sahilmgandhi 18:6a4db94011d3 3980 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
sahilmgandhi 18:6a4db94011d3 3981 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
sahilmgandhi 18:6a4db94011d3 3982 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
sahilmgandhi 18:6a4db94011d3 3983
sahilmgandhi 18:6a4db94011d3 3984 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
sahilmgandhi 18:6a4db94011d3 3985 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
sahilmgandhi 18:6a4db94011d3 3986 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
sahilmgandhi 18:6a4db94011d3 3987 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
sahilmgandhi 18:6a4db94011d3 3988 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
sahilmgandhi 18:6a4db94011d3 3989 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
sahilmgandhi 18:6a4db94011d3 3990
sahilmgandhi 18:6a4db94011d3 3991 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
sahilmgandhi 18:6a4db94011d3 3992 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3993 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3994 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3995 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3996 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3997 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
sahilmgandhi 18:6a4db94011d3 3998 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
sahilmgandhi 18:6a4db94011d3 3999
sahilmgandhi 18:6a4db94011d3 4000 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4001 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 4002 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 4003 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
sahilmgandhi 18:6a4db94011d3 4004 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 4005 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 4006 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 4007 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
sahilmgandhi 18:6a4db94011d3 4008 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 4009
sahilmgandhi 18:6a4db94011d3 4010 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
sahilmgandhi 18:6a4db94011d3 4011 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
sahilmgandhi 18:6a4db94011d3 4012
sahilmgandhi 18:6a4db94011d3 4013 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
sahilmgandhi 18:6a4db94011d3 4014 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4015 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4016 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4017 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4018 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4019 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4020 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4021 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4022
sahilmgandhi 18:6a4db94011d3 4023 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
sahilmgandhi 18:6a4db94011d3 4024 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4025 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4026 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4027 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4028 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4029 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4030 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4031 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4032
sahilmgandhi 18:6a4db94011d3 4033 /******************** Bit definition forUSB_OTG_HAINT register ********************/
sahilmgandhi 18:6a4db94011d3 4034 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
sahilmgandhi 18:6a4db94011d3 4035
sahilmgandhi 18:6a4db94011d3 4036 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4037 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 4038 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 4039 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
sahilmgandhi 18:6a4db94011d3 4040 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
sahilmgandhi 18:6a4db94011d3 4041 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
sahilmgandhi 18:6a4db94011d3 4042 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
sahilmgandhi 18:6a4db94011d3 4043 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 4044
sahilmgandhi 18:6a4db94011d3 4045 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
sahilmgandhi 18:6a4db94011d3 4046 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
sahilmgandhi 18:6a4db94011d3 4047 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
sahilmgandhi 18:6a4db94011d3 4048 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
sahilmgandhi 18:6a4db94011d3 4049 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
sahilmgandhi 18:6a4db94011d3 4050 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
sahilmgandhi 18:6a4db94011d3 4051 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
sahilmgandhi 18:6a4db94011d3 4052 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
sahilmgandhi 18:6a4db94011d3 4053 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
sahilmgandhi 18:6a4db94011d3 4054 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
sahilmgandhi 18:6a4db94011d3 4055 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
sahilmgandhi 18:6a4db94011d3 4056 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
sahilmgandhi 18:6a4db94011d3 4057 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
sahilmgandhi 18:6a4db94011d3 4058 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
sahilmgandhi 18:6a4db94011d3 4059 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
sahilmgandhi 18:6a4db94011d3 4060 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
sahilmgandhi 18:6a4db94011d3 4061 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
sahilmgandhi 18:6a4db94011d3 4062 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
sahilmgandhi 18:6a4db94011d3 4063 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
sahilmgandhi 18:6a4db94011d3 4064 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
sahilmgandhi 18:6a4db94011d3 4065 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
sahilmgandhi 18:6a4db94011d3 4066 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
sahilmgandhi 18:6a4db94011d3 4067 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
sahilmgandhi 18:6a4db94011d3 4068 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
sahilmgandhi 18:6a4db94011d3 4069 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
sahilmgandhi 18:6a4db94011d3 4070 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
sahilmgandhi 18:6a4db94011d3 4071 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
sahilmgandhi 18:6a4db94011d3 4072
sahilmgandhi 18:6a4db94011d3 4073 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4074 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
sahilmgandhi 18:6a4db94011d3 4075 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
sahilmgandhi 18:6a4db94011d3 4076 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
sahilmgandhi 18:6a4db94011d3 4077 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
sahilmgandhi 18:6a4db94011d3 4078 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 4079 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
sahilmgandhi 18:6a4db94011d3 4080 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
sahilmgandhi 18:6a4db94011d3 4081 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
sahilmgandhi 18:6a4db94011d3 4082 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
sahilmgandhi 18:6a4db94011d3 4083 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
sahilmgandhi 18:6a4db94011d3 4084 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
sahilmgandhi 18:6a4db94011d3 4085 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
sahilmgandhi 18:6a4db94011d3 4086 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
sahilmgandhi 18:6a4db94011d3 4087 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
sahilmgandhi 18:6a4db94011d3 4088 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
sahilmgandhi 18:6a4db94011d3 4089 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
sahilmgandhi 18:6a4db94011d3 4090 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
sahilmgandhi 18:6a4db94011d3 4091 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
sahilmgandhi 18:6a4db94011d3 4092 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
sahilmgandhi 18:6a4db94011d3 4093 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
sahilmgandhi 18:6a4db94011d3 4094 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
sahilmgandhi 18:6a4db94011d3 4095 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 4096 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
sahilmgandhi 18:6a4db94011d3 4097 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 4098 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 4099 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 4100
sahilmgandhi 18:6a4db94011d3 4101 /******************** Bit definition forUSB_OTG_DAINT register ********************/
sahilmgandhi 18:6a4db94011d3 4102 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
sahilmgandhi 18:6a4db94011d3 4103 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
sahilmgandhi 18:6a4db94011d3 4104
sahilmgandhi 18:6a4db94011d3 4105 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4106 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
sahilmgandhi 18:6a4db94011d3 4107
sahilmgandhi 18:6a4db94011d3 4108 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
sahilmgandhi 18:6a4db94011d3 4109 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4110 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4111 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4112 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4113
sahilmgandhi 18:6a4db94011d3 4114 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4115 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4116 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4117
sahilmgandhi 18:6a4db94011d3 4118 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 4119
sahilmgandhi 18:6a4db94011d3 4120 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
sahilmgandhi 18:6a4db94011d3 4121 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4122 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4123 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4124 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4125 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
sahilmgandhi 18:6a4db94011d3 4126
sahilmgandhi 18:6a4db94011d3 4127 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 4128 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4129 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4130
sahilmgandhi 18:6a4db94011d3 4131 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
sahilmgandhi 18:6a4db94011d3 4132 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4133 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4134 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4135 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4136
sahilmgandhi 18:6a4db94011d3 4137 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 4138 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4139 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4140 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4141 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4142
sahilmgandhi 18:6a4db94011d3 4143 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 4144 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4145 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4146 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4147 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4148
sahilmgandhi 18:6a4db94011d3 4149 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 4150
sahilmgandhi 18:6a4db94011d3 4151 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
sahilmgandhi 18:6a4db94011d3 4152 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4153 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4154 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4155 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4156 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
sahilmgandhi 18:6a4db94011d3 4157
sahilmgandhi 18:6a4db94011d3 4158 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 4159 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4160 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4161
sahilmgandhi 18:6a4db94011d3 4162 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
sahilmgandhi 18:6a4db94011d3 4163 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4164 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4165 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4166 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4167
sahilmgandhi 18:6a4db94011d3 4168 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 4169 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4170 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4171 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4172 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4173
sahilmgandhi 18:6a4db94011d3 4174 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 4175 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4176 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4177 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4178 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4179
sahilmgandhi 18:6a4db94011d3 4180 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 4181 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
sahilmgandhi 18:6a4db94011d3 4182
sahilmgandhi 18:6a4db94011d3 4183 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
sahilmgandhi 18:6a4db94011d3 4184 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
sahilmgandhi 18:6a4db94011d3 4185
sahilmgandhi 18:6a4db94011d3 4186 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 4187 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 4188 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 4189 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 4190 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 4191
sahilmgandhi 18:6a4db94011d3 4192 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
sahilmgandhi 18:6a4db94011d3 4193 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
sahilmgandhi 18:6a4db94011d3 4194
sahilmgandhi 18:6a4db94011d3 4195 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
sahilmgandhi 18:6a4db94011d3 4196 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
sahilmgandhi 18:6a4db94011d3 4197
sahilmgandhi 18:6a4db94011d3 4198 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
sahilmgandhi 18:6a4db94011d3 4199 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4200 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4201 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4202 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4203 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4204 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4205 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4206 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4207
sahilmgandhi 18:6a4db94011d3 4208 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
sahilmgandhi 18:6a4db94011d3 4209 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4210 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4211 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4212 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4213 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4214 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4215 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4216
sahilmgandhi 18:6a4db94011d3 4217 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
sahilmgandhi 18:6a4db94011d3 4218 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
sahilmgandhi 18:6a4db94011d3 4219 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
sahilmgandhi 18:6a4db94011d3 4220
sahilmgandhi 18:6a4db94011d3 4221 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
sahilmgandhi 18:6a4db94011d3 4222 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4223 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4224 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4225 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4226 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4227 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4228 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4229 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4230 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 4231 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
sahilmgandhi 18:6a4db94011d3 4232
sahilmgandhi 18:6a4db94011d3 4233 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
sahilmgandhi 18:6a4db94011d3 4234 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4235 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4236 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4237 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4238 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4239 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4240 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4241 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4242 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 4243 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
sahilmgandhi 18:6a4db94011d3 4244
sahilmgandhi 18:6a4db94011d3 4245 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4246 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 4247
sahilmgandhi 18:6a4db94011d3 4248 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
sahilmgandhi 18:6a4db94011d3 4249 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
sahilmgandhi 18:6a4db94011d3 4250 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
sahilmgandhi 18:6a4db94011d3 4251
sahilmgandhi 18:6a4db94011d3 4252 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
sahilmgandhi 18:6a4db94011d3 4253 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
sahilmgandhi 18:6a4db94011d3 4254 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
sahilmgandhi 18:6a4db94011d3 4255 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
sahilmgandhi 18:6a4db94011d3 4256 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
sahilmgandhi 18:6a4db94011d3 4257 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
sahilmgandhi 18:6a4db94011d3 4258 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
sahilmgandhi 18:6a4db94011d3 4259
sahilmgandhi 18:6a4db94011d3 4260 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4261 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
sahilmgandhi 18:6a4db94011d3 4262 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
sahilmgandhi 18:6a4db94011d3 4263
sahilmgandhi 18:6a4db94011d3 4264 /******************** Bit definition forUSB_OTG_CID register ********************/
sahilmgandhi 18:6a4db94011d3 4265 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
sahilmgandhi 18:6a4db94011d3 4266
sahilmgandhi 18:6a4db94011d3 4267 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
sahilmgandhi 18:6a4db94011d3 4268 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 4269 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 4270 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
sahilmgandhi 18:6a4db94011d3 4271 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 4272 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 4273 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 4274 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
sahilmgandhi 18:6a4db94011d3 4275 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 4276 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
sahilmgandhi 18:6a4db94011d3 4277
sahilmgandhi 18:6a4db94011d3 4278 /******************** Bit definition forUSB_OTG_HPRT register ********************/
sahilmgandhi 18:6a4db94011d3 4279 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
sahilmgandhi 18:6a4db94011d3 4280 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
sahilmgandhi 18:6a4db94011d3 4281 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
sahilmgandhi 18:6a4db94011d3 4282 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
sahilmgandhi 18:6a4db94011d3 4283 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
sahilmgandhi 18:6a4db94011d3 4284 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
sahilmgandhi 18:6a4db94011d3 4285 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
sahilmgandhi 18:6a4db94011d3 4286 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
sahilmgandhi 18:6a4db94011d3 4287 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
sahilmgandhi 18:6a4db94011d3 4288
sahilmgandhi 18:6a4db94011d3 4289 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
sahilmgandhi 18:6a4db94011d3 4290 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4291 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4292 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
sahilmgandhi 18:6a4db94011d3 4293
sahilmgandhi 18:6a4db94011d3 4294 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
sahilmgandhi 18:6a4db94011d3 4295 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4296 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4297 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4298 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4299
sahilmgandhi 18:6a4db94011d3 4300 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
sahilmgandhi 18:6a4db94011d3 4301 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4302 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4303
sahilmgandhi 18:6a4db94011d3 4304 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
sahilmgandhi 18:6a4db94011d3 4305 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 4306 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 4307 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
sahilmgandhi 18:6a4db94011d3 4308 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 4309 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 4310 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 4311 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
sahilmgandhi 18:6a4db94011d3 4312 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 4313 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
sahilmgandhi 18:6a4db94011d3 4314 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
sahilmgandhi 18:6a4db94011d3 4315 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
sahilmgandhi 18:6a4db94011d3 4316
sahilmgandhi 18:6a4db94011d3 4317 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 4318 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
sahilmgandhi 18:6a4db94011d3 4319 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 4320
sahilmgandhi 18:6a4db94011d3 4321 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
sahilmgandhi 18:6a4db94011d3 4322 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
sahilmgandhi 18:6a4db94011d3 4323 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
sahilmgandhi 18:6a4db94011d3 4324 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
sahilmgandhi 18:6a4db94011d3 4325 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
sahilmgandhi 18:6a4db94011d3 4326
sahilmgandhi 18:6a4db94011d3 4327 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 4328 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4329 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4330 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
sahilmgandhi 18:6a4db94011d3 4331
sahilmgandhi 18:6a4db94011d3 4332 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
sahilmgandhi 18:6a4db94011d3 4333 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4334 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4335 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4336 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4337 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
sahilmgandhi 18:6a4db94011d3 4338 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
sahilmgandhi 18:6a4db94011d3 4339 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
sahilmgandhi 18:6a4db94011d3 4340 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
sahilmgandhi 18:6a4db94011d3 4341 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
sahilmgandhi 18:6a4db94011d3 4342 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
sahilmgandhi 18:6a4db94011d3 4343
sahilmgandhi 18:6a4db94011d3 4344 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
sahilmgandhi 18:6a4db94011d3 4345 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
sahilmgandhi 18:6a4db94011d3 4346
sahilmgandhi 18:6a4db94011d3 4347 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 4348 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4349 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4350 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4351 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4352 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
sahilmgandhi 18:6a4db94011d3 4353 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
sahilmgandhi 18:6a4db94011d3 4354
sahilmgandhi 18:6a4db94011d3 4355 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 4356 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4357 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4358
sahilmgandhi 18:6a4db94011d3 4359 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
sahilmgandhi 18:6a4db94011d3 4360 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4361 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4362
sahilmgandhi 18:6a4db94011d3 4363 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
sahilmgandhi 18:6a4db94011d3 4364 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4365 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4366 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4367 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4368 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4369 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4370 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4371 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
sahilmgandhi 18:6a4db94011d3 4372 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
sahilmgandhi 18:6a4db94011d3 4373 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
sahilmgandhi 18:6a4db94011d3 4374
sahilmgandhi 18:6a4db94011d3 4375 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
sahilmgandhi 18:6a4db94011d3 4376
sahilmgandhi 18:6a4db94011d3 4377 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
sahilmgandhi 18:6a4db94011d3 4378 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4379 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4380 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4381 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4382 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4383 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4384 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4385
sahilmgandhi 18:6a4db94011d3 4386 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
sahilmgandhi 18:6a4db94011d3 4387 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4388 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4389 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4390 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4391 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4392 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4393 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4394
sahilmgandhi 18:6a4db94011d3 4395 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
sahilmgandhi 18:6a4db94011d3 4396 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4397 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4398 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
sahilmgandhi 18:6a4db94011d3 4399 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
sahilmgandhi 18:6a4db94011d3 4400
sahilmgandhi 18:6a4db94011d3 4401 /******************** Bit definition forUSB_OTG_HCINT register ********************/
sahilmgandhi 18:6a4db94011d3 4402 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
sahilmgandhi 18:6a4db94011d3 4403 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
sahilmgandhi 18:6a4db94011d3 4404 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
sahilmgandhi 18:6a4db94011d3 4405 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
sahilmgandhi 18:6a4db94011d3 4406 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
sahilmgandhi 18:6a4db94011d3 4407 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
sahilmgandhi 18:6a4db94011d3 4408 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
sahilmgandhi 18:6a4db94011d3 4409 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
sahilmgandhi 18:6a4db94011d3 4410 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
sahilmgandhi 18:6a4db94011d3 4411 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
sahilmgandhi 18:6a4db94011d3 4412 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
sahilmgandhi 18:6a4db94011d3 4413
sahilmgandhi 18:6a4db94011d3 4414 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
sahilmgandhi 18:6a4db94011d3 4415 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
sahilmgandhi 18:6a4db94011d3 4416 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
sahilmgandhi 18:6a4db94011d3 4417 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
sahilmgandhi 18:6a4db94011d3 4418 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
sahilmgandhi 18:6a4db94011d3 4419 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
sahilmgandhi 18:6a4db94011d3 4420 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
sahilmgandhi 18:6a4db94011d3 4421 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
sahilmgandhi 18:6a4db94011d3 4422 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
sahilmgandhi 18:6a4db94011d3 4423 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
sahilmgandhi 18:6a4db94011d3 4424 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
sahilmgandhi 18:6a4db94011d3 4425 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
sahilmgandhi 18:6a4db94011d3 4426
sahilmgandhi 18:6a4db94011d3 4427 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 4428 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
sahilmgandhi 18:6a4db94011d3 4429 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
sahilmgandhi 18:6a4db94011d3 4430 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
sahilmgandhi 18:6a4db94011d3 4431 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 4432 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 4433 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
sahilmgandhi 18:6a4db94011d3 4434 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 4435 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
sahilmgandhi 18:6a4db94011d3 4436 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
sahilmgandhi 18:6a4db94011d3 4437 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
sahilmgandhi 18:6a4db94011d3 4438 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
sahilmgandhi 18:6a4db94011d3 4439
sahilmgandhi 18:6a4db94011d3 4440 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 4441
sahilmgandhi 18:6a4db94011d3 4442 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 4443 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 4444 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 4445 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 4446 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 4447 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 4448 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
sahilmgandhi 18:6a4db94011d3 4449 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 4450 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4451 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4452
sahilmgandhi 18:6a4db94011d3 4453 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
sahilmgandhi 18:6a4db94011d3 4454 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
sahilmgandhi 18:6a4db94011d3 4455
sahilmgandhi 18:6a4db94011d3 4456 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
sahilmgandhi 18:6a4db94011d3 4457 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
sahilmgandhi 18:6a4db94011d3 4458
sahilmgandhi 18:6a4db94011d3 4459 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
sahilmgandhi 18:6a4db94011d3 4460 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
sahilmgandhi 18:6a4db94011d3 4461
sahilmgandhi 18:6a4db94011d3 4462 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
sahilmgandhi 18:6a4db94011d3 4463 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 4464 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 4465
sahilmgandhi 18:6a4db94011d3 4466 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
sahilmgandhi 18:6a4db94011d3 4467
sahilmgandhi 18:6a4db94011d3 4468 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4469 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
sahilmgandhi 18:6a4db94011d3 4470 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
sahilmgandhi 18:6a4db94011d3 4471 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
sahilmgandhi 18:6a4db94011d3 4472 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
sahilmgandhi 18:6a4db94011d3 4473 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 4474 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4475 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4476 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
sahilmgandhi 18:6a4db94011d3 4477 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
sahilmgandhi 18:6a4db94011d3 4478 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
sahilmgandhi 18:6a4db94011d3 4479 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
sahilmgandhi 18:6a4db94011d3 4480 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
sahilmgandhi 18:6a4db94011d3 4481 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
sahilmgandhi 18:6a4db94011d3 4482
sahilmgandhi 18:6a4db94011d3 4483 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
sahilmgandhi 18:6a4db94011d3 4484 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
sahilmgandhi 18:6a4db94011d3 4485 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
sahilmgandhi 18:6a4db94011d3 4486 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
sahilmgandhi 18:6a4db94011d3 4487 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
sahilmgandhi 18:6a4db94011d3 4488 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
sahilmgandhi 18:6a4db94011d3 4489 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
sahilmgandhi 18:6a4db94011d3 4490
sahilmgandhi 18:6a4db94011d3 4491 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 4492
sahilmgandhi 18:6a4db94011d3 4493 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 4494 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 4495
sahilmgandhi 18:6a4db94011d3 4496 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
sahilmgandhi 18:6a4db94011d3 4497 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4498 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4499
sahilmgandhi 18:6a4db94011d3 4500 /******************** Bit definition for PCGCCTL register ********************/
sahilmgandhi 18:6a4db94011d3 4501 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
sahilmgandhi 18:6a4db94011d3 4502 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4503 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4504
sahilmgandhi 18:6a4db94011d3 4505 /**
sahilmgandhi 18:6a4db94011d3 4506 * @}
sahilmgandhi 18:6a4db94011d3 4507 */
sahilmgandhi 18:6a4db94011d3 4508
sahilmgandhi 18:6a4db94011d3 4509 /**
sahilmgandhi 18:6a4db94011d3 4510 * @}
sahilmgandhi 18:6a4db94011d3 4511 */
sahilmgandhi 18:6a4db94011d3 4512
sahilmgandhi 18:6a4db94011d3 4513 /** @addtogroup Exported_macros
sahilmgandhi 18:6a4db94011d3 4514 * @{
sahilmgandhi 18:6a4db94011d3 4515 */
sahilmgandhi 18:6a4db94011d3 4516
sahilmgandhi 18:6a4db94011d3 4517 /******************************* ADC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 4518 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
sahilmgandhi 18:6a4db94011d3 4519
sahilmgandhi 18:6a4db94011d3 4520 /******************************* CRC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 4521 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
sahilmgandhi 18:6a4db94011d3 4522
sahilmgandhi 18:6a4db94011d3 4523 /******************************** DMA Instances *******************************/
sahilmgandhi 18:6a4db94011d3 4524 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
sahilmgandhi 18:6a4db94011d3 4525 ((INSTANCE) == DMA1_Stream1) || \
sahilmgandhi 18:6a4db94011d3 4526 ((INSTANCE) == DMA1_Stream2) || \
sahilmgandhi 18:6a4db94011d3 4527 ((INSTANCE) == DMA1_Stream3) || \
sahilmgandhi 18:6a4db94011d3 4528 ((INSTANCE) == DMA1_Stream4) || \
sahilmgandhi 18:6a4db94011d3 4529 ((INSTANCE) == DMA1_Stream5) || \
sahilmgandhi 18:6a4db94011d3 4530 ((INSTANCE) == DMA1_Stream6) || \
sahilmgandhi 18:6a4db94011d3 4531 ((INSTANCE) == DMA1_Stream7) || \
sahilmgandhi 18:6a4db94011d3 4532 ((INSTANCE) == DMA2_Stream0) || \
sahilmgandhi 18:6a4db94011d3 4533 ((INSTANCE) == DMA2_Stream1) || \
sahilmgandhi 18:6a4db94011d3 4534 ((INSTANCE) == DMA2_Stream2) || \
sahilmgandhi 18:6a4db94011d3 4535 ((INSTANCE) == DMA2_Stream3) || \
sahilmgandhi 18:6a4db94011d3 4536 ((INSTANCE) == DMA2_Stream4) || \
sahilmgandhi 18:6a4db94011d3 4537 ((INSTANCE) == DMA2_Stream5) || \
sahilmgandhi 18:6a4db94011d3 4538 ((INSTANCE) == DMA2_Stream6) || \
sahilmgandhi 18:6a4db94011d3 4539 ((INSTANCE) == DMA2_Stream7))
sahilmgandhi 18:6a4db94011d3 4540
sahilmgandhi 18:6a4db94011d3 4541 /******************************* GPIO Instances *******************************/
sahilmgandhi 18:6a4db94011d3 4542 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 4543 ((INSTANCE) == GPIOB) || \
sahilmgandhi 18:6a4db94011d3 4544 ((INSTANCE) == GPIOC) || \
sahilmgandhi 18:6a4db94011d3 4545 ((INSTANCE) == GPIOD) || \
sahilmgandhi 18:6a4db94011d3 4546 ((INSTANCE) == GPIOE) || \
sahilmgandhi 18:6a4db94011d3 4547 ((INSTANCE) == GPIOH))
sahilmgandhi 18:6a4db94011d3 4548
sahilmgandhi 18:6a4db94011d3 4549 /******************************** I2C Instances *******************************/
sahilmgandhi 18:6a4db94011d3 4550 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 4551 ((INSTANCE) == I2C2) || \
sahilmgandhi 18:6a4db94011d3 4552 ((INSTANCE) == I2C3))
sahilmgandhi 18:6a4db94011d3 4553
sahilmgandhi 18:6a4db94011d3 4554 /******************************** I2S Instances *******************************/
sahilmgandhi 18:6a4db94011d3 4555 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 4556 ((INSTANCE) == SPI3))
sahilmgandhi 18:6a4db94011d3 4557
sahilmgandhi 18:6a4db94011d3 4558 /*************************** I2S Extended Instances ***************************/
sahilmgandhi 18:6a4db94011d3 4559 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 4560 ((INSTANCE) == SPI3) || \
sahilmgandhi 18:6a4db94011d3 4561 ((INSTANCE) == I2S2ext) || \
sahilmgandhi 18:6a4db94011d3 4562 ((INSTANCE) == I2S3ext))
sahilmgandhi 18:6a4db94011d3 4563
sahilmgandhi 18:6a4db94011d3 4564 /****************************** RTC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 4565 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
sahilmgandhi 18:6a4db94011d3 4566
sahilmgandhi 18:6a4db94011d3 4567 /******************************** SPI Instances *******************************/
sahilmgandhi 18:6a4db94011d3 4568 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 4569 ((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 4570 ((INSTANCE) == SPI3) || \
sahilmgandhi 18:6a4db94011d3 4571 ((INSTANCE) == SPI4))
sahilmgandhi 18:6a4db94011d3 4572
sahilmgandhi 18:6a4db94011d3 4573 /*************************** SPI Extended Instances ***************************/
sahilmgandhi 18:6a4db94011d3 4574 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 4575 ((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 4576 ((INSTANCE) == SPI3) || \
sahilmgandhi 18:6a4db94011d3 4577 ((INSTANCE) == I2S2ext) || \
sahilmgandhi 18:6a4db94011d3 4578 ((INSTANCE) == I2S3ext))
sahilmgandhi 18:6a4db94011d3 4579
sahilmgandhi 18:6a4db94011d3 4580 /****************** TIM Instances : All supported instances *******************/
sahilmgandhi 18:6a4db94011d3 4581 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4582 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4583 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4584 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4585 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 4586 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 4587 ((INSTANCE) == TIM10) || \
sahilmgandhi 18:6a4db94011d3 4588 ((INSTANCE) == TIM11))
sahilmgandhi 18:6a4db94011d3 4589
sahilmgandhi 18:6a4db94011d3 4590 /************* TIM Instances : at least 1 capture/compare channel *************/
sahilmgandhi 18:6a4db94011d3 4591 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4592 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4593 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4594 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4595 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 4596 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 4597 ((INSTANCE) == TIM10) || \
sahilmgandhi 18:6a4db94011d3 4598 ((INSTANCE) == TIM11))
sahilmgandhi 18:6a4db94011d3 4599
sahilmgandhi 18:6a4db94011d3 4600 /************ TIM Instances : at least 2 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 4601 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4602 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4603 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4604 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4605 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 4606 ((INSTANCE) == TIM9))
sahilmgandhi 18:6a4db94011d3 4607
sahilmgandhi 18:6a4db94011d3 4608 /************ TIM Instances : at least 3 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 4609 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4610 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4611 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4612 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4613 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4614
sahilmgandhi 18:6a4db94011d3 4615 /************ TIM Instances : at least 4 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 4616 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4617 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4618 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4619 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4620 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4621
sahilmgandhi 18:6a4db94011d3 4622 /******************** TIM Instances : Advanced-control timers *****************/
sahilmgandhi 18:6a4db94011d3 4623 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
sahilmgandhi 18:6a4db94011d3 4624
sahilmgandhi 18:6a4db94011d3 4625 /******************* TIM Instances : Timer input XOR function *****************/
sahilmgandhi 18:6a4db94011d3 4626 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4627 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4628 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4629 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4630 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4631
sahilmgandhi 18:6a4db94011d3 4632 /****************** TIM Instances : DMA requests generation (UDE) *************/
sahilmgandhi 18:6a4db94011d3 4633 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4634 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4635 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4636 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4637 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4638
sahilmgandhi 18:6a4db94011d3 4639 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
sahilmgandhi 18:6a4db94011d3 4640 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4641 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4642 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4643 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4644 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4645
sahilmgandhi 18:6a4db94011d3 4646 /************ TIM Instances : DMA requests generation (COMDE) *****************/
sahilmgandhi 18:6a4db94011d3 4647 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4648 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4649 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4650 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4651 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4652
sahilmgandhi 18:6a4db94011d3 4653 /******************** TIM Instances : DMA burst feature ***********************/
sahilmgandhi 18:6a4db94011d3 4654 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4655 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4656 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4657 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4658 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4659
sahilmgandhi 18:6a4db94011d3 4660 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
sahilmgandhi 18:6a4db94011d3 4661 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4662 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4663 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4664 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4665 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 4666 ((INSTANCE) == TIM9))
sahilmgandhi 18:6a4db94011d3 4667
sahilmgandhi 18:6a4db94011d3 4668 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
sahilmgandhi 18:6a4db94011d3 4669 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4670 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4671 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4672 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4673 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 4674 ((INSTANCE) == TIM9))
sahilmgandhi 18:6a4db94011d3 4675
sahilmgandhi 18:6a4db94011d3 4676 /********************** TIM Instances : 32 bit Counter ************************/
sahilmgandhi 18:6a4db94011d3 4677 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4678 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4679
sahilmgandhi 18:6a4db94011d3 4680 /***************** TIM Instances : external trigger input availabe ************/
sahilmgandhi 18:6a4db94011d3 4681 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 4682 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4683 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 4684 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 4685 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 4686
sahilmgandhi 18:6a4db94011d3 4687 /****************** TIM Instances : remapping capability **********************/
sahilmgandhi 18:6a4db94011d3 4688 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 4689 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 4690 ((INSTANCE) == TIM11))
sahilmgandhi 18:6a4db94011d3 4691
sahilmgandhi 18:6a4db94011d3 4692 /******************* TIM Instances : output(s) available **********************/
sahilmgandhi 18:6a4db94011d3 4693 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 4694 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 4695 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4696 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 4697 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 4698 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 4699 || \
sahilmgandhi 18:6a4db94011d3 4700 (((INSTANCE) == TIM2) && \
sahilmgandhi 18:6a4db94011d3 4701 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4702 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 4703 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 4704 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 4705 || \
sahilmgandhi 18:6a4db94011d3 4706 (((INSTANCE) == TIM3) && \
sahilmgandhi 18:6a4db94011d3 4707 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4708 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 4709 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 4710 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 4711 || \
sahilmgandhi 18:6a4db94011d3 4712 (((INSTANCE) == TIM4) && \
sahilmgandhi 18:6a4db94011d3 4713 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4714 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 4715 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 4716 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 4717 || \
sahilmgandhi 18:6a4db94011d3 4718 (((INSTANCE) == TIM5) && \
sahilmgandhi 18:6a4db94011d3 4719 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4720 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 4721 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 4722 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 4723 || \
sahilmgandhi 18:6a4db94011d3 4724 (((INSTANCE) == TIM9) && \
sahilmgandhi 18:6a4db94011d3 4725 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4726 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 4727 || \
sahilmgandhi 18:6a4db94011d3 4728 (((INSTANCE) == TIM10) && \
sahilmgandhi 18:6a4db94011d3 4729 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 4730 || \
sahilmgandhi 18:6a4db94011d3 4731 (((INSTANCE) == TIM11) && \
sahilmgandhi 18:6a4db94011d3 4732 (((CHANNEL) == TIM_CHANNEL_1))))
sahilmgandhi 18:6a4db94011d3 4733
sahilmgandhi 18:6a4db94011d3 4734 /************ TIM Instances : complementary output(s) available ***************/
sahilmgandhi 18:6a4db94011d3 4735 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 4736 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 4737 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 4738 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 4739 ((CHANNEL) == TIM_CHANNEL_3))))
sahilmgandhi 18:6a4db94011d3 4740
sahilmgandhi 18:6a4db94011d3 4741 /******************** USART Instances : Synchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 4742 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 4743 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 4744 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 4745
sahilmgandhi 18:6a4db94011d3 4746 /******************** UART Instances : Asynchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 4747 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 4748 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 4749 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 4750
sahilmgandhi 18:6a4db94011d3 4751 /****************** UART Instances : Hardware Flow control ********************/
sahilmgandhi 18:6a4db94011d3 4752 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 4753 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 4754 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 4755
sahilmgandhi 18:6a4db94011d3 4756 /********************* UART Instances : Smard card mode ***********************/
sahilmgandhi 18:6a4db94011d3 4757 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 4758 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 4759 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 4760
sahilmgandhi 18:6a4db94011d3 4761 /*********************** UART Instances : IRDA mode ***************************/
sahilmgandhi 18:6a4db94011d3 4762 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 4763 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 4764 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 4765
sahilmgandhi 18:6a4db94011d3 4766 /*********************** PCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 4767 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
sahilmgandhi 18:6a4db94011d3 4768
sahilmgandhi 18:6a4db94011d3 4769 /*********************** HCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 4770 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
sahilmgandhi 18:6a4db94011d3 4771
sahilmgandhi 18:6a4db94011d3 4772 /****************************** IWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 4773 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
sahilmgandhi 18:6a4db94011d3 4774
sahilmgandhi 18:6a4db94011d3 4775 /****************************** WWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 4776 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
sahilmgandhi 18:6a4db94011d3 4777
sahilmgandhi 18:6a4db94011d3 4778 /****************************** SDIO Instances ********************************/
sahilmgandhi 18:6a4db94011d3 4779 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
sahilmgandhi 18:6a4db94011d3 4780
sahilmgandhi 18:6a4db94011d3 4781 /****************************** USB Exported Constants ************************/
sahilmgandhi 18:6a4db94011d3 4782 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
sahilmgandhi 18:6a4db94011d3 4783 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 4784 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 4785 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
sahilmgandhi 18:6a4db94011d3 4786
sahilmgandhi 18:6a4db94011d3 4787 /**
sahilmgandhi 18:6a4db94011d3 4788 * @}
sahilmgandhi 18:6a4db94011d3 4789 */
sahilmgandhi 18:6a4db94011d3 4790
sahilmgandhi 18:6a4db94011d3 4791 /**
sahilmgandhi 18:6a4db94011d3 4792 * @}
sahilmgandhi 18:6a4db94011d3 4793 */
sahilmgandhi 18:6a4db94011d3 4794
sahilmgandhi 18:6a4db94011d3 4795 /**
sahilmgandhi 18:6a4db94011d3 4796 * @}
sahilmgandhi 18:6a4db94011d3 4797 */
sahilmgandhi 18:6a4db94011d3 4798
sahilmgandhi 18:6a4db94011d3 4799 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 4800 }
sahilmgandhi 18:6a4db94011d3 4801 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 4802
sahilmgandhi 18:6a4db94011d3 4803 #endif /* __STM32F401xC_H */
sahilmgandhi 18:6a4db94011d3 4804
sahilmgandhi 18:6a4db94011d3 4805
sahilmgandhi 18:6a4db94011d3 4806
sahilmgandhi 18:6a4db94011d3 4807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/