MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sram.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_sram.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief SRAM HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides a generic firmware to drive SRAM memories
sahilmgandhi 18:6a4db94011d3 9 * mounted as external device.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 @verbatim
sahilmgandhi 18:6a4db94011d3 12 ==============================================================================
sahilmgandhi 18:6a4db94011d3 13 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 [..]
sahilmgandhi 18:6a4db94011d3 16 This driver is a generic layered driver which contains a set of APIs used to
sahilmgandhi 18:6a4db94011d3 17 control SRAM memories. It uses the FSMC layer functions to interface
sahilmgandhi 18:6a4db94011d3 18 with SRAM devices.
sahilmgandhi 18:6a4db94011d3 19 The following sequence should be followed to configure the FSMC to interface
sahilmgandhi 18:6a4db94011d3 20 with SRAM/PSRAM memories:
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
sahilmgandhi 18:6a4db94011d3 23 SRAM_HandleTypeDef hsram; and:
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
sahilmgandhi 18:6a4db94011d3 26 values of the structure member.
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
sahilmgandhi 18:6a4db94011d3 29 base register instance for NOR or SRAM device
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
sahilmgandhi 18:6a4db94011d3 32 base register instance for NOR or SRAM extended mode
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
sahilmgandhi 18:6a4db94011d3 35 mode timings; for example:
sahilmgandhi 18:6a4db94011d3 36 FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
sahilmgandhi 18:6a4db94011d3 37 and fill its fields with the allowed values of the structure member.
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
sahilmgandhi 18:6a4db94011d3 40 performs the following sequence:
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
sahilmgandhi 18:6a4db94011d3 43 (##) Control register configuration using the FSMC NORSRAM interface function
sahilmgandhi 18:6a4db94011d3 44 FSMC_NORSRAM_Init()
sahilmgandhi 18:6a4db94011d3 45 (##) Timing register configuration using the FSMC NORSRAM interface function
sahilmgandhi 18:6a4db94011d3 46 FSMC_NORSRAM_Timing_Init()
sahilmgandhi 18:6a4db94011d3 47 (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
sahilmgandhi 18:6a4db94011d3 48 FSMC_NORSRAM_Extended_Timing_Init()
sahilmgandhi 18:6a4db94011d3 49 (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 (#) At this stage you can perform read/write accesses from/to the memory connected
sahilmgandhi 18:6a4db94011d3 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
sahilmgandhi 18:6a4db94011d3 53 following APIs:
sahilmgandhi 18:6a4db94011d3 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
sahilmgandhi 18:6a4db94011d3 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
sahilmgandhi 18:6a4db94011d3 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
sahilmgandhi 18:6a4db94011d3 61 HAL_SRAM_GetState()
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 @endverbatim
sahilmgandhi 18:6a4db94011d3 64 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 65 * @attention
sahilmgandhi 18:6a4db94011d3 66 *
sahilmgandhi 18:6a4db94011d3 67 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 68 *
sahilmgandhi 18:6a4db94011d3 69 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 70 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 71 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 72 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 74 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 75 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 77 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 78 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 79 *
sahilmgandhi 18:6a4db94011d3 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 90 *
sahilmgandhi 18:6a4db94011d3 91 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 92 */
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 95 #include "stm32f2xx_hal.h"
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 98 * @{
sahilmgandhi 18:6a4db94011d3 99 */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /** @defgroup SRAM SRAM
sahilmgandhi 18:6a4db94011d3 102 * @brief SRAM driver modules
sahilmgandhi 18:6a4db94011d3 103 * @{
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105 #ifdef HAL_SRAM_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 108 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 109 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 110 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 111 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 114 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
sahilmgandhi 18:6a4db94011d3 115 * @{
sahilmgandhi 18:6a4db94011d3 116 */
sahilmgandhi 18:6a4db94011d3 117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 118 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 119 *
sahilmgandhi 18:6a4db94011d3 120 @verbatim
sahilmgandhi 18:6a4db94011d3 121 ==============================================================================
sahilmgandhi 18:6a4db94011d3 122 ##### SRAM Initialization and de_initialization functions #####
sahilmgandhi 18:6a4db94011d3 123 ==============================================================================
sahilmgandhi 18:6a4db94011d3 124 [..] This section provides functions allowing to initialize/de-initialize
sahilmgandhi 18:6a4db94011d3 125 the SRAM memory
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 @endverbatim
sahilmgandhi 18:6a4db94011d3 128 * @{
sahilmgandhi 18:6a4db94011d3 129 */
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /**
sahilmgandhi 18:6a4db94011d3 132 * @brief Performs the SRAM device initialization sequence
sahilmgandhi 18:6a4db94011d3 133 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 134 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 135 * @param Timing: Pointer to SRAM control timing structure
sahilmgandhi 18:6a4db94011d3 136 * @param ExtTiming: Pointer to SRAM extended mode timing structure
sahilmgandhi 18:6a4db94011d3 137 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 138 */
sahilmgandhi 18:6a4db94011d3 139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
sahilmgandhi 18:6a4db94011d3 140 {
sahilmgandhi 18:6a4db94011d3 141 /* Check the SRAM handle parameter */
sahilmgandhi 18:6a4db94011d3 142 if(hsram == NULL)
sahilmgandhi 18:6a4db94011d3 143 {
sahilmgandhi 18:6a4db94011d3 144 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 if(hsram->State == HAL_SRAM_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 148 {
sahilmgandhi 18:6a4db94011d3 149 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 150 hsram->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 151 /* Initialize the low level hardware (MSP) */
sahilmgandhi 18:6a4db94011d3 152 HAL_SRAM_MspInit(hsram);
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /* Initialize SRAM control Interface */
sahilmgandhi 18:6a4db94011d3 156 FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /* Initialize SRAM timing Interface */
sahilmgandhi 18:6a4db94011d3 159 FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /* Initialize SRAM extended mode timing Interface */
sahilmgandhi 18:6a4db94011d3 162 FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /* Enable the NORSRAM device */
sahilmgandhi 18:6a4db94011d3 165 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 168 }
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /**
sahilmgandhi 18:6a4db94011d3 171 * @brief Performs the SRAM device De-initialization sequence.
sahilmgandhi 18:6a4db94011d3 172 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 173 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 174 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
sahilmgandhi 18:6a4db94011d3 177 {
sahilmgandhi 18:6a4db94011d3 178 /* De-Initialize the low level hardware (MSP) */
sahilmgandhi 18:6a4db94011d3 179 HAL_SRAM_MspDeInit(hsram);
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /* Configure the SRAM registers with their reset values */
sahilmgandhi 18:6a4db94011d3 182 FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 hsram->State = HAL_SRAM_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 187 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /**
sahilmgandhi 18:6a4db94011d3 193 * @brief SRAM MSP Init.
sahilmgandhi 18:6a4db94011d3 194 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 195 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 196 * @retval None
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
sahilmgandhi 18:6a4db94011d3 199 {
sahilmgandhi 18:6a4db94011d3 200 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 201 UNUSED(hsram);
sahilmgandhi 18:6a4db94011d3 202 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 203 the HAL_SRAM_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205 }
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /**
sahilmgandhi 18:6a4db94011d3 208 * @brief SRAM MSP DeInit.
sahilmgandhi 18:6a4db94011d3 209 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 210 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 211 * @retval None
sahilmgandhi 18:6a4db94011d3 212 */
sahilmgandhi 18:6a4db94011d3 213 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
sahilmgandhi 18:6a4db94011d3 214 {
sahilmgandhi 18:6a4db94011d3 215 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 216 UNUSED(hsram);
sahilmgandhi 18:6a4db94011d3 217 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 218 the HAL_SRAM_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 219 */
sahilmgandhi 18:6a4db94011d3 220 }
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /**
sahilmgandhi 18:6a4db94011d3 223 * @brief DMA transfer complete callback.
sahilmgandhi 18:6a4db94011d3 224 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 225 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 226 * @retval None
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 229 {
sahilmgandhi 18:6a4db94011d3 230 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 231 UNUSED(hdma);
sahilmgandhi 18:6a4db94011d3 232 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 233 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 234 */
sahilmgandhi 18:6a4db94011d3 235 }
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /**
sahilmgandhi 18:6a4db94011d3 238 * @brief DMA transfer complete error callback.
sahilmgandhi 18:6a4db94011d3 239 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 240 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 241 * @retval None
sahilmgandhi 18:6a4db94011d3 242 */
sahilmgandhi 18:6a4db94011d3 243 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 244 {
sahilmgandhi 18:6a4db94011d3 245 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 246 UNUSED(hdma);
sahilmgandhi 18:6a4db94011d3 247 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 248 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 249 */
sahilmgandhi 18:6a4db94011d3 250 }
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /**
sahilmgandhi 18:6a4db94011d3 253 * @}
sahilmgandhi 18:6a4db94011d3 254 */
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
sahilmgandhi 18:6a4db94011d3 257 * @brief Input Output and memory control functions
sahilmgandhi 18:6a4db94011d3 258 *
sahilmgandhi 18:6a4db94011d3 259 @verbatim
sahilmgandhi 18:6a4db94011d3 260 ==============================================================================
sahilmgandhi 18:6a4db94011d3 261 ##### SRAM Input and Output functions #####
sahilmgandhi 18:6a4db94011d3 262 ==============================================================================
sahilmgandhi 18:6a4db94011d3 263 [..]
sahilmgandhi 18:6a4db94011d3 264 This section provides functions allowing to use and control the SRAM memory
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 @endverbatim
sahilmgandhi 18:6a4db94011d3 267 * @{
sahilmgandhi 18:6a4db94011d3 268 */
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /**
sahilmgandhi 18:6a4db94011d3 271 * @brief Reads 8-bit buffer from SRAM memory.
sahilmgandhi 18:6a4db94011d3 272 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 273 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 274 * @param pAddress: Pointer to read start address
sahilmgandhi 18:6a4db94011d3 275 * @param pDstBuffer: Pointer to destination buffer
sahilmgandhi 18:6a4db94011d3 276 * @param BufferSize: Size of the buffer to read from memory
sahilmgandhi 18:6a4db94011d3 277 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 280 {
sahilmgandhi 18:6a4db94011d3 281 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 284 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 287 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /* Read data from memory */
sahilmgandhi 18:6a4db94011d3 290 for(; BufferSize != 0U; BufferSize--)
sahilmgandhi 18:6a4db94011d3 291 {
sahilmgandhi 18:6a4db94011d3 292 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
sahilmgandhi 18:6a4db94011d3 293 pDstBuffer++;
sahilmgandhi 18:6a4db94011d3 294 pSramAddress++;
sahilmgandhi 18:6a4db94011d3 295 }
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 298 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 301 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 304 }
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /**
sahilmgandhi 18:6a4db94011d3 307 * @brief Writes 8-bit buffer to SRAM memory.
sahilmgandhi 18:6a4db94011d3 308 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 309 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 310 * @param pAddress: Pointer to write start address
sahilmgandhi 18:6a4db94011d3 311 * @param pSrcBuffer: Pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 312 * @param BufferSize: Size of the buffer to write to memory
sahilmgandhi 18:6a4db94011d3 313 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 314 */
sahilmgandhi 18:6a4db94011d3 315 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 316 {
sahilmgandhi 18:6a4db94011d3 317 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /* Check the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 320 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 326 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 329 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 332 for(; BufferSize != 0U; BufferSize--)
sahilmgandhi 18:6a4db94011d3 333 {
sahilmgandhi 18:6a4db94011d3 334 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
sahilmgandhi 18:6a4db94011d3 335 pSrcBuffer++;
sahilmgandhi 18:6a4db94011d3 336 pSramAddress++;
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 340 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 343 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 346 }
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 /**
sahilmgandhi 18:6a4db94011d3 349 * @brief Reads 16-bit buffer from SRAM memory.
sahilmgandhi 18:6a4db94011d3 350 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 351 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 352 * @param pAddress: Pointer to read start address
sahilmgandhi 18:6a4db94011d3 353 * @param pDstBuffer: Pointer to destination buffer
sahilmgandhi 18:6a4db94011d3 354 * @param BufferSize: Size of the buffer to read from memory
sahilmgandhi 18:6a4db94011d3 355 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 356 */
sahilmgandhi 18:6a4db94011d3 357 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 358 {
sahilmgandhi 18:6a4db94011d3 359 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 362 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 365 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /* Read data from memory */
sahilmgandhi 18:6a4db94011d3 368 for(; BufferSize != 0U; BufferSize--)
sahilmgandhi 18:6a4db94011d3 369 {
sahilmgandhi 18:6a4db94011d3 370 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
sahilmgandhi 18:6a4db94011d3 371 pDstBuffer++;
sahilmgandhi 18:6a4db94011d3 372 pSramAddress++;
sahilmgandhi 18:6a4db94011d3 373 }
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 376 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 379 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 /**
sahilmgandhi 18:6a4db94011d3 385 * @brief Writes 16-bit buffer to SRAM memory.
sahilmgandhi 18:6a4db94011d3 386 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 387 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 388 * @param pAddress: Pointer to write start address
sahilmgandhi 18:6a4db94011d3 389 * @param pSrcBuffer: Pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 390 * @param BufferSize: Size of the buffer to write to memory
sahilmgandhi 18:6a4db94011d3 391 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 392 */
sahilmgandhi 18:6a4db94011d3 393 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 394 {
sahilmgandhi 18:6a4db94011d3 395 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 /* Check the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 398 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
sahilmgandhi 18:6a4db94011d3 399 {
sahilmgandhi 18:6a4db94011d3 400 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 401 }
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 404 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 407 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 410 for(; BufferSize != 0U; BufferSize--)
sahilmgandhi 18:6a4db94011d3 411 {
sahilmgandhi 18:6a4db94011d3 412 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
sahilmgandhi 18:6a4db94011d3 413 pSrcBuffer++;
sahilmgandhi 18:6a4db94011d3 414 pSramAddress++;
sahilmgandhi 18:6a4db94011d3 415 }
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 418 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 421 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 /**
sahilmgandhi 18:6a4db94011d3 427 * @brief Reads 32-bit buffer from SRAM memory.
sahilmgandhi 18:6a4db94011d3 428 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 429 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 430 * @param pAddress: Pointer to read start address
sahilmgandhi 18:6a4db94011d3 431 * @param pDstBuffer: Pointer to destination buffer
sahilmgandhi 18:6a4db94011d3 432 * @param BufferSize: Size of the buffer to read from memory
sahilmgandhi 18:6a4db94011d3 433 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 434 */
sahilmgandhi 18:6a4db94011d3 435 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 436 {
sahilmgandhi 18:6a4db94011d3 437 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 438 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 441 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 /* Read data from memory */
sahilmgandhi 18:6a4db94011d3 444 for(; BufferSize != 0U; BufferSize--)
sahilmgandhi 18:6a4db94011d3 445 {
sahilmgandhi 18:6a4db94011d3 446 *pDstBuffer = *(__IO uint32_t *)pAddress;
sahilmgandhi 18:6a4db94011d3 447 pDstBuffer++;
sahilmgandhi 18:6a4db94011d3 448 pAddress++;
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 452 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 455 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 458 }
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /**
sahilmgandhi 18:6a4db94011d3 461 * @brief Writes 32-bit buffer to SRAM memory.
sahilmgandhi 18:6a4db94011d3 462 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 463 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 464 * @param pAddress: Pointer to write start address
sahilmgandhi 18:6a4db94011d3 465 * @param pSrcBuffer: Pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 466 * @param BufferSize: Size of the buffer to write to memory
sahilmgandhi 18:6a4db94011d3 467 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 468 */
sahilmgandhi 18:6a4db94011d3 469 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 470 {
sahilmgandhi 18:6a4db94011d3 471 /* Check the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 472 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
sahilmgandhi 18:6a4db94011d3 473 {
sahilmgandhi 18:6a4db94011d3 474 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 475 }
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 478 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 481 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 484 for(; BufferSize != 0U; BufferSize--)
sahilmgandhi 18:6a4db94011d3 485 {
sahilmgandhi 18:6a4db94011d3 486 *(__IO uint32_t *)pAddress = *pSrcBuffer;
sahilmgandhi 18:6a4db94011d3 487 pSrcBuffer++;
sahilmgandhi 18:6a4db94011d3 488 pAddress++;
sahilmgandhi 18:6a4db94011d3 489 }
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 492 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 495 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 498 }
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /**
sahilmgandhi 18:6a4db94011d3 501 * @brief Reads a Words data from the SRAM memory using DMA transfer.
sahilmgandhi 18:6a4db94011d3 502 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 503 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 504 * @param pAddress: Pointer to read start address
sahilmgandhi 18:6a4db94011d3 505 * @param pDstBuffer: Pointer to destination buffer
sahilmgandhi 18:6a4db94011d3 506 * @param BufferSize: Size of the buffer to read from memory
sahilmgandhi 18:6a4db94011d3 507 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 508 */
sahilmgandhi 18:6a4db94011d3 509 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 510 {
sahilmgandhi 18:6a4db94011d3 511 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 512 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 515 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 /* Configure DMA user callbacks */
sahilmgandhi 18:6a4db94011d3 518 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
sahilmgandhi 18:6a4db94011d3 519 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 /* Enable the DMA Stream */
sahilmgandhi 18:6a4db94011d3 522 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 525 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 528 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 531 }
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 /**
sahilmgandhi 18:6a4db94011d3 534 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
sahilmgandhi 18:6a4db94011d3 535 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 536 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 537 * @param pAddress: Pointer to write start address
sahilmgandhi 18:6a4db94011d3 538 * @param pSrcBuffer: Pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 539 * @param BufferSize: Size of the buffer to write to memory
sahilmgandhi 18:6a4db94011d3 540 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 541 */
sahilmgandhi 18:6a4db94011d3 542 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
sahilmgandhi 18:6a4db94011d3 543 {
sahilmgandhi 18:6a4db94011d3 544 /* Check the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 545 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
sahilmgandhi 18:6a4db94011d3 546 {
sahilmgandhi 18:6a4db94011d3 547 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 548 }
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 551 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 554 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /* Configure DMA user callbacks */
sahilmgandhi 18:6a4db94011d3 557 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
sahilmgandhi 18:6a4db94011d3 558 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /* Enable the DMA Stream */
sahilmgandhi 18:6a4db94011d3 561 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 564 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 567 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 570 }
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /**
sahilmgandhi 18:6a4db94011d3 573 * @}
sahilmgandhi 18:6a4db94011d3 574 */
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
sahilmgandhi 18:6a4db94011d3 577 * @brief management functions
sahilmgandhi 18:6a4db94011d3 578 *
sahilmgandhi 18:6a4db94011d3 579 @verbatim
sahilmgandhi 18:6a4db94011d3 580 ==============================================================================
sahilmgandhi 18:6a4db94011d3 581 ##### SRAM Control functions #####
sahilmgandhi 18:6a4db94011d3 582 ==============================================================================
sahilmgandhi 18:6a4db94011d3 583 [..]
sahilmgandhi 18:6a4db94011d3 584 This subsection provides a set of functions allowing to control dynamically
sahilmgandhi 18:6a4db94011d3 585 the SRAM interface.
sahilmgandhi 18:6a4db94011d3 586
sahilmgandhi 18:6a4db94011d3 587 @endverbatim
sahilmgandhi 18:6a4db94011d3 588 * @{
sahilmgandhi 18:6a4db94011d3 589 */
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /**
sahilmgandhi 18:6a4db94011d3 592 * @brief Enables dynamically SRAM write operation.
sahilmgandhi 18:6a4db94011d3 593 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 594 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 595 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 596 */
sahilmgandhi 18:6a4db94011d3 597 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 600 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 /* Enable write operation */
sahilmgandhi 18:6a4db94011d3 603 FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 606 hsram->State = HAL_SRAM_STATE_READY;
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 609 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 612 }
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 /**
sahilmgandhi 18:6a4db94011d3 615 * @brief Disables dynamically SRAM write operation.
sahilmgandhi 18:6a4db94011d3 616 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 617 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 618 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 619 */
sahilmgandhi 18:6a4db94011d3 620 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
sahilmgandhi 18:6a4db94011d3 621 {
sahilmgandhi 18:6a4db94011d3 622 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 623 __HAL_LOCK(hsram);
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 626 hsram->State = HAL_SRAM_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 627
sahilmgandhi 18:6a4db94011d3 628 /* Disable write operation */
sahilmgandhi 18:6a4db94011d3 629 FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631 /* Update the SRAM controller state */
sahilmgandhi 18:6a4db94011d3 632 hsram->State = HAL_SRAM_STATE_PROTECTED;
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 635 __HAL_UNLOCK(hsram);
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 638 }
sahilmgandhi 18:6a4db94011d3 639
sahilmgandhi 18:6a4db94011d3 640 /**
sahilmgandhi 18:6a4db94011d3 641 * @}
sahilmgandhi 18:6a4db94011d3 642 */
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 /** @defgroup SRAM_Exported_Functions_Group4 State functions
sahilmgandhi 18:6a4db94011d3 645 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 646 *
sahilmgandhi 18:6a4db94011d3 647 @verbatim
sahilmgandhi 18:6a4db94011d3 648 ==============================================================================
sahilmgandhi 18:6a4db94011d3 649 ##### SRAM State functions #####
sahilmgandhi 18:6a4db94011d3 650 ==============================================================================
sahilmgandhi 18:6a4db94011d3 651 [..]
sahilmgandhi 18:6a4db94011d3 652 This subsection permits to get in run-time the status of the SRAM controller
sahilmgandhi 18:6a4db94011d3 653 and the data flow.
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 @endverbatim
sahilmgandhi 18:6a4db94011d3 656 * @{
sahilmgandhi 18:6a4db94011d3 657 */
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 /**
sahilmgandhi 18:6a4db94011d3 660 * @brief Returns the SRAM controller state
sahilmgandhi 18:6a4db94011d3 661 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 662 * the configuration information for SRAM module.
sahilmgandhi 18:6a4db94011d3 663 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 664 */
sahilmgandhi 18:6a4db94011d3 665 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 return hsram->State;
sahilmgandhi 18:6a4db94011d3 668 }
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /**
sahilmgandhi 18:6a4db94011d3 671 * @}
sahilmgandhi 18:6a4db94011d3 672 */
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 /**
sahilmgandhi 18:6a4db94011d3 675 * @}
sahilmgandhi 18:6a4db94011d3 676 */
sahilmgandhi 18:6a4db94011d3 677 #endif /* HAL_SRAM_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 678 /**
sahilmgandhi 18:6a4db94011d3 679 * @}
sahilmgandhi 18:6a4db94011d3 680 */
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 /**
sahilmgandhi 18:6a4db94011d3 683 * @}
sahilmgandhi 18:6a4db94011d3 684 */
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/