MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nand.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_nand.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of NAND HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F2xx_HAL_NAND_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F2xx_HAL_NAND_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f2xx_ll_fsmc.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 51 * @{
sahilmgandhi 18:6a4db94011d3 52 */
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /** @addtogroup NAND
sahilmgandhi 18:6a4db94011d3 55 * @{
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /* Exported typedef ----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 59 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 60 /** @defgroup NAND_Exported_Types NAND Exported Types
sahilmgandhi 18:6a4db94011d3 61 * @{
sahilmgandhi 18:6a4db94011d3 62 */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**
sahilmgandhi 18:6a4db94011d3 65 * @brief HAL NAND State structures definition
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 typedef enum
sahilmgandhi 18:6a4db94011d3 68 {
sahilmgandhi 18:6a4db94011d3 69 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
sahilmgandhi 18:6a4db94011d3 70 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
sahilmgandhi 18:6a4db94011d3 71 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
sahilmgandhi 18:6a4db94011d3 72 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
sahilmgandhi 18:6a4db94011d3 73 }HAL_NAND_StateTypeDef;
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /**
sahilmgandhi 18:6a4db94011d3 76 * @brief NAND Memory electronic signature Structure definition
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78 typedef struct
sahilmgandhi 18:6a4db94011d3 79 {
sahilmgandhi 18:6a4db94011d3 80 /*<! NAND memory electronic signature maker and device IDs */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 uint8_t Maker_Id;
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 uint8_t Device_Id;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 uint8_t Third_Id;
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 uint8_t Fourth_Id;
sahilmgandhi 18:6a4db94011d3 89 }NAND_IDTypeDef;
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 /**
sahilmgandhi 18:6a4db94011d3 92 * @brief NAND Memory address Structure definition
sahilmgandhi 18:6a4db94011d3 93 */
sahilmgandhi 18:6a4db94011d3 94 typedef struct
sahilmgandhi 18:6a4db94011d3 95 {
sahilmgandhi 18:6a4db94011d3 96 uint16_t Page; /*!< NAND memory Page address */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 uint16_t Zone; /*!< NAND memory Zone address */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 uint16_t Block; /*!< NAND memory Block address */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 }NAND_AddressTypeDef;
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /**
sahilmgandhi 18:6a4db94011d3 105 * @brief NAND Memory info Structure definition
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107 typedef struct
sahilmgandhi 18:6a4db94011d3 108 {
sahilmgandhi 18:6a4db94011d3 109 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 uint32_t BlockSize; /*!< NAND memory block size number of pages */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 uint32_t BlockNbr; /*!< NAND memory number of blocks */
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
sahilmgandhi 18:6a4db94011d3 118 }NAND_InfoTypeDef;
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 /**
sahilmgandhi 18:6a4db94011d3 121 * @brief NAND handle Structure definition
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123 typedef struct
sahilmgandhi 18:6a4db94011d3 124 {
sahilmgandhi 18:6a4db94011d3 125 FSMC_NAND_TypeDef *Instance; /*!< Register base address */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 HAL_LockTypeDef Lock; /*!< NAND locking object */
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
sahilmgandhi 18:6a4db94011d3 134 }NAND_HandleTypeDef;
sahilmgandhi 18:6a4db94011d3 135 /**
sahilmgandhi 18:6a4db94011d3 136 * @}
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 140 /* Exported macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 141 /** @defgroup NAND_Exported_Macros NAND Exported Macros
sahilmgandhi 18:6a4db94011d3 142 * @{
sahilmgandhi 18:6a4db94011d3 143 */
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /** @brief Reset NAND handle state
sahilmgandhi 18:6a4db94011d3 146 * @param __HANDLE__: specifies the NAND handle.
sahilmgandhi 18:6a4db94011d3 147 * @retval None
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /**
sahilmgandhi 18:6a4db94011d3 152 * @}
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 156 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
sahilmgandhi 18:6a4db94011d3 157 * @{
sahilmgandhi 18:6a4db94011d3 158 */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 161 * @{
sahilmgandhi 18:6a4db94011d3 162 */
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /* Initialization/de-initialization functions ********************************/
sahilmgandhi 18:6a4db94011d3 165 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
sahilmgandhi 18:6a4db94011d3 166 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 167 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 168 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 169 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 170 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /**
sahilmgandhi 18:6a4db94011d3 173 * @}
sahilmgandhi 18:6a4db94011d3 174 */
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
sahilmgandhi 18:6a4db94011d3 177 * @{
sahilmgandhi 18:6a4db94011d3 178 */
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 /* IO operation functions ****************************************************/
sahilmgandhi 18:6a4db94011d3 181 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
sahilmgandhi 18:6a4db94011d3 182 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 183 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
sahilmgandhi 18:6a4db94011d3 184 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
sahilmgandhi 18:6a4db94011d3 185 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
sahilmgandhi 18:6a4db94011d3 186 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
sahilmgandhi 18:6a4db94011d3 187 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
sahilmgandhi 18:6a4db94011d3 188 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 189 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /**
sahilmgandhi 18:6a4db94011d3 192 * @}
sahilmgandhi 18:6a4db94011d3 193 */
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 196 * @{
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /* NAND Control functions ****************************************************/
sahilmgandhi 18:6a4db94011d3 200 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 201 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 202 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 /**
sahilmgandhi 18:6a4db94011d3 205 * @}
sahilmgandhi 18:6a4db94011d3 206 */
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
sahilmgandhi 18:6a4db94011d3 209 * @{
sahilmgandhi 18:6a4db94011d3 210 */
sahilmgandhi 18:6a4db94011d3 211 /* NAND State functions *******************************************************/
sahilmgandhi 18:6a4db94011d3 212 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 213 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
sahilmgandhi 18:6a4db94011d3 214 /**
sahilmgandhi 18:6a4db94011d3 215 * @}
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /**
sahilmgandhi 18:6a4db94011d3 219 * @}
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 223 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 224 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 225 /** @defgroup NAND_Private_Constants NAND Private Constants
sahilmgandhi 18:6a4db94011d3 226 * @{
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228 #define NAND_DEVICE1 ((uint32_t)0x70000000U)
sahilmgandhi 18:6a4db94011d3 229 #define NAND_DEVICE2 ((uint32_t)0x80000000U)
sahilmgandhi 18:6a4db94011d3 230 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
sahilmgandhi 18:6a4db94011d3 233 #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 #define NAND_CMD_AREA_A ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 236 #define NAND_CMD_AREA_B ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 237 #define NAND_CMD_AREA_C ((uint8_t)0x50U)
sahilmgandhi 18:6a4db94011d3 238 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 #define NAND_CMD_WRITE0 ((uint8_t)0x80U)
sahilmgandhi 18:6a4db94011d3 241 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
sahilmgandhi 18:6a4db94011d3 242 #define NAND_CMD_ERASE0 ((uint8_t)0x60U)
sahilmgandhi 18:6a4db94011d3 243 #define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
sahilmgandhi 18:6a4db94011d3 244 #define NAND_CMD_READID ((uint8_t)0x90U)
sahilmgandhi 18:6a4db94011d3 245 #define NAND_CMD_STATUS ((uint8_t)0x70U)
sahilmgandhi 18:6a4db94011d3 246 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
sahilmgandhi 18:6a4db94011d3 247 #define NAND_CMD_RESET ((uint8_t)0xFFU)
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /* NAND memory status */
sahilmgandhi 18:6a4db94011d3 250 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 251 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
sahilmgandhi 18:6a4db94011d3 252 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
sahilmgandhi 18:6a4db94011d3 253 #define NAND_BUSY ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 254 #define NAND_ERROR ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 255 #define NAND_READY ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 256 /**
sahilmgandhi 18:6a4db94011d3 257 * @}
sahilmgandhi 18:6a4db94011d3 258 */
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 261 /** @defgroup NAND_Private_Macros NAND Private Macros
sahilmgandhi 18:6a4db94011d3 262 * @{
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /**
sahilmgandhi 18:6a4db94011d3 266 * @brief NAND memory address computation.
sahilmgandhi 18:6a4db94011d3 267 * @param __ADDRESS__: NAND memory address.
sahilmgandhi 18:6a4db94011d3 268 * @param __HANDLE__ : NAND handle.
sahilmgandhi 18:6a4db94011d3 269 * @retval NAND Raw address value
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
sahilmgandhi 18:6a4db94011d3 272 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /**
sahilmgandhi 18:6a4db94011d3 275 * @brief NAND memory address cycling.
sahilmgandhi 18:6a4db94011d3 276 * @param __ADDRESS__: NAND memory address.
sahilmgandhi 18:6a4db94011d3 277 * @retval NAND address cycling value.
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
sahilmgandhi 18:6a4db94011d3 280 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
sahilmgandhi 18:6a4db94011d3 281 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
sahilmgandhi 18:6a4db94011d3 282 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
sahilmgandhi 18:6a4db94011d3 283 /**
sahilmgandhi 18:6a4db94011d3 284 * @}
sahilmgandhi 18:6a4db94011d3 285 */
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 /**
sahilmgandhi 18:6a4db94011d3 289 * @}
sahilmgandhi 18:6a4db94011d3 290 */
sahilmgandhi 18:6a4db94011d3 291 /**
sahilmgandhi 18:6a4db94011d3 292 * @}
sahilmgandhi 18:6a4db94011d3 293 */
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /**
sahilmgandhi 18:6a4db94011d3 296 * @}
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301 #endif
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 #endif /* __STM32F2xx_HAL_NAND_H */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/