MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nand.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_nand.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief NAND HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides a generic firmware to drive NAND memories mounted
sahilmgandhi 18:6a4db94011d3 9 * as external device.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 @verbatim
sahilmgandhi 18:6a4db94011d3 12 ==============================================================================
sahilmgandhi 18:6a4db94011d3 13 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 [..]
sahilmgandhi 18:6a4db94011d3 16 This driver is a generic layered driver which contains a set of APIs used to
sahilmgandhi 18:6a4db94011d3 17 control NAND flash memories. It uses the FSMC layer functions to interface
sahilmgandhi 18:6a4db94011d3 18 with NAND devices. This driver is used as follows:
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
sahilmgandhi 18:6a4db94011d3 21 with control and timing parameters for both common and attribute spaces.
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 (+) Read NAND flash memory maker and device IDs using the function
sahilmgandhi 18:6a4db94011d3 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
sahilmgandhi 18:6a4db94011d3 25 structure declared by the function caller.
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 (+) Access NAND flash memory by read/write operations using the functions
sahilmgandhi 18:6a4db94011d3 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
sahilmgandhi 18:6a4db94011d3 29 to read/write page(s)/spare area(s). These functions use specific device
sahilmgandhi 18:6a4db94011d3 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
sahilmgandhi 18:6a4db94011d3 31 structure. The read/write address information is contained by the Nand_Address_Typedef
sahilmgandhi 18:6a4db94011d3 32 structure passed as parameter.
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
sahilmgandhi 18:6a4db94011d3 37 The erase block address information is contained in the Nand_Address_Typedef
sahilmgandhi 18:6a4db94011d3 38 structure passed as parameter.
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
sahilmgandhi 18:6a4db94011d3 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
sahilmgandhi 18:6a4db94011d3 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 (+) You can monitor the NAND device HAL state by calling the function
sahilmgandhi 18:6a4db94011d3 47 HAL_NAND_GetState()
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 [..]
sahilmgandhi 18:6a4db94011d3 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
sahilmgandhi 18:6a4db94011d3 51 If a NAND flash device contains different operations and/or implementations,
sahilmgandhi 18:6a4db94011d3 52 it should be implemented separately.
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 @endverbatim
sahilmgandhi 18:6a4db94011d3 55 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 56 * @attention
sahilmgandhi 18:6a4db94011d3 57 *
sahilmgandhi 18:6a4db94011d3 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 59 *
sahilmgandhi 18:6a4db94011d3 60 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 61 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 62 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 63 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 65 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 66 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 68 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 69 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 70 *
sahilmgandhi 18:6a4db94011d3 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 81 *
sahilmgandhi 18:6a4db94011d3 82 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 86 #include "stm32f2xx_hal.h"
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 89 * @{
sahilmgandhi 18:6a4db94011d3 90 */
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 #ifdef HAL_NAND_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 /** @defgroup NAND NAND
sahilmgandhi 18:6a4db94011d3 97 * @brief NAND HAL module driver
sahilmgandhi 18:6a4db94011d3 98 * @{
sahilmgandhi 18:6a4db94011d3 99 */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 102 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 103 /** @defgroup NAND_Private_Constants NAND Private Constants
sahilmgandhi 18:6a4db94011d3 104 * @{
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /**
sahilmgandhi 18:6a4db94011d3 108 * @}
sahilmgandhi 18:6a4db94011d3 109 */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 112 /** @defgroup NAND_Private_Macros NAND Private Macros
sahilmgandhi 18:6a4db94011d3 113 * @{
sahilmgandhi 18:6a4db94011d3 114 */
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 /**
sahilmgandhi 18:6a4db94011d3 117 * @}
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 120 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 121 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 122 /** @defgroup NAND_Exported_Functions NAND Exported Functions
sahilmgandhi 18:6a4db94011d3 123 * @{
sahilmgandhi 18:6a4db94011d3 124 */
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 127 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 128 *
sahilmgandhi 18:6a4db94011d3 129 @verbatim
sahilmgandhi 18:6a4db94011d3 130 ==============================================================================
sahilmgandhi 18:6a4db94011d3 131 ##### NAND Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 132 ==============================================================================
sahilmgandhi 18:6a4db94011d3 133 [..]
sahilmgandhi 18:6a4db94011d3 134 This section provides functions allowing to initialize/de-initialize
sahilmgandhi 18:6a4db94011d3 135 the NAND memory
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 @endverbatim
sahilmgandhi 18:6a4db94011d3 138 * @{
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /**
sahilmgandhi 18:6a4db94011d3 142 * @brief Perform NAND memory Initialization sequence
sahilmgandhi 18:6a4db94011d3 143 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 144 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 145 * @param ComSpace_Timing: pointer to Common space timing structure
sahilmgandhi 18:6a4db94011d3 146 * @param AttSpace_Timing: pointer to Attribute space timing structure
sahilmgandhi 18:6a4db94011d3 147 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
sahilmgandhi 18:6a4db94011d3 150 {
sahilmgandhi 18:6a4db94011d3 151 /* Check the NAND handle state */
sahilmgandhi 18:6a4db94011d3 152 if(hnand == NULL)
sahilmgandhi 18:6a4db94011d3 153 {
sahilmgandhi 18:6a4db94011d3 154 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 155 }
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 if(hnand->State == HAL_NAND_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 158 {
sahilmgandhi 18:6a4db94011d3 159 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 160 hnand->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 161 /* Initialize the low level hardware (MSP) */
sahilmgandhi 18:6a4db94011d3 162 HAL_NAND_MspInit(hnand);
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /* Initialize NAND control Interface */
sahilmgandhi 18:6a4db94011d3 166 FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /* Initialize NAND common space timing Interface */
sahilmgandhi 18:6a4db94011d3 169 FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /* Initialize NAND attribute space timing Interface */
sahilmgandhi 18:6a4db94011d3 172 FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /* Enable the NAND device */
sahilmgandhi 18:6a4db94011d3 175 __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 178 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 181 }
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /**
sahilmgandhi 18:6a4db94011d3 184 * @brief Perform NAND memory De-Initialization sequence
sahilmgandhi 18:6a4db94011d3 185 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 186 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 187 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 188 */
sahilmgandhi 18:6a4db94011d3 189 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 190 {
sahilmgandhi 18:6a4db94011d3 191 /* Initialize the low level hardware (MSP) */
sahilmgandhi 18:6a4db94011d3 192 HAL_NAND_MspDeInit(hnand);
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /* Configure the NAND registers with their reset values */
sahilmgandhi 18:6a4db94011d3 195 FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 /* Reset the NAND controller state */
sahilmgandhi 18:6a4db94011d3 198 hnand->State = HAL_NAND_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 201 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /**
sahilmgandhi 18:6a4db94011d3 207 * @brief NAND MSP Init
sahilmgandhi 18:6a4db94011d3 208 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 209 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 210 * @retval None
sahilmgandhi 18:6a4db94011d3 211 */
sahilmgandhi 18:6a4db94011d3 212 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 213 {
sahilmgandhi 18:6a4db94011d3 214 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 215 UNUSED(hnand);
sahilmgandhi 18:6a4db94011d3 216 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 217 the HAL_NAND_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219 }
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /**
sahilmgandhi 18:6a4db94011d3 222 * @brief NAND MSP DeInit
sahilmgandhi 18:6a4db94011d3 223 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 224 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 225 * @retval None
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 230 UNUSED(hnand);
sahilmgandhi 18:6a4db94011d3 231 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 232 the HAL_NAND_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234 }
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /**
sahilmgandhi 18:6a4db94011d3 238 * @brief This function handles NAND device interrupt request.
sahilmgandhi 18:6a4db94011d3 239 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 240 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 241 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 242 */
sahilmgandhi 18:6a4db94011d3 243 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 244 {
sahilmgandhi 18:6a4db94011d3 245 /* Check NAND interrupt Rising edge flag */
sahilmgandhi 18:6a4db94011d3 246 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
sahilmgandhi 18:6a4db94011d3 247 {
sahilmgandhi 18:6a4db94011d3 248 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 249 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Clear NAND interrupt Rising edge pending bit */
sahilmgandhi 18:6a4db94011d3 252 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /* Check NAND interrupt Level flag */
sahilmgandhi 18:6a4db94011d3 256 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 259 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 /* Clear NAND interrupt Level pending bit */
sahilmgandhi 18:6a4db94011d3 262 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* Check NAND interrupt Falling edge flag */
sahilmgandhi 18:6a4db94011d3 266 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
sahilmgandhi 18:6a4db94011d3 267 {
sahilmgandhi 18:6a4db94011d3 268 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 269 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 /* Clear NAND interrupt Falling edge pending bit */
sahilmgandhi 18:6a4db94011d3 272 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /* Check NAND interrupt FIFO empty flag */
sahilmgandhi 18:6a4db94011d3 276 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
sahilmgandhi 18:6a4db94011d3 277 {
sahilmgandhi 18:6a4db94011d3 278 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 279 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 /* Clear NAND interrupt FIFO empty pending bit */
sahilmgandhi 18:6a4db94011d3 282 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 }
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /**
sahilmgandhi 18:6a4db94011d3 288 * @brief NAND interrupt feature callback
sahilmgandhi 18:6a4db94011d3 289 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 290 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 291 * @retval None
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 294 {
sahilmgandhi 18:6a4db94011d3 295 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 296 UNUSED(hnand);
sahilmgandhi 18:6a4db94011d3 297 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 298 the HAL_NAND_ITCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 299 */
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /**
sahilmgandhi 18:6a4db94011d3 303 * @}
sahilmgandhi 18:6a4db94011d3 304 */
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
sahilmgandhi 18:6a4db94011d3 307 * @brief Input Output and memory control functions
sahilmgandhi 18:6a4db94011d3 308 *
sahilmgandhi 18:6a4db94011d3 309 @verbatim
sahilmgandhi 18:6a4db94011d3 310 ==============================================================================
sahilmgandhi 18:6a4db94011d3 311 ##### NAND Input and Output functions #####
sahilmgandhi 18:6a4db94011d3 312 ==============================================================================
sahilmgandhi 18:6a4db94011d3 313 [..]
sahilmgandhi 18:6a4db94011d3 314 This section provides functions allowing to use and control the NAND
sahilmgandhi 18:6a4db94011d3 315 memory
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 @endverbatim
sahilmgandhi 18:6a4db94011d3 318 * @{
sahilmgandhi 18:6a4db94011d3 319 */
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /**
sahilmgandhi 18:6a4db94011d3 322 * @brief Read the NAND memory electronic signature
sahilmgandhi 18:6a4db94011d3 323 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 324 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 325 * @param pNAND_ID: NAND ID structure
sahilmgandhi 18:6a4db94011d3 326 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t data = 0U;
sahilmgandhi 18:6a4db94011d3 331 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 334 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 337 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 338 {
sahilmgandhi 18:6a4db94011d3 339 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 343 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 344 {
sahilmgandhi 18:6a4db94011d3 345 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 346 }
sahilmgandhi 18:6a4db94011d3 347 else
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 353 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /* Send Read ID command sequence */
sahilmgandhi 18:6a4db94011d3 356 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
sahilmgandhi 18:6a4db94011d3 357 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 /* Read the electronic signature from NAND flash */
sahilmgandhi 18:6a4db94011d3 360 data = *(__IO uint32_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 /* Return the data read */
sahilmgandhi 18:6a4db94011d3 363 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 364 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 365 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 366 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 369 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 372 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /**
sahilmgandhi 18:6a4db94011d3 378 * @brief NAND memory reset
sahilmgandhi 18:6a4db94011d3 379 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 380 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 381 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 382 */
sahilmgandhi 18:6a4db94011d3 383 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 384 {
sahilmgandhi 18:6a4db94011d3 385 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 388 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 391 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 392 {
sahilmgandhi 18:6a4db94011d3 393 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 394 }
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 397 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 398 {
sahilmgandhi 18:6a4db94011d3 399 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 400 }
sahilmgandhi 18:6a4db94011d3 401 else
sahilmgandhi 18:6a4db94011d3 402 {
sahilmgandhi 18:6a4db94011d3 403 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 407 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Send NAND reset command */
sahilmgandhi 18:6a4db94011d3 410 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFFU;
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 414 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 417 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 /**
sahilmgandhi 18:6a4db94011d3 424 * @brief Read Page(s) from NAND memory block
sahilmgandhi 18:6a4db94011d3 425 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 426 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 427 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 428 * @param pBuffer : pointer to destination read buffer
sahilmgandhi 18:6a4db94011d3 429 * @param NumPageToRead : number of pages to read from block
sahilmgandhi 18:6a4db94011d3 430 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 431 */
sahilmgandhi 18:6a4db94011d3 432 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
sahilmgandhi 18:6a4db94011d3 433 {
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 435 uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 436 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 437 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 440 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 443 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 449 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 450 {
sahilmgandhi 18:6a4db94011d3 451 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 452 }
sahilmgandhi 18:6a4db94011d3 453 else
sahilmgandhi 18:6a4db94011d3 454 {
sahilmgandhi 18:6a4db94011d3 455 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 456 }
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 459 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 462 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 463 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 464 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /* Page(s) read loop */
sahilmgandhi 18:6a4db94011d3 467 while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 468 {
sahilmgandhi 18:6a4db94011d3 469 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 470 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 473 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* Send read page command sequence */
sahilmgandhi 18:6a4db94011d3 476 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 479 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 480 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 481 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 484 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 485 {
sahilmgandhi 18:6a4db94011d3 486 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 /* Get Data into Buffer */
sahilmgandhi 18:6a4db94011d3 492 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 493 {
sahilmgandhi 18:6a4db94011d3 494 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 495 }
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /* Increment read pages number */
sahilmgandhi 18:6a4db94011d3 498 numpagesread++;
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /* Decrement pages to read */
sahilmgandhi 18:6a4db94011d3 501 NumPageToRead--;
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 504 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 508 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 511 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 }
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 /**
sahilmgandhi 18:6a4db94011d3 518 * @brief Write Page(s) to NAND memory block
sahilmgandhi 18:6a4db94011d3 519 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 520 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 521 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 522 * @param pBuffer : pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 523 * @param NumPageToWrite : number of pages to write to block
sahilmgandhi 18:6a4db94011d3 524 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 525 */
sahilmgandhi 18:6a4db94011d3 526 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
sahilmgandhi 18:6a4db94011d3 527 {
sahilmgandhi 18:6a4db94011d3 528 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 529 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 530 uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 531 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 532 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 535 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 536
sahilmgandhi 18:6a4db94011d3 537 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 538 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 544 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 545 {
sahilmgandhi 18:6a4db94011d3 546 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 547 }
sahilmgandhi 18:6a4db94011d3 548 else
sahilmgandhi 18:6a4db94011d3 549 {
sahilmgandhi 18:6a4db94011d3 550 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 551 }
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 554 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 557 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 558 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 559 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /* Page(s) write loop */
sahilmgandhi 18:6a4db94011d3 562 while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 563 {
sahilmgandhi 18:6a4db94011d3 564 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 565 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
sahilmgandhi 18:6a4db94011d3 566
sahilmgandhi 18:6a4db94011d3 567 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 568 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /* Send write page command sequence */
sahilmgandhi 18:6a4db94011d3 571 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
sahilmgandhi 18:6a4db94011d3 572 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 575 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 576 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 577 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 580 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 581 {
sahilmgandhi 18:6a4db94011d3 582 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 583 }
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 586 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593 /* Get tick */
sahilmgandhi 18:6a4db94011d3 594 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 /* Read status until NAND is ready */
sahilmgandhi 18:6a4db94011d3 597 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
sahilmgandhi 18:6a4db94011d3 600 {
sahilmgandhi 18:6a4db94011d3 601 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 602 }
sahilmgandhi 18:6a4db94011d3 603 }
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 /* Increment written pages number */
sahilmgandhi 18:6a4db94011d3 606 numpageswritten++;
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Decrement pages to write */
sahilmgandhi 18:6a4db94011d3 609 NumPageToWrite--;
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 612 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 613 }
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 616 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 619 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 622 }
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 /**
sahilmgandhi 18:6a4db94011d3 625 * @brief Read Spare area(s) from NAND memory
sahilmgandhi 18:6a4db94011d3 626 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 627 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 628 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 629 * @param pBuffer: pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 630 * @param NumSpareAreaToRead: Number of spare area to read
sahilmgandhi 18:6a4db94011d3 631 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 632 */
sahilmgandhi 18:6a4db94011d3 633 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
sahilmgandhi 18:6a4db94011d3 634 {
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 636 uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 637 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 638 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 639
sahilmgandhi 18:6a4db94011d3 640 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 641 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 644 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 645 {
sahilmgandhi 18:6a4db94011d3 646 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 647 }
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 650 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 651 {
sahilmgandhi 18:6a4db94011d3 652 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 653 }
sahilmgandhi 18:6a4db94011d3 654 else
sahilmgandhi 18:6a4db94011d3 655 {
sahilmgandhi 18:6a4db94011d3 656 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 657 }
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 660 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 663 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 664 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 665 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 /* Spare area(s) read loop */
sahilmgandhi 18:6a4db94011d3 668 while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 669 {
sahilmgandhi 18:6a4db94011d3 670 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 671 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 674 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /* Send read spare area command sequence */
sahilmgandhi 18:6a4db94011d3 677 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 680 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 681 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 682 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 683
sahilmgandhi 18:6a4db94011d3 684 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 685 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 686 {
sahilmgandhi 18:6a4db94011d3 687 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 688 }
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 /* Get Data into Buffer */
sahilmgandhi 18:6a4db94011d3 693 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 694 {
sahilmgandhi 18:6a4db94011d3 695 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 696 }
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 /* Increment read spare areas number */
sahilmgandhi 18:6a4db94011d3 699 num_spare_area_read++;
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 /* Decrement spare areas to read */
sahilmgandhi 18:6a4db94011d3 702 NumSpareAreaToRead--;
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 705 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 706 }
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 709 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 712 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 715 }
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 /**
sahilmgandhi 18:6a4db94011d3 718 * @brief Write Spare area(s) to NAND memory
sahilmgandhi 18:6a4db94011d3 719 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 720 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 721 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 722 * @param pBuffer : pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 723 * @param NumSpareAreaTowrite : number of spare areas to write to block
sahilmgandhi 18:6a4db94011d3 724 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 725 */
sahilmgandhi 18:6a4db94011d3 726 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
sahilmgandhi 18:6a4db94011d3 727 {
sahilmgandhi 18:6a4db94011d3 728 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 729 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 730 uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 731 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 732 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 735 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 738 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 739 {
sahilmgandhi 18:6a4db94011d3 740 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 741 }
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 744 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 745 {
sahilmgandhi 18:6a4db94011d3 746 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 747 }
sahilmgandhi 18:6a4db94011d3 748 else
sahilmgandhi 18:6a4db94011d3 749 {
sahilmgandhi 18:6a4db94011d3 750 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 751 }
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 /* Update the FSMC_NAND controller state */
sahilmgandhi 18:6a4db94011d3 754 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 757 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 758 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 759 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /* Spare area(s) write loop */
sahilmgandhi 18:6a4db94011d3 762 while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 763 {
sahilmgandhi 18:6a4db94011d3 764 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 765 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 768 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /* Send write Spare area command sequence */
sahilmgandhi 18:6a4db94011d3 771 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
sahilmgandhi 18:6a4db94011d3 772 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 775 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 776 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 777 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 778
sahilmgandhi 18:6a4db94011d3 779 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 780 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 781 {
sahilmgandhi 18:6a4db94011d3 782 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 786 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 787 {
sahilmgandhi 18:6a4db94011d3 788 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
sahilmgandhi 18:6a4db94011d3 789 }
sahilmgandhi 18:6a4db94011d3 790
sahilmgandhi 18:6a4db94011d3 791 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 /* Get tick */
sahilmgandhi 18:6a4db94011d3 794 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 /* Read status until NAND is ready */
sahilmgandhi 18:6a4db94011d3 797 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
sahilmgandhi 18:6a4db94011d3 798 {
sahilmgandhi 18:6a4db94011d3 799 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 802 }
sahilmgandhi 18:6a4db94011d3 803 }
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 /* Increment written spare areas number */
sahilmgandhi 18:6a4db94011d3 806 num_spare_area_written++;
sahilmgandhi 18:6a4db94011d3 807
sahilmgandhi 18:6a4db94011d3 808 /* Decrement spare areas to write */
sahilmgandhi 18:6a4db94011d3 809 NumSpareAreaTowrite--;
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 812 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 813 }
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 816 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 819 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 822 }
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 /**
sahilmgandhi 18:6a4db94011d3 825 * @brief NAND memory Block erase
sahilmgandhi 18:6a4db94011d3 826 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 827 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 828 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 829 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 830 */
sahilmgandhi 18:6a4db94011d3 831 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
sahilmgandhi 18:6a4db94011d3 832 {
sahilmgandhi 18:6a4db94011d3 833 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 834 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 835
sahilmgandhi 18:6a4db94011d3 836 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 837 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 840 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 841 {
sahilmgandhi 18:6a4db94011d3 842 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 843 }
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 846 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 847 {
sahilmgandhi 18:6a4db94011d3 848 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 849 }
sahilmgandhi 18:6a4db94011d3 850 else
sahilmgandhi 18:6a4db94011d3 851 {
sahilmgandhi 18:6a4db94011d3 852 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 853 }
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 856 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /* Send Erase block command sequence */
sahilmgandhi 18:6a4db94011d3 859 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
sahilmgandhi 18:6a4db94011d3 860
sahilmgandhi 18:6a4db94011d3 861 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 862 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 863 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 864
sahilmgandhi 18:6a4db94011d3 865 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 866 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 867 {
sahilmgandhi 18:6a4db94011d3 868 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 869 }
sahilmgandhi 18:6a4db94011d3 870
sahilmgandhi 18:6a4db94011d3 871 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 874 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 /* Get tick */
sahilmgandhi 18:6a4db94011d3 877 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879 /* Read status until NAND is ready */
sahilmgandhi 18:6a4db94011d3 880 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
sahilmgandhi 18:6a4db94011d3 881 {
sahilmgandhi 18:6a4db94011d3 882 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
sahilmgandhi 18:6a4db94011d3 883 {
sahilmgandhi 18:6a4db94011d3 884 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 885 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 888 }
sahilmgandhi 18:6a4db94011d3 889 }
sahilmgandhi 18:6a4db94011d3 890
sahilmgandhi 18:6a4db94011d3 891 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 892 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 895 }
sahilmgandhi 18:6a4db94011d3 896
sahilmgandhi 18:6a4db94011d3 897 /**
sahilmgandhi 18:6a4db94011d3 898 * @brief NAND memory read status
sahilmgandhi 18:6a4db94011d3 899 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 900 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 901 * @retval NAND status
sahilmgandhi 18:6a4db94011d3 902 */
sahilmgandhi 18:6a4db94011d3 903 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 904 {
sahilmgandhi 18:6a4db94011d3 905 uint32_t data = 0U;
sahilmgandhi 18:6a4db94011d3 906 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 907
sahilmgandhi 18:6a4db94011d3 908 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 909 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 910 {
sahilmgandhi 18:6a4db94011d3 911 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 912 }
sahilmgandhi 18:6a4db94011d3 913 else
sahilmgandhi 18:6a4db94011d3 914 {
sahilmgandhi 18:6a4db94011d3 915 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 916 }
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918 /* Send Read status operation command */
sahilmgandhi 18:6a4db94011d3 919 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
sahilmgandhi 18:6a4db94011d3 920
sahilmgandhi 18:6a4db94011d3 921 /* Read status register data */
sahilmgandhi 18:6a4db94011d3 922 data = *(__IO uint8_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 923
sahilmgandhi 18:6a4db94011d3 924 /* Return the status */
sahilmgandhi 18:6a4db94011d3 925 if((data & NAND_ERROR) == NAND_ERROR)
sahilmgandhi 18:6a4db94011d3 926 {
sahilmgandhi 18:6a4db94011d3 927 return NAND_ERROR;
sahilmgandhi 18:6a4db94011d3 928 }
sahilmgandhi 18:6a4db94011d3 929 else if((data & NAND_READY) == NAND_READY)
sahilmgandhi 18:6a4db94011d3 930 {
sahilmgandhi 18:6a4db94011d3 931 return NAND_READY;
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 return NAND_BUSY;
sahilmgandhi 18:6a4db94011d3 935 }
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 /**
sahilmgandhi 18:6a4db94011d3 938 * @brief Increment the NAND memory address
sahilmgandhi 18:6a4db94011d3 939 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 940 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 941 * @param pAddress: pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 942 * @retval The new status of the increment address operation. It can be:
sahilmgandhi 18:6a4db94011d3 943 * - NAND_VALID_ADDRESS: When the new address is valid address
sahilmgandhi 18:6a4db94011d3 944 * - NAND_INVALID_ADDRESS: When the new address is invalid address
sahilmgandhi 18:6a4db94011d3 945 */
sahilmgandhi 18:6a4db94011d3 946 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
sahilmgandhi 18:6a4db94011d3 947 {
sahilmgandhi 18:6a4db94011d3 948 uint32_t status = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 949
sahilmgandhi 18:6a4db94011d3 950 /* Increment page address */
sahilmgandhi 18:6a4db94011d3 951 pAddress->Page++;
sahilmgandhi 18:6a4db94011d3 952
sahilmgandhi 18:6a4db94011d3 953 /* Check NAND address is valid */
sahilmgandhi 18:6a4db94011d3 954 if(pAddress->Page == hnand->Info.BlockSize)
sahilmgandhi 18:6a4db94011d3 955 {
sahilmgandhi 18:6a4db94011d3 956 pAddress->Page = 0U;
sahilmgandhi 18:6a4db94011d3 957 pAddress->Block++;
sahilmgandhi 18:6a4db94011d3 958
sahilmgandhi 18:6a4db94011d3 959 if(pAddress->Block == hnand->Info.ZoneSize)
sahilmgandhi 18:6a4db94011d3 960 {
sahilmgandhi 18:6a4db94011d3 961 pAddress->Block = 0U;
sahilmgandhi 18:6a4db94011d3 962 pAddress->Zone++;
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
sahilmgandhi 18:6a4db94011d3 965 {
sahilmgandhi 18:6a4db94011d3 966 status = NAND_INVALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 967 }
sahilmgandhi 18:6a4db94011d3 968 }
sahilmgandhi 18:6a4db94011d3 969 }
sahilmgandhi 18:6a4db94011d3 970
sahilmgandhi 18:6a4db94011d3 971 return (status);
sahilmgandhi 18:6a4db94011d3 972 }
sahilmgandhi 18:6a4db94011d3 973 /**
sahilmgandhi 18:6a4db94011d3 974 * @}
sahilmgandhi 18:6a4db94011d3 975 */
sahilmgandhi 18:6a4db94011d3 976
sahilmgandhi 18:6a4db94011d3 977 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 978 * @brief management functions
sahilmgandhi 18:6a4db94011d3 979 *
sahilmgandhi 18:6a4db94011d3 980 @verbatim
sahilmgandhi 18:6a4db94011d3 981 ==============================================================================
sahilmgandhi 18:6a4db94011d3 982 ##### NAND Control functions #####
sahilmgandhi 18:6a4db94011d3 983 ==============================================================================
sahilmgandhi 18:6a4db94011d3 984 [..]
sahilmgandhi 18:6a4db94011d3 985 This subsection provides a set of functions allowing to control dynamically
sahilmgandhi 18:6a4db94011d3 986 the NAND interface.
sahilmgandhi 18:6a4db94011d3 987
sahilmgandhi 18:6a4db94011d3 988 @endverbatim
sahilmgandhi 18:6a4db94011d3 989 * @{
sahilmgandhi 18:6a4db94011d3 990 */
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 /**
sahilmgandhi 18:6a4db94011d3 994 * @brief Enables dynamically NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 995 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 996 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 997 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 998 */
sahilmgandhi 18:6a4db94011d3 999 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 1000 {
sahilmgandhi 18:6a4db94011d3 1001 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 1002 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 1003 {
sahilmgandhi 18:6a4db94011d3 1004 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1005 }
sahilmgandhi 18:6a4db94011d3 1006
sahilmgandhi 18:6a4db94011d3 1007 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1008 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1009
sahilmgandhi 18:6a4db94011d3 1010 /* Enable ECC feature */
sahilmgandhi 18:6a4db94011d3 1011 FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1014 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1015
sahilmgandhi 18:6a4db94011d3 1016 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1017 }
sahilmgandhi 18:6a4db94011d3 1018
sahilmgandhi 18:6a4db94011d3 1019 /**
sahilmgandhi 18:6a4db94011d3 1020 * @brief Disables dynamically FSMC_NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 1021 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1022 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1023 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1024 */
sahilmgandhi 18:6a4db94011d3 1025 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 1026 {
sahilmgandhi 18:6a4db94011d3 1027 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 1028 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 1029 {
sahilmgandhi 18:6a4db94011d3 1030 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032
sahilmgandhi 18:6a4db94011d3 1033 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1034 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1035
sahilmgandhi 18:6a4db94011d3 1036 /* Disable ECC feature */
sahilmgandhi 18:6a4db94011d3 1037 FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1040 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1043 }
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 /**
sahilmgandhi 18:6a4db94011d3 1046 * @brief Disables dynamically NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 1047 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1048 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1049 * @param ECCval: pointer to ECC value
sahilmgandhi 18:6a4db94011d3 1050 * @param Timeout: maximum timeout to wait
sahilmgandhi 18:6a4db94011d3 1051 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1052 */
sahilmgandhi 18:6a4db94011d3 1053 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 1054 {
sahilmgandhi 18:6a4db94011d3 1055 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1056
sahilmgandhi 18:6a4db94011d3 1057 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 1058 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 1059 {
sahilmgandhi 18:6a4db94011d3 1060 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1061 }
sahilmgandhi 18:6a4db94011d3 1062
sahilmgandhi 18:6a4db94011d3 1063 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1064 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /* Get NAND ECC value */
sahilmgandhi 18:6a4db94011d3 1067 status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1070 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 return status;
sahilmgandhi 18:6a4db94011d3 1073 }
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /**
sahilmgandhi 18:6a4db94011d3 1076 * @}
sahilmgandhi 18:6a4db94011d3 1077 */
sahilmgandhi 18:6a4db94011d3 1078
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1081 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1082 *
sahilmgandhi 18:6a4db94011d3 1083 @verbatim
sahilmgandhi 18:6a4db94011d3 1084 ==============================================================================
sahilmgandhi 18:6a4db94011d3 1085 ##### NAND State functions #####
sahilmgandhi 18:6a4db94011d3 1086 ==============================================================================
sahilmgandhi 18:6a4db94011d3 1087 [..]
sahilmgandhi 18:6a4db94011d3 1088 This subsection permits to get in run-time the status of the NAND controller
sahilmgandhi 18:6a4db94011d3 1089 and the data flow.
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 @endverbatim
sahilmgandhi 18:6a4db94011d3 1092 * @{
sahilmgandhi 18:6a4db94011d3 1093 */
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /**
sahilmgandhi 18:6a4db94011d3 1096 * @brief return the NAND state
sahilmgandhi 18:6a4db94011d3 1097 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1098 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1099 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1100 */
sahilmgandhi 18:6a4db94011d3 1101 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 1102 {
sahilmgandhi 18:6a4db94011d3 1103 return hnand->State;
sahilmgandhi 18:6a4db94011d3 1104 }
sahilmgandhi 18:6a4db94011d3 1105
sahilmgandhi 18:6a4db94011d3 1106 /**
sahilmgandhi 18:6a4db94011d3 1107 * @}
sahilmgandhi 18:6a4db94011d3 1108 */
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 /**
sahilmgandhi 18:6a4db94011d3 1111 * @}
sahilmgandhi 18:6a4db94011d3 1112 */
sahilmgandhi 18:6a4db94011d3 1113
sahilmgandhi 18:6a4db94011d3 1114 /**
sahilmgandhi 18:6a4db94011d3 1115 * @}
sahilmgandhi 18:6a4db94011d3 1116 */
sahilmgandhi 18:6a4db94011d3 1117
sahilmgandhi 18:6a4db94011d3 1118 #endif /* HAL_NAND_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 /**
sahilmgandhi 18:6a4db94011d3 1121 * @}
sahilmgandhi 18:6a4db94011d3 1122 */
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/