MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file startup_stm32f042x6.s
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.2.2
sahilmgandhi 18:6a4db94011d3 6 * @date 26-June-2015
sahilmgandhi 18:6a4db94011d3 7 * @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain.
sahilmgandhi 18:6a4db94011d3 8 * This module performs:
sahilmgandhi 18:6a4db94011d3 9 * - Set the initial SP
sahilmgandhi 18:6a4db94011d3 10 * - Set the initial PC == Reset_Handler,
sahilmgandhi 18:6a4db94011d3 11 * - Set the vector table entries with the exceptions ISR address
sahilmgandhi 18:6a4db94011d3 12 * - Branches to main in the C library (which eventually
sahilmgandhi 18:6a4db94011d3 13 * calls main()).
sahilmgandhi 18:6a4db94011d3 14 * After Reset the Cortex-M0 processor is in Thread mode,
sahilmgandhi 18:6a4db94011d3 15 * priority is Privileged, and the Stack is set to Main.
sahilmgandhi 18:6a4db94011d3 16 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 19 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 20 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 21 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 23 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 24 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 26 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 27 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 41 */
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 .syntax unified
sahilmgandhi 18:6a4db94011d3 44 .cpu cortex-m0
sahilmgandhi 18:6a4db94011d3 45 .fpu softvfp
sahilmgandhi 18:6a4db94011d3 46 .thumb
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 .global g_pfnVectors
sahilmgandhi 18:6a4db94011d3 49 .global Default_Handler
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* start address for the initialization values of the .data section.
sahilmgandhi 18:6a4db94011d3 52 defined in linker script */
sahilmgandhi 18:6a4db94011d3 53 .word _sidata
sahilmgandhi 18:6a4db94011d3 54 /* start address for the .data section. defined in linker script */
sahilmgandhi 18:6a4db94011d3 55 .word _sdata
sahilmgandhi 18:6a4db94011d3 56 /* end address for the .data section. defined in linker script */
sahilmgandhi 18:6a4db94011d3 57 .word _edata
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /**
sahilmgandhi 18:6a4db94011d3 60 * @brief This is the code that gets called when the processor first
sahilmgandhi 18:6a4db94011d3 61 * starts execution following a reset event. Only the absolutely
sahilmgandhi 18:6a4db94011d3 62 * necessary set is performed, after which the application
sahilmgandhi 18:6a4db94011d3 63 * supplied main() routine is called.
sahilmgandhi 18:6a4db94011d3 64 * @param None
sahilmgandhi 18:6a4db94011d3 65 * @retval : None
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 .section .text.Reset_Handler
sahilmgandhi 18:6a4db94011d3 69 .weak Reset_Handler
sahilmgandhi 18:6a4db94011d3 70 .type Reset_Handler, %function
sahilmgandhi 18:6a4db94011d3 71 Reset_Handler:
sahilmgandhi 18:6a4db94011d3 72 ldr r0, =_estack
sahilmgandhi 18:6a4db94011d3 73 mov sp, r0 /* set stack pointer */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /*Check if boot space corresponds to test memory*/
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 LDR R0,=0x00000004
sahilmgandhi 18:6a4db94011d3 78 LDR R1, [R0]
sahilmgandhi 18:6a4db94011d3 79 LSRS R1, R1, #24
sahilmgandhi 18:6a4db94011d3 80 LDR R2,=0x1F
sahilmgandhi 18:6a4db94011d3 81 MOVS R1, #0
sahilmgandhi 18:6a4db94011d3 82 MOVS R2, #1
sahilmgandhi 18:6a4db94011d3 83 CMP R1, R2
sahilmgandhi 18:6a4db94011d3 84 BNE ApplicationStart
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /*SYSCFG clock enable*/
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 LDR R0,=0x40021018
sahilmgandhi 18:6a4db94011d3 89 LDR R1,=0x00000001
sahilmgandhi 18:6a4db94011d3 90 STR R1, [R0]
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /*Set CFGR1 register with flash memory remap at address 0*/
sahilmgandhi 18:6a4db94011d3 93 LDR R0,=0x40010000
sahilmgandhi 18:6a4db94011d3 94 LDR R1,=0x00000000
sahilmgandhi 18:6a4db94011d3 95 STR R1, [R0]
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 ApplicationStart:
sahilmgandhi 18:6a4db94011d3 98 /* Copy the data segment initializers from flash to SRAM */
sahilmgandhi 18:6a4db94011d3 99 movs r1, #0
sahilmgandhi 18:6a4db94011d3 100 b LoopCopyDataInit
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 CopyDataInit:
sahilmgandhi 18:6a4db94011d3 103 ldr r3, =_sidata
sahilmgandhi 18:6a4db94011d3 104 ldr r3, [r3, r1]
sahilmgandhi 18:6a4db94011d3 105 str r3, [r0, r1]
sahilmgandhi 18:6a4db94011d3 106 adds r1, r1, #4
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 LoopCopyDataInit:
sahilmgandhi 18:6a4db94011d3 109 ldr r0, =_sdata
sahilmgandhi 18:6a4db94011d3 110 ldr r3, =_edata
sahilmgandhi 18:6a4db94011d3 111 adds r2, r0, r1
sahilmgandhi 18:6a4db94011d3 112 cmp r2, r3
sahilmgandhi 18:6a4db94011d3 113 bcc CopyDataInit
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /* Call the clock system intitialization function.*/
sahilmgandhi 18:6a4db94011d3 116 bl SystemInit
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* Call the application's entry point.*/
sahilmgandhi 18:6a4db94011d3 119 // bl main
sahilmgandhi 18:6a4db94011d3 120 bl _start
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 LoopForever:
sahilmgandhi 18:6a4db94011d3 123 b LoopForever
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 .size Reset_Handler, .-Reset_Handler
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /**
sahilmgandhi 18:6a4db94011d3 129 * @brief This is the code that gets called when the processor receives an
sahilmgandhi 18:6a4db94011d3 130 * unexpected interrupt. This simply enters an infinite loop, preserving
sahilmgandhi 18:6a4db94011d3 131 * the system state for examination by a debugger.
sahilmgandhi 18:6a4db94011d3 132 *
sahilmgandhi 18:6a4db94011d3 133 * @param None
sahilmgandhi 18:6a4db94011d3 134 * @retval : None
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 .section .text.Default_Handler,"ax",%progbits
sahilmgandhi 18:6a4db94011d3 137 Default_Handler:
sahilmgandhi 18:6a4db94011d3 138 Infinite_Loop:
sahilmgandhi 18:6a4db94011d3 139 b Infinite_Loop
sahilmgandhi 18:6a4db94011d3 140 .size Default_Handler, .-Default_Handler
sahilmgandhi 18:6a4db94011d3 141 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 142 *
sahilmgandhi 18:6a4db94011d3 143 * The minimal vector table for a Cortex M0. Note that the proper constructs
sahilmgandhi 18:6a4db94011d3 144 * must be placed on this to ensure that it ends up at physical address
sahilmgandhi 18:6a4db94011d3 145 * 0x0000.0000.
sahilmgandhi 18:6a4db94011d3 146 *
sahilmgandhi 18:6a4db94011d3 147 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 148 .section .isr_vector,"a",%progbits
sahilmgandhi 18:6a4db94011d3 149 .type g_pfnVectors, %object
sahilmgandhi 18:6a4db94011d3 150 .size g_pfnVectors, .-g_pfnVectors
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 g_pfnVectors:
sahilmgandhi 18:6a4db94011d3 154 .word _estack
sahilmgandhi 18:6a4db94011d3 155 .word Reset_Handler
sahilmgandhi 18:6a4db94011d3 156 .word NMI_Handler
sahilmgandhi 18:6a4db94011d3 157 .word HardFault_Handler
sahilmgandhi 18:6a4db94011d3 158 .word 0
sahilmgandhi 18:6a4db94011d3 159 .word 0
sahilmgandhi 18:6a4db94011d3 160 .word 0
sahilmgandhi 18:6a4db94011d3 161 .word 0
sahilmgandhi 18:6a4db94011d3 162 .word 0
sahilmgandhi 18:6a4db94011d3 163 .word 0
sahilmgandhi 18:6a4db94011d3 164 .word 0
sahilmgandhi 18:6a4db94011d3 165 .word SVC_Handler
sahilmgandhi 18:6a4db94011d3 166 .word 0
sahilmgandhi 18:6a4db94011d3 167 .word 0
sahilmgandhi 18:6a4db94011d3 168 .word PendSV_Handler
sahilmgandhi 18:6a4db94011d3 169 .word SysTick_Handler
sahilmgandhi 18:6a4db94011d3 170 .word WWDG_IRQHandler /* Window WatchDog */
sahilmgandhi 18:6a4db94011d3 171 .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */
sahilmgandhi 18:6a4db94011d3 172 .word RTC_IRQHandler /* RTC through the EXTI line */
sahilmgandhi 18:6a4db94011d3 173 .word FLASH_IRQHandler /* FLASH */
sahilmgandhi 18:6a4db94011d3 174 .word RCC_CRS_IRQHandler /* RCC and CRS */
sahilmgandhi 18:6a4db94011d3 175 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
sahilmgandhi 18:6a4db94011d3 176 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
sahilmgandhi 18:6a4db94011d3 177 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
sahilmgandhi 18:6a4db94011d3 178 .word TSC_IRQHandler /* TSC */
sahilmgandhi 18:6a4db94011d3 179 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
sahilmgandhi 18:6a4db94011d3 180 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
sahilmgandhi 18:6a4db94011d3 181 .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
sahilmgandhi 18:6a4db94011d3 182 .word ADC1_IRQHandler /* ADC1 */
sahilmgandhi 18:6a4db94011d3 183 .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
sahilmgandhi 18:6a4db94011d3 184 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
sahilmgandhi 18:6a4db94011d3 185 .word TIM2_IRQHandler /* TIM2 */
sahilmgandhi 18:6a4db94011d3 186 .word TIM3_IRQHandler /* TIM3 */
sahilmgandhi 18:6a4db94011d3 187 .word 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 188 .word 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 189 .word TIM14_IRQHandler /* TIM14 */
sahilmgandhi 18:6a4db94011d3 190 .word 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 191 .word TIM16_IRQHandler /* TIM16 */
sahilmgandhi 18:6a4db94011d3 192 .word TIM17_IRQHandler /* TIM17 */
sahilmgandhi 18:6a4db94011d3 193 .word I2C1_IRQHandler /* I2C1 */
sahilmgandhi 18:6a4db94011d3 194 .word 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 195 .word SPI1_IRQHandler /* SPI1 */
sahilmgandhi 18:6a4db94011d3 196 .word SPI2_IRQHandler /* SPI2 */
sahilmgandhi 18:6a4db94011d3 197 .word USART1_IRQHandler /* USART1 */
sahilmgandhi 18:6a4db94011d3 198 .word USART2_IRQHandler /* USART2 */
sahilmgandhi 18:6a4db94011d3 199 .word 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 200 .word CEC_CAN_IRQHandler /* CEC and CAN */
sahilmgandhi 18:6a4db94011d3 201 .word USB_IRQHandler /* USB */
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 204 *
sahilmgandhi 18:6a4db94011d3 205 * Provide weak aliases for each Exception handler to the Default_Handler.
sahilmgandhi 18:6a4db94011d3 206 * As they are weak aliases, any function with the same name will override
sahilmgandhi 18:6a4db94011d3 207 * this definition.
sahilmgandhi 18:6a4db94011d3 208 *
sahilmgandhi 18:6a4db94011d3 209 *******************************************************************************/
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 .weak NMI_Handler
sahilmgandhi 18:6a4db94011d3 212 .thumb_set NMI_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 .weak HardFault_Handler
sahilmgandhi 18:6a4db94011d3 215 .thumb_set HardFault_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 .weak SVC_Handler
sahilmgandhi 18:6a4db94011d3 218 .thumb_set SVC_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 .weak PendSV_Handler
sahilmgandhi 18:6a4db94011d3 221 .thumb_set PendSV_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 .weak SysTick_Handler
sahilmgandhi 18:6a4db94011d3 224 .thumb_set SysTick_Handler,Default_Handler
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 .weak WWDG_IRQHandler
sahilmgandhi 18:6a4db94011d3 227 .thumb_set WWDG_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 .weak PVD_VDDIO2_IRQHandler
sahilmgandhi 18:6a4db94011d3 230 .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 .weak RTC_IRQHandler
sahilmgandhi 18:6a4db94011d3 233 .thumb_set RTC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 .weak FLASH_IRQHandler
sahilmgandhi 18:6a4db94011d3 236 .thumb_set FLASH_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 .weak RCC_CRS_IRQHandler
sahilmgandhi 18:6a4db94011d3 239 .thumb_set RCC_CRS_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 .weak EXTI0_1_IRQHandler
sahilmgandhi 18:6a4db94011d3 242 .thumb_set EXTI0_1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 .weak EXTI2_3_IRQHandler
sahilmgandhi 18:6a4db94011d3 245 .thumb_set EXTI2_3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 .weak EXTI4_15_IRQHandler
sahilmgandhi 18:6a4db94011d3 248 .thumb_set EXTI4_15_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 .weak TSC_IRQHandler
sahilmgandhi 18:6a4db94011d3 251 .thumb_set TSC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 .weak DMA1_Channel1_IRQHandler
sahilmgandhi 18:6a4db94011d3 254 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 .weak DMA1_Channel2_3_IRQHandler
sahilmgandhi 18:6a4db94011d3 257 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 .weak DMA1_Channel4_5_IRQHandler
sahilmgandhi 18:6a4db94011d3 260 .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 .weak ADC1_IRQHandler
sahilmgandhi 18:6a4db94011d3 263 .thumb_set ADC1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 .weak TIM1_BRK_UP_TRG_COM_IRQHandler
sahilmgandhi 18:6a4db94011d3 266 .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 .weak TIM1_CC_IRQHandler
sahilmgandhi 18:6a4db94011d3 269 .thumb_set TIM1_CC_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 .weak TIM2_IRQHandler
sahilmgandhi 18:6a4db94011d3 272 .thumb_set TIM2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 .weak TIM3_IRQHandler
sahilmgandhi 18:6a4db94011d3 275 .thumb_set TIM3_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 .weak TIM14_IRQHandler
sahilmgandhi 18:6a4db94011d3 278 .thumb_set TIM14_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 .weak TIM16_IRQHandler
sahilmgandhi 18:6a4db94011d3 281 .thumb_set TIM16_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 .weak TIM17_IRQHandler
sahilmgandhi 18:6a4db94011d3 284 .thumb_set TIM17_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 .weak I2C1_IRQHandler
sahilmgandhi 18:6a4db94011d3 287 .thumb_set I2C1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 .weak SPI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 290 .thumb_set SPI1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 .weak SPI2_IRQHandler
sahilmgandhi 18:6a4db94011d3 293 .thumb_set SPI2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 .weak USART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 296 .thumb_set USART1_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 .weak USART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 299 .thumb_set USART2_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 .weak CEC_CAN_IRQHandler
sahilmgandhi 18:6a4db94011d3 302 .thumb_set CEC_CAN_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 .weak USB_IRQHandler
sahilmgandhi 18:6a4db94011d3 305 .thumb_set USB_IRQHandler,Default_Handler
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
sahilmgandhi 18:6a4db94011d3 308