MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <string.h>
sahilmgandhi 18:6a4db94011d3 17 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 18 #include "can_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "RZ_A1_Init.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 22 #include "rscan0_iodefine.h"
sahilmgandhi 18:6a4db94011d3 23 #include "r_typedefs.h"
sahilmgandhi 18:6a4db94011d3 24 #include "VKRZA1H.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #define CAN_NUM 5
sahilmgandhi 18:6a4db94011d3 27 #define CAN_SND_RCV 2
sahilmgandhi 18:6a4db94011d3 28 #define IRQ_NUM 8
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 static void can_rec_irq(uint32_t ch);
sahilmgandhi 18:6a4db94011d3 31 static void can_trx_irq(uint32_t ch);
sahilmgandhi 18:6a4db94011d3 32 static void can_err_irq(uint32_t ch, CanIrqType type);
sahilmgandhi 18:6a4db94011d3 33 static void can0_rec_irq(void);
sahilmgandhi 18:6a4db94011d3 34 static void can1_rec_irq(void);
sahilmgandhi 18:6a4db94011d3 35 static void can2_rec_irq(void);
sahilmgandhi 18:6a4db94011d3 36 static void can3_rec_irq(void);
sahilmgandhi 18:6a4db94011d3 37 static void can4_rec_irq(void);
sahilmgandhi 18:6a4db94011d3 38 static void can0_trx_irq(void);
sahilmgandhi 18:6a4db94011d3 39 static void can1_trx_irq(void);
sahilmgandhi 18:6a4db94011d3 40 static void can2_trx_irq(void);
sahilmgandhi 18:6a4db94011d3 41 static void can3_trx_irq(void);
sahilmgandhi 18:6a4db94011d3 42 static void can4_trx_irq(void);
sahilmgandhi 18:6a4db94011d3 43 static void can0_err_warning_irq(void);
sahilmgandhi 18:6a4db94011d3 44 static void can1_err_warning_irq(void);
sahilmgandhi 18:6a4db94011d3 45 static void can2_err_warning_irq(void);
sahilmgandhi 18:6a4db94011d3 46 static void can3_err_warning_irq(void);
sahilmgandhi 18:6a4db94011d3 47 static void can4_err_warning_irq(void);
sahilmgandhi 18:6a4db94011d3 48 static void can0_overrun_irq(void);
sahilmgandhi 18:6a4db94011d3 49 static void can1_overrun_irq(void);
sahilmgandhi 18:6a4db94011d3 50 static void can2_overrun_irq(void);
sahilmgandhi 18:6a4db94011d3 51 static void can3_overrun_irq(void);
sahilmgandhi 18:6a4db94011d3 52 static void can4_overrun_irq(void);
sahilmgandhi 18:6a4db94011d3 53 static void can0_passive_irq(void);
sahilmgandhi 18:6a4db94011d3 54 static void can1_passive_irq(void);
sahilmgandhi 18:6a4db94011d3 55 static void can2_passive_irq(void);
sahilmgandhi 18:6a4db94011d3 56 static void can3_passive_irq(void);
sahilmgandhi 18:6a4db94011d3 57 static void can4_passive_irq(void);
sahilmgandhi 18:6a4db94011d3 58 static void can0_arb_lost_irq(void);
sahilmgandhi 18:6a4db94011d3 59 static void can1_arb_lost_irq(void);
sahilmgandhi 18:6a4db94011d3 60 static void can2_arb_lost_irq(void);
sahilmgandhi 18:6a4db94011d3 61 static void can3_arb_lost_irq(void);
sahilmgandhi 18:6a4db94011d3 62 static void can4_arb_lost_irq(void);
sahilmgandhi 18:6a4db94011d3 63 static void can0_bus_err_irq(void);
sahilmgandhi 18:6a4db94011d3 64 static void can1_bus_err_irq(void);
sahilmgandhi 18:6a4db94011d3 65 static void can2_bus_err_irq(void);
sahilmgandhi 18:6a4db94011d3 66 static void can3_bus_err_irq(void);
sahilmgandhi 18:6a4db94011d3 67 static void can4_bus_err_irq(void);
sahilmgandhi 18:6a4db94011d3 68 static void can_reset_reg(can_t *obj);
sahilmgandhi 18:6a4db94011d3 69 static void can_reset_recv_rule(can_t *obj);
sahilmgandhi 18:6a4db94011d3 70 static void can_reset_buffer(can_t *obj);
sahilmgandhi 18:6a4db94011d3 71 static void can_reconfigure_channel(void);
sahilmgandhi 18:6a4db94011d3 72 static void can_set_frequency(can_t *obj, int f);
sahilmgandhi 18:6a4db94011d3 73 static void can_set_global_mode(int mode);
sahilmgandhi 18:6a4db94011d3 74 static void can_set_channel_mode(uint32_t ch, int mode);
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 typedef enum {
sahilmgandhi 18:6a4db94011d3 77 CAN_SEND = 0,
sahilmgandhi 18:6a4db94011d3 78 CAN_RECV
sahilmgandhi 18:6a4db94011d3 79 } CANfunc;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 typedef enum {
sahilmgandhi 18:6a4db94011d3 82 GL_OPE = 0,
sahilmgandhi 18:6a4db94011d3 83 GL_RESET,
sahilmgandhi 18:6a4db94011d3 84 GL_TEST
sahilmgandhi 18:6a4db94011d3 85 } Globalmode;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 typedef enum {
sahilmgandhi 18:6a4db94011d3 88 CH_COMM = 0,
sahilmgandhi 18:6a4db94011d3 89 CH_RESET,
sahilmgandhi 18:6a4db94011d3 90 CH_HOLD
sahilmgandhi 18:6a4db94011d3 91 } Channelmode;
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 typedef struct {
sahilmgandhi 18:6a4db94011d3 94 IRQn_Type int_num; /* Interrupt number */
sahilmgandhi 18:6a4db94011d3 95 IRQHandler handler; /* Interrupt handler */
sahilmgandhi 18:6a4db94011d3 96 } can_info_int_t;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 static can_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 99 static uint32_t can_irq_id[CAN_NUM];
sahilmgandhi 18:6a4db94011d3 100 static int can_initialized[CAN_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 #ifdef MAX_PERI
sahilmgandhi 18:6a4db94011d3 103 static const PinMap PinMap_CAN_RD[] = {
sahilmgandhi 18:6a4db94011d3 104 {P7_8 , CAN_0, 4},
sahilmgandhi 18:6a4db94011d3 105 {P9_1 , CAN_0, 3},
sahilmgandhi 18:6a4db94011d3 106 {P1_4 , CAN_1, 3},
sahilmgandhi 18:6a4db94011d3 107 {P5_9 , CAN_1, 5},
sahilmgandhi 18:6a4db94011d3 108 {P7_11 , CAN_1, 4},
sahilmgandhi 18:6a4db94011d3 109 {P4_9 , CAN_2, 6},
sahilmgandhi 18:6a4db94011d3 110 {P6_4 , CAN_2, 3},
sahilmgandhi 18:6a4db94011d3 111 {P7_2 , CAN_2, 5},
sahilmgandhi 18:6a4db94011d3 112 {P2_12 , CAN_3, 5},
sahilmgandhi 18:6a4db94011d3 113 {P4_2 , CAN_3, 4},
sahilmgandhi 18:6a4db94011d3 114 {P1_5 , CAN_4, 3},
sahilmgandhi 18:6a4db94011d3 115 {P2_14 , CAN_4, 5},
sahilmgandhi 18:6a4db94011d3 116 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 117 };
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 static const PinMap PinMap_CAN_TD[] = {
sahilmgandhi 18:6a4db94011d3 120 {P7_9 , CAN_0, 4},
sahilmgandhi 18:6a4db94011d3 121 {P9_0 , CAN_0, 3},
sahilmgandhi 18:6a4db94011d3 122 {P5_10 , CAN_1, 5},
sahilmgandhi 18:6a4db94011d3 123 {P7_10 , CAN_1, 4},
sahilmgandhi 18:6a4db94011d3 124 {P4_8 , CAN_2, 6},
sahilmgandhi 18:6a4db94011d3 125 {P6_5 , CAN_2, 3},
sahilmgandhi 18:6a4db94011d3 126 {P7_3 , CAN_2, 5},
sahilmgandhi 18:6a4db94011d3 127 {P2_13 , CAN_3, 5},
sahilmgandhi 18:6a4db94011d3 128 {P4_3 , CAN_3, 4},
sahilmgandhi 18:6a4db94011d3 129 {P4_11 , CAN_4, 6},
sahilmgandhi 18:6a4db94011d3 130 {P8_10 , CAN_4, 5},
sahilmgandhi 18:6a4db94011d3 131 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 132 };
sahilmgandhi 18:6a4db94011d3 133 #else
sahilmgandhi 18:6a4db94011d3 134 static const PinMap PinMap_CAN_RD[] = {
sahilmgandhi 18:6a4db94011d3 135 {P9_1 , CAN_0, 3},
sahilmgandhi 18:6a4db94011d3 136 {P1_4 , CAN_1, 3},
sahilmgandhi 18:6a4db94011d3 137 {P5_9 , CAN_1, 5},
sahilmgandhi 18:6a4db94011d3 138 {P4_2 , CAN_3, 4},
sahilmgandhi 18:6a4db94011d3 139 {P1_5 , CAN_4, 3},
sahilmgandhi 18:6a4db94011d3 140 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 141 };
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 static const PinMap PinMap_CAN_TD[] = {
sahilmgandhi 18:6a4db94011d3 144 {P9_0 , CAN_0, 3},
sahilmgandhi 18:6a4db94011d3 145 {P5_10 , CAN_1, 5},
sahilmgandhi 18:6a4db94011d3 146 {P4_3 , CAN_3, 4},
sahilmgandhi 18:6a4db94011d3 147 {P8_10 , CAN_4, 5},
sahilmgandhi 18:6a4db94011d3 148 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 149 };
sahilmgandhi 18:6a4db94011d3 150 #endif
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 static __IO uint32_t *CTR_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 153 &RSCAN0C0CTR,
sahilmgandhi 18:6a4db94011d3 154 &RSCAN0C1CTR,
sahilmgandhi 18:6a4db94011d3 155 &RSCAN0C2CTR,
sahilmgandhi 18:6a4db94011d3 156 &RSCAN0C3CTR,
sahilmgandhi 18:6a4db94011d3 157 &RSCAN0C4CTR,
sahilmgandhi 18:6a4db94011d3 158 };
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 static __IO uint32_t *CFG_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 161 &RSCAN0C0CFG,
sahilmgandhi 18:6a4db94011d3 162 &RSCAN0C1CFG,
sahilmgandhi 18:6a4db94011d3 163 &RSCAN0C2CFG,
sahilmgandhi 18:6a4db94011d3 164 &RSCAN0C3CFG,
sahilmgandhi 18:6a4db94011d3 165 &RSCAN0C4CFG,
sahilmgandhi 18:6a4db94011d3 166 };
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 static __IO uint32_t *RFCC_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 169 &RSCAN0RFCC0,
sahilmgandhi 18:6a4db94011d3 170 &RSCAN0RFCC1,
sahilmgandhi 18:6a4db94011d3 171 &RSCAN0RFCC2,
sahilmgandhi 18:6a4db94011d3 172 &RSCAN0RFCC3,
sahilmgandhi 18:6a4db94011d3 173 &RSCAN0RFCC4,
sahilmgandhi 18:6a4db94011d3 174 &RSCAN0RFCC5,
sahilmgandhi 18:6a4db94011d3 175 &RSCAN0RFCC6,
sahilmgandhi 18:6a4db94011d3 176 &RSCAN0RFCC7
sahilmgandhi 18:6a4db94011d3 177 };
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 static __IO uint32_t *TXQCC_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 180 &RSCAN0TXQCC0,
sahilmgandhi 18:6a4db94011d3 181 &RSCAN0TXQCC1,
sahilmgandhi 18:6a4db94011d3 182 &RSCAN0TXQCC2,
sahilmgandhi 18:6a4db94011d3 183 &RSCAN0TXQCC3,
sahilmgandhi 18:6a4db94011d3 184 &RSCAN0TXQCC4,
sahilmgandhi 18:6a4db94011d3 185 };
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 static __IO uint32_t *THLCC_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 188 &RSCAN0THLCC0,
sahilmgandhi 18:6a4db94011d3 189 &RSCAN0THLCC1,
sahilmgandhi 18:6a4db94011d3 190 &RSCAN0THLCC2,
sahilmgandhi 18:6a4db94011d3 191 &RSCAN0THLCC3,
sahilmgandhi 18:6a4db94011d3 192 &RSCAN0THLCC4,
sahilmgandhi 18:6a4db94011d3 193 };
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 static __IO uint32_t *STS_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 196 &RSCAN0C0STS,
sahilmgandhi 18:6a4db94011d3 197 &RSCAN0C1STS,
sahilmgandhi 18:6a4db94011d3 198 &RSCAN0C2STS,
sahilmgandhi 18:6a4db94011d3 199 &RSCAN0C3STS,
sahilmgandhi 18:6a4db94011d3 200 &RSCAN0C4STS,
sahilmgandhi 18:6a4db94011d3 201 };
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 static __IO uint32_t *ERFL_MATCH[] = {
sahilmgandhi 18:6a4db94011d3 204 &RSCAN0C0ERFL,
sahilmgandhi 18:6a4db94011d3 205 &RSCAN0C1ERFL,
sahilmgandhi 18:6a4db94011d3 206 &RSCAN0C2ERFL,
sahilmgandhi 18:6a4db94011d3 207 &RSCAN0C3ERFL,
sahilmgandhi 18:6a4db94011d3 208 &RSCAN0C4ERFL,
sahilmgandhi 18:6a4db94011d3 209 };
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 212 { &RSCAN0CFCC0 , &RSCAN0CFCC1 },
sahilmgandhi 18:6a4db94011d3 213 { &RSCAN0CFCC3 , &RSCAN0CFCC4 },
sahilmgandhi 18:6a4db94011d3 214 { &RSCAN0CFCC6 , &RSCAN0CFCC7 },
sahilmgandhi 18:6a4db94011d3 215 { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
sahilmgandhi 18:6a4db94011d3 216 { &RSCAN0CFCC12, &RSCAN0CFCC13 }
sahilmgandhi 18:6a4db94011d3 217 };
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 220 { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 },
sahilmgandhi 18:6a4db94011d3 221 { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 },
sahilmgandhi 18:6a4db94011d3 222 { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 },
sahilmgandhi 18:6a4db94011d3 223 { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
sahilmgandhi 18:6a4db94011d3 224 { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }
sahilmgandhi 18:6a4db94011d3 225 };
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 228 { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 },
sahilmgandhi 18:6a4db94011d3 229 { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 },
sahilmgandhi 18:6a4db94011d3 230 { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 },
sahilmgandhi 18:6a4db94011d3 231 { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
sahilmgandhi 18:6a4db94011d3 232 { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }
sahilmgandhi 18:6a4db94011d3 233 };
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 236 { &RSCAN0CFID0 , &RSCAN0CFID1 },
sahilmgandhi 18:6a4db94011d3 237 { &RSCAN0CFID3 , &RSCAN0CFID4 },
sahilmgandhi 18:6a4db94011d3 238 { &RSCAN0CFID6 , &RSCAN0CFID7 },
sahilmgandhi 18:6a4db94011d3 239 { &RSCAN0CFID9 , &RSCAN0CFID10 },
sahilmgandhi 18:6a4db94011d3 240 { &RSCAN0CFID12, &RSCAN0CFID13 }
sahilmgandhi 18:6a4db94011d3 241 };
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 244 { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 },
sahilmgandhi 18:6a4db94011d3 245 { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 },
sahilmgandhi 18:6a4db94011d3 246 { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 },
sahilmgandhi 18:6a4db94011d3 247 { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
sahilmgandhi 18:6a4db94011d3 248 { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
sahilmgandhi 18:6a4db94011d3 249 };
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 252 { &RSCAN0CFDF00 , &RSCAN0CFDF01 },
sahilmgandhi 18:6a4db94011d3 253 { &RSCAN0CFDF03 , &RSCAN0CFDF04 },
sahilmgandhi 18:6a4db94011d3 254 { &RSCAN0CFDF06 , &RSCAN0CFDF07 },
sahilmgandhi 18:6a4db94011d3 255 { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
sahilmgandhi 18:6a4db94011d3 256 { &RSCAN0CFDF012, &RSCAN0CFDF013 }
sahilmgandhi 18:6a4db94011d3 257 };
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
sahilmgandhi 18:6a4db94011d3 260 { &RSCAN0CFDF10 , &RSCAN0CFDF11 },
sahilmgandhi 18:6a4db94011d3 261 { &RSCAN0CFDF13 , &RSCAN0CFDF14 },
sahilmgandhi 18:6a4db94011d3 262 { &RSCAN0CFDF16 , &RSCAN0CFDF17 },
sahilmgandhi 18:6a4db94011d3 263 { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
sahilmgandhi 18:6a4db94011d3 264 { &RSCAN0CFDF112, &RSCAN0CFDF113 }
sahilmgandhi 18:6a4db94011d3 265 };
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
sahilmgandhi 18:6a4db94011d3 268 {
sahilmgandhi 18:6a4db94011d3 269 { /* ch0 */
sahilmgandhi 18:6a4db94011d3 270 { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */
sahilmgandhi 18:6a4db94011d3 271 { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */
sahilmgandhi 18:6a4db94011d3 272 { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
sahilmgandhi 18:6a4db94011d3 273 { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */
sahilmgandhi 18:6a4db94011d3 274 { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */
sahilmgandhi 18:6a4db94011d3 275 { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */
sahilmgandhi 18:6a4db94011d3 276 { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */
sahilmgandhi 18:6a4db94011d3 277 { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */
sahilmgandhi 18:6a4db94011d3 278 },
sahilmgandhi 18:6a4db94011d3 279 { /* ch1 */
sahilmgandhi 18:6a4db94011d3 280 { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */
sahilmgandhi 18:6a4db94011d3 281 { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */
sahilmgandhi 18:6a4db94011d3 282 { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
sahilmgandhi 18:6a4db94011d3 283 { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */
sahilmgandhi 18:6a4db94011d3 284 { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */
sahilmgandhi 18:6a4db94011d3 285 { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */
sahilmgandhi 18:6a4db94011d3 286 { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */
sahilmgandhi 18:6a4db94011d3 287 { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */
sahilmgandhi 18:6a4db94011d3 288 },
sahilmgandhi 18:6a4db94011d3 289 { /* ch2 */
sahilmgandhi 18:6a4db94011d3 290 { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */
sahilmgandhi 18:6a4db94011d3 291 { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */
sahilmgandhi 18:6a4db94011d3 292 { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
sahilmgandhi 18:6a4db94011d3 293 { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */
sahilmgandhi 18:6a4db94011d3 294 { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */
sahilmgandhi 18:6a4db94011d3 295 { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */
sahilmgandhi 18:6a4db94011d3 296 { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */
sahilmgandhi 18:6a4db94011d3 297 { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */
sahilmgandhi 18:6a4db94011d3 298 },
sahilmgandhi 18:6a4db94011d3 299 { /* ch3 */
sahilmgandhi 18:6a4db94011d3 300 { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */
sahilmgandhi 18:6a4db94011d3 301 { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */
sahilmgandhi 18:6a4db94011d3 302 { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
sahilmgandhi 18:6a4db94011d3 303 { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */
sahilmgandhi 18:6a4db94011d3 304 { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */
sahilmgandhi 18:6a4db94011d3 305 { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */
sahilmgandhi 18:6a4db94011d3 306 { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */
sahilmgandhi 18:6a4db94011d3 307 { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */
sahilmgandhi 18:6a4db94011d3 308 },
sahilmgandhi 18:6a4db94011d3 309 { /* ch4 */
sahilmgandhi 18:6a4db94011d3 310 { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */
sahilmgandhi 18:6a4db94011d3 311 { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */
sahilmgandhi 18:6a4db94011d3 312 { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
sahilmgandhi 18:6a4db94011d3 313 { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */
sahilmgandhi 18:6a4db94011d3 314 { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */
sahilmgandhi 18:6a4db94011d3 315 { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */
sahilmgandhi 18:6a4db94011d3 316 { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */
sahilmgandhi 18:6a4db94011d3 317 { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319 };
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
sahilmgandhi 18:6a4db94011d3 322 static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0;
sahilmgandhi 18:6a4db94011d3 323 static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
sahilmgandhi 18:6a4db94011d3 324 static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 327 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 328 can_irq_id[obj->ch] = id;
sahilmgandhi 18:6a4db94011d3 329 }
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 void can_irq_free(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 332 can_irq_id[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 336 __IO uint32_t *dmy_ctr;
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /* Wake-up Irq is not supported */
sahilmgandhi 18:6a4db94011d3 339 if (type != IRQ_WAKEUP) {
sahilmgandhi 18:6a4db94011d3 340 if (enable) {
sahilmgandhi 18:6a4db94011d3 341 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 342 if (type == IRQ_ERROR) {
sahilmgandhi 18:6a4db94011d3 343 /* EWIE interrupts is enable */
sahilmgandhi 18:6a4db94011d3 344 *dmy_ctr |= 0x00000200;
sahilmgandhi 18:6a4db94011d3 345 } else if (type == IRQ_OVERRUN) {
sahilmgandhi 18:6a4db94011d3 346 /* OLIE interrupts is enable */
sahilmgandhi 18:6a4db94011d3 347 *dmy_ctr |= 0x00002000;
sahilmgandhi 18:6a4db94011d3 348 } else if (type == IRQ_PASSIVE) {
sahilmgandhi 18:6a4db94011d3 349 /* EPIE interrupts is enable */
sahilmgandhi 18:6a4db94011d3 350 *dmy_ctr |= 0x00000400;
sahilmgandhi 18:6a4db94011d3 351 } else if (type == IRQ_ARB) {
sahilmgandhi 18:6a4db94011d3 352 /* ALIE interrupts is enable */
sahilmgandhi 18:6a4db94011d3 353 *dmy_ctr |= 0x00008000;
sahilmgandhi 18:6a4db94011d3 354 } else if (type == IRQ_BUS) {
sahilmgandhi 18:6a4db94011d3 355 /* BEIE interrupts is enable */
sahilmgandhi 18:6a4db94011d3 356 *dmy_ctr |= 0x00000100;
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358 InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
sahilmgandhi 18:6a4db94011d3 359 GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
sahilmgandhi 18:6a4db94011d3 360 GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
sahilmgandhi 18:6a4db94011d3 361 } else {
sahilmgandhi 18:6a4db94011d3 362 GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365 }
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 static void can_rec_irq(uint32_t ch) {
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t *dmy_cfsts;
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 371 *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 irq_handler(can_irq_id[ch], IRQ_RX);
sahilmgandhi 18:6a4db94011d3 374 }
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 static void can_trx_irq(uint32_t ch) {
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t *dmy_cfsts;
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 380 *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 irq_handler(can_irq_id[ch], IRQ_TX);
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 static void can_err_irq(uint32_t ch, CanIrqType type) {
sahilmgandhi 18:6a4db94011d3 386 __IO uint32_t *dmy_erfl;
sahilmgandhi 18:6a4db94011d3 387 int val = 1;
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 dmy_erfl = ERFL_MATCH[ch];
sahilmgandhi 18:6a4db94011d3 390 switch (type) {
sahilmgandhi 18:6a4db94011d3 391 case IRQ_ERROR:
sahilmgandhi 18:6a4db94011d3 392 *dmy_erfl &= 0xFFFFFFFD; // Clear EWF
sahilmgandhi 18:6a4db94011d3 393 break;
sahilmgandhi 18:6a4db94011d3 394 case IRQ_OVERRUN:
sahilmgandhi 18:6a4db94011d3 395 *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF
sahilmgandhi 18:6a4db94011d3 396 break;
sahilmgandhi 18:6a4db94011d3 397 case IRQ_PASSIVE:
sahilmgandhi 18:6a4db94011d3 398 *dmy_erfl &= 0xFFFFFFFB; // Clear EPF
sahilmgandhi 18:6a4db94011d3 399 break;
sahilmgandhi 18:6a4db94011d3 400 case IRQ_ARB:
sahilmgandhi 18:6a4db94011d3 401 *dmy_erfl &= 0xFFFFFF7F; // Clear ALF
sahilmgandhi 18:6a4db94011d3 402 break;
sahilmgandhi 18:6a4db94011d3 403 case IRQ_BUS:
sahilmgandhi 18:6a4db94011d3 404 *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR
sahilmgandhi 18:6a4db94011d3 405 *dmy_erfl &= 0xFFFFFFFE; // Clear BEF
sahilmgandhi 18:6a4db94011d3 406 break;
sahilmgandhi 18:6a4db94011d3 407 case IRQ_WAKEUP:
sahilmgandhi 18:6a4db94011d3 408 /* not supported */
sahilmgandhi 18:6a4db94011d3 409 /* fall through */
sahilmgandhi 18:6a4db94011d3 410 default:
sahilmgandhi 18:6a4db94011d3 411 val = 0;
sahilmgandhi 18:6a4db94011d3 412 break;
sahilmgandhi 18:6a4db94011d3 413 }
sahilmgandhi 18:6a4db94011d3 414 if (val == 1) {
sahilmgandhi 18:6a4db94011d3 415 irq_handler(can_irq_id[ch], type);
sahilmgandhi 18:6a4db94011d3 416 }
sahilmgandhi 18:6a4db94011d3 417 }
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 static void can0_rec_irq(void) {
sahilmgandhi 18:6a4db94011d3 420 can_rec_irq(CAN_0);
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 static void can1_rec_irq(void) {
sahilmgandhi 18:6a4db94011d3 424 can_rec_irq(CAN_1);
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 static void can2_rec_irq(void) {
sahilmgandhi 18:6a4db94011d3 428 can_rec_irq(CAN_2);
sahilmgandhi 18:6a4db94011d3 429 }
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 static void can3_rec_irq(void) {
sahilmgandhi 18:6a4db94011d3 432 can_rec_irq(CAN_3);
sahilmgandhi 18:6a4db94011d3 433 }
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 static void can4_rec_irq(void) {
sahilmgandhi 18:6a4db94011d3 436 can_rec_irq(CAN_4);
sahilmgandhi 18:6a4db94011d3 437 }
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 static void can0_trx_irq(void) {
sahilmgandhi 18:6a4db94011d3 440 can_trx_irq(CAN_0);
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 static void can1_trx_irq(void) {
sahilmgandhi 18:6a4db94011d3 444 can_trx_irq(CAN_1);
sahilmgandhi 18:6a4db94011d3 445 }
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 static void can2_trx_irq(void) {
sahilmgandhi 18:6a4db94011d3 448 can_trx_irq(CAN_2);
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 static void can3_trx_irq(void) {
sahilmgandhi 18:6a4db94011d3 452 can_trx_irq(CAN_3);
sahilmgandhi 18:6a4db94011d3 453 }
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 static void can4_trx_irq(void) {
sahilmgandhi 18:6a4db94011d3 456 can_trx_irq(CAN_4);
sahilmgandhi 18:6a4db94011d3 457 }
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 static void can0_err_warning_irq(void) {
sahilmgandhi 18:6a4db94011d3 460 can_err_irq(CAN_0, IRQ_ERROR);
sahilmgandhi 18:6a4db94011d3 461 }
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 static void can1_err_warning_irq(void) {
sahilmgandhi 18:6a4db94011d3 464 can_err_irq(CAN_1, IRQ_ERROR);
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 static void can2_err_warning_irq(void) {
sahilmgandhi 18:6a4db94011d3 468 can_err_irq(CAN_2, IRQ_ERROR);
sahilmgandhi 18:6a4db94011d3 469 }
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 static void can3_err_warning_irq(void) {
sahilmgandhi 18:6a4db94011d3 472 can_err_irq(CAN_3, IRQ_ERROR);
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 static void can4_err_warning_irq(void) {
sahilmgandhi 18:6a4db94011d3 476 can_err_irq(CAN_4, IRQ_ERROR);
sahilmgandhi 18:6a4db94011d3 477 }
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 static void can0_overrun_irq(void) {
sahilmgandhi 18:6a4db94011d3 480 can_err_irq(CAN_0, IRQ_OVERRUN);
sahilmgandhi 18:6a4db94011d3 481 }
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 static void can1_overrun_irq(void) {
sahilmgandhi 18:6a4db94011d3 484 can_err_irq(CAN_1, IRQ_OVERRUN);
sahilmgandhi 18:6a4db94011d3 485 }
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 static void can2_overrun_irq(void) {
sahilmgandhi 18:6a4db94011d3 488 can_err_irq(CAN_2, IRQ_OVERRUN);
sahilmgandhi 18:6a4db94011d3 489 }
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 static void can3_overrun_irq(void) {
sahilmgandhi 18:6a4db94011d3 492 can_err_irq(CAN_3, IRQ_OVERRUN);
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 static void can4_overrun_irq(void) {
sahilmgandhi 18:6a4db94011d3 496 can_err_irq(CAN_4, IRQ_OVERRUN);
sahilmgandhi 18:6a4db94011d3 497 }
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 static void can0_passive_irq(void) {
sahilmgandhi 18:6a4db94011d3 500 can_err_irq(CAN_0, IRQ_PASSIVE);
sahilmgandhi 18:6a4db94011d3 501 }
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 static void can1_passive_irq(void) {
sahilmgandhi 18:6a4db94011d3 504 can_err_irq(CAN_1, IRQ_PASSIVE);
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 static void can2_passive_irq(void) {
sahilmgandhi 18:6a4db94011d3 508 can_err_irq(CAN_2, IRQ_PASSIVE);
sahilmgandhi 18:6a4db94011d3 509 }
sahilmgandhi 18:6a4db94011d3 510
sahilmgandhi 18:6a4db94011d3 511 static void can3_passive_irq(void) {
sahilmgandhi 18:6a4db94011d3 512 can_err_irq(CAN_3, IRQ_PASSIVE);
sahilmgandhi 18:6a4db94011d3 513 }
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 static void can4_passive_irq(void) {
sahilmgandhi 18:6a4db94011d3 516 can_err_irq(CAN_4, IRQ_PASSIVE);
sahilmgandhi 18:6a4db94011d3 517 }
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 static void can0_arb_lost_irq(void) {
sahilmgandhi 18:6a4db94011d3 520 can_err_irq(CAN_0, IRQ_ARB);
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 static void can1_arb_lost_irq(void) {
sahilmgandhi 18:6a4db94011d3 524 can_err_irq(CAN_1, IRQ_ARB);
sahilmgandhi 18:6a4db94011d3 525 }
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 static void can2_arb_lost_irq(void) {
sahilmgandhi 18:6a4db94011d3 528 can_err_irq(CAN_2, IRQ_ARB);
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 static void can3_arb_lost_irq(void) {
sahilmgandhi 18:6a4db94011d3 532 can_err_irq(CAN_3, IRQ_ARB);
sahilmgandhi 18:6a4db94011d3 533 }
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 static void can4_arb_lost_irq(void) {
sahilmgandhi 18:6a4db94011d3 536 can_err_irq(CAN_4, IRQ_ARB);
sahilmgandhi 18:6a4db94011d3 537 }
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 static void can0_bus_err_irq(void) {
sahilmgandhi 18:6a4db94011d3 540 can_err_irq(CAN_0, IRQ_BUS);
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 static void can1_bus_err_irq(void) {
sahilmgandhi 18:6a4db94011d3 544 can_err_irq(CAN_1, IRQ_BUS);
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 static void can2_bus_err_irq(void) {
sahilmgandhi 18:6a4db94011d3 548 can_err_irq(CAN_2, IRQ_BUS);
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 static void can3_bus_err_irq(void) {
sahilmgandhi 18:6a4db94011d3 552 can_err_irq(CAN_3, IRQ_BUS);
sahilmgandhi 18:6a4db94011d3 553 }
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555 static void can4_bus_err_irq(void) {
sahilmgandhi 18:6a4db94011d3 556 can_err_irq(CAN_4, IRQ_BUS);
sahilmgandhi 18:6a4db94011d3 557 }
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 void can_init(can_t *obj, PinName rd, PinName td) {
sahilmgandhi 18:6a4db94011d3 560 __IO uint32_t *dmy_ctr;
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /* determine the CAN to use */
sahilmgandhi 18:6a4db94011d3 563 uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
sahilmgandhi 18:6a4db94011d3 564 uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
sahilmgandhi 18:6a4db94011d3 565 obj->ch = pinmap_merge(can_tx, can_rx);
sahilmgandhi 18:6a4db94011d3 566 MBED_ASSERT((int)obj->ch != NC);
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 /* enable CAN clock */
sahilmgandhi 18:6a4db94011d3 569 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
sahilmgandhi 18:6a4db94011d3 570 /* Has CAN RAM initialisation completed ? */
sahilmgandhi 18:6a4db94011d3 571 while ((RSCAN0GSTS & 0x08) == 0x08) {
sahilmgandhi 18:6a4db94011d3 572 __NOP();
sahilmgandhi 18:6a4db94011d3 573 }
sahilmgandhi 18:6a4db94011d3 574 /* clear Global Stop mode bit */
sahilmgandhi 18:6a4db94011d3 575 RSCAN0GCTR &= 0xFFFFFFFB;
sahilmgandhi 18:6a4db94011d3 576 /* clear Channel Stop mode bit */
sahilmgandhi 18:6a4db94011d3 577 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 578 *dmy_ctr &= 0xFFFFFFFB;
sahilmgandhi 18:6a4db94011d3 579 /* Enter global reset mode */
sahilmgandhi 18:6a4db94011d3 580 can_set_global_mode(GL_RESET);
sahilmgandhi 18:6a4db94011d3 581 /* Enter channel reset mode */
sahilmgandhi 18:6a4db94011d3 582 can_set_channel_mode(obj->ch, CH_RESET);
sahilmgandhi 18:6a4db94011d3 583 /* reset register */
sahilmgandhi 18:6a4db94011d3 584 can_reset_reg(obj);
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 can_initialized[obj->ch] = 1;
sahilmgandhi 18:6a4db94011d3 587 /* reconfigure channel which is already initialized */
sahilmgandhi 18:6a4db94011d3 588 can_reconfigure_channel();
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /* pin out the can pins */
sahilmgandhi 18:6a4db94011d3 591 pinmap_pinout(rd, PinMap_CAN_RD);
sahilmgandhi 18:6a4db94011d3 592 pinmap_pinout(td, PinMap_CAN_TD);
sahilmgandhi 18:6a4db94011d3 593 }
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 void can_free(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 596 /* disable CAN clock */
sahilmgandhi 18:6a4db94011d3 597 CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
sahilmgandhi 18:6a4db94011d3 598 }
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 int can_frequency(can_t *obj, int f) {
sahilmgandhi 18:6a4db94011d3 601 __IO uint32_t *dmy_cfcc;
sahilmgandhi 18:6a4db94011d3 602 int retval = 0;
sahilmgandhi 18:6a4db94011d3 603
sahilmgandhi 18:6a4db94011d3 604 if (f <= 1000000) {
sahilmgandhi 18:6a4db94011d3 605 /* less than 1Mhz */
sahilmgandhi 18:6a4db94011d3 606 /* set Channel Reset mode */
sahilmgandhi 18:6a4db94011d3 607 can_set_channel_mode(obj->ch, CH_RESET);
sahilmgandhi 18:6a4db94011d3 608 can_set_frequency(obj, f);
sahilmgandhi 18:6a4db94011d3 609 /* set Channel Communication mode */
sahilmgandhi 18:6a4db94011d3 610 can_set_channel_mode(obj->ch, CH_COMM);
sahilmgandhi 18:6a4db94011d3 611 /* restore CFE bit since it is cleared */
sahilmgandhi 18:6a4db94011d3 612 /* Use send/receive FIFO buffer */
sahilmgandhi 18:6a4db94011d3 613 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 614 *dmy_cfcc |= 0x01;
sahilmgandhi 18:6a4db94011d3 615 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 616 *dmy_cfcc |= 0x01;
sahilmgandhi 18:6a4db94011d3 617 retval = 1;
sahilmgandhi 18:6a4db94011d3 618 }
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 return retval;
sahilmgandhi 18:6a4db94011d3 621 }
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 void can_reset(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 624 /* Enter global reset mode */
sahilmgandhi 18:6a4db94011d3 625 can_set_global_mode(GL_RESET);
sahilmgandhi 18:6a4db94011d3 626 /* Enter channel reset mode */
sahilmgandhi 18:6a4db94011d3 627 can_set_channel_mode(obj->ch, CH_RESET);
sahilmgandhi 18:6a4db94011d3 628 /* reset register */
sahilmgandhi 18:6a4db94011d3 629 can_reset_reg(obj);
sahilmgandhi 18:6a4db94011d3 630 /* reconfigure channel which is already initialized */
sahilmgandhi 18:6a4db94011d3 631 can_reconfigure_channel();
sahilmgandhi 18:6a4db94011d3 632 }
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634 int can_write(can_t *obj, CAN_Message msg, int cc) {
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t *dmy_sts;
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t *dmy_cfsts;
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t *dmy_cfid;
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t *dmy_cfptr;
sahilmgandhi 18:6a4db94011d3 639 __IO uint32_t *dmy_cfdf0;
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t *dmy_cfdf1;
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t *dmy_cfpctr;
sahilmgandhi 18:6a4db94011d3 642 int retval = 0;
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 /* Wait to become channel communication mode */
sahilmgandhi 18:6a4db94011d3 645 dmy_sts = STS_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 646 while ((*dmy_sts & 0x07) != 0) {
sahilmgandhi 18:6a4db94011d3 647 __NOP();
sahilmgandhi 18:6a4db94011d3 648 }
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650 if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
sahilmgandhi 18:6a4db94011d3 651 /* send/receive FIFO buffer isn't full */
sahilmgandhi 18:6a4db94011d3 652 dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 653 if ((*dmy_cfsts & 0x02) != 0x02) {
sahilmgandhi 18:6a4db94011d3 654 /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
sahilmgandhi 18:6a4db94011d3 655 dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 656 *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
sahilmgandhi 18:6a4db94011d3 657 if (msg.format == CANStandard) {
sahilmgandhi 18:6a4db94011d3 658 *dmy_cfid |= (msg.id & 0x07FF);
sahilmgandhi 18:6a4db94011d3 659 } else {
sahilmgandhi 18:6a4db94011d3 660 *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
sahilmgandhi 18:6a4db94011d3 661 }
sahilmgandhi 18:6a4db94011d3 662 /* set length */
sahilmgandhi 18:6a4db94011d3 663 dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 664 *dmy_cfptr = msg.len << 28;
sahilmgandhi 18:6a4db94011d3 665 /* set data */
sahilmgandhi 18:6a4db94011d3 666 dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 667 memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
sahilmgandhi 18:6a4db94011d3 668 dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 669 memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
sahilmgandhi 18:6a4db94011d3 670 /* send request */
sahilmgandhi 18:6a4db94011d3 671 dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 672 *dmy_cfpctr = 0xFF;
sahilmgandhi 18:6a4db94011d3 673 retval = 1;
sahilmgandhi 18:6a4db94011d3 674 }
sahilmgandhi 18:6a4db94011d3 675 }
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 return retval;
sahilmgandhi 18:6a4db94011d3 678 }
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 int can_read(can_t *obj, CAN_Message *msg, int handle) {
sahilmgandhi 18:6a4db94011d3 681 __IO uint32_t *dmy_sts;
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t *dmy_cfsts;
sahilmgandhi 18:6a4db94011d3 683 __IO uint32_t *dmy_cfid;
sahilmgandhi 18:6a4db94011d3 684 __IO uint32_t *dmy_cfptr;
sahilmgandhi 18:6a4db94011d3 685 __IO uint32_t *dmy_cfdf0;
sahilmgandhi 18:6a4db94011d3 686 __IO uint32_t *dmy_cfdf1;
sahilmgandhi 18:6a4db94011d3 687 __IO uint32_t *dmy_cfpctr;
sahilmgandhi 18:6a4db94011d3 688 int retval = 0;
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 /* Wait to become channel communication mode */
sahilmgandhi 18:6a4db94011d3 691 dmy_sts = STS_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 692 while ((*dmy_sts & 0x07) != 0) {
sahilmgandhi 18:6a4db94011d3 693 __NOP();
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /* send/receive FIFO buffer isn't empty */
sahilmgandhi 18:6a4db94011d3 697 dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 698 while ((*dmy_cfsts & 0x01) != 0x01) {
sahilmgandhi 18:6a4db94011d3 699 /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
sahilmgandhi 18:6a4db94011d3 700 dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 701 msg->format = (CANFormat)(*dmy_cfid >> 31);
sahilmgandhi 18:6a4db94011d3 702 msg->type = (CANType)(*dmy_cfid >> 30);
sahilmgandhi 18:6a4db94011d3 703 if (msg->format == CANStandard) {
sahilmgandhi 18:6a4db94011d3 704 msg->id = (*dmy_cfid & 0x07FF);
sahilmgandhi 18:6a4db94011d3 705 } else {
sahilmgandhi 18:6a4db94011d3 706 msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
sahilmgandhi 18:6a4db94011d3 707 }
sahilmgandhi 18:6a4db94011d3 708 /* get length */
sahilmgandhi 18:6a4db94011d3 709 dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 710 msg->len = (unsigned char)(*dmy_cfptr >> 28);
sahilmgandhi 18:6a4db94011d3 711 /* get data */
sahilmgandhi 18:6a4db94011d3 712 dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 713 memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
sahilmgandhi 18:6a4db94011d3 714 dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 715 memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
sahilmgandhi 18:6a4db94011d3 716 /* receive(next data) request */
sahilmgandhi 18:6a4db94011d3 717 dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 718 *dmy_cfpctr = 0xFF;
sahilmgandhi 18:6a4db94011d3 719 retval = 1;
sahilmgandhi 18:6a4db94011d3 720 }
sahilmgandhi 18:6a4db94011d3 721
sahilmgandhi 18:6a4db94011d3 722 return retval;
sahilmgandhi 18:6a4db94011d3 723 }
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725 unsigned char can_rderror(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 726 __IO uint32_t *dmy_sts;
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728 dmy_sts = STS_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 729 return (unsigned char)((*dmy_sts >> 16) & 0xFF);
sahilmgandhi 18:6a4db94011d3 730 }
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 unsigned char can_tderror(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 733 __IO uint32_t *dmy_sts;
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 dmy_sts = STS_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 736 return (unsigned char)((*dmy_sts >> 24) & 0xFF);
sahilmgandhi 18:6a4db94011d3 737 }
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 int can_mode(can_t *obj, CanMode mode) {
sahilmgandhi 18:6a4db94011d3 740 __IO uint32_t *dmy_ctr;
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t *dmy_sts;
sahilmgandhi 18:6a4db94011d3 742 __IO uint32_t *dmy_cfcc;
sahilmgandhi 18:6a4db94011d3 743 int ch_cnt;
sahilmgandhi 18:6a4db94011d3 744 can_t *tmp_obj;
sahilmgandhi 18:6a4db94011d3 745 tmp_obj = obj;
sahilmgandhi 18:6a4db94011d3 746 int retval = 1;
sahilmgandhi 18:6a4db94011d3 747
sahilmgandhi 18:6a4db94011d3 748 switch (mode) {
sahilmgandhi 18:6a4db94011d3 749 case MODE_RESET:
sahilmgandhi 18:6a4db94011d3 750 can_set_global_mode(GL_RESET);
sahilmgandhi 18:6a4db94011d3 751 can_set_channel_mode(obj->ch, CH_RESET);
sahilmgandhi 18:6a4db94011d3 752 for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
sahilmgandhi 18:6a4db94011d3 753 can_initialized[ch_cnt] = 0;
sahilmgandhi 18:6a4db94011d3 754 }
sahilmgandhi 18:6a4db94011d3 755 break;
sahilmgandhi 18:6a4db94011d3 756 case MODE_NORMAL:
sahilmgandhi 18:6a4db94011d3 757 can_set_global_mode(GL_OPE);
sahilmgandhi 18:6a4db94011d3 758 can_set_channel_mode(obj->ch, CH_COMM);
sahilmgandhi 18:6a4db94011d3 759 break;
sahilmgandhi 18:6a4db94011d3 760 case MODE_SILENT:
sahilmgandhi 18:6a4db94011d3 761 can_set_channel_mode(obj->ch, CH_HOLD);
sahilmgandhi 18:6a4db94011d3 762 /* set listen only mode, enable communication test mode */
sahilmgandhi 18:6a4db94011d3 763 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 764 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
sahilmgandhi 18:6a4db94011d3 765 can_set_channel_mode(obj->ch, CH_COMM);
sahilmgandhi 18:6a4db94011d3 766 break;
sahilmgandhi 18:6a4db94011d3 767 case MODE_TEST_LOCAL:
sahilmgandhi 18:6a4db94011d3 768 can_set_channel_mode(obj->ch, CH_HOLD);
sahilmgandhi 18:6a4db94011d3 769 /* set self test mode 0, enable communication test mode */
sahilmgandhi 18:6a4db94011d3 770 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 771 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
sahilmgandhi 18:6a4db94011d3 772 can_set_channel_mode(obj->ch, CH_COMM);
sahilmgandhi 18:6a4db94011d3 773 break;
sahilmgandhi 18:6a4db94011d3 774 case MODE_TEST_GLOBAL:
sahilmgandhi 18:6a4db94011d3 775 /* set the channel between the communication test on channel 1 and channel 2 */
sahilmgandhi 18:6a4db94011d3 776 /* set Channel Hold mode */
sahilmgandhi 18:6a4db94011d3 777 for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
sahilmgandhi 18:6a4db94011d3 778 dmy_sts = STS_MATCH[tmp_obj->ch];
sahilmgandhi 18:6a4db94011d3 779 if ((*dmy_sts & 0x04) == 0x04) {
sahilmgandhi 18:6a4db94011d3 780 /* Channel Stop mode */
sahilmgandhi 18:6a4db94011d3 781 /* clear Channel Stop mode bit */
sahilmgandhi 18:6a4db94011d3 782 dmy_ctr = CTR_MATCH[tmp_obj->ch];
sahilmgandhi 18:6a4db94011d3 783 *dmy_ctr &= 0xFFFFFFFB;
sahilmgandhi 18:6a4db94011d3 784 can_set_channel_mode(tmp_obj->ch, CH_RESET);
sahilmgandhi 18:6a4db94011d3 785 }
sahilmgandhi 18:6a4db94011d3 786 can_set_channel_mode(tmp_obj->ch, CH_HOLD);
sahilmgandhi 18:6a4db94011d3 787 }
sahilmgandhi 18:6a4db94011d3 788 can_set_global_mode(GL_TEST);
sahilmgandhi 18:6a4db94011d3 789 /* enable communication test between channel1 and channel2 */
sahilmgandhi 18:6a4db94011d3 790 RSCAN0GTSTCFG = 0x06;
sahilmgandhi 18:6a4db94011d3 791 RSCAN0GTSTCTR = 0x01;
sahilmgandhi 18:6a4db94011d3 792 /* send and receive setting of channel1 and channel2 */
sahilmgandhi 18:6a4db94011d3 793 for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
sahilmgandhi 18:6a4db94011d3 794 can_reset_buffer(tmp_obj);
sahilmgandhi 18:6a4db94011d3 795 /* set global interrrupt */
sahilmgandhi 18:6a4db94011d3 796 /* THLEIE, MEIE and DEIE interrupts are disable */
sahilmgandhi 18:6a4db94011d3 797 RSCAN0GCTR &= 0xFFFFF8FF;
sahilmgandhi 18:6a4db94011d3 798 /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
sahilmgandhi 18:6a4db94011d3 799 /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
sahilmgandhi 18:6a4db94011d3 800 dmy_ctr = CTR_MATCH[tmp_obj->ch];
sahilmgandhi 18:6a4db94011d3 801 *dmy_ctr &= 0x00018700;
sahilmgandhi 18:6a4db94011d3 802 can_set_global_mode(GL_OPE);
sahilmgandhi 18:6a4db94011d3 803 can_set_channel_mode(tmp_obj->ch, CH_COMM);
sahilmgandhi 18:6a4db94011d3 804 /* Use send/receive FIFO buffer */
sahilmgandhi 18:6a4db94011d3 805 dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 806 *dmy_cfcc |= 0x01;
sahilmgandhi 18:6a4db94011d3 807 dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 808 *dmy_cfcc |= 0x01;
sahilmgandhi 18:6a4db94011d3 809 }
sahilmgandhi 18:6a4db94011d3 810 break;
sahilmgandhi 18:6a4db94011d3 811 case MODE_TEST_SILENT:
sahilmgandhi 18:6a4db94011d3 812 /* not supported */
sahilmgandhi 18:6a4db94011d3 813 /* fall through */
sahilmgandhi 18:6a4db94011d3 814 default:
sahilmgandhi 18:6a4db94011d3 815 retval = 0;
sahilmgandhi 18:6a4db94011d3 816 break;
sahilmgandhi 18:6a4db94011d3 817 }
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 return retval;
sahilmgandhi 18:6a4db94011d3 820 }
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
sahilmgandhi 18:6a4db94011d3 823 int retval = 0;
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 if ((format == CANStandard) || (format == CANExtended)) {
sahilmgandhi 18:6a4db94011d3 826 if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
sahilmgandhi 18:6a4db94011d3 827 /* set Global Reset mode and Channel Reset mode */
sahilmgandhi 18:6a4db94011d3 828 can_set_global_mode(GL_RESET);
sahilmgandhi 18:6a4db94011d3 829 can_set_channel_mode(obj->ch, CH_RESET);
sahilmgandhi 18:6a4db94011d3 830 /* enable receive rule table writing */
sahilmgandhi 18:6a4db94011d3 831 RSCAN0GAFLECTR = 0x00000100;
sahilmgandhi 18:6a4db94011d3 832 /* set the page number of receive rule table(page number = 0) */
sahilmgandhi 18:6a4db94011d3 833 RSCAN0GAFLECTR |= (obj->ch * 4);
sahilmgandhi 18:6a4db94011d3 834 /* set IDE format */
sahilmgandhi 18:6a4db94011d3 835 *dmy_gaflid = (format << 31);
sahilmgandhi 18:6a4db94011d3 836 if (format == CANExtended) {
sahilmgandhi 18:6a4db94011d3 837 /* set receive rule ID for bit28-11 */
sahilmgandhi 18:6a4db94011d3 838 *dmy_gaflid |= (id << 11);
sahilmgandhi 18:6a4db94011d3 839 } else {
sahilmgandhi 18:6a4db94011d3 840 /* set receive rule ID for bit10-0 */
sahilmgandhi 18:6a4db94011d3 841 *dmy_gaflid |= id;
sahilmgandhi 18:6a4db94011d3 842 }
sahilmgandhi 18:6a4db94011d3 843 /* set ID mask bit */
sahilmgandhi 18:6a4db94011d3 844 *dmy_gaflm = (0xC0000000 | mask);
sahilmgandhi 18:6a4db94011d3 845 /* disable receive rule table writing */
sahilmgandhi 18:6a4db94011d3 846 RSCAN0GAFLECTR &= 0xFFFFFEFF;
sahilmgandhi 18:6a4db94011d3 847 /* reconfigure channel which is already initialized */
sahilmgandhi 18:6a4db94011d3 848 can_reconfigure_channel();
sahilmgandhi 18:6a4db94011d3 849 retval = 1;
sahilmgandhi 18:6a4db94011d3 850 }
sahilmgandhi 18:6a4db94011d3 851 }
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 return retval;
sahilmgandhi 18:6a4db94011d3 854 }
sahilmgandhi 18:6a4db94011d3 855
sahilmgandhi 18:6a4db94011d3 856 void can_monitor(can_t *obj, int silent) {
sahilmgandhi 18:6a4db94011d3 857 __IO uint32_t *dmy_ctr;
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 /* set Channel Hold mode */
sahilmgandhi 18:6a4db94011d3 860 can_set_channel_mode(obj->ch, CH_HOLD);
sahilmgandhi 18:6a4db94011d3 861 if (silent) {
sahilmgandhi 18:6a4db94011d3 862 /* set listen only mode, enable communication test mode */
sahilmgandhi 18:6a4db94011d3 863 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 864 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
sahilmgandhi 18:6a4db94011d3 865 can_set_channel_mode(obj->ch, CH_COMM);
sahilmgandhi 18:6a4db94011d3 866 } else {
sahilmgandhi 18:6a4db94011d3 867 /* set normal test mode, disable communication test mode */
sahilmgandhi 18:6a4db94011d3 868 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 869 *dmy_ctr &= 0x00FFFFFF;
sahilmgandhi 18:6a4db94011d3 870 /* reset register */
sahilmgandhi 18:6a4db94011d3 871 can_reset_reg(obj);
sahilmgandhi 18:6a4db94011d3 872 /* reconfigure channel which is already initialized */
sahilmgandhi 18:6a4db94011d3 873 can_reconfigure_channel();
sahilmgandhi 18:6a4db94011d3 874 }
sahilmgandhi 18:6a4db94011d3 875 }
sahilmgandhi 18:6a4db94011d3 876
sahilmgandhi 18:6a4db94011d3 877 static void can_reset_reg(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 878 __IO uint32_t *dmy_ctr;
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */
sahilmgandhi 18:6a4db94011d3 881 /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
sahilmgandhi 18:6a4db94011d3 882 RSCAN0GCFG = 0x00000003;
sahilmgandhi 18:6a4db94011d3 883 /* set default frequency at 100k */
sahilmgandhi 18:6a4db94011d3 884 can_set_frequency(obj, 100000);
sahilmgandhi 18:6a4db94011d3 885 /* set receive rule */
sahilmgandhi 18:6a4db94011d3 886 can_reset_recv_rule(obj);
sahilmgandhi 18:6a4db94011d3 887 /* set buffer */
sahilmgandhi 18:6a4db94011d3 888 can_reset_buffer(obj);
sahilmgandhi 18:6a4db94011d3 889 /* set global interrrupt */
sahilmgandhi 18:6a4db94011d3 890 /* THLEIE, MEIE and DEIE interrupts are disable */
sahilmgandhi 18:6a4db94011d3 891 RSCAN0GCTR &= 0xFFFFF8FF;
sahilmgandhi 18:6a4db94011d3 892 /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
sahilmgandhi 18:6a4db94011d3 893 dmy_ctr = CTR_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 894 *dmy_ctr &= 0xFFFF00FF;
sahilmgandhi 18:6a4db94011d3 895 }
sahilmgandhi 18:6a4db94011d3 896
sahilmgandhi 18:6a4db94011d3 897 static void can_reset_recv_rule(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 898 /* number of receive rules of each chanel = 64 */
sahilmgandhi 18:6a4db94011d3 899 RSCAN0GAFLCFG0 = 0x40404040;
sahilmgandhi 18:6a4db94011d3 900 RSCAN0GAFLCFG1 = 0x40000000;
sahilmgandhi 18:6a4db94011d3 901 /* enable receive rule table writing */
sahilmgandhi 18:6a4db94011d3 902 RSCAN0GAFLECTR = 0x00000100;
sahilmgandhi 18:6a4db94011d3 903 /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
sahilmgandhi 18:6a4db94011d3 904 RSCAN0GAFLECTR |= (obj->ch * 4);
sahilmgandhi 18:6a4db94011d3 905 /* set standard ID, data frame and receive rule ID */
sahilmgandhi 18:6a4db94011d3 906 *dmy_gaflid = 0x07FF;
sahilmgandhi 18:6a4db94011d3 907 /* IDE bit, RTR bit and ID bit(28-0) are not compared */
sahilmgandhi 18:6a4db94011d3 908 *dmy_gaflm = 0;
sahilmgandhi 18:6a4db94011d3 909 /* DLC check is 1 bytes, not use a receive buffer */
sahilmgandhi 18:6a4db94011d3 910 *dmy_gaflp0 = 0x10000000;
sahilmgandhi 18:6a4db94011d3 911 /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
sahilmgandhi 18:6a4db94011d3 912 *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
sahilmgandhi 18:6a4db94011d3 913 /* disable receive rule table writing */
sahilmgandhi 18:6a4db94011d3 914 RSCAN0GAFLECTR &= 0xFFFFFEFF;
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 static void can_reset_buffer(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 918 __IO uint32_t *dmy_rfcc;
sahilmgandhi 18:6a4db94011d3 919 __IO uint32_t *dmy_cfcc;
sahilmgandhi 18:6a4db94011d3 920 __IO uint32_t *dmy_txqcc;
sahilmgandhi 18:6a4db94011d3 921 __IO uint32_t *dmy_thlcc;
sahilmgandhi 18:6a4db94011d3 922 int cnt;
sahilmgandhi 18:6a4db94011d3 923
sahilmgandhi 18:6a4db94011d3 924 /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
sahilmgandhi 18:6a4db94011d3 925 /* number of rows of send/receive FIFO buffer = 4 */
sahilmgandhi 18:6a4db94011d3 926 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 927 *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */
sahilmgandhi 18:6a4db94011d3 928 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 929 *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */
sahilmgandhi 18:6a4db94011d3 930 /* receive buffer is not used */
sahilmgandhi 18:6a4db94011d3 931 RSCAN0RMNB = 0;
sahilmgandhi 18:6a4db94011d3 932 /* receive FIFO buffer is not used */
sahilmgandhi 18:6a4db94011d3 933 for (cnt = 0; cnt < 8; cnt++) {
sahilmgandhi 18:6a4db94011d3 934 dmy_rfcc = RFCC_MATCH[cnt];
sahilmgandhi 18:6a4db94011d3 935 *dmy_rfcc = 0;
sahilmgandhi 18:6a4db94011d3 936 }
sahilmgandhi 18:6a4db94011d3 937 /* send queue is not used */
sahilmgandhi 18:6a4db94011d3 938 dmy_txqcc = TXQCC_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 939 *dmy_txqcc = 0;
sahilmgandhi 18:6a4db94011d3 940 /* send history is not used */
sahilmgandhi 18:6a4db94011d3 941 dmy_thlcc = THLCC_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 942 *dmy_thlcc = 0;
sahilmgandhi 18:6a4db94011d3 943
sahilmgandhi 18:6a4db94011d3 944 /* CFTXIE and CFRXIE interrupts are enable */
sahilmgandhi 18:6a4db94011d3 945 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 946 *dmy_cfcc |= 0x04;
sahilmgandhi 18:6a4db94011d3 947 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 948 *dmy_cfcc |= 0x02;
sahilmgandhi 18:6a4db94011d3 949 /* TMIEp interrupt is disable */
sahilmgandhi 18:6a4db94011d3 950 RSCAN0TMIEC0 = 0x00000000;
sahilmgandhi 18:6a4db94011d3 951 RSCAN0TMIEC1 = 0x00000000;
sahilmgandhi 18:6a4db94011d3 952 RSCAN0TMIEC2 = 0x00000000;
sahilmgandhi 18:6a4db94011d3 953 }
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 static void can_reconfigure_channel(void) {
sahilmgandhi 18:6a4db94011d3 956 __IO uint32_t *dmy_cfcc;
sahilmgandhi 18:6a4db94011d3 957 int ch_cnt;
sahilmgandhi 18:6a4db94011d3 958
sahilmgandhi 18:6a4db94011d3 959 for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
sahilmgandhi 18:6a4db94011d3 960 if (can_initialized[ch_cnt] == 1) {
sahilmgandhi 18:6a4db94011d3 961 /* set Global Operation mode and Channel Communication mode */
sahilmgandhi 18:6a4db94011d3 962 can_set_global_mode(GL_OPE);
sahilmgandhi 18:6a4db94011d3 963 can_set_channel_mode(ch_cnt, CH_COMM);
sahilmgandhi 18:6a4db94011d3 964 /* Use send/receive FIFO buffer */
sahilmgandhi 18:6a4db94011d3 965 dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
sahilmgandhi 18:6a4db94011d3 966 *dmy_cfcc |= 0x01;
sahilmgandhi 18:6a4db94011d3 967 dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
sahilmgandhi 18:6a4db94011d3 968 *dmy_cfcc |= 0x01;
sahilmgandhi 18:6a4db94011d3 969 }
sahilmgandhi 18:6a4db94011d3 970 }
sahilmgandhi 18:6a4db94011d3 971 }
sahilmgandhi 18:6a4db94011d3 972
sahilmgandhi 18:6a4db94011d3 973 static void can_set_frequency(can_t *obj, int f) {
sahilmgandhi 18:6a4db94011d3 974 __IO uint32_t *dmy_cfg;
sahilmgandhi 18:6a4db94011d3 975 int oldfreq = 0;
sahilmgandhi 18:6a4db94011d3 976 int newfreq = 0;
sahilmgandhi 18:6a4db94011d3 977 uint32_t clkc_val;
sahilmgandhi 18:6a4db94011d3 978 uint8_t tmp_tq;
sahilmgandhi 18:6a4db94011d3 979 uint8_t tq = 0;
sahilmgandhi 18:6a4db94011d3 980 uint8_t tmp_brp;
sahilmgandhi 18:6a4db94011d3 981 uint8_t brp = 0;
sahilmgandhi 18:6a4db94011d3 982 uint8_t tseg1 = 0;
sahilmgandhi 18:6a4db94011d3 983 uint8_t tseg2 = 0;
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 /* set clkc */
sahilmgandhi 18:6a4db94011d3 986 if (RZ_A1_IsClockMode0() == false) {
sahilmgandhi 18:6a4db94011d3 987 clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
sahilmgandhi 18:6a4db94011d3 988 } else {
sahilmgandhi 18:6a4db94011d3 989 clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
sahilmgandhi 18:6a4db94011d3 990 }
sahilmgandhi 18:6a4db94011d3 991 /* calculate BRP bit and Choose max value of calculated frequency */
sahilmgandhi 18:6a4db94011d3 992 for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
sahilmgandhi 18:6a4db94011d3 993 /* f = fCAN / ((BRP+1) * Tq) */
sahilmgandhi 18:6a4db94011d3 994 /* BRP = (fCAN / (f * Tq)) - 1 */
sahilmgandhi 18:6a4db94011d3 995 tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry)
sahilmgandhi 18:6a4db94011d3 996 newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
sahilmgandhi 18:6a4db94011d3 997 if (newfreq >= oldfreq) {
sahilmgandhi 18:6a4db94011d3 998 oldfreq = newfreq;
sahilmgandhi 18:6a4db94011d3 999 tq = tmp_tq;
sahilmgandhi 18:6a4db94011d3 1000 brp = tmp_brp;
sahilmgandhi 18:6a4db94011d3 1001 }
sahilmgandhi 18:6a4db94011d3 1002 }
sahilmgandhi 18:6a4db94011d3 1003 /* calculate TSEG1 bit and TSEG2 bit */
sahilmgandhi 18:6a4db94011d3 1004 tseg1 = (tq - 1) * 0.666666667;
sahilmgandhi 18:6a4db94011d3 1005 tseg2 = (tq - 1) - tseg1;
sahilmgandhi 18:6a4db94011d3 1006 /* set RSCAN0CmCFG register */
sahilmgandhi 18:6a4db94011d3 1007 dmy_cfg = CFG_MATCH[obj->ch];
sahilmgandhi 18:6a4db94011d3 1008 *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
sahilmgandhi 18:6a4db94011d3 1009 }
sahilmgandhi 18:6a4db94011d3 1010
sahilmgandhi 18:6a4db94011d3 1011 static void can_set_global_mode(int mode) {
sahilmgandhi 18:6a4db94011d3 1012 /* set Global mode */
sahilmgandhi 18:6a4db94011d3 1013 RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode);
sahilmgandhi 18:6a4db94011d3 1014 /* Wait to cahnge into Global XXXX mode */
sahilmgandhi 18:6a4db94011d3 1015 while ((RSCAN0GSTS & 0x07) != mode) {
sahilmgandhi 18:6a4db94011d3 1016 __NOP();
sahilmgandhi 18:6a4db94011d3 1017 }
sahilmgandhi 18:6a4db94011d3 1018 }
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 static void can_set_channel_mode(uint32_t ch, int mode) {
sahilmgandhi 18:6a4db94011d3 1021 __IO uint32_t *dmy_ctr;
sahilmgandhi 18:6a4db94011d3 1022 __IO uint32_t *dmy_sts;
sahilmgandhi 18:6a4db94011d3 1023
sahilmgandhi 18:6a4db94011d3 1024 /* set Channel mode */
sahilmgandhi 18:6a4db94011d3 1025 dmy_ctr = CTR_MATCH[ch];
sahilmgandhi 18:6a4db94011d3 1026 *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode);
sahilmgandhi 18:6a4db94011d3 1027 /* Wait to cahnge into Channel XXXX mode */
sahilmgandhi 18:6a4db94011d3 1028 dmy_sts = STS_MATCH[ch];
sahilmgandhi 18:6a4db94011d3 1029 while ((*dmy_sts & 0x07) != mode) {
sahilmgandhi 18:6a4db94011d3 1030 __NOP();
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032 }
sahilmgandhi 18:6a4db94011d3 1033