Mouse code for the MacroRat
mbed-dev/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file system_MBRZA1H.c |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @brief CMSIS Device System Source File for |
sahilmgandhi | 18:6a4db94011d3 | 4 | * ARM Cortex-A9 Device Series |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.00 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 09 January 2015 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | ******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 11 | /* Copyright (c) 2011 - 2015 ARM LIMITED |
sahilmgandhi | 18:6a4db94011d3 | 12 | |
sahilmgandhi | 18:6a4db94011d3 | 13 | All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 14 | Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 15 | modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 16 | - Redistributions of source code must retain the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 17 | notice, this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 18 | - Redistributions in binary form must reproduce the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 19 | notice, this list of conditions and the following disclaimer in the |
sahilmgandhi | 18:6a4db94011d3 | 20 | documentation and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | - Neither the name of ARM nor the names of its contributors may be used |
sahilmgandhi | 18:6a4db94011d3 | 22 | to endorse or promote products derived from this software without |
sahilmgandhi | 18:6a4db94011d3 | 23 | specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 26 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 27 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
sahilmgandhi | 18:6a4db94011d3 | 28 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
sahilmgandhi | 18:6a4db94011d3 | 29 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
sahilmgandhi | 18:6a4db94011d3 | 30 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
sahilmgandhi | 18:6a4db94011d3 | 31 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
sahilmgandhi | 18:6a4db94011d3 | 32 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
sahilmgandhi | 18:6a4db94011d3 | 33 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
sahilmgandhi | 18:6a4db94011d3 | 34 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 35 | POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 36 | ---------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | #include <stdint.h> |
sahilmgandhi | 18:6a4db94011d3 | 40 | #include "MBRZA1H.h" |
sahilmgandhi | 18:6a4db94011d3 | 41 | #include "RZ_A1_Init.h" |
sahilmgandhi | 18:6a4db94011d3 | 42 | |
sahilmgandhi | 18:6a4db94011d3 | 43 | |
sahilmgandhi | 18:6a4db94011d3 | 44 | #if defined(__ARMCC_VERSION) |
sahilmgandhi | 18:6a4db94011d3 | 45 | extern void $Super$$main(void); |
sahilmgandhi | 18:6a4db94011d3 | 46 | __asm void FPUEnable(void); |
sahilmgandhi | 18:6a4db94011d3 | 47 | #else |
sahilmgandhi | 18:6a4db94011d3 | 48 | void FPUEnable(void); |
sahilmgandhi | 18:6a4db94011d3 | 49 | |
sahilmgandhi | 18:6a4db94011d3 | 50 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | #define FRQCR_IFC_MSK (0x0030) |
sahilmgandhi | 18:6a4db94011d3 | 53 | #define FRQCR_IFC_SHFT (8) |
sahilmgandhi | 18:6a4db94011d3 | 54 | #define FRQCR_IFC_1P1 (0) /* x1/1 */ |
sahilmgandhi | 18:6a4db94011d3 | 55 | #define FRQCR_IFC_2P3 (1) /* x2/3 */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | #define FRQCR_IFC_1P3 (3) /* x1/3 */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | |
sahilmgandhi | 18:6a4db94011d3 | 58 | uint32_t IRQNestLevel; |
sahilmgandhi | 18:6a4db94011d3 | 59 | unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 |
sahilmgandhi | 18:6a4db94011d3 | 60 | uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | |
sahilmgandhi | 18:6a4db94011d3 | 63 | /** |
sahilmgandhi | 18:6a4db94011d3 | 64 | * Initialize the cache. |
sahilmgandhi | 18:6a4db94011d3 | 65 | * |
sahilmgandhi | 18:6a4db94011d3 | 66 | * @param none |
sahilmgandhi | 18:6a4db94011d3 | 67 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 68 | * |
sahilmgandhi | 18:6a4db94011d3 | 69 | * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. |
sahilmgandhi | 18:6a4db94011d3 | 70 | */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | #if defined(__ARMCC_VERSION) |
sahilmgandhi | 18:6a4db94011d3 | 72 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 73 | #pragma arm |
sahilmgandhi | 18:6a4db94011d3 | 74 | |
sahilmgandhi | 18:6a4db94011d3 | 75 | void InitMemorySubsystem(void) { |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before |
sahilmgandhi | 18:6a4db94011d3 | 78 | * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. |
sahilmgandhi | 18:6a4db94011d3 | 79 | * You are not required to invalidate the main TLB, even though it is recommended for safety |
sahilmgandhi | 18:6a4db94011d3 | 80 | * reasons. This ensures compatibility with future revisions of the processor. */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | unsigned int l2_id; |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | /* Invalidate undefined data */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | __ca9u_inv_tlb_all(); |
sahilmgandhi | 18:6a4db94011d3 | 86 | __v7_inv_icache_all(); |
sahilmgandhi | 18:6a4db94011d3 | 87 | __v7_inv_dcache_all(); |
sahilmgandhi | 18:6a4db94011d3 | 88 | __v7_inv_btac(); |
sahilmgandhi | 18:6a4db94011d3 | 89 | |
sahilmgandhi | 18:6a4db94011d3 | 90 | /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and |
sahilmgandhi | 18:6a4db94011d3 | 91 | * invalidate in order to flush the valid data to the next level cache. |
sahilmgandhi | 18:6a4db94011d3 | 92 | */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | __enable_mmu(); |
sahilmgandhi | 18:6a4db94011d3 | 94 | |
sahilmgandhi | 18:6a4db94011d3 | 95 | /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | __enable_caches(); |
sahilmgandhi | 18:6a4db94011d3 | 97 | __enable_btac(); |
sahilmgandhi | 18:6a4db94011d3 | 98 | |
sahilmgandhi | 18:6a4db94011d3 | 99 | /* If present, you may also need to Invalidate and Enable L2 cache here */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | l2_id = PL310_GetID(); |
sahilmgandhi | 18:6a4db94011d3 | 101 | if (l2_id) |
sahilmgandhi | 18:6a4db94011d3 | 102 | { |
sahilmgandhi | 18:6a4db94011d3 | 103 | PL310_InvAllByWay(); |
sahilmgandhi | 18:6a4db94011d3 | 104 | PL310_Enable(); |
sahilmgandhi | 18:6a4db94011d3 | 105 | } |
sahilmgandhi | 18:6a4db94011d3 | 106 | } |
sahilmgandhi | 18:6a4db94011d3 | 107 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 108 | |
sahilmgandhi | 18:6a4db94011d3 | 109 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 110 | |
sahilmgandhi | 18:6a4db94011d3 | 111 | void InitMemorySubsystem(void) { |
sahilmgandhi | 18:6a4db94011d3 | 112 | |
sahilmgandhi | 18:6a4db94011d3 | 113 | /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before |
sahilmgandhi | 18:6a4db94011d3 | 114 | * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. |
sahilmgandhi | 18:6a4db94011d3 | 115 | * You are not required to invalidate the main TLB, even though it is recommended for safety |
sahilmgandhi | 18:6a4db94011d3 | 116 | * reasons. This ensures compatibility with future revisions of the processor. */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | |
sahilmgandhi | 18:6a4db94011d3 | 118 | unsigned int l2_id; |
sahilmgandhi | 18:6a4db94011d3 | 119 | |
sahilmgandhi | 18:6a4db94011d3 | 120 | /* Invalidate undefined data */ |
sahilmgandhi | 18:6a4db94011d3 | 121 | __ca9u_inv_tlb_all(); |
sahilmgandhi | 18:6a4db94011d3 | 122 | __v7_inv_icache_all(); |
sahilmgandhi | 18:6a4db94011d3 | 123 | __v7_inv_dcache_all(); |
sahilmgandhi | 18:6a4db94011d3 | 124 | __v7_inv_btac(); |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and |
sahilmgandhi | 18:6a4db94011d3 | 127 | * invalidate in order to flush the valid data to the next level cache. |
sahilmgandhi | 18:6a4db94011d3 | 128 | */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | __enable_mmu(); |
sahilmgandhi | 18:6a4db94011d3 | 130 | |
sahilmgandhi | 18:6a4db94011d3 | 131 | /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | __enable_caches(); |
sahilmgandhi | 18:6a4db94011d3 | 133 | __enable_btac(); |
sahilmgandhi | 18:6a4db94011d3 | 134 | |
sahilmgandhi | 18:6a4db94011d3 | 135 | /* If present, you may also need to Invalidate and Enable L2 cache here */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | l2_id = PL310_GetID(); |
sahilmgandhi | 18:6a4db94011d3 | 137 | if (l2_id) |
sahilmgandhi | 18:6a4db94011d3 | 138 | { |
sahilmgandhi | 18:6a4db94011d3 | 139 | PL310_InvAllByWay(); |
sahilmgandhi | 18:6a4db94011d3 | 140 | PL310_Enable(); |
sahilmgandhi | 18:6a4db94011d3 | 141 | } |
sahilmgandhi | 18:6a4db94011d3 | 142 | } |
sahilmgandhi | 18:6a4db94011d3 | 143 | #elif defined ( __ICCARM__ ) |
sahilmgandhi | 18:6a4db94011d3 | 144 | |
sahilmgandhi | 18:6a4db94011d3 | 145 | void InitMemorySubsystem(void) { |
sahilmgandhi | 18:6a4db94011d3 | 146 | |
sahilmgandhi | 18:6a4db94011d3 | 147 | /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before |
sahilmgandhi | 18:6a4db94011d3 | 148 | * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. |
sahilmgandhi | 18:6a4db94011d3 | 149 | * You are not required to invalidate the main TLB, even though it is recommended for safety |
sahilmgandhi | 18:6a4db94011d3 | 150 | * reasons. This ensures compatibility with future revisions of the processor. */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | |
sahilmgandhi | 18:6a4db94011d3 | 152 | unsigned int l2_id; |
sahilmgandhi | 18:6a4db94011d3 | 153 | |
sahilmgandhi | 18:6a4db94011d3 | 154 | /* Invalidate undefined data */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | __ca9u_inv_tlb_all(); |
sahilmgandhi | 18:6a4db94011d3 | 156 | __v7_inv_icache_all(); |
sahilmgandhi | 18:6a4db94011d3 | 157 | __v7_inv_dcache_all(); |
sahilmgandhi | 18:6a4db94011d3 | 158 | __v7_inv_btac(); |
sahilmgandhi | 18:6a4db94011d3 | 159 | |
sahilmgandhi | 18:6a4db94011d3 | 160 | /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and |
sahilmgandhi | 18:6a4db94011d3 | 161 | * invalidate in order to flush the valid data to the next level cache. |
sahilmgandhi | 18:6a4db94011d3 | 162 | */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | __enable_mmu(); |
sahilmgandhi | 18:6a4db94011d3 | 164 | |
sahilmgandhi | 18:6a4db94011d3 | 165 | /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | __enable_caches(); |
sahilmgandhi | 18:6a4db94011d3 | 167 | __enable_btac(); |
sahilmgandhi | 18:6a4db94011d3 | 168 | |
sahilmgandhi | 18:6a4db94011d3 | 169 | /* If present, you may also need to Invalidate and Enable L2 cache here */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | l2_id = PL310_GetID(); |
sahilmgandhi | 18:6a4db94011d3 | 171 | if (l2_id) |
sahilmgandhi | 18:6a4db94011d3 | 172 | { |
sahilmgandhi | 18:6a4db94011d3 | 173 | PL310_InvAllByWay(); |
sahilmgandhi | 18:6a4db94011d3 | 174 | PL310_Enable(); |
sahilmgandhi | 18:6a4db94011d3 | 175 | } |
sahilmgandhi | 18:6a4db94011d3 | 176 | } |
sahilmgandhi | 18:6a4db94011d3 | 177 | #else |
sahilmgandhi | 18:6a4db94011d3 | 178 | |
sahilmgandhi | 18:6a4db94011d3 | 179 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; |
sahilmgandhi | 18:6a4db94011d3 | 183 | |
sahilmgandhi | 18:6a4db94011d3 | 184 | uint32_t IRQCount = sizeof IRQTable / 4; |
sahilmgandhi | 18:6a4db94011d3 | 185 | |
sahilmgandhi | 18:6a4db94011d3 | 186 | uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) |
sahilmgandhi | 18:6a4db94011d3 | 187 | { |
sahilmgandhi | 18:6a4db94011d3 | 188 | if (irq < IRQCount) { |
sahilmgandhi | 18:6a4db94011d3 | 189 | IRQTable[irq] = handler; |
sahilmgandhi | 18:6a4db94011d3 | 190 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 191 | } |
sahilmgandhi | 18:6a4db94011d3 | 192 | else { |
sahilmgandhi | 18:6a4db94011d3 | 193 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 194 | } |
sahilmgandhi | 18:6a4db94011d3 | 195 | } |
sahilmgandhi | 18:6a4db94011d3 | 196 | |
sahilmgandhi | 18:6a4db94011d3 | 197 | uint32_t InterruptHandlerUnregister (IRQn_Type irq) |
sahilmgandhi | 18:6a4db94011d3 | 198 | { |
sahilmgandhi | 18:6a4db94011d3 | 199 | if (irq < IRQCount) { |
sahilmgandhi | 18:6a4db94011d3 | 200 | IRQTable[irq] = 0; |
sahilmgandhi | 18:6a4db94011d3 | 201 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 202 | } |
sahilmgandhi | 18:6a4db94011d3 | 203 | else { |
sahilmgandhi | 18:6a4db94011d3 | 204 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 205 | } |
sahilmgandhi | 18:6a4db94011d3 | 206 | } |
sahilmgandhi | 18:6a4db94011d3 | 207 | |
sahilmgandhi | 18:6a4db94011d3 | 208 | /** |
sahilmgandhi | 18:6a4db94011d3 | 209 | * Update SystemCoreClock variable |
sahilmgandhi | 18:6a4db94011d3 | 210 | * |
sahilmgandhi | 18:6a4db94011d3 | 211 | * @param none |
sahilmgandhi | 18:6a4db94011d3 | 212 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 213 | * |
sahilmgandhi | 18:6a4db94011d3 | 214 | * @brief Updates the SystemCoreClock with current core Clock. |
sahilmgandhi | 18:6a4db94011d3 | 215 | */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | void SystemCoreClockUpdate (void) |
sahilmgandhi | 18:6a4db94011d3 | 217 | { |
sahilmgandhi | 18:6a4db94011d3 | 218 | uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | switch (frqcr_ifc) { |
sahilmgandhi | 18:6a4db94011d3 | 221 | case FRQCR_IFC_1P1: |
sahilmgandhi | 18:6a4db94011d3 | 222 | SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; |
sahilmgandhi | 18:6a4db94011d3 | 223 | break; |
sahilmgandhi | 18:6a4db94011d3 | 224 | case FRQCR_IFC_2P3: |
sahilmgandhi | 18:6a4db94011d3 | 225 | SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; |
sahilmgandhi | 18:6a4db94011d3 | 226 | break; |
sahilmgandhi | 18:6a4db94011d3 | 227 | case FRQCR_IFC_1P3: |
sahilmgandhi | 18:6a4db94011d3 | 228 | SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; |
sahilmgandhi | 18:6a4db94011d3 | 229 | break; |
sahilmgandhi | 18:6a4db94011d3 | 230 | default: |
sahilmgandhi | 18:6a4db94011d3 | 231 | /* do nothing */ |
sahilmgandhi | 18:6a4db94011d3 | 232 | break; |
sahilmgandhi | 18:6a4db94011d3 | 233 | } |
sahilmgandhi | 18:6a4db94011d3 | 234 | } |
sahilmgandhi | 18:6a4db94011d3 | 235 | |
sahilmgandhi | 18:6a4db94011d3 | 236 | |
sahilmgandhi | 18:6a4db94011d3 | 237 | /** |
sahilmgandhi | 18:6a4db94011d3 | 238 | * Initialize the system |
sahilmgandhi | 18:6a4db94011d3 | 239 | * |
sahilmgandhi | 18:6a4db94011d3 | 240 | * @param none |
sahilmgandhi | 18:6a4db94011d3 | 241 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 242 | * |
sahilmgandhi | 18:6a4db94011d3 | 243 | * @brief Setup the microcontroller system. |
sahilmgandhi | 18:6a4db94011d3 | 244 | * Initialize the System. |
sahilmgandhi | 18:6a4db94011d3 | 245 | */ |
sahilmgandhi | 18:6a4db94011d3 | 246 | void SystemInit (void) |
sahilmgandhi | 18:6a4db94011d3 | 247 | { |
sahilmgandhi | 18:6a4db94011d3 | 248 | IRQNestLevel = 0; |
sahilmgandhi | 18:6a4db94011d3 | 249 | /* do not use global variables because this function is called before |
sahilmgandhi | 18:6a4db94011d3 | 250 | reaching pre-main. RW section maybe overwritten afterwards. */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | RZ_A1_InitClock(); |
sahilmgandhi | 18:6a4db94011d3 | 252 | RZ_A1_InitBus(); |
sahilmgandhi | 18:6a4db94011d3 | 253 | |
sahilmgandhi | 18:6a4db94011d3 | 254 | //Configure GIC ICDICFR GIC_SetICDICFR() |
sahilmgandhi | 18:6a4db94011d3 | 255 | GIC_Enable(); |
sahilmgandhi | 18:6a4db94011d3 | 256 | __enable_irq(); |
sahilmgandhi | 18:6a4db94011d3 | 257 | |
sahilmgandhi | 18:6a4db94011d3 | 258 | } |
sahilmgandhi | 18:6a4db94011d3 | 259 | |
sahilmgandhi | 18:6a4db94011d3 | 260 | |
sahilmgandhi | 18:6a4db94011d3 | 261 | //Fault Status Register (IFSR/DFSR) definitions |
sahilmgandhi | 18:6a4db94011d3 | 262 | #define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup |
sahilmgandhi | 18:6a4db94011d3 | 263 | #define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external |
sahilmgandhi | 18:6a4db94011d3 | 264 | #define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 265 | #define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 266 | #define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 267 | #define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 268 | #define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 269 | #define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 270 | #define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 271 | #define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 272 | #define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 273 | #define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 274 | #define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 275 | #define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal |
sahilmgandhi | 18:6a4db94011d3 | 276 | #define FSR_DEBUG_EVENT 0x02 //internal |
sahilmgandhi | 18:6a4db94011d3 | 277 | #define FSR_SYNC_EXT_ABORT 0x08 //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 278 | #define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 279 | #define FSR_LOCKDOWN 0x14 //internal |
sahilmgandhi | 18:6a4db94011d3 | 280 | #define FSR_COPROCESSOR_ABORT 0x1a //internal |
sahilmgandhi | 18:6a4db94011d3 | 281 | #define FSR_SYNC_PARITY_ERROR 0x19 //sync/external |
sahilmgandhi | 18:6a4db94011d3 | 282 | #define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external |
sahilmgandhi | 18:6a4db94011d3 | 283 | #define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external |
sahilmgandhi | 18:6a4db94011d3 | 284 | |
sahilmgandhi | 18:6a4db94011d3 | 285 | void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { |
sahilmgandhi | 18:6a4db94011d3 | 286 | uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status |
sahilmgandhi | 18:6a4db94011d3 | 287 | |
sahilmgandhi | 18:6a4db94011d3 | 288 | switch(FS) { |
sahilmgandhi | 18:6a4db94011d3 | 289 | //Synchronous parity errors - retry |
sahilmgandhi | 18:6a4db94011d3 | 290 | case FSR_SYNC_PARITY_ERROR: |
sahilmgandhi | 18:6a4db94011d3 | 291 | case FSR_SYNC_PARITY_TTB_WALK_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 292 | case FSR_SYNC_PARITY_TTB_WALK_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 293 | return; |
sahilmgandhi | 18:6a4db94011d3 | 294 | |
sahilmgandhi | 18:6a4db94011d3 | 295 | //Your code here. Value in DFAR is invalid for some fault statuses. |
sahilmgandhi | 18:6a4db94011d3 | 296 | case FSR_ALIGNMENT_FAULT: |
sahilmgandhi | 18:6a4db94011d3 | 297 | case FSR_INSTRUCTION_CACHE_MAINTENANCE: |
sahilmgandhi | 18:6a4db94011d3 | 298 | case FSR_SYNC_EXT_TTB_WALK_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 299 | case FSR_SYNC_EXT_TTB_WALK_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 300 | case FSR_TRANSLATION_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 301 | case FSR_TRANSLATION_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 302 | case FSR_ACCESS_FLAG_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 303 | case FSR_ACCESS_FLAG_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 304 | case FSR_DOMAIN_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 305 | case FSR_DOMAIN_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 306 | case FSR_PERMISION_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 307 | case FSR_PERMISION_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 308 | case FSR_DEBUG_EVENT: |
sahilmgandhi | 18:6a4db94011d3 | 309 | case FSR_SYNC_EXT_ABORT: |
sahilmgandhi | 18:6a4db94011d3 | 310 | case FSR_TLB_CONFLICT_ABORT: |
sahilmgandhi | 18:6a4db94011d3 | 311 | case FSR_LOCKDOWN: |
sahilmgandhi | 18:6a4db94011d3 | 312 | case FSR_COPROCESSOR_ABORT: |
sahilmgandhi | 18:6a4db94011d3 | 313 | case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid |
sahilmgandhi | 18:6a4db94011d3 | 314 | case FSR_ASYNC_PARITY_ERROR: //DFAR invalid |
sahilmgandhi | 18:6a4db94011d3 | 315 | default: |
sahilmgandhi | 18:6a4db94011d3 | 316 | while(1); |
sahilmgandhi | 18:6a4db94011d3 | 317 | } |
sahilmgandhi | 18:6a4db94011d3 | 318 | } |
sahilmgandhi | 18:6a4db94011d3 | 319 | |
sahilmgandhi | 18:6a4db94011d3 | 320 | void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { |
sahilmgandhi | 18:6a4db94011d3 | 321 | uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status |
sahilmgandhi | 18:6a4db94011d3 | 322 | |
sahilmgandhi | 18:6a4db94011d3 | 323 | switch(FS) { |
sahilmgandhi | 18:6a4db94011d3 | 324 | //Synchronous parity errors - retry |
sahilmgandhi | 18:6a4db94011d3 | 325 | case FSR_SYNC_PARITY_ERROR: |
sahilmgandhi | 18:6a4db94011d3 | 326 | case FSR_SYNC_PARITY_TTB_WALK_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 327 | case FSR_SYNC_PARITY_TTB_WALK_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 328 | return; |
sahilmgandhi | 18:6a4db94011d3 | 329 | |
sahilmgandhi | 18:6a4db94011d3 | 330 | //Your code here. Value in IFAR is invalid for some fault statuses. |
sahilmgandhi | 18:6a4db94011d3 | 331 | case FSR_SYNC_EXT_TTB_WALK_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 332 | case FSR_SYNC_EXT_TTB_WALK_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 333 | case FSR_TRANSLATION_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 334 | case FSR_TRANSLATION_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 335 | case FSR_ACCESS_FLAG_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 336 | case FSR_ACCESS_FLAG_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 337 | case FSR_DOMAIN_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 338 | case FSR_DOMAIN_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 339 | case FSR_PERMISION_FAULT_FIRST: |
sahilmgandhi | 18:6a4db94011d3 | 340 | case FSR_PERMISION_FAULT_SECOND: |
sahilmgandhi | 18:6a4db94011d3 | 341 | case FSR_DEBUG_EVENT: //IFAR invalid |
sahilmgandhi | 18:6a4db94011d3 | 342 | case FSR_SYNC_EXT_ABORT: |
sahilmgandhi | 18:6a4db94011d3 | 343 | case FSR_TLB_CONFLICT_ABORT: |
sahilmgandhi | 18:6a4db94011d3 | 344 | case FSR_LOCKDOWN: |
sahilmgandhi | 18:6a4db94011d3 | 345 | case FSR_COPROCESSOR_ABORT: |
sahilmgandhi | 18:6a4db94011d3 | 346 | default: |
sahilmgandhi | 18:6a4db94011d3 | 347 | while(1); |
sahilmgandhi | 18:6a4db94011d3 | 348 | } |
sahilmgandhi | 18:6a4db94011d3 | 349 | } |
sahilmgandhi | 18:6a4db94011d3 | 350 | |
sahilmgandhi | 18:6a4db94011d3 | 351 | //returns amount to decrement lr by |
sahilmgandhi | 18:6a4db94011d3 | 352 | //this will be 0 when we have emulated the instruction and want to execute the next instruction |
sahilmgandhi | 18:6a4db94011d3 | 353 | //this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) |
sahilmgandhi | 18:6a4db94011d3 | 354 | //this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) |
sahilmgandhi | 18:6a4db94011d3 | 355 | uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { |
sahilmgandhi | 18:6a4db94011d3 | 356 | const unsigned int THUMB = 2; |
sahilmgandhi | 18:6a4db94011d3 | 357 | const unsigned int ARM = 4; |
sahilmgandhi | 18:6a4db94011d3 | 358 | //Lazy VFP/NEON initialisation and switching |
sahilmgandhi | 18:6a4db94011d3 | 359 | |
sahilmgandhi | 18:6a4db94011d3 | 360 | // (ARM ARM section A7.5) VFP data processing instruction? |
sahilmgandhi | 18:6a4db94011d3 | 361 | // (ARM ARM section A7.6) VFP/NEON register load/store instruction? |
sahilmgandhi | 18:6a4db94011d3 | 362 | // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? |
sahilmgandhi | 18:6a4db94011d3 | 363 | // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? |
sahilmgandhi | 18:6a4db94011d3 | 364 | if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || |
sahilmgandhi | 18:6a4db94011d3 | 365 | (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { |
sahilmgandhi | 18:6a4db94011d3 | 366 | if (((opcode & 0x00000E00) >> 9) == 5) { |
sahilmgandhi | 18:6a4db94011d3 | 367 | FPUEnable(); |
sahilmgandhi | 18:6a4db94011d3 | 368 | return state; |
sahilmgandhi | 18:6a4db94011d3 | 369 | } |
sahilmgandhi | 18:6a4db94011d3 | 370 | } |
sahilmgandhi | 18:6a4db94011d3 | 371 | |
sahilmgandhi | 18:6a4db94011d3 | 372 | // (ARM ARM section A7.4) NEON data processing instruction? |
sahilmgandhi | 18:6a4db94011d3 | 373 | if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || |
sahilmgandhi | 18:6a4db94011d3 | 374 | (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || |
sahilmgandhi | 18:6a4db94011d3 | 375 | // (ARM ARM section A7.7) NEON load/store instruction? |
sahilmgandhi | 18:6a4db94011d3 | 376 | (state == ARM && ((opcode >> 24) == 0xF4)) || |
sahilmgandhi | 18:6a4db94011d3 | 377 | (state == THUMB && ((opcode >> 24) == 0xF9))) { |
sahilmgandhi | 18:6a4db94011d3 | 378 | FPUEnable(); |
sahilmgandhi | 18:6a4db94011d3 | 379 | return state; |
sahilmgandhi | 18:6a4db94011d3 | 380 | } |
sahilmgandhi | 18:6a4db94011d3 | 381 | |
sahilmgandhi | 18:6a4db94011d3 | 382 | //Add code here for other Undef cases |
sahilmgandhi | 18:6a4db94011d3 | 383 | while(1); |
sahilmgandhi | 18:6a4db94011d3 | 384 | } |
sahilmgandhi | 18:6a4db94011d3 | 385 | |
sahilmgandhi | 18:6a4db94011d3 | 386 | #if defined(__ARMCC_VERSION) |
sahilmgandhi | 18:6a4db94011d3 | 387 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 388 | #pragma arm |
sahilmgandhi | 18:6a4db94011d3 | 389 | //Critical section, called from undef handler, so systick is disabled |
sahilmgandhi | 18:6a4db94011d3 | 390 | __asm void FPUEnable(void) { |
sahilmgandhi | 18:6a4db94011d3 | 391 | ARM |
sahilmgandhi | 18:6a4db94011d3 | 392 | |
sahilmgandhi | 18:6a4db94011d3 | 393 | //Permit access to VFP/NEON, registers by modifying CPACR |
sahilmgandhi | 18:6a4db94011d3 | 394 | MRC p15,0,R1,c1,c0,2 |
sahilmgandhi | 18:6a4db94011d3 | 395 | ORR R1,R1,#0x00F00000 |
sahilmgandhi | 18:6a4db94011d3 | 396 | MCR p15,0,R1,c1,c0,2 |
sahilmgandhi | 18:6a4db94011d3 | 397 | |
sahilmgandhi | 18:6a4db94011d3 | 398 | //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted |
sahilmgandhi | 18:6a4db94011d3 | 399 | ISB |
sahilmgandhi | 18:6a4db94011d3 | 400 | |
sahilmgandhi | 18:6a4db94011d3 | 401 | //Enable VFP/NEON |
sahilmgandhi | 18:6a4db94011d3 | 402 | VMRS R1,FPEXC |
sahilmgandhi | 18:6a4db94011d3 | 403 | ORR R1,R1,#0x40000000 |
sahilmgandhi | 18:6a4db94011d3 | 404 | VMSR FPEXC,R1 |
sahilmgandhi | 18:6a4db94011d3 | 405 | |
sahilmgandhi | 18:6a4db94011d3 | 406 | //Initialise VFP/NEON registers to 0 |
sahilmgandhi | 18:6a4db94011d3 | 407 | MOV R2,#0 |
sahilmgandhi | 18:6a4db94011d3 | 408 | //Initialise D16 registers to 0 |
sahilmgandhi | 18:6a4db94011d3 | 409 | VMOV D0, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 410 | VMOV D1, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 411 | VMOV D2, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 412 | VMOV D3, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 413 | VMOV D4, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 414 | VMOV D5, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 415 | VMOV D6, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 416 | VMOV D7, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 417 | VMOV D8, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 418 | VMOV D9, R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 419 | VMOV D10,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 420 | VMOV D11,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 421 | VMOV D12,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 422 | VMOV D13,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 423 | VMOV D14,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 424 | VMOV D15,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 425 | //Initialise D32 registers to 0 |
sahilmgandhi | 18:6a4db94011d3 | 426 | VMOV D16,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 427 | VMOV D17,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 428 | VMOV D18,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 429 | VMOV D19,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 430 | VMOV D20,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 431 | VMOV D21,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 432 | VMOV D22,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 433 | VMOV D23,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 434 | VMOV D24,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 435 | VMOV D25,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 436 | VMOV D26,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 437 | VMOV D27,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 438 | VMOV D28,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 439 | VMOV D29,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 440 | VMOV D30,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 441 | VMOV D31,R2,R2 |
sahilmgandhi | 18:6a4db94011d3 | 442 | //Initialise FPSCR to a known state |
sahilmgandhi | 18:6a4db94011d3 | 443 | VMRS R2,FPSCR |
sahilmgandhi | 18:6a4db94011d3 | 444 | LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. |
sahilmgandhi | 18:6a4db94011d3 | 445 | AND R2,R2,R3 |
sahilmgandhi | 18:6a4db94011d3 | 446 | VMSR FPSCR,R2 |
sahilmgandhi | 18:6a4db94011d3 | 447 | |
sahilmgandhi | 18:6a4db94011d3 | 448 | BX LR |
sahilmgandhi | 18:6a4db94011d3 | 449 | } |
sahilmgandhi | 18:6a4db94011d3 | 450 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 451 | |
sahilmgandhi | 18:6a4db94011d3 | 452 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 453 | void FPUEnable(void) { |
sahilmgandhi | 18:6a4db94011d3 | 454 | __asm__ ( |
sahilmgandhi | 18:6a4db94011d3 | 455 | ".ARM;" |
sahilmgandhi | 18:6a4db94011d3 | 456 | |
sahilmgandhi | 18:6a4db94011d3 | 457 | //Permit access to VFP/NEON, registers by modifying CPACR |
sahilmgandhi | 18:6a4db94011d3 | 458 | "MRC p15,0,R1,c1,c0,2;" |
sahilmgandhi | 18:6a4db94011d3 | 459 | "ORR R1,R1,#0x00F00000;" |
sahilmgandhi | 18:6a4db94011d3 | 460 | "MCR p15,0,R1,c1,c0,2;" |
sahilmgandhi | 18:6a4db94011d3 | 461 | |
sahilmgandhi | 18:6a4db94011d3 | 462 | //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted |
sahilmgandhi | 18:6a4db94011d3 | 463 | "ISB;" |
sahilmgandhi | 18:6a4db94011d3 | 464 | |
sahilmgandhi | 18:6a4db94011d3 | 465 | //Enable VFP/NEON |
sahilmgandhi | 18:6a4db94011d3 | 466 | "VMRS R1,FPEXC;" |
sahilmgandhi | 18:6a4db94011d3 | 467 | "ORR R1,R1,#0x40000000;" |
sahilmgandhi | 18:6a4db94011d3 | 468 | "VMSR FPEXC,R1;" |
sahilmgandhi | 18:6a4db94011d3 | 469 | |
sahilmgandhi | 18:6a4db94011d3 | 470 | //Initialise VFP/NEON registers to 0 |
sahilmgandhi | 18:6a4db94011d3 | 471 | "MOV R2,#0;" |
sahilmgandhi | 18:6a4db94011d3 | 472 | //Initialise D16 registers to 0 |
sahilmgandhi | 18:6a4db94011d3 | 473 | "VMOV D0, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 474 | "VMOV D1, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 475 | "VMOV D2, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 476 | "VMOV D3, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 477 | "VMOV D4, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 478 | "VMOV D5, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 479 | "VMOV D6, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 480 | "VMOV D7, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 481 | "VMOV D8, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 482 | "VMOV D9, R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 483 | "VMOV D10,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 484 | "VMOV D11,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 485 | "VMOV D12,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 486 | "VMOV D13,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 487 | "VMOV D14,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 488 | "VMOV D15,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 489 | //Initialise D32 registers to 0 |
sahilmgandhi | 18:6a4db94011d3 | 490 | "VMOV D16,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 491 | "VMOV D17,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 492 | "VMOV D18,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 493 | "VMOV D19,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 494 | "VMOV D20,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 495 | "VMOV D21,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 496 | "VMOV D22,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 497 | "VMOV D23,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 498 | "VMOV D24,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 499 | "VMOV D25,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 500 | "VMOV D26,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 501 | "VMOV D27,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 502 | "VMOV D28,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 503 | "VMOV D29,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 504 | "VMOV D30,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 505 | "VMOV D31,R2,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 506 | |
sahilmgandhi | 18:6a4db94011d3 | 507 | //Initialise FPSCR to a known state |
sahilmgandhi | 18:6a4db94011d3 | 508 | "VMRS R2,FPSCR;" |
sahilmgandhi | 18:6a4db94011d3 | 509 | "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. |
sahilmgandhi | 18:6a4db94011d3 | 510 | "AND R2,R2,R3;" |
sahilmgandhi | 18:6a4db94011d3 | 511 | "VMSR FPSCR,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 512 | |
sahilmgandhi | 18:6a4db94011d3 | 513 | //"BX LR;" |
sahilmgandhi | 18:6a4db94011d3 | 514 | : |
sahilmgandhi | 18:6a4db94011d3 | 515 | : |
sahilmgandhi | 18:6a4db94011d3 | 516 | :"r1", "r2", "r3"); |
sahilmgandhi | 18:6a4db94011d3 | 517 | return; |
sahilmgandhi | 18:6a4db94011d3 | 518 | } |
sahilmgandhi | 18:6a4db94011d3 | 519 | #else |
sahilmgandhi | 18:6a4db94011d3 | 520 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 521 |