Mouse code for the MacroRat
mbed-dev/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
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sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file gic.h |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @version |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @date 29 August 2013 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | ******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 10 | /* Copyright (c) 2011 - 2013 ARM LIMITED |
sahilmgandhi | 18:6a4db94011d3 | 11 | |
sahilmgandhi | 18:6a4db94011d3 | 12 | All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 13 | Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 14 | modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 15 | - Redistributions of source code must retain the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 16 | notice, this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | - Redistributions in binary form must reproduce the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 18 | notice, this list of conditions and the following disclaimer in the |
sahilmgandhi | 18:6a4db94011d3 | 19 | documentation and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 20 | - Neither the name of ARM nor the names of its contributors may be used |
sahilmgandhi | 18:6a4db94011d3 | 21 | to endorse or promote products derived from this software without |
sahilmgandhi | 18:6a4db94011d3 | 22 | specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 23 | * |
sahilmgandhi | 18:6a4db94011d3 | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
sahilmgandhi | 18:6a4db94011d3 | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
sahilmgandhi | 18:6a4db94011d3 | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
sahilmgandhi | 18:6a4db94011d3 | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
sahilmgandhi | 18:6a4db94011d3 | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
sahilmgandhi | 18:6a4db94011d3 | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
sahilmgandhi | 18:6a4db94011d3 | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 34 | POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 35 | ---------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | #ifndef GIC_H_ |
sahilmgandhi | 18:6a4db94011d3 | 38 | #define GIC_H_ |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | /* IO definitions (access restrictions to peripheral registers) */ |
sahilmgandhi | 18:6a4db94011d3 | 41 | /** |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 44 | #define __I volatile /*!< Defines 'read only' permissions */ |
sahilmgandhi | 18:6a4db94011d3 | 45 | #else |
sahilmgandhi | 18:6a4db94011d3 | 46 | #define __I volatile const /*!< Defines 'read only' permissions */ |
sahilmgandhi | 18:6a4db94011d3 | 47 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 48 | #define __O volatile /*!< Defines 'write only' permissions */ |
sahilmgandhi | 18:6a4db94011d3 | 49 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) |
sahilmgandhi | 18:6a4db94011d3 | 52 | */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 54 | { |
sahilmgandhi | 18:6a4db94011d3 | 55 | __IO uint32_t ICDDCR; |
sahilmgandhi | 18:6a4db94011d3 | 56 | __I uint32_t ICDICTR; |
sahilmgandhi | 18:6a4db94011d3 | 57 | __I uint32_t ICDIIDR; |
sahilmgandhi | 18:6a4db94011d3 | 58 | uint32_t RESERVED0[29]; |
sahilmgandhi | 18:6a4db94011d3 | 59 | __IO uint32_t ICDISR[32]; |
sahilmgandhi | 18:6a4db94011d3 | 60 | __IO uint32_t ICDISER[32]; |
sahilmgandhi | 18:6a4db94011d3 | 61 | __IO uint32_t ICDICER[32]; |
sahilmgandhi | 18:6a4db94011d3 | 62 | __IO uint32_t ICDISPR[32]; |
sahilmgandhi | 18:6a4db94011d3 | 63 | __IO uint32_t ICDICPR[32]; |
sahilmgandhi | 18:6a4db94011d3 | 64 | __I uint32_t ICDABR[32]; |
sahilmgandhi | 18:6a4db94011d3 | 65 | uint32_t RESERVED1[32]; |
sahilmgandhi | 18:6a4db94011d3 | 66 | __IO uint32_t ICDIPR[256]; |
sahilmgandhi | 18:6a4db94011d3 | 67 | __IO uint32_t ICDIPTR[256]; |
sahilmgandhi | 18:6a4db94011d3 | 68 | __IO uint32_t ICDICFR[64]; |
sahilmgandhi | 18:6a4db94011d3 | 69 | uint32_t RESERVED2[128]; |
sahilmgandhi | 18:6a4db94011d3 | 70 | __IO uint32_t ICDSGIR; |
sahilmgandhi | 18:6a4db94011d3 | 71 | } GICDistributor_Type; |
sahilmgandhi | 18:6a4db94011d3 | 72 | |
sahilmgandhi | 18:6a4db94011d3 | 73 | /** \brief Structure type to access the Controller Interface (GICC) |
sahilmgandhi | 18:6a4db94011d3 | 74 | */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 76 | { |
sahilmgandhi | 18:6a4db94011d3 | 77 | __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register |
sahilmgandhi | 18:6a4db94011d3 | 78 | __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register |
sahilmgandhi | 18:6a4db94011d3 | 79 | __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register |
sahilmgandhi | 18:6a4db94011d3 | 80 | __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register |
sahilmgandhi | 18:6a4db94011d3 | 81 | __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register |
sahilmgandhi | 18:6a4db94011d3 | 82 | __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register |
sahilmgandhi | 18:6a4db94011d3 | 83 | __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register |
sahilmgandhi | 18:6a4db94011d3 | 84 | __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register |
sahilmgandhi | 18:6a4db94011d3 | 85 | |
sahilmgandhi | 18:6a4db94011d3 | 86 | uint32_t RESERVED[55]; |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register |
sahilmgandhi | 18:6a4db94011d3 | 89 | } GICInterface_Type; |
sahilmgandhi | 18:6a4db94011d3 | 90 | |
sahilmgandhi | 18:6a4db94011d3 | 91 | /*@} end of GICD */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | |
sahilmgandhi | 18:6a4db94011d3 | 93 | /* ########################## GIC functions #################################### */ |
sahilmgandhi | 18:6a4db94011d3 | 94 | /** \brief Functions that manage interrupts via the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 95 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 96 | */ |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface |
sahilmgandhi | 18:6a4db94011d3 | 99 | |
sahilmgandhi | 18:6a4db94011d3 | 100 | Enables the forwarding of pending interrupts to the CPU interfaces. |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | void GIC_EnableDistributor(void); |
sahilmgandhi | 18:6a4db94011d3 | 104 | |
sahilmgandhi | 18:6a4db94011d3 | 105 | /** \brief Disable Distributor |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | Disables the forwarding of pending interrupts to the CPU interfaces. |
sahilmgandhi | 18:6a4db94011d3 | 108 | |
sahilmgandhi | 18:6a4db94011d3 | 109 | */ |
sahilmgandhi | 18:6a4db94011d3 | 110 | void GIC_DisableDistributor(void); |
sahilmgandhi | 18:6a4db94011d3 | 111 | |
sahilmgandhi | 18:6a4db94011d3 | 112 | /** \brief Provides information about the configuration of the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 113 | Provides information about the configuration of the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 114 | - whether the GIC implements the Security Extensions |
sahilmgandhi | 18:6a4db94011d3 | 115 | - the maximum number of interrupt IDs that the GIC supports |
sahilmgandhi | 18:6a4db94011d3 | 116 | - the number of CPU interfaces implemented |
sahilmgandhi | 18:6a4db94011d3 | 117 | - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | \return Distributor Information. |
sahilmgandhi | 18:6a4db94011d3 | 120 | */ |
sahilmgandhi | 18:6a4db94011d3 | 121 | uint32_t GIC_DistributorInfo(void); |
sahilmgandhi | 18:6a4db94011d3 | 122 | |
sahilmgandhi | 18:6a4db94011d3 | 123 | /** \brief Distributor Implementer Identification Register. |
sahilmgandhi | 18:6a4db94011d3 | 124 | |
sahilmgandhi | 18:6a4db94011d3 | 125 | Distributor Implementer Identification Register |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | \return Implementer Information. |
sahilmgandhi | 18:6a4db94011d3 | 128 | */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | uint32_t GIC_DistributorImplementer(void); |
sahilmgandhi | 18:6a4db94011d3 | 130 | |
sahilmgandhi | 18:6a4db94011d3 | 131 | /** \brief Set list of processors that the interrupt is sent to if it is asserted. |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 134 | This field stores the list of processors that the interrupt is sent to if it is asserted. |
sahilmgandhi | 18:6a4db94011d3 | 135 | |
sahilmgandhi | 18:6a4db94011d3 | 136 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 137 | \param [in] target CPU target |
sahilmgandhi | 18:6a4db94011d3 | 138 | */ |
sahilmgandhi | 18:6a4db94011d3 | 139 | void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | /** \brief Get list of processors that the interrupt is sent to if it is asserted. |
sahilmgandhi | 18:6a4db94011d3 | 142 | |
sahilmgandhi | 18:6a4db94011d3 | 143 | The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 144 | This field stores the list of processors that the interrupt is sent to if it is asserted. |
sahilmgandhi | 18:6a4db94011d3 | 145 | |
sahilmgandhi | 18:6a4db94011d3 | 146 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 147 | \param [in] target CPU target |
sahilmgandhi | 18:6a4db94011d3 | 148 | */ |
sahilmgandhi | 18:6a4db94011d3 | 149 | uint32_t GIC_GetTarget(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 150 | |
sahilmgandhi | 18:6a4db94011d3 | 151 | /** \brief Enable Interface |
sahilmgandhi | 18:6a4db94011d3 | 152 | |
sahilmgandhi | 18:6a4db94011d3 | 153 | Enables the signalling of interrupts to the target processors. |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | void GIC_EnableInterface(void); |
sahilmgandhi | 18:6a4db94011d3 | 157 | |
sahilmgandhi | 18:6a4db94011d3 | 158 | /** \brief Disable Interface |
sahilmgandhi | 18:6a4db94011d3 | 159 | |
sahilmgandhi | 18:6a4db94011d3 | 160 | Disables the signalling of interrupts to the target processors. |
sahilmgandhi | 18:6a4db94011d3 | 161 | |
sahilmgandhi | 18:6a4db94011d3 | 162 | */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | void GIC_DisableInterface(void); |
sahilmgandhi | 18:6a4db94011d3 | 164 | |
sahilmgandhi | 18:6a4db94011d3 | 165 | /** \brief Acknowledge Interrupt |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | The function acknowledges the highest priority pending interrupt and returns its IRQ number. |
sahilmgandhi | 18:6a4db94011d3 | 168 | |
sahilmgandhi | 18:6a4db94011d3 | 169 | \return Interrupt number |
sahilmgandhi | 18:6a4db94011d3 | 170 | */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | IRQn_Type GIC_AcknowledgePending(void); |
sahilmgandhi | 18:6a4db94011d3 | 172 | |
sahilmgandhi | 18:6a4db94011d3 | 173 | /** \brief End Interrupt |
sahilmgandhi | 18:6a4db94011d3 | 174 | |
sahilmgandhi | 18:6a4db94011d3 | 175 | The function writes the end of interrupt register, indicating that handling of the interrupt is complete. |
sahilmgandhi | 18:6a4db94011d3 | 176 | |
sahilmgandhi | 18:6a4db94011d3 | 177 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 178 | */ |
sahilmgandhi | 18:6a4db94011d3 | 179 | void GIC_EndInterrupt(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | /** \brief Enable Interrupt |
sahilmgandhi | 18:6a4db94011d3 | 183 | |
sahilmgandhi | 18:6a4db94011d3 | 184 | Set-enable bit for each interrupt supported by the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 185 | |
sahilmgandhi | 18:6a4db94011d3 | 186 | \param [in] IRQn External interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 187 | */ |
sahilmgandhi | 18:6a4db94011d3 | 188 | void GIC_EnableIRQ(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 189 | |
sahilmgandhi | 18:6a4db94011d3 | 190 | /** \brief Disable Interrupt |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | Clear-enable bit for each interrupt supported by the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | \param [in] IRQn Number of the external interrupt to disable |
sahilmgandhi | 18:6a4db94011d3 | 195 | */ |
sahilmgandhi | 18:6a4db94011d3 | 196 | void GIC_DisableIRQ(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 197 | |
sahilmgandhi | 18:6a4db94011d3 | 198 | /** \brief Set Pending Interrupt |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | Set-pending bit for each interrupt supported by the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 201 | |
sahilmgandhi | 18:6a4db94011d3 | 202 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 203 | */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | void GIC_SetPendingIRQ(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | /** \brief Clear Pending Interrupt |
sahilmgandhi | 18:6a4db94011d3 | 207 | |
sahilmgandhi | 18:6a4db94011d3 | 208 | Clear-pending bit for each interrupt supported by the GIC |
sahilmgandhi | 18:6a4db94011d3 | 209 | |
sahilmgandhi | 18:6a4db94011d3 | 210 | \param [in] IRQn Number of the interrupt for clear pending |
sahilmgandhi | 18:6a4db94011d3 | 211 | */ |
sahilmgandhi | 18:6a4db94011d3 | 212 | void GIC_ClearPendingIRQ(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 213 | |
sahilmgandhi | 18:6a4db94011d3 | 214 | /** \brief Int_config field for each interrupt supported by the GIC. |
sahilmgandhi | 18:6a4db94011d3 | 215 | |
sahilmgandhi | 18:6a4db94011d3 | 216 | This field identifies whether the corresponding interrupt is: |
sahilmgandhi | 18:6a4db94011d3 | 217 | (1) edge-triggered or (0) level-sensitive |
sahilmgandhi | 18:6a4db94011d3 | 218 | (1) 1-N model or (0) N-N model |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 221 | \param [in] edge_level (1) edge-triggered or (0) level-sensitive |
sahilmgandhi | 18:6a4db94011d3 | 222 | \param [in] model (1) 1-N model or (0) N-N model |
sahilmgandhi | 18:6a4db94011d3 | 223 | */ |
sahilmgandhi | 18:6a4db94011d3 | 224 | void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); |
sahilmgandhi | 18:6a4db94011d3 | 225 | |
sahilmgandhi | 18:6a4db94011d3 | 226 | |
sahilmgandhi | 18:6a4db94011d3 | 227 | /** \brief Set Interrupt Priority |
sahilmgandhi | 18:6a4db94011d3 | 228 | |
sahilmgandhi | 18:6a4db94011d3 | 229 | The function sets the priority of an interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 230 | |
sahilmgandhi | 18:6a4db94011d3 | 231 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 232 | \param [in] priority Priority to set. |
sahilmgandhi | 18:6a4db94011d3 | 233 | */ |
sahilmgandhi | 18:6a4db94011d3 | 234 | void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); |
sahilmgandhi | 18:6a4db94011d3 | 235 | |
sahilmgandhi | 18:6a4db94011d3 | 236 | /** \brief Get Interrupt Priority |
sahilmgandhi | 18:6a4db94011d3 | 237 | |
sahilmgandhi | 18:6a4db94011d3 | 238 | The function reads the priority of an interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 239 | |
sahilmgandhi | 18:6a4db94011d3 | 240 | \param [in] IRQn Interrupt number. |
sahilmgandhi | 18:6a4db94011d3 | 241 | \return Interrupt Priority. |
sahilmgandhi | 18:6a4db94011d3 | 242 | */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | uint32_t GIC_GetPriority(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 244 | |
sahilmgandhi | 18:6a4db94011d3 | 245 | /** \brief CPU Interface Priority Mask Register |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | The priority mask level for the CPU interface. If the priority of an interrupt is higher than the |
sahilmgandhi | 18:6a4db94011d3 | 248 | value indicated by this field, the interface signals the interrupt to the processor. |
sahilmgandhi | 18:6a4db94011d3 | 249 | |
sahilmgandhi | 18:6a4db94011d3 | 250 | \param [in] Mask. |
sahilmgandhi | 18:6a4db94011d3 | 251 | */ |
sahilmgandhi | 18:6a4db94011d3 | 252 | void GIC_InterfacePriorityMask(uint32_t priority); |
sahilmgandhi | 18:6a4db94011d3 | 253 | |
sahilmgandhi | 18:6a4db94011d3 | 254 | /** \brief Set the binary point. |
sahilmgandhi | 18:6a4db94011d3 | 255 | |
sahilmgandhi | 18:6a4db94011d3 | 256 | Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. |
sahilmgandhi | 18:6a4db94011d3 | 257 | |
sahilmgandhi | 18:6a4db94011d3 | 258 | \param [in] Mask. |
sahilmgandhi | 18:6a4db94011d3 | 259 | */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | void GIC_SetBinaryPoint(uint32_t binary_point); |
sahilmgandhi | 18:6a4db94011d3 | 261 | |
sahilmgandhi | 18:6a4db94011d3 | 262 | /** \brief Get the binary point. |
sahilmgandhi | 18:6a4db94011d3 | 263 | |
sahilmgandhi | 18:6a4db94011d3 | 264 | Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. |
sahilmgandhi | 18:6a4db94011d3 | 265 | |
sahilmgandhi | 18:6a4db94011d3 | 266 | \return Binary point. |
sahilmgandhi | 18:6a4db94011d3 | 267 | */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | uint32_t GIC_GetBinaryPoint(uint32_t binary_point); |
sahilmgandhi | 18:6a4db94011d3 | 269 | |
sahilmgandhi | 18:6a4db94011d3 | 270 | /** \brief Get Interrupt state. |
sahilmgandhi | 18:6a4db94011d3 | 271 | |
sahilmgandhi | 18:6a4db94011d3 | 272 | Get the interrupt state, whether pending and/or active |
sahilmgandhi | 18:6a4db94011d3 | 273 | |
sahilmgandhi | 18:6a4db94011d3 | 274 | \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active |
sahilmgandhi | 18:6a4db94011d3 | 275 | */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 277 | |
sahilmgandhi | 18:6a4db94011d3 | 278 | /** \brief Send Software Generated interrupt |
sahilmgandhi | 18:6a4db94011d3 | 279 | |
sahilmgandhi | 18:6a4db94011d3 | 280 | Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. |
sahilmgandhi | 18:6a4db94011d3 | 281 | GIC_InterfacePriorityMask |
sahilmgandhi | 18:6a4db94011d3 | 282 | \param [in] IRQn The Interrupt ID of the SGI. |
sahilmgandhi | 18:6a4db94011d3 | 283 | \param [in] target_list CPUTargetList |
sahilmgandhi | 18:6a4db94011d3 | 284 | \param [in] filter_list TargetListFilter |
sahilmgandhi | 18:6a4db94011d3 | 285 | */ |
sahilmgandhi | 18:6a4db94011d3 | 286 | void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); |
sahilmgandhi | 18:6a4db94011d3 | 287 | |
sahilmgandhi | 18:6a4db94011d3 | 288 | /** \brief API call to initialise the interrupt distributor |
sahilmgandhi | 18:6a4db94011d3 | 289 | |
sahilmgandhi | 18:6a4db94011d3 | 290 | API call to initialise the interrupt distributor |
sahilmgandhi | 18:6a4db94011d3 | 291 | |
sahilmgandhi | 18:6a4db94011d3 | 292 | */ |
sahilmgandhi | 18:6a4db94011d3 | 293 | void GIC_DistInit(void); |
sahilmgandhi | 18:6a4db94011d3 | 294 | |
sahilmgandhi | 18:6a4db94011d3 | 295 | /** \brief API call to initialise the CPU interface |
sahilmgandhi | 18:6a4db94011d3 | 296 | |
sahilmgandhi | 18:6a4db94011d3 | 297 | API call to initialise the CPU interface |
sahilmgandhi | 18:6a4db94011d3 | 298 | |
sahilmgandhi | 18:6a4db94011d3 | 299 | */ |
sahilmgandhi | 18:6a4db94011d3 | 300 | void GIC_CPUInterfaceInit(void); |
sahilmgandhi | 18:6a4db94011d3 | 301 | |
sahilmgandhi | 18:6a4db94011d3 | 302 | /** \brief API call to set the Interrupt Configuration Registers |
sahilmgandhi | 18:6a4db94011d3 | 303 | |
sahilmgandhi | 18:6a4db94011d3 | 304 | API call to initialise the Interrupt Configuration Registers |
sahilmgandhi | 18:6a4db94011d3 | 305 | |
sahilmgandhi | 18:6a4db94011d3 | 306 | */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | void GIC_SetICDICFR (const uint32_t *ICDICFRn); |
sahilmgandhi | 18:6a4db94011d3 | 308 | |
sahilmgandhi | 18:6a4db94011d3 | 309 | /** \brief API call to Enable the GIC |
sahilmgandhi | 18:6a4db94011d3 | 310 | |
sahilmgandhi | 18:6a4db94011d3 | 311 | API call to Enable the GIC |
sahilmgandhi | 18:6a4db94011d3 | 312 | |
sahilmgandhi | 18:6a4db94011d3 | 313 | */ |
sahilmgandhi | 18:6a4db94011d3 | 314 | void GIC_Enable(void); |
sahilmgandhi | 18:6a4db94011d3 | 315 | |
sahilmgandhi | 18:6a4db94011d3 | 316 | #endif /* GIC_H_ */ |