MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file wdt_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief WDT HW register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3283 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup wdt
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <p>
sahilmgandhi 18:6a4db94011d3 31 * Watchdog Timer HW register map description
sahilmgandhi 18:6a4db94011d3 32 * </p>
sahilmgandhi 18:6a4db94011d3 33 *
sahilmgandhi 18:6a4db94011d3 34 */
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 37 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 38 #endif
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 #ifndef WDT_MAP_H_
sahilmgandhi 18:6a4db94011d3 41 #define WDT_MAP_H_
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 typedef struct {
sahilmgandhi 18:6a4db94011d3 46 __IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
sahilmgandhi 18:6a4db94011d3 47 __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
sahilmgandhi 18:6a4db94011d3 48 union {
sahilmgandhi 18:6a4db94011d3 49 struct {
sahilmgandhi 18:6a4db94011d3 50 __IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
sahilmgandhi 18:6a4db94011d3 51 } BITS;
sahilmgandhi 18:6a4db94011d3 52 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 53 } CONTROL; /* 0x4000A008 */
sahilmgandhi 18:6a4db94011d3 54 __O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
sahilmgandhi 18:6a4db94011d3 55 __O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
sahilmgandhi 18:6a4db94011d3 56 union {
sahilmgandhi 18:6a4db94011d3 57 struct {
sahilmgandhi 18:6a4db94011d3 58 __I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
sahilmgandhi 18:6a4db94011d3 59 __I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
sahilmgandhi 18:6a4db94011d3 60 __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
sahilmgandhi 18:6a4db94011d3 61 __IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
sahilmgandhi 18:6a4db94011d3 62 } BITS;
sahilmgandhi 18:6a4db94011d3 63 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 64 } STATUS; /* 0x4000A014 */
sahilmgandhi 18:6a4db94011d3 65 } WdtReg_t, *WdtReg_pt;
sahilmgandhi 18:6a4db94011d3 66 #endif /* WDT_MAP_H_ */