MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file timer_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief Timer HW register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3423 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-06-09 11:16:49 +0530 (Tue, 09 Jun 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup timer
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <p>
sahilmgandhi 18:6a4db94011d3 31 * Timer HW register map description
sahilmgandhi 18:6a4db94011d3 32 * </p>
sahilmgandhi 18:6a4db94011d3 33 *
sahilmgandhi 18:6a4db94011d3 34 * <h1> Reference document(s) </h1>
sahilmgandhi 18:6a4db94011d3 35 * <p>
sahilmgandhi 18:6a4db94011d3 36 * <a href="../pdf/IPC7200_Timer_APB_DS_v1P2.pdf" target="_blank">
sahilmgandhi 18:6a4db94011d3 37 * IPC7200 APB Timer Design Specification v1.2</a>
sahilmgandhi 18:6a4db94011d3 38 * </p>
sahilmgandhi 18:6a4db94011d3 39 */
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #ifndef TIMER_MAP_H_
sahilmgandhi 18:6a4db94011d3 42 #define TIMER_MAP_H_
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 45 extern "C" {
sahilmgandhi 18:6a4db94011d3 46 #endif
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** Timer HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 51 typedef struct {
sahilmgandhi 18:6a4db94011d3 52 __IO uint32_t LOAD; /**< 16bit counter (re-)load value */
sahilmgandhi 18:6a4db94011d3 53 __I uint32_t VALUE; /**< 16bit current counter value */
sahilmgandhi 18:6a4db94011d3 54 union {
sahilmgandhi 18:6a4db94011d3 55 struct {
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t PAD0 :2; /**< Always reads 0 */
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t PRESCALE :3; /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
sahilmgandhi 18:6a4db94011d3 58 __IO uint32_t PAD1 :1; /**< Always reads 0 */
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t MODE :1; /**< 0:free-run, 1:periodic */
sahilmgandhi 18:6a4db94011d3 60 __IO uint32_t ENABLE :1; /**< 0: disable, 1:enable */
sahilmgandhi 18:6a4db94011d3 61 __I uint32_t INT :1; /**< interrupt status */
sahilmgandhi 18:6a4db94011d3 62 } BITS;
sahilmgandhi 18:6a4db94011d3 63 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 64 } CONTROL;
sahilmgandhi 18:6a4db94011d3 65 __O uint32_t CLEAR; /**< Write any value to clear the interrupt */
sahilmgandhi 18:6a4db94011d3 66 } TimerReg_t, *TimerReg_pt;
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 69 }
sahilmgandhi 18:6a4db94011d3 70 #endif
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #endif /* TIMER_MAP_H_ */