MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file spi_ipc7207_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief SPI IPC 7207 HW register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 2110 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup spi_ipc7207
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <p>
sahilmgandhi 18:6a4db94011d3 31 * SPI HW register map description
sahilmgandhi 18:6a4db94011d3 32 * </p>
sahilmgandhi 18:6a4db94011d3 33 *
sahilmgandhi 18:6a4db94011d3 34 * <h1> Reference document(s) </h1>
sahilmgandhi 18:6a4db94011d3 35 * <p>
sahilmgandhi 18:6a4db94011d3 36 * <a href="../pdf/IPC7207_SPI_APB_DS_v1P2.pdf" target="_blank">
sahilmgandhi 18:6a4db94011d3 37 * IPC7207 APB SPI Design Specification v1.2 </a>
sahilmgandhi 18:6a4db94011d3 38 * </p>
sahilmgandhi 18:6a4db94011d3 39 */
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #ifndef SPI_IPC7207_MAP_H_
sahilmgandhi 18:6a4db94011d3 42 #define SPI_IPC7207_MAP_H_
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /** SPI HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 47 typedef struct {
sahilmgandhi 18:6a4db94011d3 48 __O uint32_t TX_DATA;
sahilmgandhi 18:6a4db94011d3 49 __I uint32_t RX_DATA;
sahilmgandhi 18:6a4db94011d3 50 __IO uint32_t FDIV;
sahilmgandhi 18:6a4db94011d3 51 union {
sahilmgandhi 18:6a4db94011d3 52 struct {
sahilmgandhi 18:6a4db94011d3 53 __IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
sahilmgandhi 18:6a4db94011d3 54 __IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
sahilmgandhi 18:6a4db94011d3 55 __IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
sahilmgandhi 18:6a4db94011d3 58 __IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
sahilmgandhi 18:6a4db94011d3 60 } BITS;
sahilmgandhi 18:6a4db94011d3 61 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 62 } CONTROL;
sahilmgandhi 18:6a4db94011d3 63 union {
sahilmgandhi 18:6a4db94011d3 64 struct {
sahilmgandhi 18:6a4db94011d3 65 __I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
sahilmgandhi 18:6a4db94011d3 66 __I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
sahilmgandhi 18:6a4db94011d3 67 __I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
sahilmgandhi 18:6a4db94011d3 68 __I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
sahilmgandhi 18:6a4db94011d3 69 __I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
sahilmgandhi 18:6a4db94011d3 70 __I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
sahilmgandhi 18:6a4db94011d3 71 __I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
sahilmgandhi 18:6a4db94011d3 72 __I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
sahilmgandhi 18:6a4db94011d3 73 } BITS;
sahilmgandhi 18:6a4db94011d3 74 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 75 } STATUS;
sahilmgandhi 18:6a4db94011d3 76 union {
sahilmgandhi 18:6a4db94011d3 77 struct {
sahilmgandhi 18:6a4db94011d3 78 __IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
sahilmgandhi 18:6a4db94011d3 79 __IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
sahilmgandhi 18:6a4db94011d3 80 } BITS;
sahilmgandhi 18:6a4db94011d3 81 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 82 } SLAVE_SELECT;
sahilmgandhi 18:6a4db94011d3 83 __IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
sahilmgandhi 18:6a4db94011d3 84 __IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
sahilmgandhi 18:6a4db94011d3 85 __I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
sahilmgandhi 18:6a4db94011d3 86 __O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
sahilmgandhi 18:6a4db94011d3 87 __IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
sahilmgandhi 18:6a4db94011d3 88 __IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
sahilmgandhi 18:6a4db94011d3 89 __I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
sahilmgandhi 18:6a4db94011d3 90 __I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
sahilmgandhi 18:6a4db94011d3 91 } SpiIpc7207Reg_t, *SpiIpc7207Reg_pt;
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 #endif /* SPI_IPC7207_MAP_H_ */