MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file rtc_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief Real Time Clock HW register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor.
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3008 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup rtc
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <p>
sahilmgandhi 18:6a4db94011d3 31 * Teal Time Clock HW register map description
sahilmgandhi 18:6a4db94011d3 32 * </p>
sahilmgandhi 18:6a4db94011d3 33 *
sahilmgandhi 18:6a4db94011d3 34 * <h1> Reference document(s) </h1>
sahilmgandhi 18:6a4db94011d3 35 * <p>
sahilmgandhi 18:6a4db94011d3 36 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
sahilmgandhi 18:6a4db94011d3 37 * IPC7206 APB RTC Design Specification v1.0 </a>
sahilmgandhi 18:6a4db94011d3 38 * </p>
sahilmgandhi 18:6a4db94011d3 39 */
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #ifndef RTC_MAP_H_
sahilmgandhi 18:6a4db94011d3 42 #define RTC_MAP_H_
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /** Real Time Clock Control HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 47 typedef struct {
sahilmgandhi 18:6a4db94011d3 48 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
sahilmgandhi 18:6a4db94011d3 49 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
sahilmgandhi 18:6a4db94011d3 50 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
sahilmgandhi 18:6a4db94011d3 51 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
sahilmgandhi 18:6a4db94011d3 52 union {
sahilmgandhi 18:6a4db94011d3 53 struct {
sahilmgandhi 18:6a4db94011d3 54 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
sahilmgandhi 18:6a4db94011d3 55 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
sahilmgandhi 18:6a4db94011d3 58 } BITS;
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 60 } CONTROL; /* 0x4000F010 */
sahilmgandhi 18:6a4db94011d3 61 union {
sahilmgandhi 18:6a4db94011d3 62 struct {
sahilmgandhi 18:6a4db94011d3 63 /**<Any write to the status register will clear the error bit. */
sahilmgandhi 18:6a4db94011d3 64 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
sahilmgandhi 18:6a4db94011d3 65 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
sahilmgandhi 18:6a4db94011d3 66 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
sahilmgandhi 18:6a4db94011d3 67 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
sahilmgandhi 18:6a4db94011d3 68 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
sahilmgandhi 18:6a4db94011d3 69 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
sahilmgandhi 18:6a4db94011d3 70 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
sahilmgandhi 18:6a4db94011d3 71 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
sahilmgandhi 18:6a4db94011d3 72 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
sahilmgandhi 18:6a4db94011d3 73 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
sahilmgandhi 18:6a4db94011d3 74 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
sahilmgandhi 18:6a4db94011d3 75 } BITS;
sahilmgandhi 18:6a4db94011d3 76 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 77 } STATUS; /* 0x4000F014 */
sahilmgandhi 18:6a4db94011d3 78 union {
sahilmgandhi 18:6a4db94011d3 79 struct {
sahilmgandhi 18:6a4db94011d3 80 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
sahilmgandhi 18:6a4db94011d3 81 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
sahilmgandhi 18:6a4db94011d3 82 } BITS;
sahilmgandhi 18:6a4db94011d3 83 __O uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 84 } INT_CLEAR; /* 0x4000F018 */
sahilmgandhi 18:6a4db94011d3 85 } RtcReg_t, *RtcReg_pt;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 #endif /* RTC_MAP_H_ */