MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file rtc.c
sahilmgandhi 18:6a4db94011d3 4 * @brief Implementation of a Rtc driver
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3525 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup rtc
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
sahilmgandhi 18:6a4db94011d3 31 * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
sahilmgandhi 18:6a4db94011d3 32 * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
sahilmgandhi 18:6a4db94011d3 33 * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
sahilmgandhi 18:6a4db94011d3 34 * Use the Reset bit in the Control Register to reset the counters to their default values.
sahilmgandhi 18:6a4db94011d3 35 * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
sahilmgandhi 18:6a4db94011d3 36 * internally to time the incrementing of the Seconds Counter.
sahilmgandhi 18:6a4db94011d3 37 * There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
sahilmgandhi 18:6a4db94011d3 38 * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
sahilmgandhi 18:6a4db94011d3 39 * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
sahilmgandhi 18:6a4db94011d3 40 * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
sahilmgandhi 18:6a4db94011d3 41 * if the alarm occurs upon a Counter increment condition.
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 */
sahilmgandhi 18:6a4db94011d3 44 #include "rtc.h"
sahilmgandhi 18:6a4db94011d3 45 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 46 #include "lp_ticker_api.h"
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 static uint16_t SubSecond;
sahilmgandhi 18:6a4db94011d3 49 static uint64_t LastRtcTimeus;
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 52 void fRtcInit(void)
sahilmgandhi 18:6a4db94011d3 53 {
sahilmgandhi 18:6a4db94011d3 54 CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
sahilmgandhi 18:6a4db94011d3 55 CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Reset RTC control register */
sahilmgandhi 18:6a4db94011d3 58 RTCREG->CONTROL.WORD = False;
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /* Initialize all counters */
sahilmgandhi 18:6a4db94011d3 61 RTCREG->SECOND_COUNTER = False;
sahilmgandhi 18:6a4db94011d3 62 RTCREG->SUB_SECOND_COUNTER = False;
sahilmgandhi 18:6a4db94011d3 63 RTCREG->SECOND_ALARM = False;
sahilmgandhi 18:6a4db94011d3 64 RTCREG->SUB_SECOND_ALARM = False;
sahilmgandhi 18:6a4db94011d3 65 LastRtcTimeus = 0;
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 /* Reset RTC Status register */
sahilmgandhi 18:6a4db94011d3 68 RTCREG->STATUS.WORD = False;
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /* Clear interrupt status */
sahilmgandhi 18:6a4db94011d3 71 RTCREG->INT_CLEAR.WORD = False;
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /* Start sec & sub_sec counter */
sahilmgandhi 18:6a4db94011d3 74 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
sahilmgandhi 18:6a4db94011d3 75 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 76 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /* enable interruption associated with the rtc at NVIC level */
sahilmgandhi 18:6a4db94011d3 79 NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
sahilmgandhi 18:6a4db94011d3 80 NVIC_ClearPendingIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 81 NVIC_EnableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 return;
sahilmgandhi 18:6a4db94011d3 86 }
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 89 void fRtcFree(void)
sahilmgandhi 18:6a4db94011d3 90 {
sahilmgandhi 18:6a4db94011d3 91 /* Reset RTC control register */
sahilmgandhi 18:6a4db94011d3 92 RTCREG->CONTROL.WORD = False;
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* disable interruption associated with the rtc */
sahilmgandhi 18:6a4db94011d3 95 NVIC_DisableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 101 void fRtcSetInterrupt(uint32_t timestamp)
sahilmgandhi 18:6a4db94011d3 102 {
sahilmgandhi 18:6a4db94011d3 103 SubSecond = False;
sahilmgandhi 18:6a4db94011d3 104 uint32_t Second = False, EnableInterrupt = False;
sahilmgandhi 18:6a4db94011d3 105 uint8_t DividerAdjust = 1;
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 if(timestamp) {
sahilmgandhi 18:6a4db94011d3 108 if(timestamp >= RTC_SEC_TO_US) {
sahilmgandhi 18:6a4db94011d3 109 /* TimeStamp is big enough to set second alarm */
sahilmgandhi 18:6a4db94011d3 110 Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
sahilmgandhi 18:6a4db94011d3 111 RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /* Enable second interrupt */
sahilmgandhi 18:6a4db94011d3 114 EnableInterrupt = True << RTC_CONTROL_SEC_CNT_INT_BIT_POS;
sahilmgandhi 18:6a4db94011d3 115 }
sahilmgandhi 18:6a4db94011d3 116 timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
sahilmgandhi 18:6a4db94011d3 117 if(timestamp > False) {
sahilmgandhi 18:6a4db94011d3 118 /* We have some thing for sub second */
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 /* Convert micro second to sub_seconds(each count = 30.5 us) */
sahilmgandhi 18:6a4db94011d3 121 if(timestamp > 131000) {
sahilmgandhi 18:6a4db94011d3 122 DividerAdjust = 100;
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
sahilmgandhi 18:6a4db94011d3 126 Temp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
sahilmgandhi 18:6a4db94011d3 127 SubSecond = Temp & RTC_SUB_SEC_MASK;
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 if(SubSecond <= 5) {
sahilmgandhi 18:6a4db94011d3 130 SubSecond = 0;
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 if(SubSecond > False) {
sahilmgandhi 18:6a4db94011d3 134 /* Second interrupt not enabled */
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /* Set SUB SEC_ALARM */
sahilmgandhi 18:6a4db94011d3 137 RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* Enable sub second interrupt */
sahilmgandhi 18:6a4db94011d3 140 EnableInterrupt |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 }
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 RTCREG->CONTROL.WORD |= EnableInterrupt;
sahilmgandhi 18:6a4db94011d3 145 /* Enable RTC interrupt */
sahilmgandhi 18:6a4db94011d3 146 NVIC_EnableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 149 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 150 (True << RTC_STATUS_SEC_ALARM_WRT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 151 (True << RTC_STATUS_CONTROL_WRT_BIT_POS))) == True);
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 return;
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 157 void fRtcDisableInterrupt(void)
sahilmgandhi 18:6a4db94011d3 158 {
sahilmgandhi 18:6a4db94011d3 159 /* Disable RTC interrupt */
sahilmgandhi 18:6a4db94011d3 160 NVIC_DisableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 161 }
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 164 void fRtcEnableInterrupt(void)
sahilmgandhi 18:6a4db94011d3 165 {
sahilmgandhi 18:6a4db94011d3 166 /* Enable RTC interrupt */
sahilmgandhi 18:6a4db94011d3 167 NVIC_EnableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 168 }
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 171 void fRtcClearInterrupt(void)
sahilmgandhi 18:6a4db94011d3 172 {
sahilmgandhi 18:6a4db94011d3 173 /* Disable subsec/sec interrupt */
sahilmgandhi 18:6a4db94011d3 174 /* Clear sec & sub_sec interrupts */
sahilmgandhi 18:6a4db94011d3 175 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 176 (True << RTC_INT_CLR_SEC_BIT_POS));
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 179 (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS))) == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 183 uint64_t fRtcRead(void)
sahilmgandhi 18:6a4db94011d3 184 {
sahilmgandhi 18:6a4db94011d3 185 uint32_t Second;
sahilmgandhi 18:6a4db94011d3 186 uint16_t SubSecond;
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
sahilmgandhi 18:6a4db94011d3 189 * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
sahilmgandhi 18:6a4db94011d3 190 * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
sahilmgandhi 18:6a4db94011d3 191 * If you read a zero in the sub-second counter then increment the second counter by 1.
sahilmgandhi 18:6a4db94011d3 192 * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
sahilmgandhi 18:6a4db94011d3 193 */
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /* Read the Second and Sub-second counters, then read the Second counter again.
sahilmgandhi 18:6a4db94011d3 196 * If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 do {
sahilmgandhi 18:6a4db94011d3 200 Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
sahilmgandhi 18:6a4db94011d3 201 SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK; /* Get SUB_SEC_COUNTER reg value */
sahilmgandhi 18:6a4db94011d3 202 } while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 //note: casting to float removed to avoid reduction in resolution
sahilmgandhi 18:6a4db94011d3 205 uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /*check that the time did not go backwards */
sahilmgandhi 18:6a4db94011d3 208 MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
sahilmgandhi 18:6a4db94011d3 209 LastRtcTimeus = RtcTimeus;
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 return RtcTimeus;
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 215 void fRtcWrite(uint64_t RtcTimeus)
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 uint32_t Second = False;
sahilmgandhi 18:6a4db94011d3 218 uint16_t SubSecond = False;
sahilmgandhi 18:6a4db94011d3 219 /* Stop RTC */
sahilmgandhi 18:6a4db94011d3 220 RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 221 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 if(RtcTimeus > RTC_SEC_TO_US) {
sahilmgandhi 18:6a4db94011d3 224 /* TimeStamp is big enough to set second counter */
sahilmgandhi 18:6a4db94011d3 225 Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
sahilmgandhi 18:6a4db94011d3 226 }
sahilmgandhi 18:6a4db94011d3 227 RTCREG->SECOND_COUNTER = Second;
sahilmgandhi 18:6a4db94011d3 228 RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
sahilmgandhi 18:6a4db94011d3 229 if(RtcTimeus > False) {
sahilmgandhi 18:6a4db94011d3 230 /* Convert TimeStamp to sub_seconds */
sahilmgandhi 18:6a4db94011d3 231 SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 /* Set SUB_SEC_ALARM */
sahilmgandhi 18:6a4db94011d3 234 RTCREG->SUB_SECOND_COUNTER = SubSecond;
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 237 /* Start RTC */
sahilmgandhi 18:6a4db94011d3 238 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 239 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /* See rtc.h for details */
sahilmgandhi 18:6a4db94011d3 245 void fRtcHandler(void)
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 /* SUB_SECOND/SECOND interrupt occured */
sahilmgandhi 18:6a4db94011d3 248 volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /* Disable RTC interrupt */
sahilmgandhi 18:6a4db94011d3 251 NVIC_DisableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /* Clear sec & sub_sec interrupts */
sahilmgandhi 18:6a4db94011d3 254 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 255 (True << RTC_INT_CLR_SEC_BIT_POS));
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 /* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be resolved in REV G */
sahilmgandhi 18:6a4db94011d3 258 if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
sahilmgandhi 18:6a4db94011d3 259 /* Second interrupt occured */
sahilmgandhi 18:6a4db94011d3 260 if(SubSecond > False) {
sahilmgandhi 18:6a4db94011d3 261 /* Set SUB SEC_ALARM */
sahilmgandhi 18:6a4db94011d3 262 RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
sahilmgandhi 18:6a4db94011d3 263 /* Enable sub second interrupt */
sahilmgandhi 18:6a4db94011d3 264 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
sahilmgandhi 18:6a4db94011d3 265 } else {
sahilmgandhi 18:6a4db94011d3 266 /* We reach here after second interrupt is occured */
sahilmgandhi 18:6a4db94011d3 267 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 268 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
sahilmgandhi 18:6a4db94011d3 269 }
sahilmgandhi 18:6a4db94011d3 270 } else {
sahilmgandhi 18:6a4db94011d3 271 /* We reach here after sub_second or (Sub second + second) interrupt occured */
sahilmgandhi 18:6a4db94011d3 272 /* Disable Second and sub_second interrupt */
sahilmgandhi 18:6a4db94011d3 273 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 274 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
sahilmgandhi 18:6a4db94011d3 275 }
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 NVIC_EnableIRQ(Rtc_IRQn);
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
sahilmgandhi 18:6a4db94011d3 280 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 281 (True << RTC_STATUS_CONTROL_WRT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 282 (True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 283 (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS))) == True);
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 lp_ticker_irq_handler();
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 boolean fIsRtcEnabled(void)
sahilmgandhi 18:6a4db94011d3 289 {
sahilmgandhi 18:6a4db94011d3 290 if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
sahilmgandhi 18:6a4db94011d3 291 return True;
sahilmgandhi 18:6a4db94011d3 292 } else {
sahilmgandhi 18:6a4db94011d3 293 return False;
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295 }