MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file rfAna_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief rfAna hw module register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 2953 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2014-09-15 18:13:01 +0530 (Mon, 15 Sep 2014) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup rfAna
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <p>
sahilmgandhi 18:6a4db94011d3 31 * Rf and Analog control and trimming hw module register map
sahilmgandhi 18:6a4db94011d3 32 * </p>
sahilmgandhi 18:6a4db94011d3 33 */
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #ifndef RFANA_MAP_H_
sahilmgandhi 18:6a4db94011d3 36 #define RFANA_MAP_H_
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 39 * *
sahilmgandhi 18:6a4db94011d3 40 * Header files *
sahilmgandhi 18:6a4db94011d3 41 * *
sahilmgandhi 18:6a4db94011d3 42 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /**************************************************************************************************
sahilmgandhi 18:6a4db94011d3 47 * *
sahilmgandhi 18:6a4db94011d3 48 * Type definitions *
sahilmgandhi 18:6a4db94011d3 49 * *
sahilmgandhi 18:6a4db94011d3 50 **************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /** rfAna register map (control part) */
sahilmgandhi 18:6a4db94011d3 53 typedef struct {
sahilmgandhi 18:6a4db94011d3 54 union {
sahilmgandhi 18:6a4db94011d3 55 struct {
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t FRACT_WORD:24;
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t INT_WORD:8;
sahilmgandhi 18:6a4db94011d3 58 } BITS;
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 60 } TX_LO_CONTROL;
sahilmgandhi 18:6a4db94011d3 61 union {
sahilmgandhi 18:6a4db94011d3 62 struct {
sahilmgandhi 18:6a4db94011d3 63 __IO uint32_t FRACT_WORD:24;
sahilmgandhi 18:6a4db94011d3 64 __IO uint32_t INT_WORD:8;
sahilmgandhi 18:6a4db94011d3 65 } BITS;
sahilmgandhi 18:6a4db94011d3 66 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 67 } RX_LO_CONTROL;
sahilmgandhi 18:6a4db94011d3 68 union {
sahilmgandhi 18:6a4db94011d3 69 struct {
sahilmgandhi 18:6a4db94011d3 70 __IO uint32_t PLL_RESET_TIME:10;
sahilmgandhi 18:6a4db94011d3 71 __I uint32_t RESERVED:6;
sahilmgandhi 18:6a4db94011d3 72 __IO uint32_t PLL_LOCK_TIME:10;
sahilmgandhi 18:6a4db94011d3 73 } BITS;
sahilmgandhi 18:6a4db94011d3 74 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 75 } PLL_TIMING;
sahilmgandhi 18:6a4db94011d3 76 union {
sahilmgandhi 18:6a4db94011d3 77 struct {
sahilmgandhi 18:6a4db94011d3 78 __IO uint32_t LNA_GAIN_MODE:1;
sahilmgandhi 18:6a4db94011d3 79 __IO uint32_t ADC_DITHER_MODE:1;
sahilmgandhi 18:6a4db94011d3 80 } BITS;
sahilmgandhi 18:6a4db94011d3 81 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 82 } RX_CONTROL;
sahilmgandhi 18:6a4db94011d3 83 __IO uint32_t TX_POWER;
sahilmgandhi 18:6a4db94011d3 84 __I uint32_t RECEIVER_GAIN;
sahilmgandhi 18:6a4db94011d3 85 } RfAnaReg_t, *RfAnaReg_pt;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 /** rfAna register map (trimming part) */
sahilmgandhi 18:6a4db94011d3 88 typedef struct {
sahilmgandhi 18:6a4db94011d3 89 __IO uint32_t PMU_TRIM;
sahilmgandhi 18:6a4db94011d3 90 __IO uint32_t RESERVED;
sahilmgandhi 18:6a4db94011d3 91 __IO uint32_t RX_CHAIN_TRIM;
sahilmgandhi 18:6a4db94011d3 92 union {
sahilmgandhi 18:6a4db94011d3 93 struct {
sahilmgandhi 18:6a4db94011d3 94 __I uint32_t BIAS_VCO_TRIM:4;
sahilmgandhi 18:6a4db94011d3 95 __I uint32_t MODULATION_TRIM:4;
sahilmgandhi 18:6a4db94011d3 96 __IO uint32_t TX_VCO_TRIM:4;
sahilmgandhi 18:6a4db94011d3 97 __IO uint32_t RX_VCO_TRIM:4;
sahilmgandhi 18:6a4db94011d3 98 __I uint32_t DIV_TRIM:3;
sahilmgandhi 18:6a4db94011d3 99 __I uint32_t REG_TRIM:2;
sahilmgandhi 18:6a4db94011d3 100 __I uint32_t LFR_TRIM:3;
sahilmgandhi 18:6a4db94011d3 101 __I uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 102 __I uint32_t CHARGE_PUMP_RANGE:4;
sahilmgandhi 18:6a4db94011d3 103 } BITS;
sahilmgandhi 18:6a4db94011d3 104 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 105 } PLL_TRIM;
sahilmgandhi 18:6a4db94011d3 106 __IO uint32_t PLL_VCO_TAP_LOCATION;
sahilmgandhi 18:6a4db94011d3 107 union {
sahilmgandhi 18:6a4db94011d3 108 struct {
sahilmgandhi 18:6a4db94011d3 109 __IO uint32_t TX_TUNE:4;
sahilmgandhi 18:6a4db94011d3 110 __IO uint32_t PA_REGULATOR_TRIM:4;
sahilmgandhi 18:6a4db94011d3 111 __IO uint32_t REGULATOR_TRIM:2;
sahilmgandhi 18:6a4db94011d3 112 __IO uint32_t RESERVED:2;
sahilmgandhi 18:6a4db94011d3 113 } BITS;
sahilmgandhi 18:6a4db94011d3 114 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 115 } TX_TRIM;
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 __IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
sahilmgandhi 18:6a4db94011d3 118 __IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
sahilmgandhi 18:6a4db94011d3 119 __IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
sahilmgandhi 18:6a4db94011d3 120 __IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
sahilmgandhi 18:6a4db94011d3 122 } RfAnaTrimReg_t, *RfAnaTrimReg_pt;
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 #endif /* RFANA_MAP_H_ */