MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file rfAna.c
sahilmgandhi 18:6a4db94011d3 4 * @brief Implementation of rfAna hw module functions
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3445 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup rfAna
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 * <h1> Reference document(s) </h1>
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 35 * *
sahilmgandhi 18:6a4db94011d3 36 * Header files *
sahilmgandhi 18:6a4db94011d3 37 * *
sahilmgandhi 18:6a4db94011d3 38 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 #include "memory_map.h"
sahilmgandhi 18:6a4db94011d3 41 #include "rfAna.h"
sahilmgandhi 18:6a4db94011d3 42 #include "clock.h"
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 45 * *
sahilmgandhi 18:6a4db94011d3 46 * Global variables *
sahilmgandhi 18:6a4db94011d3 47 * *
sahilmgandhi 18:6a4db94011d3 48 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** Rf channel and tx power lookup tables (constant)
sahilmgandhi 18:6a4db94011d3 51 * @details
sahilmgandhi 18:6a4db94011d3 52 *
sahilmgandhi 18:6a4db94011d3 53 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
sahilmgandhi 18:6a4db94011d3 54 * It has 16 entries corresponding to 16 15.4 channels.
sahilmgandhi 18:6a4db94011d3 55 * Entry 1 <-> Channel 11
sahilmgandhi 18:6a4db94011d3 56 * ...
sahilmgandhi 18:6a4db94011d3 57 * Entry 16 <-> Channel 26
sahilmgandhi 18:6a4db94011d3 58 *
sahilmgandhi 18:6a4db94011d3 59 * Each entry is compound of 4 items.
sahilmgandhi 18:6a4db94011d3 60 * Item 0: Rx Frequency integer divide portion
sahilmgandhi 18:6a4db94011d3 61 * Item 1: Rx Frequency fractional divide portion
sahilmgandhi 18:6a4db94011d3 62 * Item 2: Tx Frequency integer divide portion
sahilmgandhi 18:6a4db94011d3 63 * Item 3: Tx Frequency fractional divide portion
sahilmgandhi 18:6a4db94011d3 64 *
sahilmgandhi 18:6a4db94011d3 65 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
sahilmgandhi 18:6a4db94011d3 66 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
sahilmgandhi 18:6a4db94011d3 67 * Entry 1 <-> -32dB
sahilmgandhi 18:6a4db94011d3 68 * Entry 2 <-> -31dB
sahilmgandhi 18:6a4db94011d3 69 * ...
sahilmgandhi 18:6a4db94011d3 70 * Entry 2 <-> 9dB
sahilmgandhi 18:6a4db94011d3 71 * Entry 43 <-> +10dB
sahilmgandhi 18:6a4db94011d3 72 *
sahilmgandhi 18:6a4db94011d3 73 * Each entry is compound of 1 byte.
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 // RR: Making high side injection changes to RevD
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /** This rf LUT is built for high side injection, using low side injection
sahilmgandhi 18:6a4db94011d3 79 * would requiere to change this LUT. */
sahilmgandhi 18:6a4db94011d3 80 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
sahilmgandhi 18:6a4db94011d3 81 {0x50,0x017F52,0x4B,0x014001},
sahilmgandhi 18:6a4db94011d3 82 {0x51,0xFE29FB,0x4B,0x01E001},
sahilmgandhi 18:6a4db94011d3 83 {0x51,0xFED4A6,0x4C,0xFE7FFF},
sahilmgandhi 18:6a4db94011d3 84 {0x51,0xFF7F51,0x4C,0xFF1FFF},
sahilmgandhi 18:6a4db94011d3 85 {0x51,0x0029FC,0x4C,0xFFC000},
sahilmgandhi 18:6a4db94011d3 86 {0x51,0x00D4A7,0x4C,0x006000},
sahilmgandhi 18:6a4db94011d3 87 {0x51,0x017F52,0x4C,0x010001},
sahilmgandhi 18:6a4db94011d3 88 {0x52,0xFE29FB,0x4C,0x01A001},
sahilmgandhi 18:6a4db94011d3 89 {0x52,0xFED4A6,0x4D,0xFE3FFF},
sahilmgandhi 18:6a4db94011d3 90 {0x52,0xFF7F51,0x4D,0xFEDFFF},
sahilmgandhi 18:6a4db94011d3 91 {0x52,0x0029FC,0x4D,0xFF8000},
sahilmgandhi 18:6a4db94011d3 92 {0x52,0x00D4A7,0x4D,0x002000},
sahilmgandhi 18:6a4db94011d3 93 {0x52,0x017F52,0x4D,0x00C001},
sahilmgandhi 18:6a4db94011d3 94 {0x53,0xFE29FB,0x4D,0x016001},
sahilmgandhi 18:6a4db94011d3 95 {0x53,0xFED4A6,0x4E,0xFDFFFE}
sahilmgandhi 18:6a4db94011d3 96 };
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
sahilmgandhi 18:6a4db94011d3 99 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
sahilmgandhi 18:6a4db94011d3 100 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
sahilmgandhi 18:6a4db94011d3 101 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
sahilmgandhi 18:6a4db94011d3 102 13,14,15,16,17,18,19,20,20,20
sahilmgandhi 18:6a4db94011d3 103 }; // +1dBm to +10 dBm
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 106 * *
sahilmgandhi 18:6a4db94011d3 107 * Functions *
sahilmgandhi 18:6a4db94011d3 108 * *
sahilmgandhi 18:6a4db94011d3 109 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 void fRfAnaInit()
sahilmgandhi 18:6a4db94011d3 112 {
sahilmgandhi 18:6a4db94011d3 113 // Enable rfana clock
sahilmgandhi 18:6a4db94011d3 114 CLOCK_ENABLE(CLOCK_RFANA);
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 // Set PLL timing
sahilmgandhi 18:6a4db94011d3 117 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
sahilmgandhi 18:6a4db94011d3 118 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 // Set other parameters
sahilmgandhi 18:6a4db94011d3 121 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
sahilmgandhi 18:6a4db94011d3 122 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 boolean fRfAnaIoctl (uint32_t request, void *argument)
sahilmgandhi 18:6a4db94011d3 126 {
sahilmgandhi 18:6a4db94011d3 127 uint8_t channel, txPower;
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
sahilmgandhi 18:6a4db94011d3 130 CLOCK_ENABLE(CLOCK_RFANA);
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 switch(request) {
sahilmgandhi 18:6a4db94011d3 133 case SET_RF_CHANNEL:
sahilmgandhi 18:6a4db94011d3 134 channel = *(uint8_t*)argument;
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 // Set tx/rx integer/fractional divide portions
sahilmgandhi 18:6a4db94011d3 137 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
sahilmgandhi 18:6a4db94011d3 138 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
sahilmgandhi 18:6a4db94011d3 139 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
sahilmgandhi 18:6a4db94011d3 140 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 // Set tx/rx vco trims
sahilmgandhi 18:6a4db94011d3 143 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
sahilmgandhi 18:6a4db94011d3 144 * from trims stored in dedicated registers available in digital.*/
sahilmgandhi 18:6a4db94011d3 145 if (channel < 19) {
sahilmgandhi 18:6a4db94011d3 146 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
sahilmgandhi 18:6a4db94011d3 147 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
sahilmgandhi 18:6a4db94011d3 148 } else {
sahilmgandhi 18:6a4db94011d3 149 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
sahilmgandhi 18:6a4db94011d3 150 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
sahilmgandhi 18:6a4db94011d3 151 }
sahilmgandhi 18:6a4db94011d3 152 break;
sahilmgandhi 18:6a4db94011d3 153 case SET_TX_POWER:
sahilmgandhi 18:6a4db94011d3 154 txPower = *(uint8_t*)argument;
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 // Set tx power register
sahilmgandhi 18:6a4db94011d3 157 if ((txPower & 0x20) == 0) {
sahilmgandhi 18:6a4db94011d3 158 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
sahilmgandhi 18:6a4db94011d3 159 } else {
sahilmgandhi 18:6a4db94011d3 160 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
sahilmgandhi 18:6a4db94011d3 161 }
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 break;
sahilmgandhi 18:6a4db94011d3 164 default:
sahilmgandhi 18:6a4db94011d3 165 return False;
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167 return True;
sahilmgandhi 18:6a4db94011d3 168 }