MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file us_ticker_api.h
sahilmgandhi 18:6a4db94011d3 4 * @brief Implementation of a Timer driver
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-11-15 $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup timer
sahilmgandhi 18:6a4db94011d3 28 */
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 31 #include "timer.h"
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #define US_TIMER TIMER0
sahilmgandhi 18:6a4db94011d3 34 #define US_TICKER TIMER1
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 static int us_ticker_inited = 0;
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 static void us_timer_init(void);
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 static uint32_t us_ticker_target = 0;
sahilmgandhi 18:6a4db94011d3 41 static volatile uint32_t msb_counter = 0;
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 void us_ticker_init(void)
sahilmgandhi 18:6a4db94011d3 44 {
sahilmgandhi 18:6a4db94011d3 45 if (!us_ticker_inited) {
sahilmgandhi 18:6a4db94011d3 46 us_timer_init();
sahilmgandhi 18:6a4db94011d3 47 }
sahilmgandhi 18:6a4db94011d3 48 }
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 51 * Timer for us timing reference
sahilmgandhi 18:6a4db94011d3 52 *
sahilmgandhi 18:6a4db94011d3 53 * Uptime counter for scheduling reference. It uses TIMER0.
sahilmgandhi 18:6a4db94011d3 54 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
sahilmgandhi 18:6a4db94011d3 55 * which is why a software timer is required to get 32-bit word length.
sahilmgandhi 18:6a4db94011d3 56 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 57 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
sahilmgandhi 18:6a4db94011d3 58 /* TODO - Add msb_counter rollover protection at 16 bits count? */
sahilmgandhi 18:6a4db94011d3 59 /* TODO - How is overflow handled? */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /* Timer 0 for free running time */
sahilmgandhi 18:6a4db94011d3 62 extern void us_timer_isr(void)
sahilmgandhi 18:6a4db94011d3 63 {
sahilmgandhi 18:6a4db94011d3 64 TIM0REG->CLEAR = 0;
sahilmgandhi 18:6a4db94011d3 65 msb_counter++;
sahilmgandhi 18:6a4db94011d3 66 }
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 /* Initializing TIMER 0(TImer) and TIMER 1(Ticker) */
sahilmgandhi 18:6a4db94011d3 69 static void us_timer_init(void)
sahilmgandhi 18:6a4db94011d3 70 {
sahilmgandhi 18:6a4db94011d3 71 /* Enable the timer0 periphery clock */
sahilmgandhi 18:6a4db94011d3 72 CLOCK_ENABLE(CLOCK_TIMER0);
sahilmgandhi 18:6a4db94011d3 73 /* Enable the timer0 periphery clock */
sahilmgandhi 18:6a4db94011d3 74 CLOCK_ENABLE(CLOCK_TIMER1);
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 /* Timer init */
sahilmgandhi 18:6a4db94011d3 77 /* load timer value */
sahilmgandhi 18:6a4db94011d3 78 TIM0REG->LOAD = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /* set timer prescale 32 (1 us), mode & enable */
sahilmgandhi 18:6a4db94011d3 81 TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 82 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 83 (TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /* Ticker init */
sahilmgandhi 18:6a4db94011d3 86 /* load timer value */
sahilmgandhi 18:6a4db94011d3 87 TIM1REG->LOAD = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /* set timer prescale 32 (1 us), mode & enable */
sahilmgandhi 18:6a4db94011d3 90 TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 91 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /* Register & enable interrupt associated with the timer */
sahilmgandhi 18:6a4db94011d3 94 NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
sahilmgandhi 18:6a4db94011d3 95 NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr);
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /* Clear pending irqs */
sahilmgandhi 18:6a4db94011d3 98 NVIC_ClearPendingIRQ(Tim0_IRQn);
sahilmgandhi 18:6a4db94011d3 99 NVIC_ClearPendingIRQ(Tim1_IRQn);
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /* Setup NVIC for timer */
sahilmgandhi 18:6a4db94011d3 102 NVIC_EnableIRQ(Tim0_IRQn);
sahilmgandhi 18:6a4db94011d3 103 NVIC_EnableIRQ(Tim1_IRQn);
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 us_ticker_inited = 1;
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* Reads 32 bit timer's current value (16 bit s/w timer | 16 bit h/w timer) */
sahilmgandhi 18:6a4db94011d3 109 uint32_t us_ticker_read()
sahilmgandhi 18:6a4db94011d3 110 {
sahilmgandhi 18:6a4db94011d3 111 uint32_t retval, tim0cval;
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 if (!us_ticker_inited) {
sahilmgandhi 18:6a4db94011d3 114 us_timer_init();
sahilmgandhi 18:6a4db94011d3 115 }
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 /* Get the current tick from the hw and sw timers */
sahilmgandhi 18:6a4db94011d3 118 tim0cval = TIM0REG->VALUE; /* read current time */
sahilmgandhi 18:6a4db94011d3 119 retval = (0xFFFF - tim0cval); /* subtract down count */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 NVIC_DisableIRQ(Tim0_IRQn);
sahilmgandhi 18:6a4db94011d3 122 if (TIM0REG->CONTROL.BITS.INT) {
sahilmgandhi 18:6a4db94011d3 123 TIM0REG->CLEAR = 0;
sahilmgandhi 18:6a4db94011d3 124 msb_counter++;
sahilmgandhi 18:6a4db94011d3 125 tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
sahilmgandhi 18:6a4db94011d3 126 retval = (0xFFFF - tim0cval);
sahilmgandhi 18:6a4db94011d3 127 }
sahilmgandhi 18:6a4db94011d3 128 retval |= msb_counter << 16; /* add software bits */
sahilmgandhi 18:6a4db94011d3 129 NVIC_EnableIRQ(Tim0_IRQn);
sahilmgandhi 18:6a4db94011d3 130 return retval;
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 134 * Event Timer
sahilmgandhi 18:6a4db94011d3 135 *
sahilmgandhi 18:6a4db94011d3 136 * Schedules interrupts at given (32bit)us interval of time. It uses TIMER1.
sahilmgandhi 18:6a4db94011d3 137 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
sahilmgandhi 18:6a4db94011d3 138 * which is why a software timer is required to get 32-bit word length.
sahilmgandhi 18:6a4db94011d3 139 *******************************************************************************/
sahilmgandhi 18:6a4db94011d3 140 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /* TImer 1 disbale interrupt */
sahilmgandhi 18:6a4db94011d3 143 void us_ticker_disable_interrupt(void)
sahilmgandhi 18:6a4db94011d3 144 {
sahilmgandhi 18:6a4db94011d3 145 /* Disable the TIMER1 interrupt */
sahilmgandhi 18:6a4db94011d3 146 TIM1REG->CONTROL.BITS.ENABLE = 0x0;
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /* TImer 1 clear interrupt */
sahilmgandhi 18:6a4db94011d3 150 void us_ticker_clear_interrupt(void)
sahilmgandhi 18:6a4db94011d3 151 {
sahilmgandhi 18:6a4db94011d3 152 /* Clear the Ticker (TIMER1) interrupt */
sahilmgandhi 18:6a4db94011d3 153 TIM1REG->CLEAR = 0;
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /* Setting TImer 1 (ticker) */
sahilmgandhi 18:6a4db94011d3 157 inline static void ticker_set(uint32_t count)
sahilmgandhi 18:6a4db94011d3 158 {
sahilmgandhi 18:6a4db94011d3 159 /* Disable TIMER1, load the new value, and re-enable */
sahilmgandhi 18:6a4db94011d3 160 TIM1REG->CONTROL.BITS.ENABLE = 0;
sahilmgandhi 18:6a4db94011d3 161 TIM1REG->LOAD = count;
sahilmgandhi 18:6a4db94011d3 162 TIM1REG->CONTROL.BITS.ENABLE = 1;
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /* TImer 1 - ticker ISR */
sahilmgandhi 18:6a4db94011d3 166 extern void us_ticker_isr(void)
sahilmgandhi 18:6a4db94011d3 167 {
sahilmgandhi 18:6a4db94011d3 168 /* Clear IRQ flag */
sahilmgandhi 18:6a4db94011d3 169 TIM1REG->CLEAR = 0;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 int32_t delta = us_ticker_target - us_ticker_read();
sahilmgandhi 18:6a4db94011d3 172 if (delta <= 0) {
sahilmgandhi 18:6a4db94011d3 173 TIM1REG->CONTROL.BITS.ENABLE = False;
sahilmgandhi 18:6a4db94011d3 174 us_ticker_irq_handler();
sahilmgandhi 18:6a4db94011d3 175 } else {
sahilmgandhi 18:6a4db94011d3 176 // Clamp at max value of timer
sahilmgandhi 18:6a4db94011d3 177 if (delta > 0xFFFF) {
sahilmgandhi 18:6a4db94011d3 178 delta = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 ticker_set(delta);
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /* Set timer 1 ticker interrupt */
sahilmgandhi 18:6a4db94011d3 186 void us_ticker_set_interrupt(timestamp_t timestamp)
sahilmgandhi 18:6a4db94011d3 187 {
sahilmgandhi 18:6a4db94011d3 188 us_ticker_target = (uint32_t)timestamp;
sahilmgandhi 18:6a4db94011d3 189 int32_t delta = us_ticker_target - us_ticker_read();
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 if (delta <= 0) {
sahilmgandhi 18:6a4db94011d3 192 /* This event was in the past */
sahilmgandhi 18:6a4db94011d3 193 //us_ticker_irq_handler();
sahilmgandhi 18:6a4db94011d3 194 // This event was in the past.
sahilmgandhi 18:6a4db94011d3 195 // Set the interrupt as pending, but don't process it here.
sahilmgandhi 18:6a4db94011d3 196 // This prevents a recurive loop under heavy load
sahilmgandhi 18:6a4db94011d3 197 // which can lead to a stack overflow.
sahilmgandhi 18:6a4db94011d3 198 NVIC_SetPendingIRQ(Tim1_IRQn);
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 return;
sahilmgandhi 18:6a4db94011d3 201 }
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 // Clamp at max value of timer
sahilmgandhi 18:6a4db94011d3 204 if (delta > 0xFFFF) {
sahilmgandhi 18:6a4db94011d3 205 delta = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 206 }
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 ticker_set(delta);
sahilmgandhi 18:6a4db94011d3 209 }