MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file spi.c
sahilmgandhi 18:6a4db94011d3 4 * @brief Implementation of a IPC 7207 SPI master driver
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * @version $Rev: $
sahilmgandhi 18:6a4db94011d3 8 * @date $Date: 2016-02-05 $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup spi
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32 #if DEVICE_SPI
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #include "spi.h"
sahilmgandhi 18:6a4db94011d3 35 #include "clock.h"
sahilmgandhi 18:6a4db94011d3 36 #include "objects.h"
sahilmgandhi 18:6a4db94011d3 37 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 38 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 39 #include "spi_ipc7207_map.h"
sahilmgandhi 18:6a4db94011d3 40 #include "crossbar.h"
sahilmgandhi 18:6a4db94011d3 41 #include "pad.h"
sahilmgandhi 18:6a4db94011d3 42 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /** Initializes a spi device.
sahilmgandhi 18:6a4db94011d3 45 * @details
sahilmgandhi 18:6a4db94011d3 46 *
sahilmgandhi 18:6a4db94011d3 47 * @param obj A spi device instance.
sahilmgandhi 18:6a4db94011d3 48 * @param mosi pin to used as SPI MOSI
sahilmgandhi 18:6a4db94011d3 49 * @param miso pin to used as SPI MISO
sahilmgandhi 18:6a4db94011d3 50 * @param sclk pin to used as SPI SCLK
sahilmgandhi 18:6a4db94011d3 51 * @return None
sahilmgandhi 18:6a4db94011d3 52 */
sahilmgandhi 18:6a4db94011d3 53 void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
sahilmgandhi 18:6a4db94011d3 54 {
sahilmgandhi 18:6a4db94011d3 55 uint32_t clockDivisor;
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* determine the SPI to use */
sahilmgandhi 18:6a4db94011d3 58 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 59 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 60 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 61 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 64 SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
sahilmgandhi 18:6a4db94011d3 67 MBED_ASSERT((int)obj->membase != NC);
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /* Check device to be activated */
sahilmgandhi 18:6a4db94011d3 70 if(obj->membase == SPI1REG) {
sahilmgandhi 18:6a4db94011d3 71 /* SPI 1 selected */
sahilmgandhi 18:6a4db94011d3 72 CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */
sahilmgandhi 18:6a4db94011d3 73 } else {
sahilmgandhi 18:6a4db94011d3 74 /* SPI 2 selected */
sahilmgandhi 18:6a4db94011d3 75 CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */
sahilmgandhi 18:6a4db94011d3 76 }
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 CLOCK_ENABLE(CLOCK_CROSSB);
sahilmgandhi 18:6a4db94011d3 79 /* Cross bar setting: Map GPIOs to SPI */
sahilmgandhi 18:6a4db94011d3 80 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 81 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 /* Configure GPIO Direction */
sahilmgandhi 18:6a4db94011d3 84 CLOCK_ENABLE(CLOCK_GPIO);
sahilmgandhi 18:6a4db94011d3 85 GPIOREG->W_OUT |= ((True << sclk) | (True << mosi) | (True << ssel)); /* Set pins as output */
sahilmgandhi 18:6a4db94011d3 86 GPIOREG->W_IN |= (True << miso); /* Set pin as input */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* Pad settings */
sahilmgandhi 18:6a4db94011d3 89 CLOCK_ENABLE(CLOCK_PAD);
sahilmgandhi 18:6a4db94011d3 90 pin_mode(sclk, PushPullPullDown);
sahilmgandhi 18:6a4db94011d3 91 pin_mode(mosi, PushPullPullDown);
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /* PAD drive strength */
sahilmgandhi 18:6a4db94011d3 94 PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE));
sahilmgandhi 18:6a4db94011d3 95 padRegOffset->PADIO0.BITS.POWER = True; /* sclk: Drive strength */
sahilmgandhi 18:6a4db94011d3 96 padRegOffset->PADIO1.BITS.POWER = True; /* mosi: Drive strength */
sahilmgandhi 18:6a4db94011d3 97 if(miso != NC) {
sahilmgandhi 18:6a4db94011d3 98 pinmap_pinout(miso, PinMap_SPI_MISO); /* Cross bar settings */
sahilmgandhi 18:6a4db94011d3 99 pin_mode(miso, OpenDrainNoPull); /* Pad setting */
sahilmgandhi 18:6a4db94011d3 100 padRegOffset->PADIO2.BITS.POWER = True; /* miso: Drive strength */
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102 if(ssel != NC) {
sahilmgandhi 18:6a4db94011d3 103 pinmap_pinout(ssel, PinMap_SPI_SSEL); /* Cross bar settings */
sahilmgandhi 18:6a4db94011d3 104 pin_mode(ssel, PushPullPullUp); /* Pad setting */
sahilmgandhi 18:6a4db94011d3 105 padRegOffset->PADIO3.BITS.POWER = True; /* ssel: Drive strength */
sahilmgandhi 18:6a4db94011d3 106 SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = SPI_SLAVE_SELECT_NORM_BEHAVE; /* Slave select: Normal behavior */
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 CLOCK_DISABLE(CLOCK_PAD);
sahilmgandhi 18:6a4db94011d3 109 CLOCK_DISABLE(CLOCK_GPIO);
sahilmgandhi 18:6a4db94011d3 110 CLOCK_DISABLE(CLOCK_CROSSB);
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /* disable/reset the spi port: Clear control register*/
sahilmgandhi 18:6a4db94011d3 113 obj->membase->CONTROL.WORD = False;
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /* set default baud rate to 1MHz */
sahilmgandhi 18:6a4db94011d3 116 clockDivisor = ((fClockGetPeriphClockfrequency() / SPI_DEFAULT_SPEED) >> True) - True;
sahilmgandhi 18:6a4db94011d3 117 obj->membase->FDIV = clockDivisor;
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/
sahilmgandhi 18:6a4db94011d3 120 obj->membase->TX_WATERMARK = True;
sahilmgandhi 18:6a4db94011d3 121 obj->membase->RX_WATERMARK = True;
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/
sahilmgandhi 18:6a4db94011d3 124 obj->membase->IRQ_ENABLE = False;
sahilmgandhi 18:6a4db94011d3 125 obj->membase->IRQ_CLEAR = SPI_BYTE_MASK; /* Clear all */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 /* configure slave select */
sahilmgandhi 18:6a4db94011d3 128 obj->membase->SLAVE_SELECT.WORD = SPI_SLAVE_SELECT_DEFAULT;
sahilmgandhi 18:6a4db94011d3 129 obj->membase->SLAVE_SELECT_POLARITY = False;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /* Configure control register parameters: 8 bits, master, CPOL = 0, Idle low. CPHA = 0, First transmit occurs before first edge of SCLK. MSB first. Sample incoming data on opposite edge of SCLK from when outgoing data is driven. enable the spi port */
sahilmgandhi 18:6a4db94011d3 132 obj->membase->CONTROL.WORD = SPI_DEFAULT_CONFIG;
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /** Close a spi device.
sahilmgandhi 18:6a4db94011d3 136 * @details
sahilmgandhi 18:6a4db94011d3 137 *
sahilmgandhi 18:6a4db94011d3 138 * @param obj The spi device to close.
sahilmgandhi 18:6a4db94011d3 139 * @return None
sahilmgandhi 18:6a4db94011d3 140 */
sahilmgandhi 18:6a4db94011d3 141 void fSpiClose(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 142 {
sahilmgandhi 18:6a4db94011d3 143 /* disable the spi port */
sahilmgandhi 18:6a4db94011d3 144 obj->membase->CONTROL.BITS.ENABLE = False;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /* disable interruption associated with spi */
sahilmgandhi 18:6a4db94011d3 147 NVIC_DisableIRQ(obj->irq);
sahilmgandhi 18:6a4db94011d3 148 }
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 /**
sahilmgandhi 18:6a4db94011d3 151 * Write data to an SPI device.
sahilmgandhi 18:6a4db94011d3 152 * The data is written from the buffer into the transmit register.
sahilmgandhi 18:6a4db94011d3 153 * This function blocks untill write and read happens.
sahilmgandhi 18:6a4db94011d3 154 *
sahilmgandhi 18:6a4db94011d3 155 * @param obj The device to write to.
sahilmgandhi 18:6a4db94011d3 156 * @param buf The buffer to write from (the contents of the buffer may not be modified).
sahilmgandhi 18:6a4db94011d3 157 * @return the value received during send
sahilmgandhi 18:6a4db94011d3 158 */
sahilmgandhi 18:6a4db94011d3 159 int fSpiWriteB(spi_t *obj, uint32_t const buf)
sahilmgandhi 18:6a4db94011d3 160 {
sahilmgandhi 18:6a4db94011d3 161 int byte;
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
sahilmgandhi 18:6a4db94011d3 164 obj->membase->TX_DATA = buf;
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
sahilmgandhi 18:6a4db94011d3 167 byte = obj->membase->RX_DATA;
sahilmgandhi 18:6a4db94011d3 168 return byte;
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 #endif /* DEVICE_SPI */