MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file i2c.c
sahilmgandhi 18:6a4db94011d3 4 * @brief I2C driver
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2016-04-12 $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup i2c
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 * <h1> Reference document(s) </h1>
sahilmgandhi 18:6a4db94011d3 32 * <p>
sahilmgandhi 18:6a4db94011d3 33 * IPC7208 APB I2C Master Design Specification v1.3
sahilmgandhi 18:6a4db94011d3 34 * </p>
sahilmgandhi 18:6a4db94011d3 35 * The I2C bus is an industry-standard two-wire (clock and data) serial communication bus between master(initiator) and slave device.
sahilmgandhi 18:6a4db94011d3 36 * Within the procedure of the I2C-bus, unique situations arise which are defined as START and STOP conditions .A HIGH to LOW transition on
sahilmgandhi 18:6a4db94011d3 37 * the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.A LOW to HIGH transition on the
sahilmgandhi 18:6a4db94011d3 38 * SDA line while SCL is HIGH defines a STOP condition.START and STOP conditions are always generated by the master. The bus is considered
sahilmgandhi 18:6a4db94011d3 39 * to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.
sahilmgandhi 18:6a4db94011d3 40 * A master may start a transfer only if the bus is free. Two or more masters may generate a START condition.
sahilmgandhi 18:6a4db94011d3 41 * Every byte put on the SDA line must be 8-bits long.Each byte has to be followed by an acknowledge bit.
sahilmgandhi 18:6a4db94011d3 42 * This APB(Advanced peripheral bus) I2C Master is an APB Slave peripheral that can also serves as an I2C bus Master. The Command register
sahilmgandhi 18:6a4db94011d3 43 * is the programming interface to the I2C Engine. The commands arrive at the I2C Engine via the Command FIFO,so the first valid command
sahilmgandhi 18:6a4db94011d3 44 * that is written to the Command register is the first I2C instruction implemented on the I2C bus.Because the command interface provides
sahilmgandhi 18:6a4db94011d3 45 * the basic building blocks for any I2C transaction, access to a wide range of I2C slave devices is supported.
sahilmgandhi 18:6a4db94011d3 46 * I2C can be enabled by setting bit 7 of the control register .
sahilmgandhi 18:6a4db94011d3 47 * There is a generated clock (a divided version of the APB clock) in this module that may be used as the I2C System Clock.
sahilmgandhi 18:6a4db94011d3 48 * There are two FIFO in the I2C; Command FIFO and Read data FIFO
sahilmgandhi 18:6a4db94011d3 49 * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO.
sahilmgandhi 18:6a4db94011d3 50 * if the command FIFO is empty , up to 32 commands can be written to the command interface , it is programmer's responsibility to keep
sahilmgandhi 18:6a4db94011d3 51 * the track of command FIFO's status either by interrupt or by polling method by reading status register, which represents Operational
sahilmgandhi 18:6a4db94011d3 52 * Status of the I2C Module and its sub-modules.The action from the processor may be necessary after reading the status register.Reading
sahilmgandhi 18:6a4db94011d3 53 * the Status register clears the blkInt Interrupt signal.Read data FIFO is where data read by the processor from I2C slave is placed .
sahilmgandhi 18:6a4db94011d3 54 *
sahilmgandhi 18:6a4db94011d3 55 *
sahilmgandhi 18:6a4db94011d3 56 * <h1> Functional description (internal) </h1>
sahilmgandhi 18:6a4db94011d3 57 * <p>
sahilmgandhi 18:6a4db94011d3 58 *
sahilmgandhi 18:6a4db94011d3 59 * </p>
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61 #if DEVICE_I2C
sahilmgandhi 18:6a4db94011d3 62 #include "i2c.h"
sahilmgandhi 18:6a4db94011d3 63 #include "mbed_wait_api.h"
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /* See i2c.h for details */
sahilmgandhi 18:6a4db94011d3 66 void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
sahilmgandhi 18:6a4db94011d3 67 {
sahilmgandhi 18:6a4db94011d3 68 uint32_t clockDivisor;
sahilmgandhi 18:6a4db94011d3 69 /* determine the I2C to use */
sahilmgandhi 18:6a4db94011d3 70 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 71 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 72 obj->membase = (I2cIpc7208Reg_pt)pinmap_merge(i2c_sda, i2c_scl);
sahilmgandhi 18:6a4db94011d3 73 MBED_ASSERT((int)obj->membase != NC);
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /* By default disbale interrupts */
sahilmgandhi 18:6a4db94011d3 76 obj->membase->IER.WORD = False;
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /* enable interrupt associated with the device */
sahilmgandhi 18:6a4db94011d3 79 if(obj->membase == I2C1REG) {
sahilmgandhi 18:6a4db94011d3 80 CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
sahilmgandhi 18:6a4db94011d3 81 NVIC_ClearPendingIRQ(I2C_IRQn);
sahilmgandhi 18:6a4db94011d3 82 NVIC_EnableIRQ(I2C_IRQn);
sahilmgandhi 18:6a4db94011d3 83 } else {
sahilmgandhi 18:6a4db94011d3 84 CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
sahilmgandhi 18:6a4db94011d3 85 NVIC_ClearPendingIRQ(I2C2_IRQn);
sahilmgandhi 18:6a4db94011d3 86 NVIC_EnableIRQ(I2C2_IRQn);
sahilmgandhi 18:6a4db94011d3 87 }
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /*select I2C clock source */
sahilmgandhi 18:6a4db94011d3 90 obj->membase->CR.BITS.I2C_CLK_SRC = True;
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /* enable I2C clock divider */
sahilmgandhi 18:6a4db94011d3 93 obj->membase->CR.BITS.I2C_APB_CD_EN = True;
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /* set default baud rate at 100k */
sahilmgandhi 18:6a4db94011d3 96 clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
sahilmgandhi 18:6a4db94011d3 97 obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
sahilmgandhi 18:6a4db94011d3 98 obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* Cross bar setting */
sahilmgandhi 18:6a4db94011d3 101 pinmap_pinout(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 102 pinmap_pinout(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /*Enable open drain & pull up for sda & scl pin */
sahilmgandhi 18:6a4db94011d3 105 pin_mode(sda, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 106 pin_mode(scl, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* PAD drive strength */
sahilmgandhi 18:6a4db94011d3 109 PadReg_t *padRegSda = (PadReg_t*)(PADREG_BASE + (sda * PAD_REG_ADRS_BYTE_SIZE));
sahilmgandhi 18:6a4db94011d3 110 PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 CLOCK_ENABLE(CLOCK_PAD);
sahilmgandhi 18:6a4db94011d3 113 padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
sahilmgandhi 18:6a4db94011d3 114 padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
sahilmgandhi 18:6a4db94011d3 115 CLOCK_DISABLE(CLOCK_PAD);
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 CLOCK_ENABLE(CLOCK_GPIO);
sahilmgandhi 18:6a4db94011d3 118 GPIOREG->W_OUT |= ((True << sda) | (True << scl));
sahilmgandhi 18:6a4db94011d3 119 CLOCK_DISABLE(CLOCK_GPIO);
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Enable i2c module */
sahilmgandhi 18:6a4db94011d3 122 obj->membase->CR.BITS.I2C_MODULE_EN = True;
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /* See i2c.h for details */
sahilmgandhi 18:6a4db94011d3 126 void fI2cFrequency(i2c_t *obj, uint32_t hz)
sahilmgandhi 18:6a4db94011d3 127 {
sahilmgandhi 18:6a4db94011d3 128 /* Set user baud rate */
sahilmgandhi 18:6a4db94011d3 129 uint32_t clockDivisor;
sahilmgandhi 18:6a4db94011d3 130 clockDivisor = ((fClockGetPeriphClockfrequency() / hz) >> 2) - 2;
sahilmgandhi 18:6a4db94011d3 131 obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
sahilmgandhi 18:6a4db94011d3 132 obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /* See i2c.h for details */
sahilmgandhi 18:6a4db94011d3 136 int32_t fI2cStart(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 137 {
sahilmgandhi 18:6a4db94011d3 138 /* Send start bit */
sahilmgandhi 18:6a4db94011d3 139 SEND_COMMAND(I2C_CMD_START);
sahilmgandhi 18:6a4db94011d3 140 return I2C_API_STATUS_SUCCESS;
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 /* See i2c.h for details */
sahilmgandhi 18:6a4db94011d3 144 int32_t fI2cStop(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 145 {
sahilmgandhi 18:6a4db94011d3 146 /* Send stop bit */
sahilmgandhi 18:6a4db94011d3 147 SEND_COMMAND(I2C_CMD_STOP);
sahilmgandhi 18:6a4db94011d3 148 if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT |
sahilmgandhi 18:6a4db94011d3 149 I2C_STATUS_CMD_FIFO_OFL_BIT |
sahilmgandhi 18:6a4db94011d3 150 I2C_STATUS_BUS_ERR_BIT)) {
sahilmgandhi 18:6a4db94011d3 151 /* I2c error occured */
sahilmgandhi 18:6a4db94011d3 152 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154 return I2C_API_STATUS_SUCCESS;
sahilmgandhi 18:6a4db94011d3 155 }
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /* See i2c.h for details */
sahilmgandhi 18:6a4db94011d3 158 int32_t fI2cReadB(i2c_t *obj, char *buf, int len)
sahilmgandhi 18:6a4db94011d3 159 {
sahilmgandhi 18:6a4db94011d3 160 int32_t read = 0;
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 while (read < len) {
sahilmgandhi 18:6a4db94011d3 163 /* Send read command */
sahilmgandhi 18:6a4db94011d3 164 SEND_COMMAND(I2C_CMD_RDAT8);
sahilmgandhi 18:6a4db94011d3 165 while(!RD_DATA_READY) {
sahilmgandhi 18:6a4db94011d3 166 if (I2C_BUS_ERR_CHECK) {
sahilmgandhi 18:6a4db94011d3 167 /* Bus error occured */
sahilmgandhi 18:6a4db94011d3 168 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171 buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */
sahilmgandhi 18:6a4db94011d3 174 SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */
sahilmgandhi 18:6a4db94011d3 175 } else {
sahilmgandhi 18:6a4db94011d3 176 /* No ack */
sahilmgandhi 18:6a4db94011d3 177 SEND_COMMAND(I2C_CMD_WDAT1);
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 /* check for FIFO underflow */
sahilmgandhi 18:6a4db94011d3 181 if(I2C_UFL_CHECK) {
sahilmgandhi 18:6a4db94011d3 182 return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184 if(I2C_BUS_ERR_CHECK) {
sahilmgandhi 18:6a4db94011d3 185 /* Bus error */
sahilmgandhi 18:6a4db94011d3 186 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 187 }
sahilmgandhi 18:6a4db94011d3 188 }
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 return read;
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /* See i2c.h for details */
sahilmgandhi 18:6a4db94011d3 194 int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len)
sahilmgandhi 18:6a4db94011d3 195 {
sahilmgandhi 18:6a4db94011d3 196 int32_t write = 0;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 while (write < len) {
sahilmgandhi 18:6a4db94011d3 199 /* Send write command */
sahilmgandhi 18:6a4db94011d3 200 SEND_COMMAND(I2C_CMD_WDAT8);
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 if(buf[write] == I2C_CMD_RDAT8) {
sahilmgandhi 18:6a4db94011d3 203 /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
sahilmgandhi 18:6a4db94011d3 204 then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a
sahilmgandhi 18:6a4db94011d3 205 RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
sahilmgandhi 18:6a4db94011d3 206 /* Send 0x13 bit wise */
sahilmgandhi 18:6a4db94011d3 207 SEND_COMMAND(I2C_CMD_WDAT0);
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 SEND_COMMAND(I2C_CMD_WDAT0);
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 SEND_COMMAND(I2C_CMD_WDAT0);
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 SEND_COMMAND(I2C_CMD_WDAT1);
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 SEND_COMMAND(I2C_CMD_WDAT0);
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 SEND_COMMAND(I2C_CMD_WDAT0);
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 SEND_COMMAND(I2C_CMD_WDAT1);
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 SEND_COMMAND(I2C_CMD_WDAT1);
sahilmgandhi 18:6a4db94011d3 222 } else {
sahilmgandhi 18:6a4db94011d3 223 /* Send data */
sahilmgandhi 18:6a4db94011d3 224 SEND_COMMAND(buf[write++]);
sahilmgandhi 18:6a4db94011d3 225 }
sahilmgandhi 18:6a4db94011d3 226 SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 if (I2C_BUS_ERR_CHECK) {
sahilmgandhi 18:6a4db94011d3 229 /* Bus error */
sahilmgandhi 18:6a4db94011d3 230 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
sahilmgandhi 18:6a4db94011d3 234 }
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 return write;
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 #endif /* DEVICE_I2C */