Mouse code for the MacroRat
mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file cmsis_nvic.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @brief Contains relocatable exception table. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @internal |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @author ON Semiconductor. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * $Rev: 0.1 $ |
sahilmgandhi | 18:6a4db94011d3 | 8 | * $Date: 2015-11-06 $ |
sahilmgandhi | 18:6a4db94011d3 | 9 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). |
sahilmgandhi | 18:6a4db94011d3 | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
sahilmgandhi | 18:6a4db94011d3 | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
sahilmgandhi | 18:6a4db94011d3 | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
sahilmgandhi | 18:6a4db94011d3 | 14 | * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and |
sahilmgandhi | 18:6a4db94011d3 | 15 | * if applicable the software license agreement. Do not use this software and/or |
sahilmgandhi | 18:6a4db94011d3 | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
sahilmgandhi | 18:6a4db94011d3 | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
sahilmgandhi | 18:6a4db94011d3 | 18 | * terms and conditions. |
sahilmgandhi | 18:6a4db94011d3 | 19 | * |
sahilmgandhi | 18:6a4db94011d3 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
sahilmgandhi | 18:6a4db94011d3 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
sahilmgandhi | 18:6a4db94011d3 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
sahilmgandhi | 18:6a4db94011d3 | 25 | * @endinternal |
sahilmgandhi | 18:6a4db94011d3 | 26 | * |
sahilmgandhi | 18:6a4db94011d3 | 27 | * @ingroup |
sahilmgandhi | 18:6a4db94011d3 | 28 | * |
sahilmgandhi | 18:6a4db94011d3 | 29 | * @details |
sahilmgandhi | 18:6a4db94011d3 | 30 | */ |
sahilmgandhi | 18:6a4db94011d3 | 31 | |
sahilmgandhi | 18:6a4db94011d3 | 32 | #include <cmsis_nvic.h> |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM |
sahilmgandhi | 18:6a4db94011d3 | 35 | #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
sahilmgandhi | 18:6a4db94011d3 | 39 | { |
sahilmgandhi | 18:6a4db94011d3 | 40 | static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | vectors[IRQn + 16] = vector; |
sahilmgandhi | 18:6a4db94011d3 | 43 | } |