MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file clock_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief CLOCK hw module register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 2848 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup clock
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #ifndef CLOCK_MAP_H_
sahilmgandhi 18:6a4db94011d3 33 #define CLOCK_MAP_H_
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 36 * *
sahilmgandhi 18:6a4db94011d3 37 * Header files *
sahilmgandhi 18:6a4db94011d3 38 * *
sahilmgandhi 18:6a4db94011d3 39 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 /**************************************************************************************************
sahilmgandhi 18:6a4db94011d3 44 * *
sahilmgandhi 18:6a4db94011d3 45 * Type definitions *
sahilmgandhi 18:6a4db94011d3 46 * *
sahilmgandhi 18:6a4db94011d3 47 **************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** Clock control HW structure overlay */
sahilmgandhi 18:6a4db94011d3 50 typedef struct {
sahilmgandhi 18:6a4db94011d3 51 union {
sahilmgandhi 18:6a4db94011d3 52 struct {
sahilmgandhi 18:6a4db94011d3 53 __IO uint32_t OSC_SEL:1;
sahilmgandhi 18:6a4db94011d3 54 __IO uint32_t PAD0:1;
sahilmgandhi 18:6a4db94011d3 55 __IO uint32_t CAL32K:1;
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t CAL32M:1;
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t RTCEN:1;
sahilmgandhi 18:6a4db94011d3 58 } BITS;
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 60 } CCR; /**< 0x4001B000 Clock control register */
sahilmgandhi 18:6a4db94011d3 61 union {
sahilmgandhi 18:6a4db94011d3 62 struct {
sahilmgandhi 18:6a4db94011d3 63 __I uint32_t XTAL32M:1;
sahilmgandhi 18:6a4db94011d3 64 __I uint32_t XTAL32K:1;
sahilmgandhi 18:6a4db94011d3 65 __I uint32_t CAL32K:1;
sahilmgandhi 18:6a4db94011d3 66 __I uint32_t DONE32K:1;
sahilmgandhi 18:6a4db94011d3 67 __I uint32_t CAL32MFAIL:1;
sahilmgandhi 18:6a4db94011d3 68 __I uint32_t CAL32MDONE:1;
sahilmgandhi 18:6a4db94011d3 69 } BITS;
sahilmgandhi 18:6a4db94011d3 70 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 71 } CSR; /**< 0x4001B004 Clock status register */
sahilmgandhi 18:6a4db94011d3 72 union {
sahilmgandhi 18:6a4db94011d3 73 struct {
sahilmgandhi 18:6a4db94011d3 74 __IO uint32_t IE32K:1;
sahilmgandhi 18:6a4db94011d3 75 __IO uint32_t IE32M:1;
sahilmgandhi 18:6a4db94011d3 76 } BITS;
sahilmgandhi 18:6a4db94011d3 77 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 78 } IER; /**< 0x4001B008 Interrup enable register */
sahilmgandhi 18:6a4db94011d3 79 __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
sahilmgandhi 18:6a4db94011d3 80 union {
sahilmgandhi 18:6a4db94011d3 81 struct {
sahilmgandhi 18:6a4db94011d3 82 __IO uint32_t TIMER0:1;
sahilmgandhi 18:6a4db94011d3 83 __IO uint32_t TIMER1:1;
sahilmgandhi 18:6a4db94011d3 84 __IO uint32_t TIMER2:1;
sahilmgandhi 18:6a4db94011d3 85 __IO uint32_t PAD0:2;
sahilmgandhi 18:6a4db94011d3 86 __IO uint32_t UART1:1;
sahilmgandhi 18:6a4db94011d3 87 __IO uint32_t SPI:1;
sahilmgandhi 18:6a4db94011d3 88 __IO uint32_t I2C:1;
sahilmgandhi 18:6a4db94011d3 89 __IO uint32_t UART2:1;
sahilmgandhi 18:6a4db94011d3 90 __IO uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 91 __IO uint32_t WDOG:1;
sahilmgandhi 18:6a4db94011d3 92 __IO uint32_t PWM:1;
sahilmgandhi 18:6a4db94011d3 93 __IO uint32_t GPIO:1;
sahilmgandhi 18:6a4db94011d3 94 __IO uint32_t PAD2:2;
sahilmgandhi 18:6a4db94011d3 95 __IO uint32_t RTC:1;
sahilmgandhi 18:6a4db94011d3 96 __IO uint32_t XBAR:1;
sahilmgandhi 18:6a4db94011d3 97 __IO uint32_t RAND:1;
sahilmgandhi 18:6a4db94011d3 98 __IO uint32_t PAD3:2;
sahilmgandhi 18:6a4db94011d3 99 __IO uint32_t MACHW:1;
sahilmgandhi 18:6a4db94011d3 100 __IO uint32_t ADC:1;
sahilmgandhi 18:6a4db94011d3 101 __IO uint32_t AES:1;
sahilmgandhi 18:6a4db94011d3 102 __IO uint32_t FLASH:1;
sahilmgandhi 18:6a4db94011d3 103 __IO uint32_t PAD4:1;
sahilmgandhi 18:6a4db94011d3 104 __IO uint32_t RFANA:1;
sahilmgandhi 18:6a4db94011d3 105 __IO uint32_t IO:1;
sahilmgandhi 18:6a4db94011d3 106 __IO uint32_t PAD5:1;
sahilmgandhi 18:6a4db94011d3 107 __IO uint32_t PAD:1;
sahilmgandhi 18:6a4db94011d3 108 __IO uint32_t PMU:1;
sahilmgandhi 18:6a4db94011d3 109 __IO uint32_t PAD6:1;
sahilmgandhi 18:6a4db94011d3 110 __IO uint32_t TEST:1;
sahilmgandhi 18:6a4db94011d3 111 } BITS;
sahilmgandhi 18:6a4db94011d3 112 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 113 } PDIS; /**< 0x4001B010 Periphery disable */
sahilmgandhi 18:6a4db94011d3 114 __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
sahilmgandhi 18:6a4db94011d3 115 __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
sahilmgandhi 18:6a4db94011d3 116 __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
sahilmgandhi 18:6a4db94011d3 117 __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
sahilmgandhi 18:6a4db94011d3 118 __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
sahilmgandhi 18:6a4db94011d3 119 union {
sahilmgandhi 18:6a4db94011d3 120 struct {
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t BOOST :2; /* Boost done signal tap control */
sahilmgandhi 18:6a4db94011d3 123 __IO uint32_t READY :2; /* Ready signal tap control */
sahilmgandhi 18:6a4db94011d3 124 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
sahilmgandhi 18:6a4db94011d3 125 __IO uint32_t PAD :20; /* Unused bits */
sahilmgandhi 18:6a4db94011d3 126 } BITS;
sahilmgandhi 18:6a4db94011d3 127 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 128 } TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 union {
sahilmgandhi 18:6a4db94011d3 131 struct {
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t BOOST :2; /* Boost done signal tap control */
sahilmgandhi 18:6a4db94011d3 134 __IO uint32_t READY :2; /* Ready signal tap control */
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
sahilmgandhi 18:6a4db94011d3 136 __IO uint32_t PAD :20; /* Unused bits */
sahilmgandhi 18:6a4db94011d3 137 } BITS;
sahilmgandhi 18:6a4db94011d3 138 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 139 } TRIM_32K_EXT;
sahilmgandhi 18:6a4db94011d3 140 union {
sahilmgandhi 18:6a4db94011d3 141 struct {
sahilmgandhi 18:6a4db94011d3 142 __IO uint32_t OV32M;
sahilmgandhi 18:6a4db94011d3 143 __IO uint32_t EN32M;
sahilmgandhi 18:6a4db94011d3 144 __IO uint32_t OV32K;
sahilmgandhi 18:6a4db94011d3 145 __IO uint32_t EN32K;
sahilmgandhi 18:6a4db94011d3 146 } BITS;
sahilmgandhi 18:6a4db94011d3 147 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 148 } CER; /**< 0x4001B038 clock enable register*/
sahilmgandhi 18:6a4db94011d3 149 } ClockReg_t, *ClockReg_pt;
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #endif /* CLOCK_MAP_H_ */