MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/system_LPC8xx.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * @file: system_LPC8xx.c
sahilmgandhi 18:6a4db94011d3 3 * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
sahilmgandhi 18:6a4db94011d3 4 * for the NXP LPC8xx Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version: V1.0
sahilmgandhi 18:6a4db94011d3 6 * @date: 16. Aug. 2012
sahilmgandhi 18:6a4db94011d3 7 *----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2012 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
sahilmgandhi 18:6a4db94011d3 12 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 13 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 22 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 23 #include "LPC82x.h"
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /*
sahilmgandhi 18:6a4db94011d3 26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 27 */
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /*--------------------- Clock Configuration ----------------------------------*/
sahilmgandhi 18:6a4db94011d3 30 //
sahilmgandhi 18:6a4db94011d3 31 // <e> Clock Configuration
sahilmgandhi 18:6a4db94011d3 32 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 33 // <h> System Oscillator Control Register (SYSOSCCTRL)
sahilmgandhi 18:6a4db94011d3 34 // <o.0> BYPASS: System Oscillator Bypass Enable
sahilmgandhi 18:6a4db94011d3 35 // <i> If enabled then PLL input (sys_osc_clk) is fed
sahilmgandhi 18:6a4db94011d3 36 // <i> directly from XTALIN and XTALOUT pins.
sahilmgandhi 18:6a4db94011d3 37 // <o.1> FREQRANGE: System Oscillator Frequency Range
sahilmgandhi 18:6a4db94011d3 38 // <i> Determines frequency range for Low-power oscillator.
sahilmgandhi 18:6a4db94011d3 39 // <0=> 1 - 20 MHz
sahilmgandhi 18:6a4db94011d3 40 // <1=> 15 - 25 MHz
sahilmgandhi 18:6a4db94011d3 41 // </h>
sahilmgandhi 18:6a4db94011d3 42 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 43 //
sahilmgandhi 18:6a4db94011d3 44 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
sahilmgandhi 18:6a4db94011d3 45 // <o.0..4> DIVSEL: Select Divider for Fclkana
sahilmgandhi 18:6a4db94011d3 46 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
sahilmgandhi 18:6a4db94011d3 47 // <0-31>
sahilmgandhi 18:6a4db94011d3 48 // <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
sahilmgandhi 18:6a4db94011d3 49 // <0=> Undefined
sahilmgandhi 18:6a4db94011d3 50 // <1=> 0.6 MHz
sahilmgandhi 18:6a4db94011d3 51 // <2=> 1.05 MHz
sahilmgandhi 18:6a4db94011d3 52 // <3=> 1.4 MHz
sahilmgandhi 18:6a4db94011d3 53 // <4=> 1.75 MHz
sahilmgandhi 18:6a4db94011d3 54 // <5=> 2.1 MHz
sahilmgandhi 18:6a4db94011d3 55 // <6=> 2.4 MHz
sahilmgandhi 18:6a4db94011d3 56 // <7=> 2.7 MHz
sahilmgandhi 18:6a4db94011d3 57 // <8=> 3.0 MHz
sahilmgandhi 18:6a4db94011d3 58 // <9=> 3.25 MHz
sahilmgandhi 18:6a4db94011d3 59 // <10=> 3.5 MHz
sahilmgandhi 18:6a4db94011d3 60 // <11=> 3.75 MHz
sahilmgandhi 18:6a4db94011d3 61 // <12=> 4.0 MHz
sahilmgandhi 18:6a4db94011d3 62 // <13=> 4.2 MHz
sahilmgandhi 18:6a4db94011d3 63 // <14=> 4.4 MHz
sahilmgandhi 18:6a4db94011d3 64 // <15=> 4.6 MHz
sahilmgandhi 18:6a4db94011d3 65 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 66 // </h>
sahilmgandhi 18:6a4db94011d3 67 // <h> System PLL Control Register (SYSPLLCTRL)
sahilmgandhi 18:6a4db94011d3 68 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 69 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 70 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 71 // <o.0..4> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 72 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 73 // <0-31>
sahilmgandhi 18:6a4db94011d3 74 // <o.5..6> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 75 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 76 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 77 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 78 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 79 // </h>
sahilmgandhi 18:6a4db94011d3 80 #define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 81 //
sahilmgandhi 18:6a4db94011d3 82 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
sahilmgandhi 18:6a4db94011d3 83 // <o.0..1> SEL: System PLL Clock Source
sahilmgandhi 18:6a4db94011d3 84 // <0=> IRC
sahilmgandhi 18:6a4db94011d3 85 // <1=> Crystal Oscillator
sahilmgandhi 18:6a4db94011d3 86 // <2=> Reserved
sahilmgandhi 18:6a4db94011d3 87 // <3=> CLKIN. External clock input.
sahilmgandhi 18:6a4db94011d3 88 // </h>
sahilmgandhi 18:6a4db94011d3 89 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 90 //
sahilmgandhi 18:6a4db94011d3 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
sahilmgandhi 18:6a4db94011d3 92 // <o.0..1> SEL: Clock Source for Main Clock
sahilmgandhi 18:6a4db94011d3 93 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 94 // <1=> PLL input
sahilmgandhi 18:6a4db94011d3 95 // <2=> Watchdog Oscillator
sahilmgandhi 18:6a4db94011d3 96 // <3=> PLL output
sahilmgandhi 18:6a4db94011d3 97 // </h>
sahilmgandhi 18:6a4db94011d3 98 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
sahilmgandhi 18:6a4db94011d3 100 // <o.0..7> DIV: System AHB Clock Divider
sahilmgandhi 18:6a4db94011d3 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
sahilmgandhi 18:6a4db94011d3 102 // <i> 0 = is disabled
sahilmgandhi 18:6a4db94011d3 103 // <0-255>
sahilmgandhi 18:6a4db94011d3 104 // </h>
sahilmgandhi 18:6a4db94011d3 105 #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
sahilmgandhi 18:6a4db94011d3 106 // </e>
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 //#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /*
sahilmgandhi 18:6a4db94011d3 111 #if (CLOCK_SETUP == 0)
sahilmgandhi 18:6a4db94011d3 112 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 113 #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 114 #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 115 #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 116 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 117 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
sahilmgandhi 18:6a4db94011d3 118 #elif (CLOCK_SETUP == 2)
sahilmgandhi 18:6a4db94011d3 119 // #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 120 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 121 #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 122 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 123 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 124 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
sahilmgandhi 18:6a4db94011d3 125 #endif
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /*
sahilmgandhi 18:6a4db94011d3 129 //-------- <<< end of configuration section >>> ------------------------------
sahilmgandhi 18:6a4db94011d3 130 */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 133 Check the register settings
sahilmgandhi 18:6a4db94011d3 134 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 135 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
sahilmgandhi 18:6a4db94011d3 136 #define CHECK_RSVD(val, mask) (val & mask)
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /* Clock Configuration -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 139 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 140 #error "SYSOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 141 #endif
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 144 #error "WDTOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
sahilmgandhi 18:6a4db94011d3 148 #error "SYSPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 149 #endif
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 152 #error "SYSPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 153 #endif
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 156 #error "MAINCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 157 #endif
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
sahilmgandhi 18:6a4db94011d3 160 #error "SYSAHBCLKDIV: Value out of range!"
sahilmgandhi 18:6a4db94011d3 161 #endif
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 165 DEFINES
sahilmgandhi 18:6a4db94011d3 166 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 169 Define clocks
sahilmgandhi 18:6a4db94011d3 170 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 171 #define __XTAL (12000000UL) /* Oscillator frequency */
sahilmgandhi 18:6a4db94011d3 172 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
sahilmgandhi 18:6a4db94011d3 173 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 174 #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
sahilmgandhi 18:6a4db94011d3 178 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 181 #if (__FREQSEL == 0)
sahilmgandhi 18:6a4db94011d3 182 #define __WDT_OSC_CLK ( 0) /* undefined */
sahilmgandhi 18:6a4db94011d3 183 #elif (__FREQSEL == 1)
sahilmgandhi 18:6a4db94011d3 184 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 185 #elif (__FREQSEL == 2)
sahilmgandhi 18:6a4db94011d3 186 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 187 #elif (__FREQSEL == 3)
sahilmgandhi 18:6a4db94011d3 188 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 189 #elif (__FREQSEL == 4)
sahilmgandhi 18:6a4db94011d3 190 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 191 #elif (__FREQSEL == 5)
sahilmgandhi 18:6a4db94011d3 192 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 193 #elif (__FREQSEL == 6)
sahilmgandhi 18:6a4db94011d3 194 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 195 #elif (__FREQSEL == 7)
sahilmgandhi 18:6a4db94011d3 196 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 197 #elif (__FREQSEL == 8)
sahilmgandhi 18:6a4db94011d3 198 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 199 #elif (__FREQSEL == 9)
sahilmgandhi 18:6a4db94011d3 200 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 201 #elif (__FREQSEL == 10)
sahilmgandhi 18:6a4db94011d3 202 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 203 #elif (__FREQSEL == 11)
sahilmgandhi 18:6a4db94011d3 204 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 205 #elif (__FREQSEL == 12)
sahilmgandhi 18:6a4db94011d3 206 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 207 #elif (__FREQSEL == 13)
sahilmgandhi 18:6a4db94011d3 208 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 209 #elif (__FREQSEL == 14)
sahilmgandhi 18:6a4db94011d3 210 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 211 #else
sahilmgandhi 18:6a4db94011d3 212 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 213 #endif
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /* sys_pllclkin calculation */
sahilmgandhi 18:6a4db94011d3 216 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 217 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 218 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 219 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 220 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 221 #define __SYS_PLLCLKIN (__CLKIN_CLK)
sahilmgandhi 18:6a4db94011d3 222 #else
sahilmgandhi 18:6a4db94011d3 223 #define __SYS_PLLCLKIN (0)
sahilmgandhi 18:6a4db94011d3 224 #endif
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /* main clock calculation */
sahilmgandhi 18:6a4db94011d3 229 #if ((MAINCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 230 #define __MAIN_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 231 #elif ((MAINCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 232 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
sahilmgandhi 18:6a4db94011d3 233 #elif ((MAINCLKSEL_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 234 #if (__FREQSEL == 0)
sahilmgandhi 18:6a4db94011d3 235 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
sahilmgandhi 18:6a4db94011d3 236 #else
sahilmgandhi 18:6a4db94011d3 237 #define __MAIN_CLOCK (__WDT_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 238 #endif
sahilmgandhi 18:6a4db94011d3 239 #elif ((MAINCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 240 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
sahilmgandhi 18:6a4db94011d3 241 #else
sahilmgandhi 18:6a4db94011d3 242 #define __MAIN_CLOCK (0)
sahilmgandhi 18:6a4db94011d3 243 #endif
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 #else
sahilmgandhi 18:6a4db94011d3 248 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 249 #endif // CLOCK_SETUP
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 253 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 254 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 255 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 256 uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 259 Clock functions
sahilmgandhi 18:6a4db94011d3 260 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 261 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 262 {
sahilmgandhi 18:6a4db94011d3 263 uint32_t wdt_osc = 0;
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 266 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
sahilmgandhi 18:6a4db94011d3 267 case 0: wdt_osc = 0; break;
sahilmgandhi 18:6a4db94011d3 268 case 1: wdt_osc = 500000; break;
sahilmgandhi 18:6a4db94011d3 269 case 2: wdt_osc = 800000; break;
sahilmgandhi 18:6a4db94011d3 270 case 3: wdt_osc = 1100000; break;
sahilmgandhi 18:6a4db94011d3 271 case 4: wdt_osc = 1400000; break;
sahilmgandhi 18:6a4db94011d3 272 case 5: wdt_osc = 1600000; break;
sahilmgandhi 18:6a4db94011d3 273 case 6: wdt_osc = 1800000; break;
sahilmgandhi 18:6a4db94011d3 274 case 7: wdt_osc = 2000000; break;
sahilmgandhi 18:6a4db94011d3 275 case 8: wdt_osc = 2200000; break;
sahilmgandhi 18:6a4db94011d3 276 case 9: wdt_osc = 2400000; break;
sahilmgandhi 18:6a4db94011d3 277 case 10: wdt_osc = 2600000; break;
sahilmgandhi 18:6a4db94011d3 278 case 11: wdt_osc = 2700000; break;
sahilmgandhi 18:6a4db94011d3 279 case 12: wdt_osc = 2900000; break;
sahilmgandhi 18:6a4db94011d3 280 case 13: wdt_osc = 3100000; break;
sahilmgandhi 18:6a4db94011d3 281 case 14: wdt_osc = 3200000; break;
sahilmgandhi 18:6a4db94011d3 282 case 15: wdt_osc = 3400000; break;
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 287 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 288 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 289 break;
sahilmgandhi 18:6a4db94011d3 290 case 1: /* Input Clock to System PLL */
sahilmgandhi 18:6a4db94011d3 291 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 292 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 293 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 294 break;
sahilmgandhi 18:6a4db94011d3 295 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 296 SystemCoreClock = __SYS_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 297 break;
sahilmgandhi 18:6a4db94011d3 298 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 299 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 300 break;
sahilmgandhi 18:6a4db94011d3 301 case 3: /* CLKIN pin */
sahilmgandhi 18:6a4db94011d3 302 SystemCoreClock = __CLKIN_CLK;
sahilmgandhi 18:6a4db94011d3 303 break;
sahilmgandhi 18:6a4db94011d3 304 }
sahilmgandhi 18:6a4db94011d3 305 break;
sahilmgandhi 18:6a4db94011d3 306 case 2: /* WDT Oscillator */
sahilmgandhi 18:6a4db94011d3 307 SystemCoreClock = wdt_osc;
sahilmgandhi 18:6a4db94011d3 308 break;
sahilmgandhi 18:6a4db94011d3 309 case 3: /* System PLL Clock Out */
sahilmgandhi 18:6a4db94011d3 310 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 311 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 312 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 313 break;
sahilmgandhi 18:6a4db94011d3 314 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 315 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 316 break;
sahilmgandhi 18:6a4db94011d3 317 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 318 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 319 break;
sahilmgandhi 18:6a4db94011d3 320 case 3: /* CLKIN pin */
sahilmgandhi 18:6a4db94011d3 321 SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 322 break;
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324 break;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 }
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /**
sahilmgandhi 18:6a4db94011d3 332 * Initialize the system
sahilmgandhi 18:6a4db94011d3 333 *
sahilmgandhi 18:6a4db94011d3 334 * @param none
sahilmgandhi 18:6a4db94011d3 335 * @return none
sahilmgandhi 18:6a4db94011d3 336 *
sahilmgandhi 18:6a4db94011d3 337 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 338 * Initialize the System.
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 void SystemInit (void) {
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /* System clock to the IOCON & the SWM need to be enabled or
sahilmgandhi 18:6a4db94011d3 343 most of the I/O related peripherals won't work. */
sahilmgandhi 18:6a4db94011d3 344 LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 349 volatile uint32_t i;
sahilmgandhi 18:6a4db94011d3 350 LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
sahilmgandhi 18:6a4db94011d3 351 LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
sahilmgandhi 18:6a4db94011d3 352 LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
sahilmgandhi 18:6a4db94011d3 353 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
sahilmgandhi 18:6a4db94011d3 354 for (i = 0; i < 200; i++) __NOP();
sahilmgandhi 18:6a4db94011d3 355 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 356 #endif
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 359 LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
sahilmgandhi 18:6a4db94011d3 360 LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
sahilmgandhi 18:6a4db94011d3 361 for (i = 0; i < 200; i++) __NOP();
sahilmgandhi 18:6a4db94011d3 362 #endif
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
sahilmgandhi 18:6a4db94011d3 365 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 366 LPC_SYSCON->SYSPLLCLKUEN = 0;
sahilmgandhi 18:6a4db94011d3 367 LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
sahilmgandhi 18:6a4db94011d3 368 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
sahilmgandhi 18:6a4db94011d3 371 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 372 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
sahilmgandhi 18:6a4db94011d3 373 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 374 #endif
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 #if (((MAINCLKSEL_Val & 0x03) == 2) )
sahilmgandhi 18:6a4db94011d3 377 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 378 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
sahilmgandhi 18:6a4db94011d3 379 for (i = 0; i < 200; i++) __NOP();
sahilmgandhi 18:6a4db94011d3 380 #endif
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
sahilmgandhi 18:6a4db94011d3 383 LPC_SYSCON->MAINCLKUEN = 0;
sahilmgandhi 18:6a4db94011d3 384 LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
sahilmgandhi 18:6a4db94011d3 385 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
sahilmgandhi 18:6a4db94011d3 388 #endif
sahilmgandhi 18:6a4db94011d3 389 }