MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
sahilmgandhi 18:6a4db94011d3 17 */
sahilmgandhi 18:6a4db94011d3 18 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 19 #include <math.h>
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 22 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 23 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 24 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 // SCU mode for SPI pins
sahilmgandhi 18:6a4db94011d3 27 #define SCU_PINIO_SPI SCU_PINIO_FAST
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 static const PinMap PinMap_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 30 {P1_19, SPI_1, (SCU_PINIO_SPI | 1)},
sahilmgandhi 18:6a4db94011d3 31 {P3_0, SPI_0, (SCU_PINIO_SPI | 4)},
sahilmgandhi 18:6a4db94011d3 32 {P3_3, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 33 {PF_0, SPI_0, (SCU_PINIO_SPI | 0)},
sahilmgandhi 18:6a4db94011d3 34 {PF_4, SPI_1, (SCU_PINIO_SPI | 0)},
sahilmgandhi 18:6a4db94011d3 35 {NC, NC, 0}
sahilmgandhi 18:6a4db94011d3 36 };
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 static const PinMap PinMap_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 39 {P0_1, SPI_1, (SCU_PINIO_SPI | 1)},
sahilmgandhi 18:6a4db94011d3 40 {P1_2, SPI_0, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 41 {P1_4, SPI_1, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 42 {P3_7, SPI_0, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 43 {P3_8, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 44 {P9_2, SPI_0, (SCU_PINIO_SPI | 7)},
sahilmgandhi 18:6a4db94011d3 45 {PF_3, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 46 {PF_7, SPI_1, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 47 {NC, NC, 0}
sahilmgandhi 18:6a4db94011d3 48 };
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 static const PinMap PinMap_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 51 {P0_0, SPI_1, (SCU_PINIO_SPI | 1)},
sahilmgandhi 18:6a4db94011d3 52 {P1_1, SPI_0, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 53 {P1_3, SPI_1, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 54 {P3_6, SPI_0, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 55 {P3_7, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 56 {P9_1, SPI_0, (SCU_PINIO_SPI | 7)},
sahilmgandhi 18:6a4db94011d3 57 {PF_2, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 58 {PF_6, SPI_1, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 59 {NC, NC, 0}
sahilmgandhi 18:6a4db94011d3 60 };
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 static const PinMap PinMap_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 63 {P1_0, SPI_0, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 64 {P1_5, SPI_1, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 65 {P1_20, SPI_1, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 66 {P3_6, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 67 {P3_8, SPI_0, (SCU_PINIO_SPI | 5)},
sahilmgandhi 18:6a4db94011d3 68 {P9_0, SPI_0, (SCU_PINIO_SPI | 7)},
sahilmgandhi 18:6a4db94011d3 69 {PF_1, SPI_0, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 70 {PF_5, SPI_1, (SCU_PINIO_SPI | 2)},
sahilmgandhi 18:6a4db94011d3 71 {NC, NC, 0}
sahilmgandhi 18:6a4db94011d3 72 };
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 static inline int ssp_disable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 75 static inline int ssp_enable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 78 // determine the SPI to use
sahilmgandhi 18:6a4db94011d3 79 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 80 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 81 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 82 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 83 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 84 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 obj->spi = (LPC_SSP_T*)pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 87 MBED_ASSERT((int)obj->spi != NC);
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // enable clocking
sahilmgandhi 18:6a4db94011d3 90 switch ((int)obj->spi) {
sahilmgandhi 18:6a4db94011d3 91 case SPI_0: LPC_CGU->BASE_CLK[CLK_BASE_SSP0] = (1 << 11) | (CLKIN_MAINPLL << 24); break;
sahilmgandhi 18:6a4db94011d3 92 case SPI_1: LPC_CGU->BASE_CLK[CLK_BASE_SSP1] = (1 << 11) | (CLKIN_MAINPLL << 24); break;
sahilmgandhi 18:6a4db94011d3 93 }
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 // pin out the spi pins
sahilmgandhi 18:6a4db94011d3 96 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 97 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 98 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 99 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 100 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102 }
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 void spi_free(spi_t *obj) {}
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sahilmgandhi 18:6a4db94011d3 107 MBED_ASSERT(((bits >= 4) && (bits <= 16)) || ((mode >= 0) && (mode <= 3)));
sahilmgandhi 18:6a4db94011d3 108 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 int polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 111 int phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 // set it up
sahilmgandhi 18:6a4db94011d3 114 int DSS = bits - 1; // DSS (data select size)
sahilmgandhi 18:6a4db94011d3 115 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
sahilmgandhi 18:6a4db94011d3 116 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 int FRF = 0; // FRF (frame format) = SPI
sahilmgandhi 18:6a4db94011d3 119 uint32_t tmp = obj->spi->CR0;
sahilmgandhi 18:6a4db94011d3 120 tmp &= ~(0xFFFF);
sahilmgandhi 18:6a4db94011d3 121 tmp |= DSS << 0
sahilmgandhi 18:6a4db94011d3 122 | FRF << 4
sahilmgandhi 18:6a4db94011d3 123 | SPO << 6
sahilmgandhi 18:6a4db94011d3 124 | SPH << 7;
sahilmgandhi 18:6a4db94011d3 125 obj->spi->CR0 = tmp;
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 tmp = obj->spi->CR1;
sahilmgandhi 18:6a4db94011d3 128 tmp &= ~(0xD);
sahilmgandhi 18:6a4db94011d3 129 tmp |= 0 << 0 // LBM - loop back mode - off
sahilmgandhi 18:6a4db94011d3 130 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
sahilmgandhi 18:6a4db94011d3 131 | 0 << 3; // SOD - slave output disable - na
sahilmgandhi 18:6a4db94011d3 132 obj->spi->CR1 = tmp;
sahilmgandhi 18:6a4db94011d3 133 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 void spi_frequency(spi_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 137 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 int prescaler;
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
sahilmgandhi 18:6a4db94011d3 144 int prescale_hz = PCLK / prescaler;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 // calculate the divider
sahilmgandhi 18:6a4db94011d3 147 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 // check we can support the divider
sahilmgandhi 18:6a4db94011d3 150 if (divider < 256) {
sahilmgandhi 18:6a4db94011d3 151 // prescaler
sahilmgandhi 18:6a4db94011d3 152 obj->spi->CPSR = prescaler;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 // divider
sahilmgandhi 18:6a4db94011d3 155 obj->spi->CR0 &= ~(0xFFFF << 8);
sahilmgandhi 18:6a4db94011d3 156 obj->spi->CR0 |= (divider - 1) << 8;
sahilmgandhi 18:6a4db94011d3 157 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 158 return;
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161 error("Couldn't setup requested SPI frequency");
sahilmgandhi 18:6a4db94011d3 162 }
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 static inline int ssp_disable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 165 return obj->spi->CR1 &= ~(1 << 1);
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 static inline int ssp_enable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 169 return obj->spi->CR1 |= (1 << 1);
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 static inline int ssp_readable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 173 return obj->spi->SR & (1 << 2);
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 static inline int ssp_writeable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 177 return obj->spi->SR & (1 << 1);
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 static inline void ssp_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 181 while (!ssp_writeable(obj));
sahilmgandhi 18:6a4db94011d3 182 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 static inline int ssp_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 186 while (!ssp_readable(obj));
sahilmgandhi 18:6a4db94011d3 187 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 188 }
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 static inline int ssp_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 191 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 int spi_master_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 195 ssp_write(obj, value);
sahilmgandhi 18:6a4db94011d3 196 return ssp_read(obj);
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 int spi_slave_receive(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 200 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 201 }
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 int spi_slave_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 204 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 205 }
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 void spi_slave_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 208 while (ssp_writeable(obj) == 0) ;
sahilmgandhi 18:6a4db94011d3 209 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 210 }
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 int spi_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 213 return ssp_busy(obj);
sahilmgandhi 18:6a4db94011d3 214 }