MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PeripheralNames.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 17 #define MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 22 extern "C" {
sahilmgandhi 18:6a4db94011d3 23 #endif
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 typedef enum {
sahilmgandhi 18:6a4db94011d3 26 UART_0 = (int)LPC_USART0_BASE,
sahilmgandhi 18:6a4db94011d3 27 UART_1 = (int)LPC_UART1_BASE,
sahilmgandhi 18:6a4db94011d3 28 UART_2 = (int)LPC_USART2_BASE,
sahilmgandhi 18:6a4db94011d3 29 UART_3 = (int)LPC_USART3_BASE
sahilmgandhi 18:6a4db94011d3 30 } UARTName;
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 typedef enum {
sahilmgandhi 18:6a4db94011d3 33 ADC0_0 = 0,
sahilmgandhi 18:6a4db94011d3 34 ADC0_1,
sahilmgandhi 18:6a4db94011d3 35 ADC0_2,
sahilmgandhi 18:6a4db94011d3 36 ADC0_3,
sahilmgandhi 18:6a4db94011d3 37 ADC0_4,
sahilmgandhi 18:6a4db94011d3 38 ADC0_5,
sahilmgandhi 18:6a4db94011d3 39 ADC0_6,
sahilmgandhi 18:6a4db94011d3 40 ADC0_7,
sahilmgandhi 18:6a4db94011d3 41 ADC1_0,
sahilmgandhi 18:6a4db94011d3 42 ADC1_1,
sahilmgandhi 18:6a4db94011d3 43 ADC1_2,
sahilmgandhi 18:6a4db94011d3 44 ADC1_3,
sahilmgandhi 18:6a4db94011d3 45 ADC1_4,
sahilmgandhi 18:6a4db94011d3 46 ADC1_5,
sahilmgandhi 18:6a4db94011d3 47 ADC1_6,
sahilmgandhi 18:6a4db94011d3 48 ADC1_7,
sahilmgandhi 18:6a4db94011d3 49 ADC_pin0_0,
sahilmgandhi 18:6a4db94011d3 50 ADC_pin0_1,
sahilmgandhi 18:6a4db94011d3 51 ADC_pin0_2,
sahilmgandhi 18:6a4db94011d3 52 ADC_pin0_3,
sahilmgandhi 18:6a4db94011d3 53 ADC_pin0_4,
sahilmgandhi 18:6a4db94011d3 54 ADC_pin0_5,
sahilmgandhi 18:6a4db94011d3 55 ADC_pin0_6,
sahilmgandhi 18:6a4db94011d3 56 ADC_pin0_7,
sahilmgandhi 18:6a4db94011d3 57 ADC_pin1_0,
sahilmgandhi 18:6a4db94011d3 58 ADC_pin1_1,
sahilmgandhi 18:6a4db94011d3 59 ADC_pin1_2,
sahilmgandhi 18:6a4db94011d3 60 ADC_pin1_3,
sahilmgandhi 18:6a4db94011d3 61 ADC_pin1_4,
sahilmgandhi 18:6a4db94011d3 62 ADC_pin1_5,
sahilmgandhi 18:6a4db94011d3 63 ADC_pin1_6,
sahilmgandhi 18:6a4db94011d3 64 ADC_pin1_7
sahilmgandhi 18:6a4db94011d3 65 } ADCName;
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 typedef enum {
sahilmgandhi 18:6a4db94011d3 68 DAC_0 = 0
sahilmgandhi 18:6a4db94011d3 69 } DACName;
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 typedef enum {
sahilmgandhi 18:6a4db94011d3 72 SPI_0 = (int)LPC_SSP0_BASE,
sahilmgandhi 18:6a4db94011d3 73 SPI_1 = (int)LPC_SSP1_BASE
sahilmgandhi 18:6a4db94011d3 74 } SPIName;
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 typedef enum {
sahilmgandhi 18:6a4db94011d3 77 I2C_0 = (int)LPC_I2C0_BASE,
sahilmgandhi 18:6a4db94011d3 78 I2C_1 = (int)LPC_I2C1_BASE
sahilmgandhi 18:6a4db94011d3 79 } I2CName;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 typedef enum {
sahilmgandhi 18:6a4db94011d3 82 PWM_0,
sahilmgandhi 18:6a4db94011d3 83 PWM_1,
sahilmgandhi 18:6a4db94011d3 84 PWM_2,
sahilmgandhi 18:6a4db94011d3 85 PWM_3,
sahilmgandhi 18:6a4db94011d3 86 PWM_4,
sahilmgandhi 18:6a4db94011d3 87 PWM_5,
sahilmgandhi 18:6a4db94011d3 88 PWM_6,
sahilmgandhi 18:6a4db94011d3 89 PWM_7,
sahilmgandhi 18:6a4db94011d3 90 PWM_8,
sahilmgandhi 18:6a4db94011d3 91 PWM_9,
sahilmgandhi 18:6a4db94011d3 92 PWM_10,
sahilmgandhi 18:6a4db94011d3 93 PWM_11,
sahilmgandhi 18:6a4db94011d3 94 PWM_12,
sahilmgandhi 18:6a4db94011d3 95 PWM_13,
sahilmgandhi 18:6a4db94011d3 96 PWM_14,
sahilmgandhi 18:6a4db94011d3 97 PWM_15
sahilmgandhi 18:6a4db94011d3 98 } PWMName;
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 typedef enum {
sahilmgandhi 18:6a4db94011d3 101 CAN_0 = (int)LPC_C_CAN0_BASE,
sahilmgandhi 18:6a4db94011d3 102 CAN_1 = (int)LPC_C_CAN1_BASE
sahilmgandhi 18:6a4db94011d3 103 } CANName;
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 #define STDIO_UART_TX USBTX
sahilmgandhi 18:6a4db94011d3 106 #define STDIO_UART_RX USBRX
sahilmgandhi 18:6a4db94011d3 107 #define STDIO_UART UART_0
sahilmgandhi 18:6a4db94011d3 108 #define STDIO_BAUD 9600
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 // Default peripherals
sahilmgandhi 18:6a4db94011d3 111 #define MBED_SPI0 SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SSEL
sahilmgandhi 18:6a4db94011d3 112 #define MBED_SPI1 SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_SSEL
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 #define MBED_UART0 UART0_TX, UART0_RX
sahilmgandhi 18:6a4db94011d3 115 #define MBED_UART1 UART1_TX, UART1_RX
sahilmgandhi 18:6a4db94011d3 116 #define MBED_UART2 UART2_TX, UART2_RX
sahilmgandhi 18:6a4db94011d3 117 #define MBED_UART3 UART3_TX, UART3_RX
sahilmgandhi 18:6a4db94011d3 118 #define MBED_UARTUSB USBTX, USBRX
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 #define COM1 MBED_UART0
sahilmgandhi 18:6a4db94011d3 121 #define COM2 MBED_UART1
sahilmgandhi 18:6a4db94011d3 122 #define COM3 MBED_UART2
sahilmgandhi 18:6a4db94011d3 123 #define COM4 MBED_UART3
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 #define MBED_I2C0 I2C0_SDA, I2C0_SCL
sahilmgandhi 18:6a4db94011d3 126 #define MBED_I2C1 I2C1_SDA, I2C1_SCL
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 #define MBED_CAN0 p30, p29
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 #define MBED_ANALOGOUT0 DAC0
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 #define MBED_ANALOGIN0 ADC0
sahilmgandhi 18:6a4db94011d3 133 #define MBED_ANALOGIN1 ADC1
sahilmgandhi 18:6a4db94011d3 134 #define MBED_ANALOGIN2 ADC2
sahilmgandhi 18:6a4db94011d3 135 #define MBED_ANALOGIN3 ADC3
sahilmgandhi 18:6a4db94011d3 136 #define MBED_ANALOGIN4 ADC4
sahilmgandhi 18:6a4db94011d3 137 #define MBED_ANALOGIN5 ADC5
sahilmgandhi 18:6a4db94011d3 138 #define MBED_ANALOGIN6 ADC6
sahilmgandhi 18:6a4db94011d3 139 #define MBED_ANALOGIN7 ADC7
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 #define MBED_PWMOUT0 p26
sahilmgandhi 18:6a4db94011d3 142 #define MBED_PWMOUT1 p25
sahilmgandhi 18:6a4db94011d3 143 #define MBED_PWMOUT2 p24
sahilmgandhi 18:6a4db94011d3 144 #define MBED_PWMOUT3 p23
sahilmgandhi 18:6a4db94011d3 145 #define MBED_PWMOUT4 p22
sahilmgandhi 18:6a4db94011d3 146 #define MBED_PWMOUT5 p21
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150 #endif
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 #endif