MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 18 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #define CHANNEL_NUM 64
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 24 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 static void handle_interrupt_in(void) {
sahilmgandhi 18:6a4db94011d3 27 // Read in all current interrupt registers. We do this once as the
sahilmgandhi 18:6a4db94011d3 28 // GPIO interrupt registers are on the APB bus, and this is slow.
sahilmgandhi 18:6a4db94011d3 29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 uint8_t bitloc;
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 // Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 37 while(rise0 > 0) {
sahilmgandhi 18:6a4db94011d3 38 // CLZ returns number of leading zeros, 31 minus that is location of
sahilmgandhi 18:6a4db94011d3 39 // first pending interrupt
sahilmgandhi 18:6a4db94011d3 40 bitloc = 31 - __CLZ(rise0);
sahilmgandhi 18:6a4db94011d3 41 if (channel_ids[bitloc] != 0)
sahilmgandhi 18:6a4db94011d3 42 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 // Both clear the interrupt with clear register, and remove it from
sahilmgandhi 18:6a4db94011d3 45 // our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 46 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 47 rise0 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 48 }
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 // Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 51 while(fall0 > 0) {
sahilmgandhi 18:6a4db94011d3 52 // CLZ returns number of leading zeros, 31 minus that is location of
sahilmgandhi 18:6a4db94011d3 53 // first pending interrupt
sahilmgandhi 18:6a4db94011d3 54 bitloc = 31 - __CLZ(fall0);
sahilmgandhi 18:6a4db94011d3 55 if (channel_ids[bitloc] != 0)
sahilmgandhi 18:6a4db94011d3 56 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 // Both clear the interrupt with clear register, and remove it from
sahilmgandhi 18:6a4db94011d3 59 // our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 60 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 61 fall0 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 // Same for port 2
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 // Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 67 while(rise2 > 0) {
sahilmgandhi 18:6a4db94011d3 68 // CLZ returns number of leading zeros, 31 minus that is location of
sahilmgandhi 18:6a4db94011d3 69 // first pending interrupt
sahilmgandhi 18:6a4db94011d3 70 bitloc = 31 - __CLZ(rise2);
sahilmgandhi 18:6a4db94011d3 71 if (channel_ids[bitloc+32] != 0)
sahilmgandhi 18:6a4db94011d3 72 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 // Both clear the interrupt with clear register, and remove it from
sahilmgandhi 18:6a4db94011d3 75 // our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 76 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 77 rise2 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 // Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 81 while(fall2 > 0) {
sahilmgandhi 18:6a4db94011d3 82 // CLZ returns number of leading zeros, 31 minus that is location of
sahilmgandhi 18:6a4db94011d3 83 // first pending interrupt
sahilmgandhi 18:6a4db94011d3 84 bitloc = 31 - __CLZ(fall2);
sahilmgandhi 18:6a4db94011d3 85 if (channel_ids[bitloc+32] != 0)
sahilmgandhi 18:6a4db94011d3 86 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 // Both clear the interrupt with clear register, and remove it from
sahilmgandhi 18:6a4db94011d3 89 // our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 90 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 91 fall2 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 92 }
sahilmgandhi 18:6a4db94011d3 93 }
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 96 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 obj->port = ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
sahilmgandhi 18:6a4db94011d3 101 obj->pin = (int)pin % 32;
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 // Interrupts available only on GPIO0 and GPIO2
sahilmgandhi 18:6a4db94011d3 104 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
sahilmgandhi 18:6a4db94011d3 105 error("pins on this port cannot generate interrupts");
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 // put us in the interrupt table
sahilmgandhi 18:6a4db94011d3 109 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
sahilmgandhi 18:6a4db94011d3 110 channel_ids[index] = id;
sahilmgandhi 18:6a4db94011d3 111 obj->ch = index;
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
sahilmgandhi 18:6a4db94011d3 114 NVIC_EnableIRQ(GPIO_IRQn);
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 return 0;
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 120 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 121 }
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 124 // ensure nothing is pending
sahilmgandhi 18:6a4db94011d3 125 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 126 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
sahilmgandhi 18:6a4db94011d3 127 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
sahilmgandhi 18:6a4db94011d3 128 }
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 // enable the pin interrupt
sahilmgandhi 18:6a4db94011d3 131 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 132 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 133 case LPC_GPIO0_BASE:
sahilmgandhi 18:6a4db94011d3 134 if (enable) {
sahilmgandhi 18:6a4db94011d3 135 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 136 } else {
sahilmgandhi 18:6a4db94011d3 137 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 138 }
sahilmgandhi 18:6a4db94011d3 139 break;
sahilmgandhi 18:6a4db94011d3 140 case LPC_GPIO2_BASE:
sahilmgandhi 18:6a4db94011d3 141 if (enable) {
sahilmgandhi 18:6a4db94011d3 142 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 143 } else {
sahilmgandhi 18:6a4db94011d3 144 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146 break;
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148 } else {
sahilmgandhi 18:6a4db94011d3 149 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 150 case LPC_GPIO0_BASE:
sahilmgandhi 18:6a4db94011d3 151 if (enable) {
sahilmgandhi 18:6a4db94011d3 152 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 153 } else {
sahilmgandhi 18:6a4db94011d3 154 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 155 }
sahilmgandhi 18:6a4db94011d3 156 break;
sahilmgandhi 18:6a4db94011d3 157 case LPC_GPIO2_BASE:
sahilmgandhi 18:6a4db94011d3 158 if (enable) {
sahilmgandhi 18:6a4db94011d3 159 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 160 } else {
sahilmgandhi 18:6a4db94011d3 161 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 162 }
sahilmgandhi 18:6a4db94011d3 163 break;
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165 }
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 169 NVIC_EnableIRQ(GPIO_IRQn);
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 173 NVIC_DisableIRQ(GPIO_IRQn);
sahilmgandhi 18:6a4db94011d3 174 }