Mouse code for the MacroRat
mbed-dev/targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_CR/LPC407x_8x.ld@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* |
sahilmgandhi | 18:6a4db94011d3 | 2 | * GENERATED FILE - DO NOT EDIT |
sahilmgandhi | 18:6a4db94011d3 | 3 | * (C) Code Red Technologies Ltd, 2008-2013 |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Generated linker script file for LPC4088 |
sahilmgandhi | 18:6a4db94011d3 | 5 | * Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] )) |
sahilmgandhi | 18:6a4db94011d3 | 6 | * By LPCXpresso v5.1.2 [Build 2065] [2013-02-20] on Wed Apr 17 14:50:07 CEST 2013 |
sahilmgandhi | 18:6a4db94011d3 | 7 | */ |
sahilmgandhi | 18:6a4db94011d3 | 8 | |
sahilmgandhi | 18:6a4db94011d3 | 9 | |
sahilmgandhi | 18:6a4db94011d3 | 10 | GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) |
sahilmgandhi | 18:6a4db94011d3 | 11 | |
sahilmgandhi | 18:6a4db94011d3 | 12 | MEMORY |
sahilmgandhi | 18:6a4db94011d3 | 13 | { |
sahilmgandhi | 18:6a4db94011d3 | 14 | /* Define each memory region */ |
sahilmgandhi | 18:6a4db94011d3 | 15 | MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */ |
sahilmgandhi | 18:6a4db94011d3 | 17 | RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */ |
sahilmgandhi | 18:6a4db94011d3 | 18 | |
sahilmgandhi | 18:6a4db94011d3 | 19 | } |
sahilmgandhi | 18:6a4db94011d3 | 20 | /* Define a symbol for the top of each memory region */ |
sahilmgandhi | 18:6a4db94011d3 | 21 | __top_MFlash512 = 0x0 + 0x80000; |
sahilmgandhi | 18:6a4db94011d3 | 22 | __top_RamLoc64 = 0x10000000 + 0x10000; |
sahilmgandhi | 18:6a4db94011d3 | 23 | __top_RamPeriph32 = 0x20000000 + 0x8000; |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | ENTRY(ResetISR) |
sahilmgandhi | 18:6a4db94011d3 | 26 | |
sahilmgandhi | 18:6a4db94011d3 | 27 | SECTIONS |
sahilmgandhi | 18:6a4db94011d3 | 28 | { |
sahilmgandhi | 18:6a4db94011d3 | 29 | |
sahilmgandhi | 18:6a4db94011d3 | 30 | /* MAIN TEXT SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 31 | .text : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 32 | { |
sahilmgandhi | 18:6a4db94011d3 | 33 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 34 | KEEP(*(.isr_vector)) |
sahilmgandhi | 18:6a4db94011d3 | 35 | |
sahilmgandhi | 18:6a4db94011d3 | 36 | /* Global Section Table */ |
sahilmgandhi | 18:6a4db94011d3 | 37 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 38 | __section_table_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 39 | __data_section_table = .; |
sahilmgandhi | 18:6a4db94011d3 | 40 | LONG(LOADADDR(.data)); |
sahilmgandhi | 18:6a4db94011d3 | 41 | LONG( ADDR(.data)) ; |
sahilmgandhi | 18:6a4db94011d3 | 42 | LONG( SIZEOF(.data)); |
sahilmgandhi | 18:6a4db94011d3 | 43 | LONG(LOADADDR(.data_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 44 | LONG( ADDR(.data_RAM2)) ; |
sahilmgandhi | 18:6a4db94011d3 | 45 | LONG( SIZEOF(.data_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 46 | __data_section_table_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 47 | __bss_section_table = .; |
sahilmgandhi | 18:6a4db94011d3 | 48 | LONG( ADDR(.bss)); |
sahilmgandhi | 18:6a4db94011d3 | 49 | LONG( SIZEOF(.bss)); |
sahilmgandhi | 18:6a4db94011d3 | 50 | LONG( ADDR(.bss_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 51 | LONG( SIZEOF(.bss_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 52 | __bss_section_table_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 53 | __section_table_end = . ; |
sahilmgandhi | 18:6a4db94011d3 | 54 | /* End of Global Section Table */ |
sahilmgandhi | 18:6a4db94011d3 | 55 | |
sahilmgandhi | 18:6a4db94011d3 | 56 | |
sahilmgandhi | 18:6a4db94011d3 | 57 | *(.after_vectors*) |
sahilmgandhi | 18:6a4db94011d3 | 58 | |
sahilmgandhi | 18:6a4db94011d3 | 59 | *(.text*) |
sahilmgandhi | 18:6a4db94011d3 | 60 | *(.rodata .rodata.*) |
sahilmgandhi | 18:6a4db94011d3 | 61 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 62 | |
sahilmgandhi | 18:6a4db94011d3 | 63 | /* C++ constructors etc */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 65 | KEEP(*(.init)) |
sahilmgandhi | 18:6a4db94011d3 | 66 | |
sahilmgandhi | 18:6a4db94011d3 | 67 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 68 | __preinit_array_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 69 | KEEP (*(.preinit_array)) |
sahilmgandhi | 18:6a4db94011d3 | 70 | __preinit_array_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 71 | |
sahilmgandhi | 18:6a4db94011d3 | 72 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 73 | __init_array_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 74 | KEEP (*(SORT(.init_array.*))) |
sahilmgandhi | 18:6a4db94011d3 | 75 | KEEP (*(.init_array)) |
sahilmgandhi | 18:6a4db94011d3 | 76 | __init_array_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 77 | |
sahilmgandhi | 18:6a4db94011d3 | 78 | KEEP(*(.fini)); |
sahilmgandhi | 18:6a4db94011d3 | 79 | |
sahilmgandhi | 18:6a4db94011d3 | 80 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 81 | KEEP (*crtbegin.o(.ctors)) |
sahilmgandhi | 18:6a4db94011d3 | 82 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) |
sahilmgandhi | 18:6a4db94011d3 | 83 | KEEP (*(SORT(.ctors.*))) |
sahilmgandhi | 18:6a4db94011d3 | 84 | KEEP (*crtend.o(.ctors)) |
sahilmgandhi | 18:6a4db94011d3 | 85 | |
sahilmgandhi | 18:6a4db94011d3 | 86 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 87 | KEEP (*crtbegin.o(.dtors)) |
sahilmgandhi | 18:6a4db94011d3 | 88 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) |
sahilmgandhi | 18:6a4db94011d3 | 89 | KEEP (*(SORT(.dtors.*))) |
sahilmgandhi | 18:6a4db94011d3 | 90 | KEEP (*crtend.o(.dtors)) |
sahilmgandhi | 18:6a4db94011d3 | 91 | /* End C++ */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | } > MFlash512 |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | /* |
sahilmgandhi | 18:6a4db94011d3 | 95 | * for exception handling/unwind - some Newlib functions (in common |
sahilmgandhi | 18:6a4db94011d3 | 96 | * with C++ and STDC++) use this. |
sahilmgandhi | 18:6a4db94011d3 | 97 | */ |
sahilmgandhi | 18:6a4db94011d3 | 98 | .ARM.extab : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 99 | { |
sahilmgandhi | 18:6a4db94011d3 | 100 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
sahilmgandhi | 18:6a4db94011d3 | 101 | } > MFlash512 |
sahilmgandhi | 18:6a4db94011d3 | 102 | __exidx_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | .ARM.exidx : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 105 | { |
sahilmgandhi | 18:6a4db94011d3 | 106 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
sahilmgandhi | 18:6a4db94011d3 | 107 | } > MFlash512 |
sahilmgandhi | 18:6a4db94011d3 | 108 | __exidx_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | _etext = .; |
sahilmgandhi | 18:6a4db94011d3 | 111 | |
sahilmgandhi | 18:6a4db94011d3 | 112 | |
sahilmgandhi | 18:6a4db94011d3 | 113 | /* DATA section for RamPeriph32 */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | .data_RAM2 : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 115 | { |
sahilmgandhi | 18:6a4db94011d3 | 116 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 117 | *(.data.$RAM2*) |
sahilmgandhi | 18:6a4db94011d3 | 118 | *(.data.$RamPeriph32*) |
sahilmgandhi | 18:6a4db94011d3 | 119 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 120 | } > RamPeriph32 AT>MFlash512 |
sahilmgandhi | 18:6a4db94011d3 | 121 | |
sahilmgandhi | 18:6a4db94011d3 | 122 | /* MAIN DATA SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | |
sahilmgandhi | 18:6a4db94011d3 | 125 | .uninit_RESERVED : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 126 | { |
sahilmgandhi | 18:6a4db94011d3 | 127 | KEEP(*(.bss.$RESERVED*)) |
sahilmgandhi | 18:6a4db94011d3 | 128 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 129 | _end_uninit_RESERVED = .; |
sahilmgandhi | 18:6a4db94011d3 | 130 | } > RamLoc64 |
sahilmgandhi | 18:6a4db94011d3 | 131 | |
sahilmgandhi | 18:6a4db94011d3 | 132 | .data : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 133 | { |
sahilmgandhi | 18:6a4db94011d3 | 134 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 135 | _data = .; |
sahilmgandhi | 18:6a4db94011d3 | 136 | *(vtable) |
sahilmgandhi | 18:6a4db94011d3 | 137 | *(.data*) |
sahilmgandhi | 18:6a4db94011d3 | 138 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 139 | _edata = .; |
sahilmgandhi | 18:6a4db94011d3 | 140 | } > RamLoc64 AT>MFlash512 |
sahilmgandhi | 18:6a4db94011d3 | 141 | |
sahilmgandhi | 18:6a4db94011d3 | 142 | /* BSS section for RamPeriph32 */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | .bss_RAM2 : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 144 | { |
sahilmgandhi | 18:6a4db94011d3 | 145 | *(.bss.$RAM2*) |
sahilmgandhi | 18:6a4db94011d3 | 146 | *(.bss.$RamPeriph32*) |
sahilmgandhi | 18:6a4db94011d3 | 147 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 148 | } > RamPeriph32 |
sahilmgandhi | 18:6a4db94011d3 | 149 | |
sahilmgandhi | 18:6a4db94011d3 | 150 | /* MAIN BSS SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | .bss : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 152 | { |
sahilmgandhi | 18:6a4db94011d3 | 153 | _bss = .; |
sahilmgandhi | 18:6a4db94011d3 | 154 | *(.bss*) |
sahilmgandhi | 18:6a4db94011d3 | 155 | *(COMMON) |
sahilmgandhi | 18:6a4db94011d3 | 156 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 157 | _ebss = .; |
sahilmgandhi | 18:6a4db94011d3 | 158 | PROVIDE(end = .); |
sahilmgandhi | 18:6a4db94011d3 | 159 | __end__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 160 | } > RamLoc64 |
sahilmgandhi | 18:6a4db94011d3 | 161 | |
sahilmgandhi | 18:6a4db94011d3 | 162 | /* NOINIT section for RamPeriph32 */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | .noinit_RAM2 (NOLOAD) : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 164 | { |
sahilmgandhi | 18:6a4db94011d3 | 165 | *(.noinit.$RAM2*) |
sahilmgandhi | 18:6a4db94011d3 | 166 | *(.noinit.$RamPeriph32*) |
sahilmgandhi | 18:6a4db94011d3 | 167 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 168 | } > RamPeriph32 |
sahilmgandhi | 18:6a4db94011d3 | 169 | |
sahilmgandhi | 18:6a4db94011d3 | 170 | /* DEFAULT NOINIT SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | .noinit (NOLOAD): ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 172 | { |
sahilmgandhi | 18:6a4db94011d3 | 173 | _noinit = .; |
sahilmgandhi | 18:6a4db94011d3 | 174 | *(.noinit*) |
sahilmgandhi | 18:6a4db94011d3 | 175 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 176 | _end_noinit = .; |
sahilmgandhi | 18:6a4db94011d3 | 177 | } > RamLoc64 |
sahilmgandhi | 18:6a4db94011d3 | 178 | |
sahilmgandhi | 18:6a4db94011d3 | 179 | PROVIDE(_pvHeapStart = .); |
sahilmgandhi | 18:6a4db94011d3 | 180 | PROVIDE(_vStackTop = __top_RamLoc64 - 0); |
sahilmgandhi | 18:6a4db94011d3 | 181 | } |