MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC408X/device/LPC407x_8x_177x_8x.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /****************************************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25
sahilmgandhi 18:6a4db94011d3 3 *//**
sahilmgandhi 18:6a4db94011d3 4 * @file LPC407x_8x_177x_8x.h
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 7 * NXP LPC407x_8x_177x_8x.
sahilmgandhi 18:6a4db94011d3 8 * @version V0.7
sahilmgandhi 18:6a4db94011d3 9 * @date 20. June 2012
sahilmgandhi 18:6a4db94011d3 10 * @author NXP MCU SW Application Team
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Copyright(C) 2012, NXP Semiconductor
sahilmgandhi 18:6a4db94011d3 13 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 ***********************************************************************
sahilmgandhi 18:6a4db94011d3 16 * Software that is described herein is for illustrative purposes only
sahilmgandhi 18:6a4db94011d3 17 * which provides customers with programming information regarding the
sahilmgandhi 18:6a4db94011d3 18 * products. This software is supplied "AS IS" without any warranties.
sahilmgandhi 18:6a4db94011d3 19 * NXP Semiconductors assumes no responsibility or liability for the
sahilmgandhi 18:6a4db94011d3 20 * use of the software, conveys no license or title under any patent,
sahilmgandhi 18:6a4db94011d3 21 * copyright, or mask work right to the product. NXP Semiconductors
sahilmgandhi 18:6a4db94011d3 22 * reserves the right to make changes in the software without
sahilmgandhi 18:6a4db94011d3 23 * notification. NXP Semiconductors also make no representation or
sahilmgandhi 18:6a4db94011d3 24 * warranty that such application will be suitable for the specified
sahilmgandhi 18:6a4db94011d3 25 * use without further testing or modification.
sahilmgandhi 18:6a4db94011d3 26 * Permission to use, copy, modify, and distribute this software and its
sahilmgandhi 18:6a4db94011d3 27 * documentation is hereby granted, under NXP Semiconductors'
sahilmgandhi 18:6a4db94011d3 28 * relevant copyright in the software, without fee, provided that it
sahilmgandhi 18:6a4db94011d3 29 * is used in conjunction with NXP Semiconductors microcontrollers. This
sahilmgandhi 18:6a4db94011d3 30 * copyright, permission, and disclaimer notice must appear in all copies of
sahilmgandhi 18:6a4db94011d3 31 * this code.
sahilmgandhi 18:6a4db94011d3 32 **********************************************************************/
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #ifndef __LPC407x_8x_177x_8x_H__
sahilmgandhi 18:6a4db94011d3 35 #define __LPC407x_8x_177x_8x_H__
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #if defined(__CORTEX_M4) && !defined(CORE_M4)
sahilmgandhi 18:6a4db94011d3 38 #define CORE_M4
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 // ##################
sahilmgandhi 18:6a4db94011d3 42 // Code Red - excluded extern "C" as unrequired
sahilmgandhi 18:6a4db94011d3 43 // ##################
sahilmgandhi 18:6a4db94011d3 44 #if 0
sahilmgandhi 18:6a4db94011d3 45 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 46 extern "C" {
sahilmgandhi 18:6a4db94011d3 47 #endif
sahilmgandhi 18:6a4db94011d3 48 #endif
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 54 {
sahilmgandhi 18:6a4db94011d3 55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
sahilmgandhi 18:6a4db94011d3 56 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 57 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 58 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 59 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 60 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 61 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 62 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 63 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 64 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 65 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
sahilmgandhi 18:6a4db94011d3 68 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 69 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
sahilmgandhi 18:6a4db94011d3 70 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
sahilmgandhi 18:6a4db94011d3 71 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
sahilmgandhi 18:6a4db94011d3 72 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
sahilmgandhi 18:6a4db94011d3 73 UART0_IRQn = 5, /*!< UART0 Interrupt */
sahilmgandhi 18:6a4db94011d3 74 UART1_IRQn = 6, /*!< UART1 Interrupt */
sahilmgandhi 18:6a4db94011d3 75 UART2_IRQn = 7, /*!< UART2 Interrupt */
sahilmgandhi 18:6a4db94011d3 76 UART3_IRQn = 8, /*!< UART3 Interrupt */
sahilmgandhi 18:6a4db94011d3 77 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
sahilmgandhi 18:6a4db94011d3 78 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
sahilmgandhi 18:6a4db94011d3 79 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
sahilmgandhi 18:6a4db94011d3 80 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
sahilmgandhi 18:6a4db94011d3 81 Reserved0_IRQn = 13, /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 82 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
sahilmgandhi 18:6a4db94011d3 83 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
sahilmgandhi 18:6a4db94011d3 84 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
sahilmgandhi 18:6a4db94011d3 85 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
sahilmgandhi 18:6a4db94011d3 86 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 87 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 88 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 89 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 90 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
sahilmgandhi 18:6a4db94011d3 91 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
sahilmgandhi 18:6a4db94011d3 92 USB_IRQn = 24, /*!< USB Interrupt */
sahilmgandhi 18:6a4db94011d3 93 CAN_IRQn = 25, /*!< CAN Interrupt */
sahilmgandhi 18:6a4db94011d3 94 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
sahilmgandhi 18:6a4db94011d3 95 I2S_IRQn = 27, /*!< I2S Interrupt */
sahilmgandhi 18:6a4db94011d3 96 ENET_IRQn = 28, /*!< Ethernet Interrupt */
sahilmgandhi 18:6a4db94011d3 97 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
sahilmgandhi 18:6a4db94011d3 98 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
sahilmgandhi 18:6a4db94011d3 99 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
sahilmgandhi 18:6a4db94011d3 100 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
sahilmgandhi 18:6a4db94011d3 101 USBActivity_IRQn = 33, /*!< USB Activity interrupt */
sahilmgandhi 18:6a4db94011d3 102 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
sahilmgandhi 18:6a4db94011d3 103 UART4_IRQn = 35, /*!< UART4 Interrupt */
sahilmgandhi 18:6a4db94011d3 104 SSP2_IRQn = 36, /*!< SSP2 Interrupt */
sahilmgandhi 18:6a4db94011d3 105 LCD_IRQn = 37, /*!< LCD Interrupt */
sahilmgandhi 18:6a4db94011d3 106 GPIO_IRQn = 38, /*!< GPIO Interrupt */
sahilmgandhi 18:6a4db94011d3 107 PWM0_IRQn = 39, /*!< 39 PWM0 */
sahilmgandhi 18:6a4db94011d3 108 EEPROM_IRQn = 40, /*!< 40 EEPROM */
sahilmgandhi 18:6a4db94011d3 109 CMP0_IRQn = 41, /*!< 41 CMP0 */
sahilmgandhi 18:6a4db94011d3 110 CMP1_IRQn = 42 /*!< 42 CMP1 */
sahilmgandhi 18:6a4db94011d3 111 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 114 /* ================ Processor and Core Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 115 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 116 #ifdef CORE_M4
sahilmgandhi 18:6a4db94011d3 117 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
sahilmgandhi 18:6a4db94011d3 118 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
sahilmgandhi 18:6a4db94011d3 119 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 120 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 122 #define __FPU_PRESENT 1 /*!< FPU present or not */
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 126 #else
sahilmgandhi 18:6a4db94011d3 127 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 128 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 129 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 130 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 #endif
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 145 /* ================ Device Specific Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 146 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 149 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 150 #endif
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
sahilmgandhi 18:6a4db94011d3 153 typedef struct /* Common Registers */
sahilmgandhi 18:6a4db94011d3 154 {
sahilmgandhi 18:6a4db94011d3 155 __I uint32_t IntStat;
sahilmgandhi 18:6a4db94011d3 156 __I uint32_t IntTCStat;
sahilmgandhi 18:6a4db94011d3 157 __O uint32_t IntTCClear;
sahilmgandhi 18:6a4db94011d3 158 __I uint32_t IntErrStat;
sahilmgandhi 18:6a4db94011d3 159 __O uint32_t IntErrClr;
sahilmgandhi 18:6a4db94011d3 160 __I uint32_t RawIntTCStat;
sahilmgandhi 18:6a4db94011d3 161 __I uint32_t RawIntErrStat;
sahilmgandhi 18:6a4db94011d3 162 __I uint32_t EnbldChns;
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t SoftBReq;
sahilmgandhi 18:6a4db94011d3 164 __IO uint32_t SoftSReq;
sahilmgandhi 18:6a4db94011d3 165 __IO uint32_t SoftLBReq;
sahilmgandhi 18:6a4db94011d3 166 __IO uint32_t SoftLSReq;
sahilmgandhi 18:6a4db94011d3 167 __IO uint32_t Config;
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t Sync;
sahilmgandhi 18:6a4db94011d3 169 } LPC_GPDMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 typedef struct /* Channel Registers */
sahilmgandhi 18:6a4db94011d3 172 {
sahilmgandhi 18:6a4db94011d3 173 __IO uint32_t CSrcAddr;
sahilmgandhi 18:6a4db94011d3 174 __IO uint32_t CDestAddr;
sahilmgandhi 18:6a4db94011d3 175 __IO uint32_t CLLI;
sahilmgandhi 18:6a4db94011d3 176 __IO uint32_t CControl;
sahilmgandhi 18:6a4db94011d3 177 __IO uint32_t CConfig;
sahilmgandhi 18:6a4db94011d3 178 } LPC_GPDMACH_TypeDef;
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 /*------------- System Control (SC) ------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 181 typedef struct
sahilmgandhi 18:6a4db94011d3 182 {
sahilmgandhi 18:6a4db94011d3 183 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
sahilmgandhi 18:6a4db94011d3 184 uint32_t RESERVED0[31];
sahilmgandhi 18:6a4db94011d3 185 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
sahilmgandhi 18:6a4db94011d3 186 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
sahilmgandhi 18:6a4db94011d3 187 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
sahilmgandhi 18:6a4db94011d3 188 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
sahilmgandhi 18:6a4db94011d3 189 uint32_t RESERVED1[4];
sahilmgandhi 18:6a4db94011d3 190 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
sahilmgandhi 18:6a4db94011d3 191 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
sahilmgandhi 18:6a4db94011d3 192 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
sahilmgandhi 18:6a4db94011d3 193 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
sahilmgandhi 18:6a4db94011d3 194 uint32_t RESERVED2[4];
sahilmgandhi 18:6a4db94011d3 195 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
sahilmgandhi 18:6a4db94011d3 196 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
sahilmgandhi 18:6a4db94011d3 197 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
sahilmgandhi 18:6a4db94011d3 198 uint32_t RESERVED3[13];
sahilmgandhi 18:6a4db94011d3 199 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
sahilmgandhi 18:6a4db94011d3 200 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
sahilmgandhi 18:6a4db94011d3 201 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
sahilmgandhi 18:6a4db94011d3 205 uint32_t RESERVED4[10];
sahilmgandhi 18:6a4db94011d3 206 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 207 uint32_t RESERVED5[1];
sahilmgandhi 18:6a4db94011d3 208 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
sahilmgandhi 18:6a4db94011d3 210 uint32_t RESERVED6[12];
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
sahilmgandhi 18:6a4db94011d3 212 uint32_t RESERVED7[1];
sahilmgandhi 18:6a4db94011d3 213 __IO uint32_t MATRIXARB; /*!< Offset: 0x188 (R/W) Matrix Arbitration Register */
sahilmgandhi 18:6a4db94011d3 214 uint32_t RESERVED71[5];
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
sahilmgandhi 18:6a4db94011d3 217 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
sahilmgandhi 18:6a4db94011d3 218 uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t SPIFICLKSEL;
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
sahilmgandhi 18:6a4db94011d3 222 uint32_t RESERVED10[1];
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
sahilmgandhi 18:6a4db94011d3 226 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
sahilmgandhi 18:6a4db94011d3 228 uint32_t RESERVED11[2];
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
sahilmgandhi 18:6a4db94011d3 231 } LPC_SC_TypeDef;
sahilmgandhi 18:6a4db94011d3 232 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
sahilmgandhi 18:6a4db94011d3 233 typedef struct
sahilmgandhi 18:6a4db94011d3 234 {
sahilmgandhi 18:6a4db94011d3 235 __IO uint32_t MAC1; /* MAC Registers */
sahilmgandhi 18:6a4db94011d3 236 __IO uint32_t MAC2;
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t IPGT;
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t IPGR;
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t CLRT;
sahilmgandhi 18:6a4db94011d3 240 __IO uint32_t MAXF;
sahilmgandhi 18:6a4db94011d3 241 __IO uint32_t SUPP;
sahilmgandhi 18:6a4db94011d3 242 __IO uint32_t TEST;
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t MCFG;
sahilmgandhi 18:6a4db94011d3 244 __IO uint32_t MCMD;
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t MADR;
sahilmgandhi 18:6a4db94011d3 246 __O uint32_t MWTD;
sahilmgandhi 18:6a4db94011d3 247 __I uint32_t MRDD;
sahilmgandhi 18:6a4db94011d3 248 __I uint32_t MIND;
sahilmgandhi 18:6a4db94011d3 249 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 250 __IO uint32_t SA0;
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t SA1;
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t SA2;
sahilmgandhi 18:6a4db94011d3 253 uint32_t RESERVED1[45];
sahilmgandhi 18:6a4db94011d3 254 __IO uint32_t Command; /* Control Registers */
sahilmgandhi 18:6a4db94011d3 255 __I uint32_t Status;
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t RxDescriptor;
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t RxStatus;
sahilmgandhi 18:6a4db94011d3 258 __IO uint32_t RxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 259 __I uint32_t RxProduceIndex;
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t RxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t TxDescriptor;
sahilmgandhi 18:6a4db94011d3 262 __IO uint32_t TxStatus;
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t TxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 264 __IO uint32_t TxProduceIndex;
sahilmgandhi 18:6a4db94011d3 265 __I uint32_t TxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 266 uint32_t RESERVED2[10];
sahilmgandhi 18:6a4db94011d3 267 __I uint32_t TSV0;
sahilmgandhi 18:6a4db94011d3 268 __I uint32_t TSV1;
sahilmgandhi 18:6a4db94011d3 269 __I uint32_t RSV;
sahilmgandhi 18:6a4db94011d3 270 uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t FlowControlCounter;
sahilmgandhi 18:6a4db94011d3 272 __I uint32_t FlowControlStatus;
sahilmgandhi 18:6a4db94011d3 273 uint32_t RESERVED4[34];
sahilmgandhi 18:6a4db94011d3 274 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
sahilmgandhi 18:6a4db94011d3 275 __I uint32_t RxFilterWoLStatus;
sahilmgandhi 18:6a4db94011d3 276 __O uint32_t RxFilterWoLClear;
sahilmgandhi 18:6a4db94011d3 277 uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t HashFilterL;
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t HashFilterH;
sahilmgandhi 18:6a4db94011d3 280 uint32_t RESERVED6[882];
sahilmgandhi 18:6a4db94011d3 281 __I uint32_t IntStatus; /* Module Control Registers */
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 283 __O uint32_t IntClear;
sahilmgandhi 18:6a4db94011d3 284 __O uint32_t IntSet;
sahilmgandhi 18:6a4db94011d3 285 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 286 __IO uint32_t PowerDown;
sahilmgandhi 18:6a4db94011d3 287 uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 288 __IO uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 289 } LPC_EMAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /*------------- LCD controller (LCD) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 292 typedef struct
sahilmgandhi 18:6a4db94011d3 293 {
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t TIMH; /* LCD Registers */
sahilmgandhi 18:6a4db94011d3 295 __IO uint32_t TIMV;
sahilmgandhi 18:6a4db94011d3 296 __IO uint32_t POL;
sahilmgandhi 18:6a4db94011d3 297 __IO uint32_t LE;
sahilmgandhi 18:6a4db94011d3 298 __IO uint32_t UPBASE;
sahilmgandhi 18:6a4db94011d3 299 __IO uint32_t LPBASE;
sahilmgandhi 18:6a4db94011d3 300 __IO uint32_t CTRL;
sahilmgandhi 18:6a4db94011d3 301 __IO uint32_t INTMSK;
sahilmgandhi 18:6a4db94011d3 302 __I uint32_t INTRAW;
sahilmgandhi 18:6a4db94011d3 303 __I uint32_t INTSTAT;
sahilmgandhi 18:6a4db94011d3 304 __O uint32_t INTCLR;
sahilmgandhi 18:6a4db94011d3 305 __I uint32_t UPCURR;
sahilmgandhi 18:6a4db94011d3 306 __I uint32_t LPCURR;
sahilmgandhi 18:6a4db94011d3 307 uint32_t RESERVED0[115];
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t PAL[128];
sahilmgandhi 18:6a4db94011d3 309 uint32_t RESERVED1[256];
sahilmgandhi 18:6a4db94011d3 310 __IO uint32_t CRSR_IMG[256];
sahilmgandhi 18:6a4db94011d3 311 __IO uint32_t CRSR_CTRL;
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t CRSR_CFG;
sahilmgandhi 18:6a4db94011d3 313 __IO uint32_t CRSR_PAL0;
sahilmgandhi 18:6a4db94011d3 314 __IO uint32_t CRSR_PAL1;
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t CRSR_XY;
sahilmgandhi 18:6a4db94011d3 316 __IO uint32_t CRSR_CLIP;
sahilmgandhi 18:6a4db94011d3 317 uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 318 __IO uint32_t CRSR_INTMSK;
sahilmgandhi 18:6a4db94011d3 319 __O uint32_t CRSR_INTCLR;
sahilmgandhi 18:6a4db94011d3 320 __I uint32_t CRSR_INTRAW;
sahilmgandhi 18:6a4db94011d3 321 __I uint32_t CRSR_INTSTAT;
sahilmgandhi 18:6a4db94011d3 322 } LPC_LCD_TypeDef;
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /*------------- Universal Serial Bus (USB) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 325 typedef struct
sahilmgandhi 18:6a4db94011d3 326 {
sahilmgandhi 18:6a4db94011d3 327 __I uint32_t Revision; /* USB Host Registers */
sahilmgandhi 18:6a4db94011d3 328 __IO uint32_t Control;
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t CommandStatus;
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t InterruptStatus;
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t InterruptEnable;
sahilmgandhi 18:6a4db94011d3 332 __IO uint32_t InterruptDisable;
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t HCCA;
sahilmgandhi 18:6a4db94011d3 334 __I uint32_t PeriodCurrentED;
sahilmgandhi 18:6a4db94011d3 335 __IO uint32_t ControlHeadED;
sahilmgandhi 18:6a4db94011d3 336 __IO uint32_t ControlCurrentED;
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t BulkHeadED;
sahilmgandhi 18:6a4db94011d3 338 __IO uint32_t BulkCurrentED;
sahilmgandhi 18:6a4db94011d3 339 __I uint32_t DoneHead;
sahilmgandhi 18:6a4db94011d3 340 __IO uint32_t FmInterval;
sahilmgandhi 18:6a4db94011d3 341 __I uint32_t FmRemaining;
sahilmgandhi 18:6a4db94011d3 342 __I uint32_t FmNumber;
sahilmgandhi 18:6a4db94011d3 343 __IO uint32_t PeriodicStart;
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t LSTreshold;
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t RhDescriptorA;
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t RhDescriptorB;
sahilmgandhi 18:6a4db94011d3 347 __IO uint32_t RhStatus;
sahilmgandhi 18:6a4db94011d3 348 __IO uint32_t RhPortStatus1;
sahilmgandhi 18:6a4db94011d3 349 __IO uint32_t RhPortStatus2;
sahilmgandhi 18:6a4db94011d3 350 uint32_t RESERVED0[40];
sahilmgandhi 18:6a4db94011d3 351 __I uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 __I uint32_t IntSt; /* USB On-The-Go Registers */
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t IntEn;
sahilmgandhi 18:6a4db94011d3 355 __O uint32_t IntSet;
sahilmgandhi 18:6a4db94011d3 356 __O uint32_t IntClr;
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t StCtrl;
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t Tmr;
sahilmgandhi 18:6a4db94011d3 359 uint32_t RESERVED1[58];
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t DevIntEn;
sahilmgandhi 18:6a4db94011d3 363 __O uint32_t DevIntClr;
sahilmgandhi 18:6a4db94011d3 364 __O uint32_t DevIntSet;
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 __O uint32_t CmdCode; /* USB Device SIE Command Registers */
sahilmgandhi 18:6a4db94011d3 367 __I uint32_t CmdData;
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 __I uint32_t RxData; /* USB Device Transfer Registers */
sahilmgandhi 18:6a4db94011d3 370 __O uint32_t TxData;
sahilmgandhi 18:6a4db94011d3 371 __I uint32_t RxPLen;
sahilmgandhi 18:6a4db94011d3 372 __O uint32_t TxPLen;
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t Ctrl;
sahilmgandhi 18:6a4db94011d3 374 __O uint32_t DevIntPri;
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t EpIntEn;
sahilmgandhi 18:6a4db94011d3 378 __O uint32_t EpIntClr;
sahilmgandhi 18:6a4db94011d3 379 __O uint32_t EpIntSet;
sahilmgandhi 18:6a4db94011d3 380 __O uint32_t EpIntPri;
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
sahilmgandhi 18:6a4db94011d3 383 __O uint32_t EpInd;
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t MaxPSize;
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 __I uint32_t DMARSt; /* USB Device DMA Registers */
sahilmgandhi 18:6a4db94011d3 387 __O uint32_t DMARClr;
sahilmgandhi 18:6a4db94011d3 388 __O uint32_t DMARSet;
sahilmgandhi 18:6a4db94011d3 389 uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t UDCAH;
sahilmgandhi 18:6a4db94011d3 391 __I uint32_t EpDMASt;
sahilmgandhi 18:6a4db94011d3 392 __O uint32_t EpDMAEn;
sahilmgandhi 18:6a4db94011d3 393 __O uint32_t EpDMADis;
sahilmgandhi 18:6a4db94011d3 394 __I uint32_t DMAIntSt;
sahilmgandhi 18:6a4db94011d3 395 __IO uint32_t DMAIntEn;
sahilmgandhi 18:6a4db94011d3 396 uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 397 __I uint32_t EoTIntSt;
sahilmgandhi 18:6a4db94011d3 398 __O uint32_t EoTIntClr;
sahilmgandhi 18:6a4db94011d3 399 __O uint32_t EoTIntSet;
sahilmgandhi 18:6a4db94011d3 400 __I uint32_t NDDRIntSt;
sahilmgandhi 18:6a4db94011d3 401 __O uint32_t NDDRIntClr;
sahilmgandhi 18:6a4db94011d3 402 __O uint32_t NDDRIntSet;
sahilmgandhi 18:6a4db94011d3 403 __I uint32_t SysErrIntSt;
sahilmgandhi 18:6a4db94011d3 404 __O uint32_t SysErrIntClr;
sahilmgandhi 18:6a4db94011d3 405 __O uint32_t SysErrIntSet;
sahilmgandhi 18:6a4db94011d3 406 uint32_t RESERVED4[15];
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 union {
sahilmgandhi 18:6a4db94011d3 409 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
sahilmgandhi 18:6a4db94011d3 410 __O uint32_t I2C_TX;
sahilmgandhi 18:6a4db94011d3 411 };
sahilmgandhi 18:6a4db94011d3 412 __IO uint32_t I2C_STS;
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t I2C_CTL;
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t I2C_CLKHI;
sahilmgandhi 18:6a4db94011d3 415 __O uint32_t I2C_CLKLO;
sahilmgandhi 18:6a4db94011d3 416 uint32_t RESERVED5[824];
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 union {
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t OTGClkCtrl;
sahilmgandhi 18:6a4db94011d3 421 };
sahilmgandhi 18:6a4db94011d3 422 union {
sahilmgandhi 18:6a4db94011d3 423 __I uint32_t USBClkSt;
sahilmgandhi 18:6a4db94011d3 424 __I uint32_t OTGClkSt;
sahilmgandhi 18:6a4db94011d3 425 };
sahilmgandhi 18:6a4db94011d3 426 } LPC_USB_TypeDef;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /*------------- CRC Engine (CRC) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 429 typedef struct
sahilmgandhi 18:6a4db94011d3 430 {
sahilmgandhi 18:6a4db94011d3 431 __IO uint32_t MODE;
sahilmgandhi 18:6a4db94011d3 432 __IO uint32_t SEED;
sahilmgandhi 18:6a4db94011d3 433 union {
sahilmgandhi 18:6a4db94011d3 434 __I uint32_t SUM;
sahilmgandhi 18:6a4db94011d3 435 struct {
sahilmgandhi 18:6a4db94011d3 436 __O uint32_t DATA;
sahilmgandhi 18:6a4db94011d3 437 } WR_DATA_DWORD;
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 struct {
sahilmgandhi 18:6a4db94011d3 440 __O uint16_t DATA;
sahilmgandhi 18:6a4db94011d3 441 uint16_t RESERVED;
sahilmgandhi 18:6a4db94011d3 442 }WR_DATA_WORD;
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 struct {
sahilmgandhi 18:6a4db94011d3 445 __O uint8_t DATA;
sahilmgandhi 18:6a4db94011d3 446 uint8_t RESERVED[3];
sahilmgandhi 18:6a4db94011d3 447 }WR_DATA_BYTE;
sahilmgandhi 18:6a4db94011d3 448 };
sahilmgandhi 18:6a4db94011d3 449 } LPC_CRC_TypeDef;
sahilmgandhi 18:6a4db94011d3 450 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
sahilmgandhi 18:6a4db94011d3 451 typedef struct
sahilmgandhi 18:6a4db94011d3 452 {
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t DIR;
sahilmgandhi 18:6a4db94011d3 454 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t MASK;
sahilmgandhi 18:6a4db94011d3 456 __IO uint32_t PIN;
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t SET;
sahilmgandhi 18:6a4db94011d3 458 __O uint32_t CLR;
sahilmgandhi 18:6a4db94011d3 459 } LPC_GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 typedef struct
sahilmgandhi 18:6a4db94011d3 462 {
sahilmgandhi 18:6a4db94011d3 463 __I uint32_t IntStatus;
sahilmgandhi 18:6a4db94011d3 464 __I uint32_t IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 465 __I uint32_t IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 466 __O uint32_t IO0IntClr;
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t IO0IntEnR;
sahilmgandhi 18:6a4db94011d3 468 __IO uint32_t IO0IntEnF;
sahilmgandhi 18:6a4db94011d3 469 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 470 __I uint32_t IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 471 __I uint32_t IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 472 __O uint32_t IO2IntClr;
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t IO2IntEnR;
sahilmgandhi 18:6a4db94011d3 474 __IO uint32_t IO2IntEnF;
sahilmgandhi 18:6a4db94011d3 475 } LPC_GPIOINT_TypeDef;
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /*------------- External Memory Controller (EMC) -----------------------------*/
sahilmgandhi 18:6a4db94011d3 478 typedef struct
sahilmgandhi 18:6a4db94011d3 479 {
sahilmgandhi 18:6a4db94011d3 480 __IO uint32_t Control;
sahilmgandhi 18:6a4db94011d3 481 __I uint32_t Status;
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t Config;
sahilmgandhi 18:6a4db94011d3 483 uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t DynamicControl;
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t DynamicRefresh;
sahilmgandhi 18:6a4db94011d3 486 __IO uint32_t DynamicReadConfig;
sahilmgandhi 18:6a4db94011d3 487 uint32_t RESERVED1[1];
sahilmgandhi 18:6a4db94011d3 488 __IO uint32_t DynamicRP;
sahilmgandhi 18:6a4db94011d3 489 __IO uint32_t DynamicRAS;
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t DynamicSREX;
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t DynamicAPR;
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t DynamicDAL;
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t DynamicWR;
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t DynamicRC;
sahilmgandhi 18:6a4db94011d3 495 __IO uint32_t DynamicRFC;
sahilmgandhi 18:6a4db94011d3 496 __IO uint32_t DynamicXSR;
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t DynamicRRD;
sahilmgandhi 18:6a4db94011d3 498 __IO uint32_t DynamicMRD;
sahilmgandhi 18:6a4db94011d3 499 uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 500 __IO uint32_t StaticExtendedWait;
sahilmgandhi 18:6a4db94011d3 501 uint32_t RESERVED3[31];
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t DynamicConfig0;
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t DynamicRasCas0;
sahilmgandhi 18:6a4db94011d3 504 uint32_t RESERVED4[6];
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t DynamicConfig1;
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t DynamicRasCas1;
sahilmgandhi 18:6a4db94011d3 507 uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t DynamicConfig2;
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t DynamicRasCas2;
sahilmgandhi 18:6a4db94011d3 510 uint32_t RESERVED6[6];
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t DynamicConfig3;
sahilmgandhi 18:6a4db94011d3 512 __IO uint32_t DynamicRasCas3;
sahilmgandhi 18:6a4db94011d3 513 uint32_t RESERVED7[38];
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t StaticConfig0;
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t StaticWaitWen0;
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t StaticWaitOen0;
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t StaticWaitRd0;
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t StaticWaitPage0;
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t StaticWaitWr0;
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t StaticWaitTurn0;
sahilmgandhi 18:6a4db94011d3 521 uint32_t RESERVED8[1];
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t StaticConfig1;
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t StaticWaitWen1;
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t StaticWaitOen1;
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t StaticWaitRd1;
sahilmgandhi 18:6a4db94011d3 526 __IO uint32_t StaticWaitPage1;
sahilmgandhi 18:6a4db94011d3 527 __IO uint32_t StaticWaitWr1;
sahilmgandhi 18:6a4db94011d3 528 __IO uint32_t StaticWaitTurn1;
sahilmgandhi 18:6a4db94011d3 529 uint32_t RESERVED9[1];
sahilmgandhi 18:6a4db94011d3 530 __IO uint32_t StaticConfig2;
sahilmgandhi 18:6a4db94011d3 531 __IO uint32_t StaticWaitWen2;
sahilmgandhi 18:6a4db94011d3 532 __IO uint32_t StaticWaitOen2;
sahilmgandhi 18:6a4db94011d3 533 __IO uint32_t StaticWaitRd2;
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t StaticWaitPage2;
sahilmgandhi 18:6a4db94011d3 535 __IO uint32_t StaticWaitWr2;
sahilmgandhi 18:6a4db94011d3 536 __IO uint32_t StaticWaitTurn2;
sahilmgandhi 18:6a4db94011d3 537 uint32_t RESERVED10[1];
sahilmgandhi 18:6a4db94011d3 538 __IO uint32_t StaticConfig3;
sahilmgandhi 18:6a4db94011d3 539 __IO uint32_t StaticWaitWen3;
sahilmgandhi 18:6a4db94011d3 540 __IO uint32_t StaticWaitOen3;
sahilmgandhi 18:6a4db94011d3 541 __IO uint32_t StaticWaitRd3;
sahilmgandhi 18:6a4db94011d3 542 __IO uint32_t StaticWaitPage3;
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t StaticWaitWr3;
sahilmgandhi 18:6a4db94011d3 544 __IO uint32_t StaticWaitTurn3;
sahilmgandhi 18:6a4db94011d3 545 } LPC_EMC_TypeDef;
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 548 typedef struct
sahilmgandhi 18:6a4db94011d3 549 {
sahilmgandhi 18:6a4db94011d3 550 __IO uint8_t MOD;
sahilmgandhi 18:6a4db94011d3 551 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 553 __O uint8_t FEED;
sahilmgandhi 18:6a4db94011d3 554 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 555 __I uint32_t TV;
sahilmgandhi 18:6a4db94011d3 556 uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t WARNINT;
sahilmgandhi 18:6a4db94011d3 558 __IO uint32_t WINDOW;
sahilmgandhi 18:6a4db94011d3 559 } LPC_WDT_TypeDef;
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /*------------- Timer (TIM) --------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 562 typedef struct
sahilmgandhi 18:6a4db94011d3 563 {
sahilmgandhi 18:6a4db94011d3 564 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
sahilmgandhi 18:6a4db94011d3 565 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 566 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
sahilmgandhi 18:6a4db94011d3 568 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
sahilmgandhi 18:6a4db94011d3 569 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
sahilmgandhi 18:6a4db94011d3 573 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 575 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
sahilmgandhi 18:6a4db94011d3 576 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
sahilmgandhi 18:6a4db94011d3 577 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
sahilmgandhi 18:6a4db94011d3 579 uint32_t RESERVED1[12];
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 581 } LPC_TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 585 typedef struct
sahilmgandhi 18:6a4db94011d3 586 {
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 589 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
sahilmgandhi 18:6a4db94011d3 591 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
sahilmgandhi 18:6a4db94011d3 592 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 593 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
sahilmgandhi 18:6a4db94011d3 594 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
sahilmgandhi 18:6a4db94011d3 595 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 598 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
sahilmgandhi 18:6a4db94011d3 599 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
sahilmgandhi 18:6a4db94011d3 600 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
sahilmgandhi 18:6a4db94011d3 601 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
sahilmgandhi 18:6a4db94011d3 602 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 603 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
sahilmgandhi 18:6a4db94011d3 604 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
sahilmgandhi 18:6a4db94011d3 605 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
sahilmgandhi 18:6a4db94011d3 608 uint32_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 610 } LPC_PWM_TypeDef;
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
sahilmgandhi 18:6a4db94011d3 613 /* There are three types of UARTs on the chip:
sahilmgandhi 18:6a4db94011d3 614 (1) UART0,UART2, and UART3 are the standard UART.
sahilmgandhi 18:6a4db94011d3 615 (2) UART1 is the standard with modem capability.
sahilmgandhi 18:6a4db94011d3 616 (3) USART(UART4) is the sync/async UART with smart card capability.
sahilmgandhi 18:6a4db94011d3 617 More details can be found on the Users Manual. */
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 #if 0
sahilmgandhi 18:6a4db94011d3 620 typedef struct
sahilmgandhi 18:6a4db94011d3 621 {
sahilmgandhi 18:6a4db94011d3 622 union {
sahilmgandhi 18:6a4db94011d3 623 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 624 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 625 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 626 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 627 };
sahilmgandhi 18:6a4db94011d3 628 union {
sahilmgandhi 18:6a4db94011d3 629 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 631 };
sahilmgandhi 18:6a4db94011d3 632 union {
sahilmgandhi 18:6a4db94011d3 633 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 634 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 635 };
sahilmgandhi 18:6a4db94011d3 636 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 637 uint8_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 638 __I uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 639 uint8_t RESERVED2[7];
sahilmgandhi 18:6a4db94011d3 640 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 641 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 643 __IO uint8_t ICR;
sahilmgandhi 18:6a4db94011d3 644 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 645 __IO uint8_t FDR;
sahilmgandhi 18:6a4db94011d3 646 uint8_t RESERVED5[7];
sahilmgandhi 18:6a4db94011d3 647 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 648 uint8_t RESERVED6[39];
sahilmgandhi 18:6a4db94011d3 649 __I uint8_t FIFOLVL;
sahilmgandhi 18:6a4db94011d3 650 } LPC_UART_TypeDef;
sahilmgandhi 18:6a4db94011d3 651 #else
sahilmgandhi 18:6a4db94011d3 652 typedef struct
sahilmgandhi 18:6a4db94011d3 653 {
sahilmgandhi 18:6a4db94011d3 654 union
sahilmgandhi 18:6a4db94011d3 655 {
sahilmgandhi 18:6a4db94011d3 656 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 657 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 658 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 659 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 660 };
sahilmgandhi 18:6a4db94011d3 661 union
sahilmgandhi 18:6a4db94011d3 662 {
sahilmgandhi 18:6a4db94011d3 663 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 664 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 665 };
sahilmgandhi 18:6a4db94011d3 666 union
sahilmgandhi 18:6a4db94011d3 667 {
sahilmgandhi 18:6a4db94011d3 668 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 669 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 670 };
sahilmgandhi 18:6a4db94011d3 671 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 672 uint8_t RESERVED1[7];//Reserved
sahilmgandhi 18:6a4db94011d3 673 __I uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 674 uint8_t RESERVED2[7];//Reserved
sahilmgandhi 18:6a4db94011d3 675 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 676 uint8_t RESERVED3[3];//Reserved
sahilmgandhi 18:6a4db94011d3 677 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 678 __IO uint8_t ICR;
sahilmgandhi 18:6a4db94011d3 679 uint8_t RESERVED4[3];//Reserved
sahilmgandhi 18:6a4db94011d3 680 __IO uint8_t FDR;
sahilmgandhi 18:6a4db94011d3 681 uint8_t RESERVED5[7];//Reserved
sahilmgandhi 18:6a4db94011d3 682 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 683 uint8_t RESERVED8[27];//Reserved
sahilmgandhi 18:6a4db94011d3 684 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 685 uint8_t RESERVED9[3];//Reserved
sahilmgandhi 18:6a4db94011d3 686 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 687 uint8_t RESERVED10[3];//Reserved
sahilmgandhi 18:6a4db94011d3 688 __IO uint8_t RS485DLY;
sahilmgandhi 18:6a4db94011d3 689 uint8_t RESERVED11[3];//Reserved
sahilmgandhi 18:6a4db94011d3 690 __I uint8_t FIFOLVL;
sahilmgandhi 18:6a4db94011d3 691 }LPC_UART_TypeDef;
sahilmgandhi 18:6a4db94011d3 692 #endif
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 typedef struct
sahilmgandhi 18:6a4db94011d3 696 {
sahilmgandhi 18:6a4db94011d3 697 union {
sahilmgandhi 18:6a4db94011d3 698 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 699 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 700 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 701 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 702 };
sahilmgandhi 18:6a4db94011d3 703 union {
sahilmgandhi 18:6a4db94011d3 704 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 706 };
sahilmgandhi 18:6a4db94011d3 707 union {
sahilmgandhi 18:6a4db94011d3 708 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 709 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 710 };
sahilmgandhi 18:6a4db94011d3 711 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 712 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 713 __IO uint8_t MCR;
sahilmgandhi 18:6a4db94011d3 714 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 715 __I uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 716 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 717 __I uint8_t MSR;
sahilmgandhi 18:6a4db94011d3 718 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 719 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 720 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 721 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 722 uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 723 __IO uint32_t FDR;
sahilmgandhi 18:6a4db94011d3 724 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 725 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 726 uint8_t RESERVED8[27];
sahilmgandhi 18:6a4db94011d3 727 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 728 uint8_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 729 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 730 uint8_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 731 __IO uint8_t RS485DLY;
sahilmgandhi 18:6a4db94011d3 732 uint8_t RESERVED11[3];
sahilmgandhi 18:6a4db94011d3 733 __I uint8_t FIFOLVL;
sahilmgandhi 18:6a4db94011d3 734 } LPC_UART1_TypeDef;
sahilmgandhi 18:6a4db94011d3 735
sahilmgandhi 18:6a4db94011d3 736 typedef struct
sahilmgandhi 18:6a4db94011d3 737 {
sahilmgandhi 18:6a4db94011d3 738 union {
sahilmgandhi 18:6a4db94011d3 739 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 740 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
sahilmgandhi 18:6a4db94011d3 742 };
sahilmgandhi 18:6a4db94011d3 743 union {
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
sahilmgandhi 18:6a4db94011d3 745 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
sahilmgandhi 18:6a4db94011d3 746 };
sahilmgandhi 18:6a4db94011d3 747 union {
sahilmgandhi 18:6a4db94011d3 748 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 749 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
sahilmgandhi 18:6a4db94011d3 750 };
sahilmgandhi 18:6a4db94011d3 751 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 752 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 753 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 754 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
sahilmgandhi 18:6a4db94011d3 756 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 757 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 758 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
sahilmgandhi 18:6a4db94011d3 759 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
sahilmgandhi 18:6a4db94011d3 760 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
sahilmgandhi 18:6a4db94011d3 761 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
sahilmgandhi 18:6a4db94011d3 762 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 763 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
sahilmgandhi 18:6a4db94011d3 764 uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 765 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 766 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 767 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
sahilmgandhi 18:6a4db94011d3 769 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
sahilmgandhi 18:6a4db94011d3 771 uint32_t RESERVED2[989];
sahilmgandhi 18:6a4db94011d3 772 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
sahilmgandhi 18:6a4db94011d3 773 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
sahilmgandhi 18:6a4db94011d3 774 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
sahilmgandhi 18:6a4db94011d3 775 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
sahilmgandhi 18:6a4db94011d3 776 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
sahilmgandhi 18:6a4db94011d3 777 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
sahilmgandhi 18:6a4db94011d3 778 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
sahilmgandhi 18:6a4db94011d3 779 uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 780 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
sahilmgandhi 18:6a4db94011d3 781 } LPC_UART4_TypeDef;
sahilmgandhi 18:6a4db94011d3 782 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
sahilmgandhi 18:6a4db94011d3 783 typedef struct
sahilmgandhi 18:6a4db94011d3 784 {
sahilmgandhi 18:6a4db94011d3 785 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
sahilmgandhi 18:6a4db94011d3 786 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 787 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
sahilmgandhi 18:6a4db94011d3 788 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
sahilmgandhi 18:6a4db94011d3 789 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
sahilmgandhi 18:6a4db94011d3 790 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
sahilmgandhi 18:6a4db94011d3 791 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
sahilmgandhi 18:6a4db94011d3 792 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
sahilmgandhi 18:6a4db94011d3 793 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
sahilmgandhi 18:6a4db94011d3 794 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
sahilmgandhi 18:6a4db94011d3 795 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
sahilmgandhi 18:6a4db94011d3 796 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
sahilmgandhi 18:6a4db94011d3 797 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
sahilmgandhi 18:6a4db94011d3 798 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
sahilmgandhi 18:6a4db94011d3 799 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
sahilmgandhi 18:6a4db94011d3 800 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
sahilmgandhi 18:6a4db94011d3 801 } LPC_I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 804 typedef struct
sahilmgandhi 18:6a4db94011d3 805 {
sahilmgandhi 18:6a4db94011d3 806 __IO uint8_t ILR;
sahilmgandhi 18:6a4db94011d3 807 uint8_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 808 __IO uint8_t CCR;
sahilmgandhi 18:6a4db94011d3 809 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 810 __IO uint8_t CIIR;
sahilmgandhi 18:6a4db94011d3 811 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 812 __IO uint8_t AMR;
sahilmgandhi 18:6a4db94011d3 813 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 814 __I uint32_t CTIME0;
sahilmgandhi 18:6a4db94011d3 815 __I uint32_t CTIME1;
sahilmgandhi 18:6a4db94011d3 816 __I uint32_t CTIME2;
sahilmgandhi 18:6a4db94011d3 817 __IO uint8_t SEC;
sahilmgandhi 18:6a4db94011d3 818 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 819 __IO uint8_t MIN;
sahilmgandhi 18:6a4db94011d3 820 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 821 __IO uint8_t HOUR;
sahilmgandhi 18:6a4db94011d3 822 uint8_t RESERVED6[3];
sahilmgandhi 18:6a4db94011d3 823 __IO uint8_t DOM;
sahilmgandhi 18:6a4db94011d3 824 uint8_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 825 __IO uint8_t DOW;
sahilmgandhi 18:6a4db94011d3 826 uint8_t RESERVED8[3];
sahilmgandhi 18:6a4db94011d3 827 __IO uint16_t DOY;
sahilmgandhi 18:6a4db94011d3 828 uint16_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 829 __IO uint8_t MONTH;
sahilmgandhi 18:6a4db94011d3 830 uint8_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 831 __IO uint16_t YEAR;
sahilmgandhi 18:6a4db94011d3 832 uint16_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 833 __IO uint32_t CALIBRATION;
sahilmgandhi 18:6a4db94011d3 834 __IO uint32_t GPREG0;
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t GPREG1;
sahilmgandhi 18:6a4db94011d3 836 __IO uint32_t GPREG2;
sahilmgandhi 18:6a4db94011d3 837 __IO uint32_t GPREG3;
sahilmgandhi 18:6a4db94011d3 838 __IO uint32_t GPREG4;
sahilmgandhi 18:6a4db94011d3 839 __IO uint8_t RTC_AUXEN;
sahilmgandhi 18:6a4db94011d3 840 uint8_t RESERVED12[3];
sahilmgandhi 18:6a4db94011d3 841 __IO uint8_t RTC_AUX;
sahilmgandhi 18:6a4db94011d3 842 uint8_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 843 __IO uint8_t ALSEC;
sahilmgandhi 18:6a4db94011d3 844 uint8_t RESERVED14[3];
sahilmgandhi 18:6a4db94011d3 845 __IO uint8_t ALMIN;
sahilmgandhi 18:6a4db94011d3 846 uint8_t RESERVED15[3];
sahilmgandhi 18:6a4db94011d3 847 __IO uint8_t ALHOUR;
sahilmgandhi 18:6a4db94011d3 848 uint8_t RESERVED16[3];
sahilmgandhi 18:6a4db94011d3 849 __IO uint8_t ALDOM;
sahilmgandhi 18:6a4db94011d3 850 uint8_t RESERVED17[3];
sahilmgandhi 18:6a4db94011d3 851 __IO uint8_t ALDOW;
sahilmgandhi 18:6a4db94011d3 852 uint8_t RESERVED18[3];
sahilmgandhi 18:6a4db94011d3 853 __IO uint16_t ALDOY;
sahilmgandhi 18:6a4db94011d3 854 uint16_t RESERVED19;
sahilmgandhi 18:6a4db94011d3 855 __IO uint8_t ALMON;
sahilmgandhi 18:6a4db94011d3 856 uint8_t RESERVED20[3];
sahilmgandhi 18:6a4db94011d3 857 __IO uint16_t ALYEAR;
sahilmgandhi 18:6a4db94011d3 858 uint16_t RESERVED21;
sahilmgandhi 18:6a4db94011d3 859 __IO uint32_t ERSTATUS;
sahilmgandhi 18:6a4db94011d3 860 __IO uint32_t ERCONTROL;
sahilmgandhi 18:6a4db94011d3 861 __IO uint32_t ERCOUNTERS;
sahilmgandhi 18:6a4db94011d3 862 uint32_t RESERVED22;
sahilmgandhi 18:6a4db94011d3 863 __IO uint32_t ERFIRSTSTAMP0;
sahilmgandhi 18:6a4db94011d3 864 __IO uint32_t ERFIRSTSTAMP1;
sahilmgandhi 18:6a4db94011d3 865 __IO uint32_t ERFIRSTSTAMP2;
sahilmgandhi 18:6a4db94011d3 866 uint32_t RESERVED23;
sahilmgandhi 18:6a4db94011d3 867 __IO uint32_t ERLASTSTAMP0;
sahilmgandhi 18:6a4db94011d3 868 __IO uint32_t ERLASTSTAMP1;
sahilmgandhi 18:6a4db94011d3 869 __IO uint32_t ERLASTSTAMP2;
sahilmgandhi 18:6a4db94011d3 870 } LPC_RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 871
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 875 typedef struct
sahilmgandhi 18:6a4db94011d3 876 {
sahilmgandhi 18:6a4db94011d3 877 __IO uint32_t P0_0; /* 0x000 */
sahilmgandhi 18:6a4db94011d3 878 __IO uint32_t P0_1;
sahilmgandhi 18:6a4db94011d3 879 __IO uint32_t P0_2;
sahilmgandhi 18:6a4db94011d3 880 __IO uint32_t P0_3;
sahilmgandhi 18:6a4db94011d3 881 __IO uint32_t P0_4;
sahilmgandhi 18:6a4db94011d3 882 __IO uint32_t P0_5;
sahilmgandhi 18:6a4db94011d3 883 __IO uint32_t P0_6;
sahilmgandhi 18:6a4db94011d3 884 __IO uint32_t P0_7;
sahilmgandhi 18:6a4db94011d3 885
sahilmgandhi 18:6a4db94011d3 886 __IO uint32_t P0_8; /* 0x020 */
sahilmgandhi 18:6a4db94011d3 887 __IO uint32_t P0_9;
sahilmgandhi 18:6a4db94011d3 888 __IO uint32_t P0_10;
sahilmgandhi 18:6a4db94011d3 889 __IO uint32_t P0_11;
sahilmgandhi 18:6a4db94011d3 890 __IO uint32_t P0_12;
sahilmgandhi 18:6a4db94011d3 891 __IO uint32_t P0_13;
sahilmgandhi 18:6a4db94011d3 892 __IO uint32_t P0_14;
sahilmgandhi 18:6a4db94011d3 893 __IO uint32_t P0_15;
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 __IO uint32_t P0_16; /* 0x040 */
sahilmgandhi 18:6a4db94011d3 896 __IO uint32_t P0_17;
sahilmgandhi 18:6a4db94011d3 897 __IO uint32_t P0_18;
sahilmgandhi 18:6a4db94011d3 898 __IO uint32_t P0_19;
sahilmgandhi 18:6a4db94011d3 899 __IO uint32_t P0_20;
sahilmgandhi 18:6a4db94011d3 900 __IO uint32_t P0_21;
sahilmgandhi 18:6a4db94011d3 901 __IO uint32_t P0_22;
sahilmgandhi 18:6a4db94011d3 902 __IO uint32_t P0_23;
sahilmgandhi 18:6a4db94011d3 903
sahilmgandhi 18:6a4db94011d3 904 __IO uint32_t P0_24; /* 0x060 */
sahilmgandhi 18:6a4db94011d3 905 __IO uint32_t P0_25;
sahilmgandhi 18:6a4db94011d3 906 __IO uint32_t P0_26;
sahilmgandhi 18:6a4db94011d3 907 __IO uint32_t P0_27;
sahilmgandhi 18:6a4db94011d3 908 __IO uint32_t P0_28;
sahilmgandhi 18:6a4db94011d3 909 __IO uint32_t P0_29;
sahilmgandhi 18:6a4db94011d3 910 __IO uint32_t P0_30;
sahilmgandhi 18:6a4db94011d3 911 __IO uint32_t P0_31;
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 __IO uint32_t P1_0; /* 0x080 */
sahilmgandhi 18:6a4db94011d3 914 __IO uint32_t P1_1;
sahilmgandhi 18:6a4db94011d3 915 __IO uint32_t P1_2;
sahilmgandhi 18:6a4db94011d3 916 __IO uint32_t P1_3;
sahilmgandhi 18:6a4db94011d3 917 __IO uint32_t P1_4;
sahilmgandhi 18:6a4db94011d3 918 __IO uint32_t P1_5;
sahilmgandhi 18:6a4db94011d3 919 __IO uint32_t P1_6;
sahilmgandhi 18:6a4db94011d3 920 __IO uint32_t P1_7;
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 __IO uint32_t P1_8; /* 0x0A0 */
sahilmgandhi 18:6a4db94011d3 923 __IO uint32_t P1_9;
sahilmgandhi 18:6a4db94011d3 924 __IO uint32_t P1_10;
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t P1_11;
sahilmgandhi 18:6a4db94011d3 926 __IO uint32_t P1_12;
sahilmgandhi 18:6a4db94011d3 927 __IO uint32_t P1_13;
sahilmgandhi 18:6a4db94011d3 928 __IO uint32_t P1_14;
sahilmgandhi 18:6a4db94011d3 929 __IO uint32_t P1_15;
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 __IO uint32_t P1_16; /* 0x0C0 */
sahilmgandhi 18:6a4db94011d3 932 __IO uint32_t P1_17;
sahilmgandhi 18:6a4db94011d3 933 __IO uint32_t P1_18;
sahilmgandhi 18:6a4db94011d3 934 __IO uint32_t P1_19;
sahilmgandhi 18:6a4db94011d3 935 __IO uint32_t P1_20;
sahilmgandhi 18:6a4db94011d3 936 __IO uint32_t P1_21;
sahilmgandhi 18:6a4db94011d3 937 __IO uint32_t P1_22;
sahilmgandhi 18:6a4db94011d3 938 __IO uint32_t P1_23;
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 __IO uint32_t P1_24; /* 0x0E0 */
sahilmgandhi 18:6a4db94011d3 941 __IO uint32_t P1_25;
sahilmgandhi 18:6a4db94011d3 942 __IO uint32_t P1_26;
sahilmgandhi 18:6a4db94011d3 943 __IO uint32_t P1_27;
sahilmgandhi 18:6a4db94011d3 944 __IO uint32_t P1_28;
sahilmgandhi 18:6a4db94011d3 945 __IO uint32_t P1_29;
sahilmgandhi 18:6a4db94011d3 946 __IO uint32_t P1_30;
sahilmgandhi 18:6a4db94011d3 947 __IO uint32_t P1_31;
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 __IO uint32_t P2_0; /* 0x100 */
sahilmgandhi 18:6a4db94011d3 950 __IO uint32_t P2_1;
sahilmgandhi 18:6a4db94011d3 951 __IO uint32_t P2_2;
sahilmgandhi 18:6a4db94011d3 952 __IO uint32_t P2_3;
sahilmgandhi 18:6a4db94011d3 953 __IO uint32_t P2_4;
sahilmgandhi 18:6a4db94011d3 954 __IO uint32_t P2_5;
sahilmgandhi 18:6a4db94011d3 955 __IO uint32_t P2_6;
sahilmgandhi 18:6a4db94011d3 956 __IO uint32_t P2_7;
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958 __IO uint32_t P2_8; /* 0x120 */
sahilmgandhi 18:6a4db94011d3 959 __IO uint32_t P2_9;
sahilmgandhi 18:6a4db94011d3 960 __IO uint32_t P2_10;
sahilmgandhi 18:6a4db94011d3 961 __IO uint32_t P2_11;
sahilmgandhi 18:6a4db94011d3 962 __IO uint32_t P2_12;
sahilmgandhi 18:6a4db94011d3 963 __IO uint32_t P2_13;
sahilmgandhi 18:6a4db94011d3 964 __IO uint32_t P2_14;
sahilmgandhi 18:6a4db94011d3 965 __IO uint32_t P2_15;
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 __IO uint32_t P2_16; /* 0x140 */
sahilmgandhi 18:6a4db94011d3 968 __IO uint32_t P2_17;
sahilmgandhi 18:6a4db94011d3 969 __IO uint32_t P2_18;
sahilmgandhi 18:6a4db94011d3 970 __IO uint32_t P2_19;
sahilmgandhi 18:6a4db94011d3 971 __IO uint32_t P2_20;
sahilmgandhi 18:6a4db94011d3 972 __IO uint32_t P2_21;
sahilmgandhi 18:6a4db94011d3 973 __IO uint32_t P2_22;
sahilmgandhi 18:6a4db94011d3 974 __IO uint32_t P2_23;
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 __IO uint32_t P2_24; /* 0x160 */
sahilmgandhi 18:6a4db94011d3 977 __IO uint32_t P2_25;
sahilmgandhi 18:6a4db94011d3 978 __IO uint32_t P2_26;
sahilmgandhi 18:6a4db94011d3 979 __IO uint32_t P2_27;
sahilmgandhi 18:6a4db94011d3 980 __IO uint32_t P2_28;
sahilmgandhi 18:6a4db94011d3 981 __IO uint32_t P2_29;
sahilmgandhi 18:6a4db94011d3 982 __IO uint32_t P2_30;
sahilmgandhi 18:6a4db94011d3 983 __IO uint32_t P2_31;
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 __IO uint32_t P3_0; /* 0x180 */
sahilmgandhi 18:6a4db94011d3 986 __IO uint32_t P3_1;
sahilmgandhi 18:6a4db94011d3 987 __IO uint32_t P3_2;
sahilmgandhi 18:6a4db94011d3 988 __IO uint32_t P3_3;
sahilmgandhi 18:6a4db94011d3 989 __IO uint32_t P3_4;
sahilmgandhi 18:6a4db94011d3 990 __IO uint32_t P3_5;
sahilmgandhi 18:6a4db94011d3 991 __IO uint32_t P3_6;
sahilmgandhi 18:6a4db94011d3 992 __IO uint32_t P3_7;
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 __IO uint32_t P3_8; /* 0x1A0 */
sahilmgandhi 18:6a4db94011d3 995 __IO uint32_t P3_9;
sahilmgandhi 18:6a4db94011d3 996 __IO uint32_t P3_10;
sahilmgandhi 18:6a4db94011d3 997 __IO uint32_t P3_11;
sahilmgandhi 18:6a4db94011d3 998 __IO uint32_t P3_12;
sahilmgandhi 18:6a4db94011d3 999 __IO uint32_t P3_13;
sahilmgandhi 18:6a4db94011d3 1000 __IO uint32_t P3_14;
sahilmgandhi 18:6a4db94011d3 1001 __IO uint32_t P3_15;
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 __IO uint32_t P3_16; /* 0x1C0 */
sahilmgandhi 18:6a4db94011d3 1004 __IO uint32_t P3_17;
sahilmgandhi 18:6a4db94011d3 1005 __IO uint32_t P3_18;
sahilmgandhi 18:6a4db94011d3 1006 __IO uint32_t P3_19;
sahilmgandhi 18:6a4db94011d3 1007 __IO uint32_t P3_20;
sahilmgandhi 18:6a4db94011d3 1008 __IO uint32_t P3_21;
sahilmgandhi 18:6a4db94011d3 1009 __IO uint32_t P3_22;
sahilmgandhi 18:6a4db94011d3 1010 __IO uint32_t P3_23;
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 __IO uint32_t P3_24; /* 0x1E0 */
sahilmgandhi 18:6a4db94011d3 1013 __IO uint32_t P3_25;
sahilmgandhi 18:6a4db94011d3 1014 __IO uint32_t P3_26;
sahilmgandhi 18:6a4db94011d3 1015 __IO uint32_t P3_27;
sahilmgandhi 18:6a4db94011d3 1016 __IO uint32_t P3_28;
sahilmgandhi 18:6a4db94011d3 1017 __IO uint32_t P3_29;
sahilmgandhi 18:6a4db94011d3 1018 __IO uint32_t P3_30;
sahilmgandhi 18:6a4db94011d3 1019 __IO uint32_t P3_31;
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 __IO uint32_t P4_0; /* 0x200 */
sahilmgandhi 18:6a4db94011d3 1022 __IO uint32_t P4_1;
sahilmgandhi 18:6a4db94011d3 1023 __IO uint32_t P4_2;
sahilmgandhi 18:6a4db94011d3 1024 __IO uint32_t P4_3;
sahilmgandhi 18:6a4db94011d3 1025 __IO uint32_t P4_4;
sahilmgandhi 18:6a4db94011d3 1026 __IO uint32_t P4_5;
sahilmgandhi 18:6a4db94011d3 1027 __IO uint32_t P4_6;
sahilmgandhi 18:6a4db94011d3 1028 __IO uint32_t P4_7;
sahilmgandhi 18:6a4db94011d3 1029
sahilmgandhi 18:6a4db94011d3 1030 __IO uint32_t P4_8; /* 0x220 */
sahilmgandhi 18:6a4db94011d3 1031 __IO uint32_t P4_9;
sahilmgandhi 18:6a4db94011d3 1032 __IO uint32_t P4_10;
sahilmgandhi 18:6a4db94011d3 1033 __IO uint32_t P4_11;
sahilmgandhi 18:6a4db94011d3 1034 __IO uint32_t P4_12;
sahilmgandhi 18:6a4db94011d3 1035 __IO uint32_t P4_13;
sahilmgandhi 18:6a4db94011d3 1036 __IO uint32_t P4_14;
sahilmgandhi 18:6a4db94011d3 1037 __IO uint32_t P4_15;
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 __IO uint32_t P4_16; /* 0x240 */
sahilmgandhi 18:6a4db94011d3 1040 __IO uint32_t P4_17;
sahilmgandhi 18:6a4db94011d3 1041 __IO uint32_t P4_18;
sahilmgandhi 18:6a4db94011d3 1042 __IO uint32_t P4_19;
sahilmgandhi 18:6a4db94011d3 1043 __IO uint32_t P4_20;
sahilmgandhi 18:6a4db94011d3 1044 __IO uint32_t P4_21;
sahilmgandhi 18:6a4db94011d3 1045 __IO uint32_t P4_22;
sahilmgandhi 18:6a4db94011d3 1046 __IO uint32_t P4_23;
sahilmgandhi 18:6a4db94011d3 1047
sahilmgandhi 18:6a4db94011d3 1048 __IO uint32_t P4_24; /* 0x260 */
sahilmgandhi 18:6a4db94011d3 1049 __IO uint32_t P4_25;
sahilmgandhi 18:6a4db94011d3 1050 __IO uint32_t P4_26;
sahilmgandhi 18:6a4db94011d3 1051 __IO uint32_t P4_27;
sahilmgandhi 18:6a4db94011d3 1052 __IO uint32_t P4_28;
sahilmgandhi 18:6a4db94011d3 1053 __IO uint32_t P4_29;
sahilmgandhi 18:6a4db94011d3 1054 __IO uint32_t P4_30;
sahilmgandhi 18:6a4db94011d3 1055 __IO uint32_t P4_31;
sahilmgandhi 18:6a4db94011d3 1056
sahilmgandhi 18:6a4db94011d3 1057 __IO uint32_t P5_0; /* 0x280 */
sahilmgandhi 18:6a4db94011d3 1058 __IO uint32_t P5_1;
sahilmgandhi 18:6a4db94011d3 1059 __IO uint32_t P5_2;
sahilmgandhi 18:6a4db94011d3 1060 __IO uint32_t P5_3;
sahilmgandhi 18:6a4db94011d3 1061 __IO uint32_t P5_4; /* 0x290 */
sahilmgandhi 18:6a4db94011d3 1062 } LPC_IOCON_TypeDef;
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066
sahilmgandhi 18:6a4db94011d3 1067
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
sahilmgandhi 18:6a4db94011d3 1070 typedef struct
sahilmgandhi 18:6a4db94011d3 1071 {
sahilmgandhi 18:6a4db94011d3 1072 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
sahilmgandhi 18:6a4db94011d3 1073 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
sahilmgandhi 18:6a4db94011d3 1074 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1075 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
sahilmgandhi 18:6a4db94011d3 1076 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1077 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1078 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1079 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1080 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1081 __IO uint32_t DMACR;
sahilmgandhi 18:6a4db94011d3 1082 } LPC_SSP_TypeDef;
sahilmgandhi 18:6a4db94011d3 1083
sahilmgandhi 18:6a4db94011d3 1084 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 1085 typedef struct
sahilmgandhi 18:6a4db94011d3 1086 {
sahilmgandhi 18:6a4db94011d3 1087 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1088 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1089 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1090 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1091 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
sahilmgandhi 18:6a4db94011d3 1092 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 1093 __IO uint32_t ADTRM;
sahilmgandhi 18:6a4db94011d3 1094 } LPC_ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 1095
sahilmgandhi 18:6a4db94011d3 1096 /*------------- Controller Area Network (CAN) --------------------------------*/
sahilmgandhi 18:6a4db94011d3 1097 typedef struct
sahilmgandhi 18:6a4db94011d3 1098 {
sahilmgandhi 18:6a4db94011d3 1099 __IO uint32_t mask[512]; /* ID Masks */
sahilmgandhi 18:6a4db94011d3 1100 } LPC_CANAF_RAM_TypeDef;
sahilmgandhi 18:6a4db94011d3 1101
sahilmgandhi 18:6a4db94011d3 1102 typedef struct /* Acceptance Filter Registers */
sahilmgandhi 18:6a4db94011d3 1103 {
sahilmgandhi 18:6a4db94011d3 1104 ///Offset: 0x00000000 - Acceptance Filter Register
sahilmgandhi 18:6a4db94011d3 1105 __IO uint32_t AFMR;
sahilmgandhi 18:6a4db94011d3 1106
sahilmgandhi 18:6a4db94011d3 1107 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
sahilmgandhi 18:6a4db94011d3 1108 __IO uint32_t SFF_sa;
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 ///Offset: 0x00000008 - Standard Frame Group Start Address Register
sahilmgandhi 18:6a4db94011d3 1111 __IO uint32_t SFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 ///Offset: 0x0000000C - Extended Frame Start Address Register
sahilmgandhi 18:6a4db94011d3 1114 __IO uint32_t EFF_sa;
sahilmgandhi 18:6a4db94011d3 1115
sahilmgandhi 18:6a4db94011d3 1116 ///Offset: 0x00000010 - Extended Frame Group Start Address Register
sahilmgandhi 18:6a4db94011d3 1117 __IO uint32_t EFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 1118
sahilmgandhi 18:6a4db94011d3 1119 ///Offset: 0x00000014 - End of AF Tables register
sahilmgandhi 18:6a4db94011d3 1120 __IO uint32_t ENDofTable;
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122 ///Offset: 0x00000018 - LUT Error Address register
sahilmgandhi 18:6a4db94011d3 1123 __I uint32_t LUTerrAd;
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 ///Offset: 0x0000001C - LUT Error Register
sahilmgandhi 18:6a4db94011d3 1126 __I uint32_t LUTerr;
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 ///Offset: 0x00000020 - CAN Central Transmit Status Register
sahilmgandhi 18:6a4db94011d3 1129 __IO uint32_t FCANIE;
sahilmgandhi 18:6a4db94011d3 1130
sahilmgandhi 18:6a4db94011d3 1131 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
sahilmgandhi 18:6a4db94011d3 1132 __IO uint32_t FCANIC0;
sahilmgandhi 18:6a4db94011d3 1133
sahilmgandhi 18:6a4db94011d3 1134 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
sahilmgandhi 18:6a4db94011d3 1135 __IO uint32_t FCANIC1;
sahilmgandhi 18:6a4db94011d3 1136 } LPC_CANAF_TypeDef;
sahilmgandhi 18:6a4db94011d3 1137
sahilmgandhi 18:6a4db94011d3 1138 typedef struct /* Central Registers */
sahilmgandhi 18:6a4db94011d3 1139 {
sahilmgandhi 18:6a4db94011d3 1140 __I uint32_t TxSR;
sahilmgandhi 18:6a4db94011d3 1141 __I uint32_t RxSR;
sahilmgandhi 18:6a4db94011d3 1142 __I uint32_t MSR;
sahilmgandhi 18:6a4db94011d3 1143 } LPC_CANCR_TypeDef;
sahilmgandhi 18:6a4db94011d3 1144
sahilmgandhi 18:6a4db94011d3 1145 typedef struct /* Controller Registers */
sahilmgandhi 18:6a4db94011d3 1146 {
sahilmgandhi 18:6a4db94011d3 1147 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
sahilmgandhi 18:6a4db94011d3 1148 __IO uint32_t MOD;
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 ///Offset: 0x00000004 - Command bits that affect the state
sahilmgandhi 18:6a4db94011d3 1151 __O uint32_t CMR;
sahilmgandhi 18:6a4db94011d3 1152
sahilmgandhi 18:6a4db94011d3 1153 ///Offset: 0x00000008 - Global Controller Status and Error Counters
sahilmgandhi 18:6a4db94011d3 1154 __IO uint32_t GSR;
sahilmgandhi 18:6a4db94011d3 1155
sahilmgandhi 18:6a4db94011d3 1156 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
sahilmgandhi 18:6a4db94011d3 1157 __I uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 1158
sahilmgandhi 18:6a4db94011d3 1159 ///Offset: 0x00000010 - Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 1160 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 1161
sahilmgandhi 18:6a4db94011d3 1162 ///Offset: 0x00000014 - Bus Timing Register
sahilmgandhi 18:6a4db94011d3 1163 __IO uint32_t BTR;
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 ///Offset: 0x00000018 - Error Warning Limit
sahilmgandhi 18:6a4db94011d3 1166 __IO uint32_t EWL;
sahilmgandhi 18:6a4db94011d3 1167
sahilmgandhi 18:6a4db94011d3 1168 ///Offset: 0x0000001C - Status Register
sahilmgandhi 18:6a4db94011d3 1169 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 1170
sahilmgandhi 18:6a4db94011d3 1171 ///Offset: 0x00000020 - Receive frame status
sahilmgandhi 18:6a4db94011d3 1172 __IO uint32_t RFS;
sahilmgandhi 18:6a4db94011d3 1173
sahilmgandhi 18:6a4db94011d3 1174 ///Offset: 0x00000024 - Received Identifier
sahilmgandhi 18:6a4db94011d3 1175 __IO uint32_t RID;
sahilmgandhi 18:6a4db94011d3 1176
sahilmgandhi 18:6a4db94011d3 1177 ///Offset: 0x00000028 - Received data bytes 1-4
sahilmgandhi 18:6a4db94011d3 1178 __IO uint32_t RDA;
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 ///Offset: 0x0000002C - Received data bytes 5-8
sahilmgandhi 18:6a4db94011d3 1181 __IO uint32_t RDB;
sahilmgandhi 18:6a4db94011d3 1182
sahilmgandhi 18:6a4db94011d3 1183 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
sahilmgandhi 18:6a4db94011d3 1184 __IO uint32_t TFI1;
sahilmgandhi 18:6a4db94011d3 1185
sahilmgandhi 18:6a4db94011d3 1186 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
sahilmgandhi 18:6a4db94011d3 1187 __IO uint32_t TID1;
sahilmgandhi 18:6a4db94011d3 1188
sahilmgandhi 18:6a4db94011d3 1189 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
sahilmgandhi 18:6a4db94011d3 1190 __IO uint32_t TDA1;
sahilmgandhi 18:6a4db94011d3 1191
sahilmgandhi 18:6a4db94011d3 1192 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
sahilmgandhi 18:6a4db94011d3 1193 __IO uint32_t TDB1;
sahilmgandhi 18:6a4db94011d3 1194
sahilmgandhi 18:6a4db94011d3 1195 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
sahilmgandhi 18:6a4db94011d3 1196 __IO uint32_t TFI2;
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
sahilmgandhi 18:6a4db94011d3 1199 __IO uint32_t TID2;
sahilmgandhi 18:6a4db94011d3 1200
sahilmgandhi 18:6a4db94011d3 1201 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
sahilmgandhi 18:6a4db94011d3 1202 __IO uint32_t TDA2;
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
sahilmgandhi 18:6a4db94011d3 1205 __IO uint32_t TDB2;
sahilmgandhi 18:6a4db94011d3 1206
sahilmgandhi 18:6a4db94011d3 1207 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
sahilmgandhi 18:6a4db94011d3 1208 __IO uint32_t TFI3;
sahilmgandhi 18:6a4db94011d3 1209
sahilmgandhi 18:6a4db94011d3 1210 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
sahilmgandhi 18:6a4db94011d3 1211 __IO uint32_t TID3;
sahilmgandhi 18:6a4db94011d3 1212
sahilmgandhi 18:6a4db94011d3 1213 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
sahilmgandhi 18:6a4db94011d3 1214 __IO uint32_t TDA3;
sahilmgandhi 18:6a4db94011d3 1215
sahilmgandhi 18:6a4db94011d3 1216 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
sahilmgandhi 18:6a4db94011d3 1217 __IO uint32_t TDB3;
sahilmgandhi 18:6a4db94011d3 1218 } LPC_CAN_TypeDef;
sahilmgandhi 18:6a4db94011d3 1219
sahilmgandhi 18:6a4db94011d3 1220 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 1221 typedef struct
sahilmgandhi 18:6a4db94011d3 1222 {
sahilmgandhi 18:6a4db94011d3 1223 __IO uint32_t CR;
sahilmgandhi 18:6a4db94011d3 1224 __IO uint32_t CTRL;
sahilmgandhi 18:6a4db94011d3 1225 __IO uint32_t CNTVAL;
sahilmgandhi 18:6a4db94011d3 1226 } LPC_DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 1227
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1230 typedef struct
sahilmgandhi 18:6a4db94011d3 1231 {
sahilmgandhi 18:6a4db94011d3 1232 __IO uint32_t DAO;
sahilmgandhi 18:6a4db94011d3 1233 __IO uint32_t DAI;
sahilmgandhi 18:6a4db94011d3 1234 __O uint32_t TXFIFO;
sahilmgandhi 18:6a4db94011d3 1235 __I uint32_t RXFIFO;
sahilmgandhi 18:6a4db94011d3 1236 __I uint32_t STATE;
sahilmgandhi 18:6a4db94011d3 1237 __IO uint32_t DMA1;
sahilmgandhi 18:6a4db94011d3 1238 __IO uint32_t DMA2;
sahilmgandhi 18:6a4db94011d3 1239 __IO uint32_t IRQ;
sahilmgandhi 18:6a4db94011d3 1240 __IO uint32_t TXRATE;
sahilmgandhi 18:6a4db94011d3 1241 __IO uint32_t RXRATE;
sahilmgandhi 18:6a4db94011d3 1242 __IO uint32_t TXBITRATE;
sahilmgandhi 18:6a4db94011d3 1243 __IO uint32_t RXBITRATE;
sahilmgandhi 18:6a4db94011d3 1244 __IO uint32_t TXMODE;
sahilmgandhi 18:6a4db94011d3 1245 __IO uint32_t RXMODE;
sahilmgandhi 18:6a4db94011d3 1246 } LPC_I2S_TypeDef;
sahilmgandhi 18:6a4db94011d3 1247
sahilmgandhi 18:6a4db94011d3 1248
sahilmgandhi 18:6a4db94011d3 1249
sahilmgandhi 18:6a4db94011d3 1250
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252
sahilmgandhi 18:6a4db94011d3 1253 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
sahilmgandhi 18:6a4db94011d3 1254 typedef struct
sahilmgandhi 18:6a4db94011d3 1255 {
sahilmgandhi 18:6a4db94011d3 1256 __I uint32_t CON;
sahilmgandhi 18:6a4db94011d3 1257 __O uint32_t CON_SET;
sahilmgandhi 18:6a4db94011d3 1258 __O uint32_t CON_CLR;
sahilmgandhi 18:6a4db94011d3 1259 __I uint32_t CAPCON;
sahilmgandhi 18:6a4db94011d3 1260 __O uint32_t CAPCON_SET;
sahilmgandhi 18:6a4db94011d3 1261 __O uint32_t CAPCON_CLR;
sahilmgandhi 18:6a4db94011d3 1262 __IO uint32_t TC0;
sahilmgandhi 18:6a4db94011d3 1263 __IO uint32_t TC1;
sahilmgandhi 18:6a4db94011d3 1264 __IO uint32_t TC2;
sahilmgandhi 18:6a4db94011d3 1265 __IO uint32_t LIM0;
sahilmgandhi 18:6a4db94011d3 1266 __IO uint32_t LIM1;
sahilmgandhi 18:6a4db94011d3 1267 __IO uint32_t LIM2;
sahilmgandhi 18:6a4db94011d3 1268 __IO uint32_t MAT0;
sahilmgandhi 18:6a4db94011d3 1269 __IO uint32_t MAT1;
sahilmgandhi 18:6a4db94011d3 1270 __IO uint32_t MAT2;
sahilmgandhi 18:6a4db94011d3 1271 __IO uint32_t DT;
sahilmgandhi 18:6a4db94011d3 1272 __IO uint32_t CP;
sahilmgandhi 18:6a4db94011d3 1273 __IO uint32_t CAP0;
sahilmgandhi 18:6a4db94011d3 1274 __IO uint32_t CAP1;
sahilmgandhi 18:6a4db94011d3 1275 __IO uint32_t CAP2;
sahilmgandhi 18:6a4db94011d3 1276 __I uint32_t INTEN;
sahilmgandhi 18:6a4db94011d3 1277 __O uint32_t INTEN_SET;
sahilmgandhi 18:6a4db94011d3 1278 __O uint32_t INTEN_CLR;
sahilmgandhi 18:6a4db94011d3 1279 __I uint32_t CNTCON;
sahilmgandhi 18:6a4db94011d3 1280 __O uint32_t CNTCON_SET;
sahilmgandhi 18:6a4db94011d3 1281 __O uint32_t CNTCON_CLR;
sahilmgandhi 18:6a4db94011d3 1282 __I uint32_t INTF;
sahilmgandhi 18:6a4db94011d3 1283 __O uint32_t INTF_SET;
sahilmgandhi 18:6a4db94011d3 1284 __O uint32_t INTF_CLR;
sahilmgandhi 18:6a4db94011d3 1285 __O uint32_t CAP_CLR;
sahilmgandhi 18:6a4db94011d3 1286 } LPC_MCPWM_TypeDef;
sahilmgandhi 18:6a4db94011d3 1287
sahilmgandhi 18:6a4db94011d3 1288 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
sahilmgandhi 18:6a4db94011d3 1289 typedef struct
sahilmgandhi 18:6a4db94011d3 1290 {
sahilmgandhi 18:6a4db94011d3 1291 __O uint32_t CON;
sahilmgandhi 18:6a4db94011d3 1292 __I uint32_t STAT;
sahilmgandhi 18:6a4db94011d3 1293 __IO uint32_t CONF;
sahilmgandhi 18:6a4db94011d3 1294 __I uint32_t POS;
sahilmgandhi 18:6a4db94011d3 1295 __IO uint32_t MAXPOS;
sahilmgandhi 18:6a4db94011d3 1296 __IO uint32_t CMPOS0;
sahilmgandhi 18:6a4db94011d3 1297 __IO uint32_t CMPOS1;
sahilmgandhi 18:6a4db94011d3 1298 __IO uint32_t CMPOS2;
sahilmgandhi 18:6a4db94011d3 1299 __I uint32_t INXCNT;
sahilmgandhi 18:6a4db94011d3 1300 __IO uint32_t INXCMP0;
sahilmgandhi 18:6a4db94011d3 1301 __IO uint32_t LOAD;
sahilmgandhi 18:6a4db94011d3 1302 __I uint32_t TIME;
sahilmgandhi 18:6a4db94011d3 1303 __I uint32_t VEL;
sahilmgandhi 18:6a4db94011d3 1304 __I uint32_t CAP;
sahilmgandhi 18:6a4db94011d3 1305 __IO uint32_t VELCOMP;
sahilmgandhi 18:6a4db94011d3 1306 __IO uint32_t FILTERPHA;
sahilmgandhi 18:6a4db94011d3 1307 __IO uint32_t FILTERPHB;
sahilmgandhi 18:6a4db94011d3 1308 __IO uint32_t FILTERINX;
sahilmgandhi 18:6a4db94011d3 1309 __IO uint32_t WINDOW;
sahilmgandhi 18:6a4db94011d3 1310 __IO uint32_t INXCMP1;
sahilmgandhi 18:6a4db94011d3 1311 __IO uint32_t INXCMP2;
sahilmgandhi 18:6a4db94011d3 1312 uint32_t RESERVED0[993];
sahilmgandhi 18:6a4db94011d3 1313 __O uint32_t IEC;
sahilmgandhi 18:6a4db94011d3 1314 __O uint32_t IES;
sahilmgandhi 18:6a4db94011d3 1315 __I uint32_t INTSTAT;
sahilmgandhi 18:6a4db94011d3 1316 __I uint32_t IE;
sahilmgandhi 18:6a4db94011d3 1317 __O uint32_t CLR;
sahilmgandhi 18:6a4db94011d3 1318 __O uint32_t SET;
sahilmgandhi 18:6a4db94011d3 1319 } LPC_QEI_TypeDef;
sahilmgandhi 18:6a4db94011d3 1320
sahilmgandhi 18:6a4db94011d3 1321 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/
sahilmgandhi 18:6a4db94011d3 1322 typedef struct
sahilmgandhi 18:6a4db94011d3 1323 {
sahilmgandhi 18:6a4db94011d3 1324 __IO uint32_t POWER;
sahilmgandhi 18:6a4db94011d3 1325 __IO uint32_t CLOCK;
sahilmgandhi 18:6a4db94011d3 1326 __IO uint32_t ARGUMENT;
sahilmgandhi 18:6a4db94011d3 1327 __IO uint32_t COMMAND;
sahilmgandhi 18:6a4db94011d3 1328 __I uint32_t RESP_CMD;
sahilmgandhi 18:6a4db94011d3 1329 __I uint32_t RESP0;
sahilmgandhi 18:6a4db94011d3 1330 __I uint32_t RESP1;
sahilmgandhi 18:6a4db94011d3 1331 __I uint32_t RESP2;
sahilmgandhi 18:6a4db94011d3 1332 __I uint32_t RESP3;
sahilmgandhi 18:6a4db94011d3 1333 __IO uint32_t DATATMR;
sahilmgandhi 18:6a4db94011d3 1334 __IO uint32_t DATALEN;
sahilmgandhi 18:6a4db94011d3 1335 __IO uint32_t DATACTRL;
sahilmgandhi 18:6a4db94011d3 1336 __I uint32_t DATACNT;
sahilmgandhi 18:6a4db94011d3 1337 __I uint32_t STATUS;
sahilmgandhi 18:6a4db94011d3 1338 __O uint32_t CLEAR;
sahilmgandhi 18:6a4db94011d3 1339 __IO uint32_t MASK0;
sahilmgandhi 18:6a4db94011d3 1340 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 1341 __I uint32_t FIFOCNT;
sahilmgandhi 18:6a4db94011d3 1342 uint32_t RESERVED1[13];
sahilmgandhi 18:6a4db94011d3 1343 __IO uint32_t FIFO[16];
sahilmgandhi 18:6a4db94011d3 1344 } LPC_MCI_TypeDef;
sahilmgandhi 18:6a4db94011d3 1345
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347
sahilmgandhi 18:6a4db94011d3 1348
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350
sahilmgandhi 18:6a4db94011d3 1351
sahilmgandhi 18:6a4db94011d3 1352
sahilmgandhi 18:6a4db94011d3 1353
sahilmgandhi 18:6a4db94011d3 1354
sahilmgandhi 18:6a4db94011d3 1355 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 1356 typedef struct
sahilmgandhi 18:6a4db94011d3 1357 {
sahilmgandhi 18:6a4db94011d3 1358 __IO uint32_t CMD; /* 0x0080 */
sahilmgandhi 18:6a4db94011d3 1359 __IO uint32_t ADDR;
sahilmgandhi 18:6a4db94011d3 1360 __IO uint32_t WDATA;
sahilmgandhi 18:6a4db94011d3 1361 __IO uint32_t RDATA;
sahilmgandhi 18:6a4db94011d3 1362 __IO uint32_t WSTATE; /* 0x0090 */
sahilmgandhi 18:6a4db94011d3 1363 __IO uint32_t CLKDIV;
sahilmgandhi 18:6a4db94011d3 1364 __IO uint32_t PWRDWN; /* 0x0098 */
sahilmgandhi 18:6a4db94011d3 1365 uint32_t RESERVED0[975];
sahilmgandhi 18:6a4db94011d3 1366 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
sahilmgandhi 18:6a4db94011d3 1367 __IO uint32_t INT_SET_ENABLE;
sahilmgandhi 18:6a4db94011d3 1368 __IO uint32_t INT_STATUS; /* 0x0FE0 */
sahilmgandhi 18:6a4db94011d3 1369 __IO uint32_t INT_ENABLE;
sahilmgandhi 18:6a4db94011d3 1370 __IO uint32_t INT_CLR_STATUS;
sahilmgandhi 18:6a4db94011d3 1371 __IO uint32_t INT_SET_STATUS;
sahilmgandhi 18:6a4db94011d3 1372 } LPC_EEPROM_TypeDef;
sahilmgandhi 18:6a4db94011d3 1373
sahilmgandhi 18:6a4db94011d3 1374
sahilmgandhi 18:6a4db94011d3 1375 /*------------- COMPARATOR ----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1376
sahilmgandhi 18:6a4db94011d3 1377 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
sahilmgandhi 18:6a4db94011d3 1378 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
sahilmgandhi 18:6a4db94011d3 1379 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
sahilmgandhi 18:6a4db94011d3 1380 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
sahilmgandhi 18:6a4db94011d3 1381 } LPC_COMPARATOR_Type;
sahilmgandhi 18:6a4db94011d3 1382
sahilmgandhi 18:6a4db94011d3 1383
sahilmgandhi 18:6a4db94011d3 1384 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 1385 #pragma no_anon_unions
sahilmgandhi 18:6a4db94011d3 1386 #endif
sahilmgandhi 18:6a4db94011d3 1387
sahilmgandhi 18:6a4db94011d3 1388 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1389 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 1390 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1391 /* Base addresses */
sahilmgandhi 18:6a4db94011d3 1392 #define LPC_FLASH_BASE (0x00000000UL)
sahilmgandhi 18:6a4db94011d3 1393 #define LPC_RAM_BASE (0x10000000UL)
sahilmgandhi 18:6a4db94011d3 1394 #define LPC_PERI_RAM_BASE (0x20000000UL)
sahilmgandhi 18:6a4db94011d3 1395 #define LPC_APB0_BASE (0x40000000UL)
sahilmgandhi 18:6a4db94011d3 1396 #define LPC_APB1_BASE (0x40080000UL)
sahilmgandhi 18:6a4db94011d3 1397 #define LPC_AHBRAM1_BASE (0x20004000UL)
sahilmgandhi 18:6a4db94011d3 1398 #define LPC_AHB_BASE (0x20080000UL)
sahilmgandhi 18:6a4db94011d3 1399 #define LPC_CM3_BASE (0xE0000000UL)
sahilmgandhi 18:6a4db94011d3 1400
sahilmgandhi 18:6a4db94011d3 1401 /* APB0 peripherals */
sahilmgandhi 18:6a4db94011d3 1402 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 1403 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
sahilmgandhi 18:6a4db94011d3 1404 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
sahilmgandhi 18:6a4db94011d3 1405 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 1406 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 1407 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
sahilmgandhi 18:6a4db94011d3 1408 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
sahilmgandhi 18:6a4db94011d3 1409 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
sahilmgandhi 18:6a4db94011d3 1410 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
sahilmgandhi 18:6a4db94011d3 1411 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
sahilmgandhi 18:6a4db94011d3 1412 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
sahilmgandhi 18:6a4db94011d3 1413 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
sahilmgandhi 18:6a4db94011d3 1414 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
sahilmgandhi 18:6a4db94011d3 1415 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
sahilmgandhi 18:6a4db94011d3 1416 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
sahilmgandhi 18:6a4db94011d3 1417 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
sahilmgandhi 18:6a4db94011d3 1418 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
sahilmgandhi 18:6a4db94011d3 1419 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
sahilmgandhi 18:6a4db94011d3 1420 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
sahilmgandhi 18:6a4db94011d3 1421 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
sahilmgandhi 18:6a4db94011d3 1422
sahilmgandhi 18:6a4db94011d3 1423 /* APB1 peripherals */
sahilmgandhi 18:6a4db94011d3 1424 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
sahilmgandhi 18:6a4db94011d3 1425 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 1426 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 1427 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
sahilmgandhi 18:6a4db94011d3 1428 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
sahilmgandhi 18:6a4db94011d3 1429 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
sahilmgandhi 18:6a4db94011d3 1430 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
sahilmgandhi 18:6a4db94011d3 1431 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
sahilmgandhi 18:6a4db94011d3 1432 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
sahilmgandhi 18:6a4db94011d3 1433 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
sahilmgandhi 18:6a4db94011d3 1434 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
sahilmgandhi 18:6a4db94011d3 1435 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
sahilmgandhi 18:6a4db94011d3 1436 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
sahilmgandhi 18:6a4db94011d3 1437 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
sahilmgandhi 18:6a4db94011d3 1438
sahilmgandhi 18:6a4db94011d3 1439 /* AHB peripherals */
sahilmgandhi 18:6a4db94011d3 1440 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 1441 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
sahilmgandhi 18:6a4db94011d3 1442 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
sahilmgandhi 18:6a4db94011d3 1443 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
sahilmgandhi 18:6a4db94011d3 1444 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
sahilmgandhi 18:6a4db94011d3 1445 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
sahilmgandhi 18:6a4db94011d3 1446 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
sahilmgandhi 18:6a4db94011d3 1447 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
sahilmgandhi 18:6a4db94011d3 1448 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
sahilmgandhi 18:6a4db94011d3 1449 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
sahilmgandhi 18:6a4db94011d3 1450 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
sahilmgandhi 18:6a4db94011d3 1451 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 1452 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 1453 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
sahilmgandhi 18:6a4db94011d3 1454 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
sahilmgandhi 18:6a4db94011d3 1455 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
sahilmgandhi 18:6a4db94011d3 1456 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
sahilmgandhi 18:6a4db94011d3 1457 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
sahilmgandhi 18:6a4db94011d3 1458 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
sahilmgandhi 18:6a4db94011d3 1459 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
sahilmgandhi 18:6a4db94011d3 1460
sahilmgandhi 18:6a4db94011d3 1461 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
sahilmgandhi 18:6a4db94011d3 1462
sahilmgandhi 18:6a4db94011d3 1463
sahilmgandhi 18:6a4db94011d3 1464 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1465 /* Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 1466 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1467 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
sahilmgandhi 18:6a4db94011d3 1468 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
sahilmgandhi 18:6a4db94011d3 1469 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
sahilmgandhi 18:6a4db94011d3 1470 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
sahilmgandhi 18:6a4db94011d3 1471 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
sahilmgandhi 18:6a4db94011d3 1472 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
sahilmgandhi 18:6a4db94011d3 1473 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
sahilmgandhi 18:6a4db94011d3 1474 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
sahilmgandhi 18:6a4db94011d3 1475 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
sahilmgandhi 18:6a4db94011d3 1476 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
sahilmgandhi 18:6a4db94011d3 1477 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
sahilmgandhi 18:6a4db94011d3 1478 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
sahilmgandhi 18:6a4db94011d3 1479 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
sahilmgandhi 18:6a4db94011d3 1480 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
sahilmgandhi 18:6a4db94011d3 1481 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
sahilmgandhi 18:6a4db94011d3 1482 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
sahilmgandhi 18:6a4db94011d3 1483 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
sahilmgandhi 18:6a4db94011d3 1484 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
sahilmgandhi 18:6a4db94011d3 1485 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
sahilmgandhi 18:6a4db94011d3 1486 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
sahilmgandhi 18:6a4db94011d3 1487 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
sahilmgandhi 18:6a4db94011d3 1488 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
sahilmgandhi 18:6a4db94011d3 1489 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
sahilmgandhi 18:6a4db94011d3 1490 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
sahilmgandhi 18:6a4db94011d3 1491 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
sahilmgandhi 18:6a4db94011d3 1492 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
sahilmgandhi 18:6a4db94011d3 1493 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
sahilmgandhi 18:6a4db94011d3 1494 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
sahilmgandhi 18:6a4db94011d3 1495 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
sahilmgandhi 18:6a4db94011d3 1496 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
sahilmgandhi 18:6a4db94011d3 1497 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
sahilmgandhi 18:6a4db94011d3 1498 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
sahilmgandhi 18:6a4db94011d3 1499 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
sahilmgandhi 18:6a4db94011d3 1500 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
sahilmgandhi 18:6a4db94011d3 1501 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
sahilmgandhi 18:6a4db94011d3 1502 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
sahilmgandhi 18:6a4db94011d3 1503 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
sahilmgandhi 18:6a4db94011d3 1504 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
sahilmgandhi 18:6a4db94011d3 1505 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
sahilmgandhi 18:6a4db94011d3 1506 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
sahilmgandhi 18:6a4db94011d3 1507 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
sahilmgandhi 18:6a4db94011d3 1508 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
sahilmgandhi 18:6a4db94011d3 1509 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
sahilmgandhi 18:6a4db94011d3 1510 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
sahilmgandhi 18:6a4db94011d3 1511 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
sahilmgandhi 18:6a4db94011d3 1512 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
sahilmgandhi 18:6a4db94011d3 1513 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
sahilmgandhi 18:6a4db94011d3 1514 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
sahilmgandhi 18:6a4db94011d3 1515 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
sahilmgandhi 18:6a4db94011d3 1516 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
sahilmgandhi 18:6a4db94011d3 1517 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
sahilmgandhi 18:6a4db94011d3 1518 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
sahilmgandhi 18:6a4db94011d3 1519 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
sahilmgandhi 18:6a4db94011d3 1520 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
sahilmgandhi 18:6a4db94011d3 1521 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
sahilmgandhi 18:6a4db94011d3 1522
sahilmgandhi 18:6a4db94011d3 1523
sahilmgandhi 18:6a4db94011d3 1524
sahilmgandhi 18:6a4db94011d3 1525 #endif // __LPC407x_8x_177x_8x_H__