MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #define CHANNEL_NUM 48
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 25 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 static void handle_interrupt_in(void) {
sahilmgandhi 18:6a4db94011d3 28 // Read in all current interrupt registers. We do this once as the
sahilmgandhi 18:6a4db94011d3 29 // GPIO interrupt registers are on the APB bus, and this is slow.
sahilmgandhi 18:6a4db94011d3 30 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 31 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 32 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 33 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 34 uint8_t bitloc;
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 while(rise0 > 0) { //Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 37 bitloc = 31 - __CLZ(rise0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sahilmgandhi 18:6a4db94011d3 38 if (channel_ids[bitloc] != 0)
sahilmgandhi 18:6a4db94011d3 39 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 42 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 43 rise0 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 44 }
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 while(fall0 > 0) { //Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 47 bitloc = 31 - __CLZ(fall0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sahilmgandhi 18:6a4db94011d3 48 if (channel_ids[bitloc] != 0)
sahilmgandhi 18:6a4db94011d3 49 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 52 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 53 fall0 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 54 }
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 //Same for port 2, only we need to watch the channel_index
sahilmgandhi 18:6a4db94011d3 57 while(rise2 > 0) { //Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 58 bitloc = 31 - __CLZ(rise2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 if (bitloc < 16) //Not sure if this is actually needed
sahilmgandhi 18:6a4db94011d3 61 if (channel_ids[bitloc+32] != 0)
sahilmgandhi 18:6a4db94011d3 62 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 65 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 66 rise2 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 while(fall2 > 0) { //Continue as long as there are interrupts pending
sahilmgandhi 18:6a4db94011d3 70 bitloc = 31 - __CLZ(fall2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 if (bitloc < 16) //Not sure if this is actually needed
sahilmgandhi 18:6a4db94011d3 73 if (channel_ids[bitloc+32] != 0)
sahilmgandhi 18:6a4db94011d3 74 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sahilmgandhi 18:6a4db94011d3 77 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
sahilmgandhi 18:6a4db94011d3 78 fall2 -= 1<<bitloc;
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80 }
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 83 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 obj->port = (int)pin & ~0x1F;
sahilmgandhi 18:6a4db94011d3 88 obj->pin = (int)pin & 0x1F;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 // Interrupts available only on GPIO0 and GPIO2
sahilmgandhi 18:6a4db94011d3 91 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
sahilmgandhi 18:6a4db94011d3 92 error("pins on this port cannot generate interrupts");
sahilmgandhi 18:6a4db94011d3 93 }
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 // put us in the interrupt table
sahilmgandhi 18:6a4db94011d3 96 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
sahilmgandhi 18:6a4db94011d3 97 channel_ids[index] = id;
sahilmgandhi 18:6a4db94011d3 98 obj->ch = index;
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
sahilmgandhi 18:6a4db94011d3 101 NVIC_EnableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 102 return 0;
sahilmgandhi 18:6a4db94011d3 103 }
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 106 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 110 // ensure nothing is pending
sahilmgandhi 18:6a4db94011d3 111 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 112 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
sahilmgandhi 18:6a4db94011d3 113 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 // enable the pin interrupt
sahilmgandhi 18:6a4db94011d3 117 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 118 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 119 case LPC_GPIO0_BASE:
sahilmgandhi 18:6a4db94011d3 120 if (enable) {
sahilmgandhi 18:6a4db94011d3 121 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 122 } else {
sahilmgandhi 18:6a4db94011d3 123 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 124 }
sahilmgandhi 18:6a4db94011d3 125 break;
sahilmgandhi 18:6a4db94011d3 126 case LPC_GPIO2_BASE:
sahilmgandhi 18:6a4db94011d3 127 if (enable) {
sahilmgandhi 18:6a4db94011d3 128 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 129 } else {
sahilmgandhi 18:6a4db94011d3 130 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132 break;
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134 } else {
sahilmgandhi 18:6a4db94011d3 135 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 136 case LPC_GPIO0_BASE:
sahilmgandhi 18:6a4db94011d3 137 if (enable) {
sahilmgandhi 18:6a4db94011d3 138 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 139 } else {
sahilmgandhi 18:6a4db94011d3 140 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 break;
sahilmgandhi 18:6a4db94011d3 143 case LPC_GPIO2_BASE:
sahilmgandhi 18:6a4db94011d3 144 if (enable) {
sahilmgandhi 18:6a4db94011d3 145 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 146 } else {
sahilmgandhi 18:6a4db94011d3 147 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 148 }
sahilmgandhi 18:6a4db94011d3 149 break;
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151 }
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 155 NVIC_EnableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 156 }
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 159 NVIC_DisableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161