Mouse code for the MacroRat
mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2006-2013 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | #include <stddef.h> |
sahilmgandhi | 18:6a4db94011d3 | 17 | #include "us_ticker_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 18 | #include "PeripheralNames.h" |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "mbed_critical.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | |
sahilmgandhi | 18:6a4db94011d3 | 21 | #define US_TICKER_TIMER_IRQn SCT3_IRQn |
sahilmgandhi | 18:6a4db94011d3 | 22 | |
sahilmgandhi | 18:6a4db94011d3 | 23 | int us_ticker_inited = 0; |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | void us_ticker_init(void) { |
sahilmgandhi | 18:6a4db94011d3 | 26 | if (us_ticker_inited) |
sahilmgandhi | 18:6a4db94011d3 | 27 | return; |
sahilmgandhi | 18:6a4db94011d3 | 28 | |
sahilmgandhi | 18:6a4db94011d3 | 29 | us_ticker_inited = 1; |
sahilmgandhi | 18:6a4db94011d3 | 30 | |
sahilmgandhi | 18:6a4db94011d3 | 31 | // Enable the SCT3 clock |
sahilmgandhi | 18:6a4db94011d3 | 32 | LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 5); |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | // Clear peripheral reset the SCT3 |
sahilmgandhi | 18:6a4db94011d3 | 35 | LPC_SYSCON->PRESETCTRL1 |= (1 << 5); |
sahilmgandhi | 18:6a4db94011d3 | 36 | LPC_SYSCON->PRESETCTRL1 &= ~(1 << 5); |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | // Configure SCT3 as a 1MHz 32-bit counter with no auto limiting or match reload |
sahilmgandhi | 18:6a4db94011d3 | 39 | char sctClkDiv = ((SystemCoreClock + 1000000 - 1) / 1000000) - 1; |
sahilmgandhi | 18:6a4db94011d3 | 40 | LPC_SCT3->CONFIG = (1 << 7) | (1 << 0); |
sahilmgandhi | 18:6a4db94011d3 | 41 | LPC_SCT3->CTRL = (sctClkDiv << 5) | (1 << 3) | (1 << 2); |
sahilmgandhi | 18:6a4db94011d3 | 42 | |
sahilmgandhi | 18:6a4db94011d3 | 43 | // Configure SCT3 event 0 to fire on match register 0 |
sahilmgandhi | 18:6a4db94011d3 | 44 | LPC_SCT3->EV0_STATE = (1 << 0); |
sahilmgandhi | 18:6a4db94011d3 | 45 | LPC_SCT3->EV0_CTRL = (0x1 << 12); |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | // Start SCT3 |
sahilmgandhi | 18:6a4db94011d3 | 48 | LPC_SCT3->CTRL &= ~(1 << 2); |
sahilmgandhi | 18:6a4db94011d3 | 49 | |
sahilmgandhi | 18:6a4db94011d3 | 50 | // Set SCT3 interrupt vector |
sahilmgandhi | 18:6a4db94011d3 | 51 | NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); |
sahilmgandhi | 18:6a4db94011d3 | 52 | NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 53 | } |
sahilmgandhi | 18:6a4db94011d3 | 54 | |
sahilmgandhi | 18:6a4db94011d3 | 55 | uint32_t us_ticker_read() { |
sahilmgandhi | 18:6a4db94011d3 | 56 | if (!us_ticker_inited) |
sahilmgandhi | 18:6a4db94011d3 | 57 | us_ticker_init(); |
sahilmgandhi | 18:6a4db94011d3 | 58 | |
sahilmgandhi | 18:6a4db94011d3 | 59 | // Return SCT3 count value |
sahilmgandhi | 18:6a4db94011d3 | 60 | return LPC_SCT3->COUNT; |
sahilmgandhi | 18:6a4db94011d3 | 61 | } |
sahilmgandhi | 18:6a4db94011d3 | 62 | |
sahilmgandhi | 18:6a4db94011d3 | 63 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
sahilmgandhi | 18:6a4db94011d3 | 64 | // Set SCT3 match register 0 (critical section) |
sahilmgandhi | 18:6a4db94011d3 | 65 | core_util_critical_section_enter(); |
sahilmgandhi | 18:6a4db94011d3 | 66 | LPC_SCT3->CTRL |= (1 << 2); |
sahilmgandhi | 18:6a4db94011d3 | 67 | LPC_SCT3->MATCH0 = (uint32_t)timestamp; |
sahilmgandhi | 18:6a4db94011d3 | 68 | LPC_SCT3->CTRL &= ~(1 << 2); |
sahilmgandhi | 18:6a4db94011d3 | 69 | core_util_critical_section_exit(); |
sahilmgandhi | 18:6a4db94011d3 | 70 | |
sahilmgandhi | 18:6a4db94011d3 | 71 | // Enable interrupt on SCT3 event 0 |
sahilmgandhi | 18:6a4db94011d3 | 72 | LPC_SCT3->EVEN = (1 << 0); |
sahilmgandhi | 18:6a4db94011d3 | 73 | } |
sahilmgandhi | 18:6a4db94011d3 | 74 | |
sahilmgandhi | 18:6a4db94011d3 | 75 | void us_ticker_disable_interrupt(void) { |
sahilmgandhi | 18:6a4db94011d3 | 76 | // Disable interrupt on SCT3 event 0 |
sahilmgandhi | 18:6a4db94011d3 | 77 | LPC_SCT3->EVEN = 0; |
sahilmgandhi | 18:6a4db94011d3 | 78 | } |
sahilmgandhi | 18:6a4db94011d3 | 79 | |
sahilmgandhi | 18:6a4db94011d3 | 80 | void us_ticker_clear_interrupt(void) { |
sahilmgandhi | 18:6a4db94011d3 | 81 | // Clear SCT3 event 0 interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 82 | LPC_SCT3->EVFLAG = (1 << 0); |
sahilmgandhi | 18:6a4db94011d3 | 83 | } |