Mouse code for the MacroRat
mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_CR/LPC1549.ld@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /*Based on following file*/ |
sahilmgandhi | 18:6a4db94011d3 | 2 | /* |
sahilmgandhi | 18:6a4db94011d3 | 3 | * GENERATED FILE - DO NOT EDIT |
sahilmgandhi | 18:6a4db94011d3 | 4 | * (c) Code Red Technologies Ltd, 2008-13 |
sahilmgandhi | 18:6a4db94011d3 | 5 | * (c) NXP Semiconductors 2013-2014 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Generated linker script file for LPC1549 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] )) |
sahilmgandhi | 18:6a4db94011d3 | 8 | * By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Tue Jun 10 00:20:53 JST 2014 |
sahilmgandhi | 18:6a4db94011d3 | 9 | */ |
sahilmgandhi | 18:6a4db94011d3 | 10 | |
sahilmgandhi | 18:6a4db94011d3 | 11 | GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) |
sahilmgandhi | 18:6a4db94011d3 | 12 | |
sahilmgandhi | 18:6a4db94011d3 | 13 | MEMORY |
sahilmgandhi | 18:6a4db94011d3 | 14 | { |
sahilmgandhi | 18:6a4db94011d3 | 15 | /* Define each memory region */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */ |
sahilmgandhi | 18:6a4db94011d3 | 17 | Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 /* 16K bytes */ |
sahilmgandhi | 18:6a4db94011d3 | 18 | Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes */ |
sahilmgandhi | 18:6a4db94011d3 | 19 | Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes */ |
sahilmgandhi | 18:6a4db94011d3 | 20 | |
sahilmgandhi | 18:6a4db94011d3 | 21 | } |
sahilmgandhi | 18:6a4db94011d3 | 22 | /* Define a symbol for the top of each memory region */ |
sahilmgandhi | 18:6a4db94011d3 | 23 | __top_MFlash256 = 0x0 + 0x40000; |
sahilmgandhi | 18:6a4db94011d3 | 24 | __top_Ram0_16 = 0x2000000 + 0x4000; |
sahilmgandhi | 18:6a4db94011d3 | 25 | __top_Ram1_16 = 0x2004000 + 0x4000; |
sahilmgandhi | 18:6a4db94011d3 | 26 | __top_Ram2_4 = 0x2008000 + 0x1000; |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | ENTRY(ResetISR) |
sahilmgandhi | 18:6a4db94011d3 | 29 | |
sahilmgandhi | 18:6a4db94011d3 | 30 | SECTIONS |
sahilmgandhi | 18:6a4db94011d3 | 31 | { |
sahilmgandhi | 18:6a4db94011d3 | 32 | |
sahilmgandhi | 18:6a4db94011d3 | 33 | /* MAIN TEXT SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 34 | .text : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 35 | { |
sahilmgandhi | 18:6a4db94011d3 | 36 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 37 | KEEP(*(.isr_vector)) |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | /* Global Section Table */ |
sahilmgandhi | 18:6a4db94011d3 | 40 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 41 | __section_table_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 42 | __data_section_table = .; |
sahilmgandhi | 18:6a4db94011d3 | 43 | LONG(LOADADDR(.data)); |
sahilmgandhi | 18:6a4db94011d3 | 44 | LONG( ADDR(.data)); |
sahilmgandhi | 18:6a4db94011d3 | 45 | LONG( SIZEOF(.data)); |
sahilmgandhi | 18:6a4db94011d3 | 46 | LONG(LOADADDR(.data_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 47 | LONG( ADDR(.data_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 48 | LONG( SIZEOF(.data_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 49 | LONG(LOADADDR(.data_RAM3)); |
sahilmgandhi | 18:6a4db94011d3 | 50 | LONG( ADDR(.data_RAM3)); |
sahilmgandhi | 18:6a4db94011d3 | 51 | LONG( SIZEOF(.data_RAM3)); |
sahilmgandhi | 18:6a4db94011d3 | 52 | __data_section_table_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 53 | __bss_section_table = .; |
sahilmgandhi | 18:6a4db94011d3 | 54 | LONG( ADDR(.bss)); |
sahilmgandhi | 18:6a4db94011d3 | 55 | LONG( SIZEOF(.bss)); |
sahilmgandhi | 18:6a4db94011d3 | 56 | LONG( ADDR(.bss_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 57 | LONG( SIZEOF(.bss_RAM2)); |
sahilmgandhi | 18:6a4db94011d3 | 58 | LONG( ADDR(.bss_RAM3)); |
sahilmgandhi | 18:6a4db94011d3 | 59 | LONG( SIZEOF(.bss_RAM3)); |
sahilmgandhi | 18:6a4db94011d3 | 60 | __bss_section_table_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 61 | __section_table_end = . ; |
sahilmgandhi | 18:6a4db94011d3 | 62 | /* End of Global Section Table */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | *(.after_vectors*) |
sahilmgandhi | 18:6a4db94011d3 | 66 | |
sahilmgandhi | 18:6a4db94011d3 | 67 | *(.text*) |
sahilmgandhi | 18:6a4db94011d3 | 68 | *(.rodata .rodata.*) |
sahilmgandhi | 18:6a4db94011d3 | 69 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 70 | |
sahilmgandhi | 18:6a4db94011d3 | 71 | /* C++ constructors etc */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 73 | KEEP(*(.init)) |
sahilmgandhi | 18:6a4db94011d3 | 74 | |
sahilmgandhi | 18:6a4db94011d3 | 75 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 76 | __preinit_array_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 77 | KEEP (*(.preinit_array)) |
sahilmgandhi | 18:6a4db94011d3 | 78 | __preinit_array_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 79 | |
sahilmgandhi | 18:6a4db94011d3 | 80 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 81 | __init_array_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 82 | KEEP (*(SORT(.init_array.*))) |
sahilmgandhi | 18:6a4db94011d3 | 83 | KEEP (*(.init_array)) |
sahilmgandhi | 18:6a4db94011d3 | 84 | __init_array_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 85 | |
sahilmgandhi | 18:6a4db94011d3 | 86 | KEEP(*(.fini)); |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | . = ALIGN(0x4); |
sahilmgandhi | 18:6a4db94011d3 | 89 | KEEP (*crtbegin.o(.ctors)) |
sahilmgandhi | 18:6a4db94011d3 | 90 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) |
sahilmgandhi | 18:6a4db94011d3 | 91 | KEEP (*(SORT(.ctors.*))) |
sahilmgandhi | 18:6a4db94011d3 | 92 | KEEP (*crtend.o(.ctors)) |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | . = ALIGN(0x4); |
sahilmgandhi | 18:6a4db94011d3 | 95 | KEEP (*crtbegin.o(.dtors)) |
sahilmgandhi | 18:6a4db94011d3 | 96 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) |
sahilmgandhi | 18:6a4db94011d3 | 97 | KEEP (*(SORT(.dtors.*))) |
sahilmgandhi | 18:6a4db94011d3 | 98 | KEEP (*crtend.o(.dtors)) |
sahilmgandhi | 18:6a4db94011d3 | 99 | } > MFlash256 |
sahilmgandhi | 18:6a4db94011d3 | 100 | |
sahilmgandhi | 18:6a4db94011d3 | 101 | /* |
sahilmgandhi | 18:6a4db94011d3 | 102 | * for exception handling/unwind - some Newlib functions (in common |
sahilmgandhi | 18:6a4db94011d3 | 103 | * with C++ and STDC++) use this. |
sahilmgandhi | 18:6a4db94011d3 | 104 | */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | .ARM.extab : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 106 | { |
sahilmgandhi | 18:6a4db94011d3 | 107 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
sahilmgandhi | 18:6a4db94011d3 | 108 | } > MFlash256 |
sahilmgandhi | 18:6a4db94011d3 | 109 | __exidx_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 110 | |
sahilmgandhi | 18:6a4db94011d3 | 111 | .ARM.exidx : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 112 | { |
sahilmgandhi | 18:6a4db94011d3 | 113 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
sahilmgandhi | 18:6a4db94011d3 | 114 | } > MFlash256 |
sahilmgandhi | 18:6a4db94011d3 | 115 | __exidx_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 116 | |
sahilmgandhi | 18:6a4db94011d3 | 117 | _etext = .; |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | /* DATA section for Ram1_16 */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | .data_RAM2 : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 121 | { |
sahilmgandhi | 18:6a4db94011d3 | 122 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 123 | *(.ramfunc.$RAM2) |
sahilmgandhi | 18:6a4db94011d3 | 124 | *(.ramfunc.$Ram1_16) |
sahilmgandhi | 18:6a4db94011d3 | 125 | *(.data.$RAM2*) |
sahilmgandhi | 18:6a4db94011d3 | 126 | *(.data.$Ram1_16*) |
sahilmgandhi | 18:6a4db94011d3 | 127 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 128 | } > Ram1_16 AT>MFlash256 |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | /* DATA section for Ram2_4 */ |
sahilmgandhi | 18:6a4db94011d3 | 131 | .data_RAM3 : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 132 | { |
sahilmgandhi | 18:6a4db94011d3 | 133 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 134 | *(.ramfunc.$RAM3) |
sahilmgandhi | 18:6a4db94011d3 | 135 | *(.ramfunc.$Ram2_4) |
sahilmgandhi | 18:6a4db94011d3 | 136 | *(.data.$RAM3*) |
sahilmgandhi | 18:6a4db94011d3 | 137 | *(.data.$Ram2_4*) |
sahilmgandhi | 18:6a4db94011d3 | 138 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 139 | } > Ram2_4 AT>MFlash256 |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | /* MAIN DATA SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | .uninit_RESERVED : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 143 | { |
sahilmgandhi | 18:6a4db94011d3 | 144 | KEEP(*(.bss.$RESERVED*)) |
sahilmgandhi | 18:6a4db94011d3 | 145 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 146 | _end_uninit_RESERVED = .; |
sahilmgandhi | 18:6a4db94011d3 | 147 | } > Ram0_16 |
sahilmgandhi | 18:6a4db94011d3 | 148 | |
sahilmgandhi | 18:6a4db94011d3 | 149 | /* Main DATA section (Ram0_16) */ |
sahilmgandhi | 18:6a4db94011d3 | 150 | .data : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 151 | { |
sahilmgandhi | 18:6a4db94011d3 | 152 | FILL(0xff) |
sahilmgandhi | 18:6a4db94011d3 | 153 | _data = . ; |
sahilmgandhi | 18:6a4db94011d3 | 154 | *(vtable) |
sahilmgandhi | 18:6a4db94011d3 | 155 | *(.ramfunc*) |
sahilmgandhi | 18:6a4db94011d3 | 156 | *(.data*) |
sahilmgandhi | 18:6a4db94011d3 | 157 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 158 | _edata = . ; |
sahilmgandhi | 18:6a4db94011d3 | 159 | } > Ram0_16 AT>MFlash256 |
sahilmgandhi | 18:6a4db94011d3 | 160 | |
sahilmgandhi | 18:6a4db94011d3 | 161 | /* BSS section for Ram1_16 */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | .bss_RAM2 : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 163 | { |
sahilmgandhi | 18:6a4db94011d3 | 164 | *(.bss.$RAM2*) |
sahilmgandhi | 18:6a4db94011d3 | 165 | *(.bss.$Ram1_16*) |
sahilmgandhi | 18:6a4db94011d3 | 166 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 167 | } > Ram1_16 |
sahilmgandhi | 18:6a4db94011d3 | 168 | /* BSS section for Ram2_4 */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | .bss_RAM3 : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 170 | { |
sahilmgandhi | 18:6a4db94011d3 | 171 | *(.bss.$RAM3*) |
sahilmgandhi | 18:6a4db94011d3 | 172 | *(.bss.$Ram2_4*) |
sahilmgandhi | 18:6a4db94011d3 | 173 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 174 | } > Ram2_4 |
sahilmgandhi | 18:6a4db94011d3 | 175 | |
sahilmgandhi | 18:6a4db94011d3 | 176 | /* MAIN BSS SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | .bss : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 178 | { |
sahilmgandhi | 18:6a4db94011d3 | 179 | _bss = .; |
sahilmgandhi | 18:6a4db94011d3 | 180 | *(.bss*) |
sahilmgandhi | 18:6a4db94011d3 | 181 | *(COMMON) |
sahilmgandhi | 18:6a4db94011d3 | 182 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 183 | _ebss = .; |
sahilmgandhi | 18:6a4db94011d3 | 184 | PROVIDE(end = .); |
sahilmgandhi | 18:6a4db94011d3 | 185 | __end__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 186 | } > Ram0_16 |
sahilmgandhi | 18:6a4db94011d3 | 187 | |
sahilmgandhi | 18:6a4db94011d3 | 188 | /* NOINIT section for Ram1_16 */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | .noinit_RAM2 (NOLOAD) : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 190 | { |
sahilmgandhi | 18:6a4db94011d3 | 191 | *(.noinit.$RAM2*) |
sahilmgandhi | 18:6a4db94011d3 | 192 | *(.noinit.$Ram1_16*) |
sahilmgandhi | 18:6a4db94011d3 | 193 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 194 | } > Ram1_16 |
sahilmgandhi | 18:6a4db94011d3 | 195 | /* NOINIT section for Ram2_4 */ |
sahilmgandhi | 18:6a4db94011d3 | 196 | .noinit_RAM3 (NOLOAD) : ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 197 | { |
sahilmgandhi | 18:6a4db94011d3 | 198 | *(.noinit.$RAM3*) |
sahilmgandhi | 18:6a4db94011d3 | 199 | *(.noinit.$Ram2_4*) |
sahilmgandhi | 18:6a4db94011d3 | 200 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 201 | } > Ram2_4 |
sahilmgandhi | 18:6a4db94011d3 | 202 | |
sahilmgandhi | 18:6a4db94011d3 | 203 | /* DEFAULT NOINIT SECTION */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | .noinit (NOLOAD): ALIGN(4) |
sahilmgandhi | 18:6a4db94011d3 | 205 | { |
sahilmgandhi | 18:6a4db94011d3 | 206 | _noinit = .; |
sahilmgandhi | 18:6a4db94011d3 | 207 | *(.noinit*) |
sahilmgandhi | 18:6a4db94011d3 | 208 | . = ALIGN(4) ; |
sahilmgandhi | 18:6a4db94011d3 | 209 | _end_noinit = .; |
sahilmgandhi | 18:6a4db94011d3 | 210 | } > Ram0_16 |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | PROVIDE(_pvHeapStart = .); |
sahilmgandhi | 18:6a4db94011d3 | 213 | PROVIDE(_vStackTop = __top_Ram0_16 - 0); |
sahilmgandhi | 18:6a4db94011d3 | 214 | } |