MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/startup_LPC15xx.S@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* File: startup_ARMCM3.s
sahilmgandhi 18:6a4db94011d3 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
sahilmgandhi 18:6a4db94011d3 3 * GNU Tools for ARM Embedded Processors
sahilmgandhi 18:6a4db94011d3 4 * Version: V1.1
sahilmgandhi 18:6a4db94011d3 5 * Date: 17 June 2011
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
sahilmgandhi 18:6a4db94011d3 9 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 10 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 17 */
sahilmgandhi 18:6a4db94011d3 18 .syntax unified
sahilmgandhi 18:6a4db94011d3 19 .arch armv7-m
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 /* Memory Model
sahilmgandhi 18:6a4db94011d3 22 The HEAP starts at the end of the DATA section and grows upward.
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 The STACK starts at the end of the RAM and grows downward.
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 The HEAP and stack STACK are only checked at compile time:
sahilmgandhi 18:6a4db94011d3 27 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 This is just a check for the bare minimum for the Heap+Stack area before
sahilmgandhi 18:6a4db94011d3 30 aborting compilation, it is not the run time limit:
sahilmgandhi 18:6a4db94011d3 31 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33 .section .stack
sahilmgandhi 18:6a4db94011d3 34 .align 3
sahilmgandhi 18:6a4db94011d3 35 #ifdef __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 36 .equ Stack_Size, __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 37 #else
sahilmgandhi 18:6a4db94011d3 38 .equ Stack_Size, 0xc00
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40 .globl __StackTop
sahilmgandhi 18:6a4db94011d3 41 .globl __StackLimit
sahilmgandhi 18:6a4db94011d3 42 __StackLimit:
sahilmgandhi 18:6a4db94011d3 43 .space Stack_Size
sahilmgandhi 18:6a4db94011d3 44 .size __StackLimit, . - __StackLimit
sahilmgandhi 18:6a4db94011d3 45 __StackTop:
sahilmgandhi 18:6a4db94011d3 46 .size __StackTop, . - __StackTop
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 .section .heap
sahilmgandhi 18:6a4db94011d3 49 .align 3
sahilmgandhi 18:6a4db94011d3 50 #ifdef __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 51 .equ Heap_Size, __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 52 #else
sahilmgandhi 18:6a4db94011d3 53 .equ Heap_Size, 0x800
sahilmgandhi 18:6a4db94011d3 54 #endif
sahilmgandhi 18:6a4db94011d3 55 .globl __HeapBase
sahilmgandhi 18:6a4db94011d3 56 .globl __HeapLimit
sahilmgandhi 18:6a4db94011d3 57 __HeapBase:
sahilmgandhi 18:6a4db94011d3 58 .space Heap_Size
sahilmgandhi 18:6a4db94011d3 59 .size __HeapBase, . - __HeapBase
sahilmgandhi 18:6a4db94011d3 60 __HeapLimit:
sahilmgandhi 18:6a4db94011d3 61 .size __HeapLimit, . - __HeapLimit
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 .section .isr_vector
sahilmgandhi 18:6a4db94011d3 64 .align 2
sahilmgandhi 18:6a4db94011d3 65 .globl __isr_vector
sahilmgandhi 18:6a4db94011d3 66 __isr_vector:
sahilmgandhi 18:6a4db94011d3 67 .long __StackTop /* Top of Stack */
sahilmgandhi 18:6a4db94011d3 68 .long Reset_Handler /* Reset Handler */
sahilmgandhi 18:6a4db94011d3 69 .long NMI_Handler /* NMI Handler */
sahilmgandhi 18:6a4db94011d3 70 .long HardFault_Handler /* Hard Fault Handler */
sahilmgandhi 18:6a4db94011d3 71 .long MemManage_Handler /* MPU Fault Handler */
sahilmgandhi 18:6a4db94011d3 72 .long BusFault_Handler /* Bus Fault Handler */
sahilmgandhi 18:6a4db94011d3 73 .long UsageFault_Handler /* Usage Fault Handler */
sahilmgandhi 18:6a4db94011d3 74 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 75 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 76 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 77 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 78 .long SVC_Handler /* SVCall Handler */
sahilmgandhi 18:6a4db94011d3 79 .long DebugMon_Handler /* Debug Monitor Handler */
sahilmgandhi 18:6a4db94011d3 80 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 81 .long PendSV_Handler /* PendSV Handler */
sahilmgandhi 18:6a4db94011d3 82 .long SysTick_Handler /* SysTick Handler */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /* External interrupts */
sahilmgandhi 18:6a4db94011d3 85 .long WDT_IRQHandler /* 0: Windowed watchdog timer */
sahilmgandhi 18:6a4db94011d3 86 .long BOD_IRQHandler /* 1: Brown-Out Detect */
sahilmgandhi 18:6a4db94011d3 87 .long FMC_IRQHandler /* 2: Flash controller */
sahilmgandhi 18:6a4db94011d3 88 .long EEPROM_IRQHandler /* 3: EEPROM controller */
sahilmgandhi 18:6a4db94011d3 89 .long DMA_IRQHandler /* 4: DMA */
sahilmgandhi 18:6a4db94011d3 90 .long GINT0_IRQHandler /* 5: GPIO group 0 */
sahilmgandhi 18:6a4db94011d3 91 .long GINT1_IRQHandler /* 6: GPIO group 1 */
sahilmgandhi 18:6a4db94011d3 92 .long PIN_INT0_IRQHandler /* 7: PIO INT0 */
sahilmgandhi 18:6a4db94011d3 93 .long PIN_INT1_IRQHandler /* 8: PIO INT1 */
sahilmgandhi 18:6a4db94011d3 94 .long PIN_INT2_IRQHandler /* 9: PIO INT2 */
sahilmgandhi 18:6a4db94011d3 95 .long PIN_INT3_IRQHandler /* 10: PIO INT3 */
sahilmgandhi 18:6a4db94011d3 96 .long PIN_INT4_IRQHandler /* 11: PIO INT4 */
sahilmgandhi 18:6a4db94011d3 97 .long PIN_INT5_IRQHandler /* 12: PIO INT5 */
sahilmgandhi 18:6a4db94011d3 98 .long PIN_INT6_IRQHandler /* 13: PIO INT6 */
sahilmgandhi 18:6a4db94011d3 99 .long PIN_INT7_IRQHandler /* 14: PIO INT7 */
sahilmgandhi 18:6a4db94011d3 100 .long RIT_IRQHandler /* 15: Repetitive Interrupt Timer */
sahilmgandhi 18:6a4db94011d3 101 .long SCT0_IRQHandler /* 16: State configurable timer */
sahilmgandhi 18:6a4db94011d3 102 .long SCT1_IRQHandler /* 17: State configurable timer */
sahilmgandhi 18:6a4db94011d3 103 .long SCT2_IRQHandler /* 18: State configurable timer */
sahilmgandhi 18:6a4db94011d3 104 .long SCT3_IRQHandler /* 19: State configurable timer */
sahilmgandhi 18:6a4db94011d3 105 .long MRT_IRQHandler /* 20: Multi-Rate Timer */
sahilmgandhi 18:6a4db94011d3 106 .long UART0_IRQHandler /* 21: UART0 */
sahilmgandhi 18:6a4db94011d3 107 .long UART1_IRQHandler /* 22: UART1 */
sahilmgandhi 18:6a4db94011d3 108 .long UART2_IRQHandler /* 23: UART2 */
sahilmgandhi 18:6a4db94011d3 109 .long I2C0_IRQHandler /* 24: I2C0 controller */
sahilmgandhi 18:6a4db94011d3 110 .long SPI0_IRQHandler /* 25: SPI0 controller */
sahilmgandhi 18:6a4db94011d3 111 .long SPI1_IRQHandler /* 26: SPI1 controller */
sahilmgandhi 18:6a4db94011d3 112 .long CAN_IRQHandler /* 27: C_CAN0 */
sahilmgandhi 18:6a4db94011d3 113 .long USB_IRQHandler /* 28: USB IRQ */
sahilmgandhi 18:6a4db94011d3 114 .long USB_FIQHandler /* 29: USB FIQ */
sahilmgandhi 18:6a4db94011d3 115 .long USBWakeup_IRQHandler /* 30: USB wake-up */
sahilmgandhi 18:6a4db94011d3 116 .long ADC0A_IRQHandler /* 31: ADC0 sequence A completion */
sahilmgandhi 18:6a4db94011d3 117 .long ADC0B_IRQHandler /* 32: ADC0 sequence B completion */
sahilmgandhi 18:6a4db94011d3 118 .long ADC0_THCMP_IRQHandler /* 33: ADC0 threshold compare */
sahilmgandhi 18:6a4db94011d3 119 .long ADC0_OVR_IRQHandler /* 34: ADC0 overrun */
sahilmgandhi 18:6a4db94011d3 120 .long ADC1A_IRQHandler /* 35: ADC1 sequence A completion */
sahilmgandhi 18:6a4db94011d3 121 .long ADC1B_IRQHandler /* 36: ADC1 sequence B completion */
sahilmgandhi 18:6a4db94011d3 122 .long ADC1_THCMP_IRQHandler /* 37: ADC1 threshold compare */
sahilmgandhi 18:6a4db94011d3 123 .long ADC1_OVR_IRQHandler /* 38: ADC1 overrun */
sahilmgandhi 18:6a4db94011d3 124 .long DAC_IRQHandler /* 39: DAC */
sahilmgandhi 18:6a4db94011d3 125 .long ACMP0_IRQHandler /* 40: Analog Comparator 0 */
sahilmgandhi 18:6a4db94011d3 126 .long ACMP1_IRQHandler /* 41: Analog Comparator 1 */
sahilmgandhi 18:6a4db94011d3 127 .long ACMP2_IRQHandler /* 42: Analog Comparator 2 */
sahilmgandhi 18:6a4db94011d3 128 .long ACMP3_IRQHandler /* 43: Analog Comparator 3 */
sahilmgandhi 18:6a4db94011d3 129 .long QEI_IRQHandler /* 44: Quadrature Encoder Interface */
sahilmgandhi 18:6a4db94011d3 130 .long RTC_ALARM_IRQHandler /* 45: RTC alarm */
sahilmgandhi 18:6a4db94011d3 131 .long RTC_WAKE_IRQHandler /* 46: RTC wake-up */
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 .size __isr_vector, . - __isr_vector
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 .text
sahilmgandhi 18:6a4db94011d3 136 .thumb
sahilmgandhi 18:6a4db94011d3 137 .thumb_func
sahilmgandhi 18:6a4db94011d3 138 .align 2
sahilmgandhi 18:6a4db94011d3 139 .globl Reset_Handler
sahilmgandhi 18:6a4db94011d3 140 .type Reset_Handler, %function
sahilmgandhi 18:6a4db94011d3 141 Reset_Handler:
sahilmgandhi 18:6a4db94011d3 142 /* Loop to copy data from read only memory to RAM. The ranges
sahilmgandhi 18:6a4db94011d3 143 * of copy from/to are specified by following symbols evaluated in
sahilmgandhi 18:6a4db94011d3 144 * linker script.
sahilmgandhi 18:6a4db94011d3 145 * _etext: End of code section, i.e., begin of data sections to copy from.
sahilmgandhi 18:6a4db94011d3 146 * __data_start__/__data_end__: RAM address range that data should be
sahilmgandhi 18:6a4db94011d3 147 * copied to. Both must be aligned to 4 bytes boundary. */
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 ldr r1, =__etext
sahilmgandhi 18:6a4db94011d3 150 ldr r2, =__data_start__
sahilmgandhi 18:6a4db94011d3 151 ldr r3, =__data_end__
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 .Lflash_to_ram_loop:
sahilmgandhi 18:6a4db94011d3 154 cmp r2, r3
sahilmgandhi 18:6a4db94011d3 155 ittt lt
sahilmgandhi 18:6a4db94011d3 156 ldrlt r0, [r1], #4
sahilmgandhi 18:6a4db94011d3 157 strlt r0, [r2], #4
sahilmgandhi 18:6a4db94011d3 158 blt .Lflash_to_ram_loop
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 ldr r0, =SystemInit
sahilmgandhi 18:6a4db94011d3 161 blx r0
sahilmgandhi 18:6a4db94011d3 162 ldr r0, =_start
sahilmgandhi 18:6a4db94011d3 163 bx r0
sahilmgandhi 18:6a4db94011d3 164 .pool
sahilmgandhi 18:6a4db94011d3 165 .size Reset_Handler, . - Reset_Handler
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 .text
sahilmgandhi 18:6a4db94011d3 168 /* Macro to define default handlers. Default handler
sahilmgandhi 18:6a4db94011d3 169 * will be weak symbol and just dead loops. They can be
sahilmgandhi 18:6a4db94011d3 170 * overwritten by other handlers */
sahilmgandhi 18:6a4db94011d3 171 .macro def_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 172 .align 1
sahilmgandhi 18:6a4db94011d3 173 .thumb_func
sahilmgandhi 18:6a4db94011d3 174 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 175 .type \handler_name, %function
sahilmgandhi 18:6a4db94011d3 176 \handler_name :
sahilmgandhi 18:6a4db94011d3 177 b .
sahilmgandhi 18:6a4db94011d3 178 .size \handler_name, . - \handler_name
sahilmgandhi 18:6a4db94011d3 179 .endm
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 def_default_handler NMI_Handler
sahilmgandhi 18:6a4db94011d3 182 def_default_handler HardFault_Handler
sahilmgandhi 18:6a4db94011d3 183 def_default_handler MemManage_Handler
sahilmgandhi 18:6a4db94011d3 184 def_default_handler BusFault_Handler
sahilmgandhi 18:6a4db94011d3 185 def_default_handler UsageFault_Handler
sahilmgandhi 18:6a4db94011d3 186 def_default_handler SVC_Handler
sahilmgandhi 18:6a4db94011d3 187 def_default_handler DebugMon_Handler
sahilmgandhi 18:6a4db94011d3 188 def_default_handler PendSV_Handler
sahilmgandhi 18:6a4db94011d3 189 def_default_handler SysTick_Handler
sahilmgandhi 18:6a4db94011d3 190 def_default_handler Default_Handler
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 .macro def_irq_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 193 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 194 .set \handler_name, Default_Handler
sahilmgandhi 18:6a4db94011d3 195 .endm
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 def_irq_default_handler WDT_IRQHandler
sahilmgandhi 18:6a4db94011d3 198 def_irq_default_handler BOD_IRQHandler
sahilmgandhi 18:6a4db94011d3 199 def_irq_default_handler FMC_IRQHandler
sahilmgandhi 18:6a4db94011d3 200 def_irq_default_handler EEPROM_IRQHandler
sahilmgandhi 18:6a4db94011d3 201 def_irq_default_handler DMA_IRQHandler
sahilmgandhi 18:6a4db94011d3 202 def_irq_default_handler GINT0_IRQHandler
sahilmgandhi 18:6a4db94011d3 203 def_irq_default_handler GINT1_IRQHandler
sahilmgandhi 18:6a4db94011d3 204 def_irq_default_handler PIN_INT0_IRQHandler
sahilmgandhi 18:6a4db94011d3 205 def_irq_default_handler PIN_INT1_IRQHandler
sahilmgandhi 18:6a4db94011d3 206 def_irq_default_handler PIN_INT2_IRQHandler
sahilmgandhi 18:6a4db94011d3 207 def_irq_default_handler PIN_INT3_IRQHandler
sahilmgandhi 18:6a4db94011d3 208 def_irq_default_handler PIN_INT4_IRQHandler
sahilmgandhi 18:6a4db94011d3 209 def_irq_default_handler PIN_INT5_IRQHandler
sahilmgandhi 18:6a4db94011d3 210 def_irq_default_handler PIN_INT6_IRQHandler
sahilmgandhi 18:6a4db94011d3 211 def_irq_default_handler PIN_INT7_IRQHandler
sahilmgandhi 18:6a4db94011d3 212 def_irq_default_handler RIT_IRQHandler
sahilmgandhi 18:6a4db94011d3 213 def_irq_default_handler SCT0_IRQHandler
sahilmgandhi 18:6a4db94011d3 214 def_irq_default_handler SCT1_IRQHandler
sahilmgandhi 18:6a4db94011d3 215 def_irq_default_handler SCT2_IRQHandler
sahilmgandhi 18:6a4db94011d3 216 def_irq_default_handler SCT3_IRQHandler
sahilmgandhi 18:6a4db94011d3 217 def_irq_default_handler MRT_IRQHandler
sahilmgandhi 18:6a4db94011d3 218 def_irq_default_handler UART0_IRQHandler
sahilmgandhi 18:6a4db94011d3 219 def_irq_default_handler UART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 220 def_irq_default_handler UART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 221 def_irq_default_handler I2C0_IRQHandler
sahilmgandhi 18:6a4db94011d3 222 def_irq_default_handler SPI0_IRQHandler
sahilmgandhi 18:6a4db94011d3 223 def_irq_default_handler SPI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 224 def_irq_default_handler CAN_IRQHandler
sahilmgandhi 18:6a4db94011d3 225 def_irq_default_handler USB_IRQHandler
sahilmgandhi 18:6a4db94011d3 226 def_irq_default_handler USB_FIQHandler
sahilmgandhi 18:6a4db94011d3 227 def_irq_default_handler USBWakeup_IRQHandler
sahilmgandhi 18:6a4db94011d3 228 def_irq_default_handler ADC0A_IRQHandler
sahilmgandhi 18:6a4db94011d3 229 def_irq_default_handler ADC0B_IRQHandler
sahilmgandhi 18:6a4db94011d3 230 def_irq_default_handler ADC0_THCMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 231 def_irq_default_handler ADC0_OVR_IRQHandler
sahilmgandhi 18:6a4db94011d3 232 def_irq_default_handler ADC1A_IRQHandler
sahilmgandhi 18:6a4db94011d3 233 def_irq_default_handler ADC1B_IRQHandler
sahilmgandhi 18:6a4db94011d3 234 def_irq_default_handler ADC1_THCMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 235 def_irq_default_handler ADC1_OVR_IRQHandler
sahilmgandhi 18:6a4db94011d3 236 def_irq_default_handler DAC_IRQHandler
sahilmgandhi 18:6a4db94011d3 237 def_irq_default_handler ACMP0_IRQHandler
sahilmgandhi 18:6a4db94011d3 238 def_irq_default_handler ACMP1_IRQHandler
sahilmgandhi 18:6a4db94011d3 239 def_irq_default_handler ACMP2_IRQHandler
sahilmgandhi 18:6a4db94011d3 240 def_irq_default_handler ACMP3_IRQHandler
sahilmgandhi 18:6a4db94011d3 241 def_irq_default_handler QEI_IRQHandler
sahilmgandhi 18:6a4db94011d3 242 def_irq_default_handler RTC_ALARM_IRQHandler
sahilmgandhi 18:6a4db94011d3 243 def_irq_default_handler RTC_WAKE_IRQHandler
sahilmgandhi 18:6a4db94011d3 244 def_irq_default_handler DEF_IRQHandler
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 .end
sahilmgandhi 18:6a4db94011d3 247