Mouse code for the MacroRat
mbed-dev/targets/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2006-2013 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | #include <stddef.h> |
sahilmgandhi | 18:6a4db94011d3 | 17 | |
sahilmgandhi | 18:6a4db94011d3 | 18 | #include "cmsis.h" |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "gpio_irq_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | #include "mbed_error.h" |
sahilmgandhi | 18:6a4db94011d3 | 21 | |
sahilmgandhi | 18:6a4db94011d3 | 22 | #if DEVICE_INTERRUPTIN |
sahilmgandhi | 18:6a4db94011d3 | 23 | |
sahilmgandhi | 18:6a4db94011d3 | 24 | #define CHANNEL_NUM 8 |
sahilmgandhi | 18:6a4db94011d3 | 25 | #define LPC_GPIO_X LPC_PINT |
sahilmgandhi | 18:6a4db94011d3 | 26 | #define PININT_IRQ PIN_INT0_IRQn |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
sahilmgandhi | 18:6a4db94011d3 | 29 | static gpio_irq_handler irq_handler; |
sahilmgandhi | 18:6a4db94011d3 | 30 | |
sahilmgandhi | 18:6a4db94011d3 | 31 | static inline void handle_interrupt_in(uint32_t channel) { |
sahilmgandhi | 18:6a4db94011d3 | 32 | uint32_t ch_bit = (1 << channel); |
sahilmgandhi | 18:6a4db94011d3 | 33 | // Return immediately if: |
sahilmgandhi | 18:6a4db94011d3 | 34 | // * The interrupt was already served |
sahilmgandhi | 18:6a4db94011d3 | 35 | // * There is no user handler |
sahilmgandhi | 18:6a4db94011d3 | 36 | // * It is a level interrupt, not an edge interrupt |
sahilmgandhi | 18:6a4db94011d3 | 37 | if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || |
sahilmgandhi | 18:6a4db94011d3 | 38 | (channel_ids[channel] == 0 ) || |
sahilmgandhi | 18:6a4db94011d3 | 39 | (LPC_GPIO_X->ISEL & ch_bit ) ) return; |
sahilmgandhi | 18:6a4db94011d3 | 40 | |
sahilmgandhi | 18:6a4db94011d3 | 41 | if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { |
sahilmgandhi | 18:6a4db94011d3 | 42 | irq_handler(channel_ids[channel], IRQ_RISE); |
sahilmgandhi | 18:6a4db94011d3 | 43 | LPC_GPIO_X->RISE = ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 44 | } |
sahilmgandhi | 18:6a4db94011d3 | 45 | if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { |
sahilmgandhi | 18:6a4db94011d3 | 46 | irq_handler(channel_ids[channel], IRQ_FALL); |
sahilmgandhi | 18:6a4db94011d3 | 47 | LPC_GPIO_X->FALL = ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 48 | } |
sahilmgandhi | 18:6a4db94011d3 | 49 | LPC_GPIO_X->IST = ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 50 | } |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | void gpio_irq0(void) {handle_interrupt_in(0);} |
sahilmgandhi | 18:6a4db94011d3 | 53 | void gpio_irq1(void) {handle_interrupt_in(1);} |
sahilmgandhi | 18:6a4db94011d3 | 54 | void gpio_irq2(void) {handle_interrupt_in(2);} |
sahilmgandhi | 18:6a4db94011d3 | 55 | void gpio_irq3(void) {handle_interrupt_in(3);} |
sahilmgandhi | 18:6a4db94011d3 | 56 | void gpio_irq4(void) {handle_interrupt_in(4);} |
sahilmgandhi | 18:6a4db94011d3 | 57 | void gpio_irq5(void) {handle_interrupt_in(5);} |
sahilmgandhi | 18:6a4db94011d3 | 58 | void gpio_irq6(void) {handle_interrupt_in(6);} |
sahilmgandhi | 18:6a4db94011d3 | 59 | void gpio_irq7(void) {handle_interrupt_in(7);} |
sahilmgandhi | 18:6a4db94011d3 | 60 | |
sahilmgandhi | 18:6a4db94011d3 | 61 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
sahilmgandhi | 18:6a4db94011d3 | 62 | // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO2_7 interrupt |
sahilmgandhi | 18:6a4db94011d3 | 63 | if (pin >= P2_8) return -1; |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | irq_handler = handler; |
sahilmgandhi | 18:6a4db94011d3 | 66 | |
sahilmgandhi | 18:6a4db94011d3 | 67 | int found_free_channel = 0; |
sahilmgandhi | 18:6a4db94011d3 | 68 | int i = 0; |
sahilmgandhi | 18:6a4db94011d3 | 69 | for (i=0; i<CHANNEL_NUM; i++) { |
sahilmgandhi | 18:6a4db94011d3 | 70 | if (channel_ids[i] == 0) { |
sahilmgandhi | 18:6a4db94011d3 | 71 | channel_ids[i] = id; |
sahilmgandhi | 18:6a4db94011d3 | 72 | obj->ch = i; |
sahilmgandhi | 18:6a4db94011d3 | 73 | found_free_channel = 1; |
sahilmgandhi | 18:6a4db94011d3 | 74 | break; |
sahilmgandhi | 18:6a4db94011d3 | 75 | } |
sahilmgandhi | 18:6a4db94011d3 | 76 | } |
sahilmgandhi | 18:6a4db94011d3 | 77 | if (!found_free_channel) return -1; |
sahilmgandhi | 18:6a4db94011d3 | 78 | |
sahilmgandhi | 18:6a4db94011d3 | 79 | /* Enable AHB clock to the PIN, GPIO and IOCON domain. */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7)); |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | /* Gets offset value for each port */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | uint32_t offset; |
sahilmgandhi | 18:6a4db94011d3 | 84 | switch ((pin >> PORT_SHIFT) & 0x3) { |
sahilmgandhi | 18:6a4db94011d3 | 85 | case 0: offset = 0; // PIO0[23:0] |
sahilmgandhi | 18:6a4db94011d3 | 86 | break; |
sahilmgandhi | 18:6a4db94011d3 | 87 | case 1: offset = 24; // PIO1[31:0] |
sahilmgandhi | 18:6a4db94011d3 | 88 | break; |
sahilmgandhi | 18:6a4db94011d3 | 89 | case 2: offset = 56; // PIO2[7:0] |
sahilmgandhi | 18:6a4db94011d3 | 90 | break; |
sahilmgandhi | 18:6a4db94011d3 | 91 | } |
sahilmgandhi | 18:6a4db94011d3 | 92 | /* Set the INTPIN number : offset + pin_number */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | LPC_SYSCON->PINTSEL[obj->ch] = (offset + ((pin >> PIN_SHIFT) & 0x1F)); |
sahilmgandhi | 18:6a4db94011d3 | 94 | |
sahilmgandhi | 18:6a4db94011d3 | 95 | // Interrupt Wake-Up Enable |
sahilmgandhi | 18:6a4db94011d3 | 96 | LPC_SYSCON->STARTERP0 |= (1 << obj->ch); |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | LPC_GPIO_PORT->DIR[(pin >> PORT_SHIFT) & 0x3] &= ~(1 << ((pin >> PIN_SHIFT) & 0x1F)); |
sahilmgandhi | 18:6a4db94011d3 | 99 | |
sahilmgandhi | 18:6a4db94011d3 | 100 | void (*channels_irq)(void) = NULL; |
sahilmgandhi | 18:6a4db94011d3 | 101 | switch (obj->ch) { |
sahilmgandhi | 18:6a4db94011d3 | 102 | case 0: channels_irq = &gpio_irq0; |
sahilmgandhi | 18:6a4db94011d3 | 103 | break; |
sahilmgandhi | 18:6a4db94011d3 | 104 | case 1: channels_irq = &gpio_irq1; |
sahilmgandhi | 18:6a4db94011d3 | 105 | break; |
sahilmgandhi | 18:6a4db94011d3 | 106 | case 2: channels_irq = &gpio_irq2; |
sahilmgandhi | 18:6a4db94011d3 | 107 | break; |
sahilmgandhi | 18:6a4db94011d3 | 108 | case 3: channels_irq = &gpio_irq3; |
sahilmgandhi | 18:6a4db94011d3 | 109 | break; |
sahilmgandhi | 18:6a4db94011d3 | 110 | case 4: channels_irq = &gpio_irq4; |
sahilmgandhi | 18:6a4db94011d3 | 111 | break; |
sahilmgandhi | 18:6a4db94011d3 | 112 | case 5: channels_irq = &gpio_irq5; |
sahilmgandhi | 18:6a4db94011d3 | 113 | break; |
sahilmgandhi | 18:6a4db94011d3 | 114 | case 6: channels_irq = &gpio_irq6; |
sahilmgandhi | 18:6a4db94011d3 | 115 | break; |
sahilmgandhi | 18:6a4db94011d3 | 116 | case 7: channels_irq = &gpio_irq7; |
sahilmgandhi | 18:6a4db94011d3 | 117 | break; |
sahilmgandhi | 18:6a4db94011d3 | 118 | } |
sahilmgandhi | 18:6a4db94011d3 | 119 | NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); |
sahilmgandhi | 18:6a4db94011d3 | 120 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
sahilmgandhi | 18:6a4db94011d3 | 121 | |
sahilmgandhi | 18:6a4db94011d3 | 122 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 123 | } |
sahilmgandhi | 18:6a4db94011d3 | 124 | |
sahilmgandhi | 18:6a4db94011d3 | 125 | void gpio_irq_free(gpio_irq_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 126 | channel_ids[obj->ch] = 0; |
sahilmgandhi | 18:6a4db94011d3 | 127 | LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch); |
sahilmgandhi | 18:6a4db94011d3 | 128 | } |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
sahilmgandhi | 18:6a4db94011d3 | 131 | unsigned int ch_bit = (1 << obj->ch); |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | // Clear interrupt |
sahilmgandhi | 18:6a4db94011d3 | 134 | if (!(LPC_GPIO_X->ISEL & ch_bit)) |
sahilmgandhi | 18:6a4db94011d3 | 135 | LPC_GPIO_X->IST = ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 136 | |
sahilmgandhi | 18:6a4db94011d3 | 137 | // Edge trigger |
sahilmgandhi | 18:6a4db94011d3 | 138 | LPC_GPIO_X->ISEL &= ~ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 139 | if (event == IRQ_RISE) { |
sahilmgandhi | 18:6a4db94011d3 | 140 | if (enable) { |
sahilmgandhi | 18:6a4db94011d3 | 141 | LPC_GPIO_X->IENR |= ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 142 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 143 | LPC_GPIO_X->IENR &= ~ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 144 | } |
sahilmgandhi | 18:6a4db94011d3 | 145 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 146 | if (enable) { |
sahilmgandhi | 18:6a4db94011d3 | 147 | LPC_GPIO_X->IENF |= ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 148 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 149 | LPC_GPIO_X->IENF &= ~ch_bit; |
sahilmgandhi | 18:6a4db94011d3 | 150 | } |
sahilmgandhi | 18:6a4db94011d3 | 151 | } |
sahilmgandhi | 18:6a4db94011d3 | 152 | } |
sahilmgandhi | 18:6a4db94011d3 | 153 | |
sahilmgandhi | 18:6a4db94011d3 | 154 | void gpio_irq_enable(gpio_irq_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 155 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
sahilmgandhi | 18:6a4db94011d3 | 156 | } |
sahilmgandhi | 18:6a4db94011d3 | 157 | |
sahilmgandhi | 18:6a4db94011d3 | 158 | void gpio_irq_disable(gpio_irq_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 159 | NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
sahilmgandhi | 18:6a4db94011d3 | 160 | } |
sahilmgandhi | 18:6a4db94011d3 | 161 | |
sahilmgandhi | 18:6a4db94011d3 | 162 | #endif |