MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file system_NUC472_442.c
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 15 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 14/05/29 1:13p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 system clock init code and assert handler
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 #include "NUC472_442.h"
sahilmgandhi 18:6a4db94011d3 13 //#include "rtc.h"
sahilmgandhi 18:6a4db94011d3 14
sahilmgandhi 18:6a4db94011d3 15 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 17 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 18 uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 19 uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
sahilmgandhi 18:6a4db94011d3 20 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC}; /*!< System clock source table */
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #if defined TARGET_NU_XRAM_SUPPORTED
sahilmgandhi 18:6a4db94011d3 23 static void nu_ebi_init(void);
sahilmgandhi 18:6a4db94011d3 24 #endif
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 27 Clock functions
sahilmgandhi 18:6a4db94011d3 28 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 29 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 30 {
sahilmgandhi 18:6a4db94011d3 31 uint32_t u32Freq, u32ClkSrc;
sahilmgandhi 18:6a4db94011d3 32 uint32_t u32HclkDiv;
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL) {
sahilmgandhi 18:6a4db94011d3 37 /* Use the clock sources directly */
sahilmgandhi 18:6a4db94011d3 38 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
sahilmgandhi 18:6a4db94011d3 39 } else {
sahilmgandhi 18:6a4db94011d3 40 /* Use PLL clock */
sahilmgandhi 18:6a4db94011d3 41 u32Freq = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 42 }
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Update System Core Clock */
sahilmgandhi 18:6a4db94011d3 47 SystemCoreClock = u32Freq/u32HclkDiv;
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
sahilmgandhi 18:6a4db94011d3 50 }
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /**
sahilmgandhi 18:6a4db94011d3 53 * Initialize the system
sahilmgandhi 18:6a4db94011d3 54 *
sahilmgandhi 18:6a4db94011d3 55 * @return none
sahilmgandhi 18:6a4db94011d3 56 *
sahilmgandhi 18:6a4db94011d3 57 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 58 */
sahilmgandhi 18:6a4db94011d3 59 void SystemInit (void)
sahilmgandhi 18:6a4db94011d3 60 {
sahilmgandhi 18:6a4db94011d3 61 //uint32_t u32RTC_EN_Flag = 0;
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /* FPU settings ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 64 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 65 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
sahilmgandhi 18:6a4db94011d3 66 (3UL << 11*2) ); /* set CP11 Full Access */
sahilmgandhi 18:6a4db94011d3 67 #endif
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /* The code snippet below is for old-version chip and has potential risk, e.g. program reboots and hangs in it with the call to NVIC_SystemReset(). Remove it for new-version chip. */
sahilmgandhi 18:6a4db94011d3 70 #if 0
sahilmgandhi 18:6a4db94011d3 71 /* ------------------ Release Tamper pin ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 72 /* Waiting for 10kHz clock ready */
sahilmgandhi 18:6a4db94011d3 73 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 u32RTC_EN_Flag = ((CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk) >> CLK_APBCLK0_RTCCKEN_Pos);
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 if(!u32RTC_EN_Flag) {
sahilmgandhi 18:6a4db94011d3 78 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Enable
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 RTC->INIT = RTC_INIT_KEY;
sahilmgandhi 18:6a4db94011d3 82 while(RTC->INIT != 0x1);
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 if(!(RTC->TAMPCTL & RTC_TAMPCTL_TIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 85 RTC->RWEN = RTC_WRITE_KEY;
sahilmgandhi 18:6a4db94011d3 86 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 RTC->RWEN = RTC_WRITE_KEY;
sahilmgandhi 18:6a4db94011d3 93 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 RTC->SPR[23] = RTC->SPR[23];
sahilmgandhi 18:6a4db94011d3 96 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 RTC->RWEN = RTC_WRITE_KEY;
sahilmgandhi 18:6a4db94011d3 99 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
sahilmgandhi 18:6a4db94011d3 102 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 RTC->RWEN = RTC_WRITE_KEY;
sahilmgandhi 18:6a4db94011d3 105 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 if(!u32RTC_EN_Flag) {
sahilmgandhi 18:6a4db94011d3 111 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Disable
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113 /*------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 114 #endif
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 #if defined TARGET_NU_XRAM_SUPPORTED
sahilmgandhi 18:6a4db94011d3 117 // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
sahilmgandhi 18:6a4db94011d3 118 nu_ebi_init();
sahilmgandhi 18:6a4db94011d3 119 #endif
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 #if defined TARGET_NU_XRAM_SUPPORTED
sahilmgandhi 18:6a4db94011d3 123 void nu_ebi_init(void)
sahilmgandhi 18:6a4db94011d3 124 {
sahilmgandhi 18:6a4db94011d3 125 /* Enable IP clock */
sahilmgandhi 18:6a4db94011d3 126 CLK_EnableModuleClock(EBI_MODULE);
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* Configure EBI multi-function pins */
sahilmgandhi 18:6a4db94011d3 129 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA10MFP_Msk) ) | SYS_GPA_MFPH_PA10MFP_EBI_A20; /* A20. = PA10 */
sahilmgandhi 18:6a4db94011d3 130 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA9MFP_Msk) ) | SYS_GPA_MFPH_PA9MFP_EBI_A19; /* A19. = PA9 */
sahilmgandhi 18:6a4db94011d3 131 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA8MFP_Msk) ) | SYS_GPA_MFPH_PA8MFP_EBI_A18; /* A18. = PA8 */
sahilmgandhi 18:6a4db94011d3 132 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA7MFP_Msk) ) | SYS_GPA_MFPL_PA7MFP_EBI_A17; /* A17. = PA7 */
sahilmgandhi 18:6a4db94011d3 133 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA6MFP_Msk) ) | SYS_GPA_MFPL_PA6MFP_EBI_A16; /* A16. = PA6 */
sahilmgandhi 18:6a4db94011d3 134 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB13MFP_Msk) ) | SYS_GPB_MFPH_PB13MFP_EBI_AD15; /* AD15 = PB13 */
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB12MFP_Msk) ) | SYS_GPB_MFPH_PB12MFP_EBI_AD14; /* AD14 = PB12 */
sahilmgandhi 18:6a4db94011d3 137 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB11MFP_Msk) ) | SYS_GPB_MFPH_PB11MFP_EBI_AD13; /* AD13 = PB11 */
sahilmgandhi 18:6a4db94011d3 138 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB10MFP_Msk) ) | SYS_GPB_MFPH_PB10MFP_EBI_AD12; /* AD12 = PB10 */
sahilmgandhi 18:6a4db94011d3 139 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB9MFP_Msk) ) | SYS_GPB_MFPH_PB9MFP_EBI_AD11; /* AD11 = PB9 */
sahilmgandhi 18:6a4db94011d3 140 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB8MFP_Msk) ) | SYS_GPB_MFPH_PB8MFP_EBI_AD10; /* AD10 = PB8 */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB7MFP_Msk) ) | SYS_GPB_MFPL_PB7MFP_EBI_AD9; /* AD9 = PB7 */
sahilmgandhi 18:6a4db94011d3 143 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB6MFP_Msk) ) | SYS_GPB_MFPL_PB6MFP_EBI_AD8; /* AD8 = PB6 */
sahilmgandhi 18:6a4db94011d3 144 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB5MFP_Msk) ) | SYS_GPB_MFPL_PB5MFP_EBI_AD7; /* AD7 = PB5 */
sahilmgandhi 18:6a4db94011d3 145 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB4MFP_Msk) ) | SYS_GPB_MFPL_PB4MFP_EBI_AD6; /* AD6 = PB4 */
sahilmgandhi 18:6a4db94011d3 146 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB3MFP_Msk) ) | SYS_GPB_MFPL_PB3MFP_EBI_AD5; /* AD5 = PB3 */
sahilmgandhi 18:6a4db94011d3 147 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB2MFP_Msk) ) | SYS_GPB_MFPL_PB2MFP_EBI_AD4; /* AD4 = PB2 */
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA14MFP_Msk) ) | SYS_GPA_MFPH_PA14MFP_EBI_AD3; /* AD3. = PA14 */
sahilmgandhi 18:6a4db94011d3 150 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA13MFP_Msk) ) | SYS_GPA_MFPH_PA13MFP_EBI_AD2; /* AD2. = PA13 */
sahilmgandhi 18:6a4db94011d3 151 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA12MFP_Msk) ) | SYS_GPA_MFPH_PA12MFP_EBI_AD1; /* AD1. = PA12 */
sahilmgandhi 18:6a4db94011d3 152 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA11MFP_Msk) ) | SYS_GPA_MFPH_PA11MFP_EBI_AD0; /* AD0. = PA11 */
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE6MFP_Msk) ) | SYS_GPE_MFPL_PE6MFP_EBI_nWR; /* PE.6 = nWR */
sahilmgandhi 18:6a4db94011d3 155 SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE7MFP_Msk) ) | SYS_GPE_MFPL_PE7MFP_EBI_nRD; /* PE.7 = nRD */
sahilmgandhi 18:6a4db94011d3 156 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE8MFP_Msk) ) | SYS_GPE_MFPH_PE8MFP_EBI_ALE; /* PE.8 = ALE */
sahilmgandhi 18:6a4db94011d3 157 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE9MFP_Msk) ) | SYS_GPE_MFPH_PE9MFP_EBI_nWRH; /* PE.9 = WRH */
sahilmgandhi 18:6a4db94011d3 158 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE10MFP_Msk) ) | SYS_GPE_MFPH_PE10MFP_EBI_nWRL; /* PE.10 = WRL */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE11MFP_Msk) ) | SYS_GPE_MFPH_PE11MFP_EBI_nCS0; /* PE.11 = nCS0 */
sahilmgandhi 18:6a4db94011d3 161 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE12MFP_Msk) ) | SYS_GPE_MFPH_PE12MFP_EBI_nCS1; /* PE.12 = nCS1 */
sahilmgandhi 18:6a4db94011d3 162 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE13MFP_Msk) ) | SYS_GPE_MFPH_PE13MFP_EBI_nCS2; /* PE.13 = nCS2 */
sahilmgandhi 18:6a4db94011d3 163 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE14MFP_Msk) ) | SYS_GPE_MFPH_PE14MFP_EBI_nCS3; /* PE.14 = nCS3 */
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 const uint32_t u32Timing = 0x21C;
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /* Open EBI interface */
sahilmgandhi 18:6a4db94011d3 168 EBI_Open(EBI_BANK0, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
sahilmgandhi 18:6a4db94011d3 169 EBI_Open(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
sahilmgandhi 18:6a4db94011d3 170 EBI_Open(EBI_BANK2, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
sahilmgandhi 18:6a4db94011d3 171 EBI_Open(EBI_BANK3, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /* Configure EBI timing */
sahilmgandhi 18:6a4db94011d3 174 EBI_SetBusTiming(EBI_BANK0, u32Timing, EBI_MCLKDIV_2);
sahilmgandhi 18:6a4db94011d3 175 EBI_SetBusTiming(EBI_BANK1, u32Timing, EBI_MCLKDIV_2);
sahilmgandhi 18:6a4db94011d3 176 EBI_SetBusTiming(EBI_BANK2, u32Timing, EBI_MCLKDIV_2);
sahilmgandhi 18:6a4db94011d3 177 EBI_SetBusTiming(EBI_BANK3, u32Timing, EBI_MCLKDIV_2);
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179 #endif
sahilmgandhi 18:6a4db94011d3 180 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/