Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2015-2016 Nuvoton |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | |
sahilmgandhi | 18:6a4db94011d3 | 17 | #ifndef MBED_CMSIS_NVIC_H |
sahilmgandhi | 18:6a4db94011d3 | 18 | #define MBED_CMSIS_NVIC_H |
sahilmgandhi | 18:6a4db94011d3 | 19 | |
sahilmgandhi | 18:6a4db94011d3 | 20 | #include "cmsis.h" |
sahilmgandhi | 18:6a4db94011d3 | 21 | |
sahilmgandhi | 18:6a4db94011d3 | 22 | #define NVIC_USER_IRQ_OFFSET 16 |
sahilmgandhi | 18:6a4db94011d3 | 23 | #define NVIC_USER_IRQ_NUMBER 142 |
sahilmgandhi | 18:6a4db94011d3 | 24 | #define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) |
sahilmgandhi | 18:6a4db94011d3 | 25 | |
sahilmgandhi | 18:6a4db94011d3 | 26 | #if defined(__CC_ARM) |
sahilmgandhi | 18:6a4db94011d3 | 27 | # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) |
sahilmgandhi | 18:6a4db94011d3 | 28 | #elif defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 29 | # pragma section = "IRAMVEC" |
sahilmgandhi | 18:6a4db94011d3 | 30 | # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC")) |
sahilmgandhi | 18:6a4db94011d3 | 31 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 32 | # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) |
sahilmgandhi | 18:6a4db94011d3 | 33 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 34 | |
sahilmgandhi | 18:6a4db94011d3 | 35 | #if defined(__CC_ARM) |
sahilmgandhi | 18:6a4db94011d3 | 36 | extern uint32_t Load$$LR$$LR_IROM1$$Base[]; |
sahilmgandhi | 18:6a4db94011d3 | 37 | #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) |
sahilmgandhi | 18:6a4db94011d3 | 38 | #elif defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 39 | #pragma section=".intvec" |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) |
sahilmgandhi | 18:6a4db94011d3 | 41 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 42 | extern uint32_t __vector_table; |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)&__vector_table) |
sahilmgandhi | 18:6a4db94011d3 | 44 | #else |
sahilmgandhi | 18:6a4db94011d3 | 45 | #error "Flash vector address not set for this toolchain" |
sahilmgandhi | 18:6a4db94011d3 | 46 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 47 | |
sahilmgandhi | 18:6a4db94011d3 | 48 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 49 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 50 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | /** Set the ISR for IRQn |
sahilmgandhi | 18:6a4db94011d3 | 53 | * |
sahilmgandhi | 18:6a4db94011d3 | 54 | * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM |
sahilmgandhi | 18:6a4db94011d3 | 55 | * the first time this function is called |
sahilmgandhi | 18:6a4db94011d3 | 56 | * @param[in] IRQn The Interrupt Request number for which a vector will be registered |
sahilmgandhi | 18:6a4db94011d3 | 57 | * @param[in] vector The ISR vector to register for IRQn |
sahilmgandhi | 18:6a4db94011d3 | 58 | */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); |
sahilmgandhi | 18:6a4db94011d3 | 60 | |
sahilmgandhi | 18:6a4db94011d3 | 61 | /** Get the ISR registered for IRQn |
sahilmgandhi | 18:6a4db94011d3 | 62 | * |
sahilmgandhi | 18:6a4db94011d3 | 63 | * Reads the Interrupt Service Routine currently registered for IRQn |
sahilmgandhi | 18:6a4db94011d3 | 64 | * @param[in] IRQn The Interrupt Request number the vector of which will be read |
sahilmgandhi | 18:6a4db94011d3 | 65 | * @return Returns the ISR registered for IRQn |
sahilmgandhi | 18:6a4db94011d3 | 66 | */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | uint32_t NVIC_GetVector(IRQn_Type IRQn); |
sahilmgandhi | 18:6a4db94011d3 | 68 | |
sahilmgandhi | 18:6a4db94011d3 | 69 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 70 | } |
sahilmgandhi | 18:6a4db94011d3 | 71 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 72 | |
sahilmgandhi | 18:6a4db94011d3 | 73 | #endif |