Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2015-2016 Nuvoton |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | |
sahilmgandhi | 18:6a4db94011d3 | 17 | #include "dma_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 18 | #include "string.h" |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "cmsis.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | #include "mbed_assert.h" |
sahilmgandhi | 18:6a4db94011d3 | 21 | #include "PeripheralNames.h" |
sahilmgandhi | 18:6a4db94011d3 | 22 | #include "nu_modutil.h" |
sahilmgandhi | 18:6a4db94011d3 | 23 | #include "nu_bitutil.h" |
sahilmgandhi | 18:6a4db94011d3 | 24 | #include "dma.h" |
sahilmgandhi | 18:6a4db94011d3 | 25 | |
sahilmgandhi | 18:6a4db94011d3 | 26 | struct nu_dma_chn_s { |
sahilmgandhi | 18:6a4db94011d3 | 27 | void (*handler)(uint32_t, uint32_t); |
sahilmgandhi | 18:6a4db94011d3 | 28 | uint32_t id; |
sahilmgandhi | 18:6a4db94011d3 | 29 | uint32_t event; |
sahilmgandhi | 18:6a4db94011d3 | 30 | }; |
sahilmgandhi | 18:6a4db94011d3 | 31 | |
sahilmgandhi | 18:6a4db94011d3 | 32 | static int dma_inited = 0; |
sahilmgandhi | 18:6a4db94011d3 | 33 | static uint32_t dma_chn_mask = 0; |
sahilmgandhi | 18:6a4db94011d3 | 34 | static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX]; |
sahilmgandhi | 18:6a4db94011d3 | 35 | |
sahilmgandhi | 18:6a4db94011d3 | 36 | static void pdma_vec(void); |
sahilmgandhi | 18:6a4db94011d3 | 37 | static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec}; |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | void dma_init(void) |
sahilmgandhi | 18:6a4db94011d3 | 41 | { |
sahilmgandhi | 18:6a4db94011d3 | 42 | if (dma_inited) { |
sahilmgandhi | 18:6a4db94011d3 | 43 | return; |
sahilmgandhi | 18:6a4db94011d3 | 44 | } |
sahilmgandhi | 18:6a4db94011d3 | 45 | |
sahilmgandhi | 18:6a4db94011d3 | 46 | dma_inited = 1; |
sahilmgandhi | 18:6a4db94011d3 | 47 | dma_chn_mask = 0; |
sahilmgandhi | 18:6a4db94011d3 | 48 | memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); |
sahilmgandhi | 18:6a4db94011d3 | 49 | |
sahilmgandhi | 18:6a4db94011d3 | 50 | // Reset this module |
sahilmgandhi | 18:6a4db94011d3 | 51 | SYS_ResetModule(dma_modinit.rsetidx); |
sahilmgandhi | 18:6a4db94011d3 | 52 | |
sahilmgandhi | 18:6a4db94011d3 | 53 | // Enable IP clock |
sahilmgandhi | 18:6a4db94011d3 | 54 | CLK_EnableModuleClock(dma_modinit.clkidx); |
sahilmgandhi | 18:6a4db94011d3 | 55 | |
sahilmgandhi | 18:6a4db94011d3 | 56 | PDMA_Open(0); |
sahilmgandhi | 18:6a4db94011d3 | 57 | |
sahilmgandhi | 18:6a4db94011d3 | 58 | NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); |
sahilmgandhi | 18:6a4db94011d3 | 59 | NVIC_EnableIRQ(dma_modinit.irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 60 | } |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | int dma_channel_allocate(uint32_t capabilities) |
sahilmgandhi | 18:6a4db94011d3 | 63 | { |
sahilmgandhi | 18:6a4db94011d3 | 64 | if (! dma_inited) { |
sahilmgandhi | 18:6a4db94011d3 | 65 | dma_init(); |
sahilmgandhi | 18:6a4db94011d3 | 66 | } |
sahilmgandhi | 18:6a4db94011d3 | 67 | |
sahilmgandhi | 18:6a4db94011d3 | 68 | #if 1 |
sahilmgandhi | 18:6a4db94011d3 | 69 | int i = nu_cto(dma_chn_mask); |
sahilmgandhi | 18:6a4db94011d3 | 70 | if (i != 32) { |
sahilmgandhi | 18:6a4db94011d3 | 71 | dma_chn_mask |= 1 << i; |
sahilmgandhi | 18:6a4db94011d3 | 72 | memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s)); |
sahilmgandhi | 18:6a4db94011d3 | 73 | return i; |
sahilmgandhi | 18:6a4db94011d3 | 74 | } |
sahilmgandhi | 18:6a4db94011d3 | 75 | #else |
sahilmgandhi | 18:6a4db94011d3 | 76 | int i; |
sahilmgandhi | 18:6a4db94011d3 | 77 | |
sahilmgandhi | 18:6a4db94011d3 | 78 | for (i = 0; i < PDMA_CH_MAX; i ++) { |
sahilmgandhi | 18:6a4db94011d3 | 79 | if ((dma_chn_mask & (1 << i)) == 0) { |
sahilmgandhi | 18:6a4db94011d3 | 80 | // Channel available |
sahilmgandhi | 18:6a4db94011d3 | 81 | dma_chn_mask |= 1 << i; |
sahilmgandhi | 18:6a4db94011d3 | 82 | memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s)); |
sahilmgandhi | 18:6a4db94011d3 | 83 | return i; |
sahilmgandhi | 18:6a4db94011d3 | 84 | } |
sahilmgandhi | 18:6a4db94011d3 | 85 | } |
sahilmgandhi | 18:6a4db94011d3 | 86 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | // No channel available |
sahilmgandhi | 18:6a4db94011d3 | 89 | return DMA_ERROR_OUT_OF_CHANNELS; |
sahilmgandhi | 18:6a4db94011d3 | 90 | } |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | int dma_channel_free(int channelid) |
sahilmgandhi | 18:6a4db94011d3 | 93 | { |
sahilmgandhi | 18:6a4db94011d3 | 94 | if (channelid != DMA_ERROR_OUT_OF_CHANNELS) { |
sahilmgandhi | 18:6a4db94011d3 | 95 | dma_chn_mask &= ~(1 << channelid); |
sahilmgandhi | 18:6a4db94011d3 | 96 | } |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 99 | } |
sahilmgandhi | 18:6a4db94011d3 | 100 | |
sahilmgandhi | 18:6a4db94011d3 | 101 | void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event) |
sahilmgandhi | 18:6a4db94011d3 | 102 | { |
sahilmgandhi | 18:6a4db94011d3 | 103 | MBED_ASSERT(dma_chn_mask & (1 << channelid)); |
sahilmgandhi | 18:6a4db94011d3 | 104 | |
sahilmgandhi | 18:6a4db94011d3 | 105 | dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler; |
sahilmgandhi | 18:6a4db94011d3 | 106 | dma_chn_arr[channelid].id = id; |
sahilmgandhi | 18:6a4db94011d3 | 107 | dma_chn_arr[channelid].event = event; |
sahilmgandhi | 18:6a4db94011d3 | 108 | |
sahilmgandhi | 18:6a4db94011d3 | 109 | // Set interrupt vector if someone has removed it. |
sahilmgandhi | 18:6a4db94011d3 | 110 | NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); |
sahilmgandhi | 18:6a4db94011d3 | 111 | NVIC_EnableIRQ(dma_modinit.irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 112 | } |
sahilmgandhi | 18:6a4db94011d3 | 113 | |
sahilmgandhi | 18:6a4db94011d3 | 114 | PDMA_T *dma_modbase(void) |
sahilmgandhi | 18:6a4db94011d3 | 115 | { |
sahilmgandhi | 18:6a4db94011d3 | 116 | return (PDMA_T *) NU_MODBASE(dma_modinit.modname); |
sahilmgandhi | 18:6a4db94011d3 | 117 | } |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | static void pdma_vec(void) |
sahilmgandhi | 18:6a4db94011d3 | 120 | { |
sahilmgandhi | 18:6a4db94011d3 | 121 | uint32_t intsts = PDMA_GET_INT_STATUS(); |
sahilmgandhi | 18:6a4db94011d3 | 122 | |
sahilmgandhi | 18:6a4db94011d3 | 123 | // Abort |
sahilmgandhi | 18:6a4db94011d3 | 124 | if (intsts & PDMA_INTSTS_ABTIF_Msk) { |
sahilmgandhi | 18:6a4db94011d3 | 125 | uint32_t abtsts = PDMA_GET_ABORT_STS(); |
sahilmgandhi | 18:6a4db94011d3 | 126 | // Clear all Abort flags |
sahilmgandhi | 18:6a4db94011d3 | 127 | PDMA_CLR_ABORT_FLAG(abtsts); |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | while (abtsts) { |
sahilmgandhi | 18:6a4db94011d3 | 130 | int chn_id = nu_ctz(abtsts); |
sahilmgandhi | 18:6a4db94011d3 | 131 | if (dma_chn_mask & (1 << chn_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 132 | struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; |
sahilmgandhi | 18:6a4db94011d3 | 133 | if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { |
sahilmgandhi | 18:6a4db94011d3 | 134 | dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); |
sahilmgandhi | 18:6a4db94011d3 | 135 | } |
sahilmgandhi | 18:6a4db94011d3 | 136 | } |
sahilmgandhi | 18:6a4db94011d3 | 137 | abtsts &= ~(1 << chn_id); |
sahilmgandhi | 18:6a4db94011d3 | 138 | } |
sahilmgandhi | 18:6a4db94011d3 | 139 | } |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | // Transfer done |
sahilmgandhi | 18:6a4db94011d3 | 142 | if (intsts & PDMA_INTSTS_TDIF_Msk) { |
sahilmgandhi | 18:6a4db94011d3 | 143 | uint32_t tdsts = PDMA_GET_TD_STS(); |
sahilmgandhi | 18:6a4db94011d3 | 144 | // Clear all transfer done flags |
sahilmgandhi | 18:6a4db94011d3 | 145 | PDMA_CLR_TD_FLAG(tdsts); |
sahilmgandhi | 18:6a4db94011d3 | 146 | |
sahilmgandhi | 18:6a4db94011d3 | 147 | while (tdsts) { |
sahilmgandhi | 18:6a4db94011d3 | 148 | int chn_id = nu_ctz(tdsts); |
sahilmgandhi | 18:6a4db94011d3 | 149 | if (dma_chn_mask & (1 << chn_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 150 | struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; |
sahilmgandhi | 18:6a4db94011d3 | 151 | if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { |
sahilmgandhi | 18:6a4db94011d3 | 152 | dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); |
sahilmgandhi | 18:6a4db94011d3 | 153 | } |
sahilmgandhi | 18:6a4db94011d3 | 154 | } |
sahilmgandhi | 18:6a4db94011d3 | 155 | tdsts &= ~(1 << chn_id); |
sahilmgandhi | 18:6a4db94011d3 | 156 | } |
sahilmgandhi | 18:6a4db94011d3 | 157 | } |
sahilmgandhi | 18:6a4db94011d3 | 158 | |
sahilmgandhi | 18:6a4db94011d3 | 159 | // Table empty |
sahilmgandhi | 18:6a4db94011d3 | 160 | if (intsts & PDMA_INTSTS_TEIF_Msk) { |
sahilmgandhi | 18:6a4db94011d3 | 161 | uint32_t scatsts = PDMA_GET_EMPTY_STS(); |
sahilmgandhi | 18:6a4db94011d3 | 162 | // Clear all table empty flags |
sahilmgandhi | 18:6a4db94011d3 | 163 | PDMA_CLR_EMPTY_FLAG(scatsts); |
sahilmgandhi | 18:6a4db94011d3 | 164 | } |
sahilmgandhi | 18:6a4db94011d3 | 165 | |
sahilmgandhi | 18:6a4db94011d3 | 166 | // Timeout |
sahilmgandhi | 18:6a4db94011d3 | 167 | uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 168 | if (reqto) { |
sahilmgandhi | 18:6a4db94011d3 | 169 | // Clear all Timeout flags |
sahilmgandhi | 18:6a4db94011d3 | 170 | PDMA->INTSTS = reqto; |
sahilmgandhi | 18:6a4db94011d3 | 171 | |
sahilmgandhi | 18:6a4db94011d3 | 172 | while (reqto) { |
sahilmgandhi | 18:6a4db94011d3 | 173 | int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos; |
sahilmgandhi | 18:6a4db94011d3 | 174 | if (dma_chn_mask & (1 << chn_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 175 | struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; |
sahilmgandhi | 18:6a4db94011d3 | 176 | if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { |
sahilmgandhi | 18:6a4db94011d3 | 177 | dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); |
sahilmgandhi | 18:6a4db94011d3 | 178 | } |
sahilmgandhi | 18:6a4db94011d3 | 179 | } |
sahilmgandhi | 18:6a4db94011d3 | 180 | reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos)); |
sahilmgandhi | 18:6a4db94011d3 | 181 | } |
sahilmgandhi | 18:6a4db94011d3 | 182 | } |
sahilmgandhi | 18:6a4db94011d3 | 183 | } |