MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 3 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 6 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * 1. Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 9 * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 12 * integrated circuit in a product or a software update for such product, must reproduce
sahilmgandhi 18:6a4db94011d3 13 * the above copyright notice, this list of conditions and the following disclaimer in
sahilmgandhi 18:6a4db94011d3 14 * the documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
sahilmgandhi 18:6a4db94011d3 17 * used to endorse or promote products derived from this software without specific prior
sahilmgandhi 18:6a4db94011d3 18 * written permission.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * 4. This software, with or without modification, must only be used with a
sahilmgandhi 18:6a4db94011d3 21 * Nordic Semiconductor ASA integrated circuit.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * 5. Any software provided in binary or object form under this license must not be reverse
sahilmgandhi 18:6a4db94011d3 24 * engineered, decompiled, modified and/or disassembled.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 36 *
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 #ifndef __NRF52_BITS_H
sahilmgandhi 18:6a4db94011d3 40 #define __NRF52_BITS_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /*lint ++flb "Enter library region" */
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /* Peripheral: AAR */
sahilmgandhi 18:6a4db94011d3 45 /* Description: Accelerated Address Resolver */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /* Register: AAR_INTENSET */
sahilmgandhi 18:6a4db94011d3 48 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
sahilmgandhi 18:6a4db94011d3 51 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 52 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 53 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 54 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 55 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
sahilmgandhi 18:6a4db94011d3 58 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 59 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 60 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 61 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 62 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /* Bit 0 : Write '1' to Enable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 65 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 66 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 67 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 68 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 69 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /* Register: AAR_INTENCLR */
sahilmgandhi 18:6a4db94011d3 72 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
sahilmgandhi 18:6a4db94011d3 75 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 76 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 77 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 78 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 79 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
sahilmgandhi 18:6a4db94011d3 82 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 83 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 84 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 85 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 86 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* Bit 0 : Write '1' to Disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 89 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 90 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 91 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 92 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 93 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /* Register: AAR_STATUS */
sahilmgandhi 18:6a4db94011d3 96 /* Description: Resolution status */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /* Bits 3..0 : The IRK that was used last time an address was resolved */
sahilmgandhi 18:6a4db94011d3 99 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 100 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /* Register: AAR_ENABLE */
sahilmgandhi 18:6a4db94011d3 103 /* Description: Enable AAR */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /* Bits 1..0 : Enable or disable AAR */
sahilmgandhi 18:6a4db94011d3 106 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 107 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 108 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 109 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /* Register: AAR_NIRK */
sahilmgandhi 18:6a4db94011d3 112 /* Description: Number of IRKs */
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
sahilmgandhi 18:6a4db94011d3 115 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
sahilmgandhi 18:6a4db94011d3 116 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* Register: AAR_IRKPTR */
sahilmgandhi 18:6a4db94011d3 119 /* Description: Pointer to IRK data structure */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Bits 31..0 : Pointer to the IRK data structure */
sahilmgandhi 18:6a4db94011d3 122 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
sahilmgandhi 18:6a4db94011d3 123 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /* Register: AAR_ADDRPTR */
sahilmgandhi 18:6a4db94011d3 126 /* Description: Pointer to the resolvable address */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
sahilmgandhi 18:6a4db94011d3 129 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
sahilmgandhi 18:6a4db94011d3 130 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /* Register: AAR_SCRATCHPTR */
sahilmgandhi 18:6a4db94011d3 133 /* Description: Pointer to data area used for temporary storage */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
sahilmgandhi 18:6a4db94011d3 136 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
sahilmgandhi 18:6a4db94011d3 137 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 /* Peripheral: AMLI */
sahilmgandhi 18:6a4db94011d3 141 /* Description: AHB Multi-Layer Interface */
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 /* Register: AMLI_RAMPRI_CPU0 */
sahilmgandhi 18:6a4db94011d3 144 /* Description: AHB bus master priority register for CPU0 */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 147 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 148 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 149 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 150 #define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 151 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 152 #define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 153 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 154 #define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 155 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 156 #define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 157 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 158 #define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 159 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 160 #define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 161 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 162 #define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 163 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 164 #define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 167 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 168 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 169 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 170 #define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 171 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 172 #define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 173 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 174 #define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 175 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 176 #define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 177 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 178 #define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 179 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 180 #define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 181 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 182 #define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 183 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 184 #define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 187 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 188 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 189 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 190 #define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 191 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 192 #define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 193 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 194 #define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 195 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 196 #define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 197 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 198 #define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 199 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 200 #define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 201 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 202 #define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 203 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 204 #define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 207 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 208 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 209 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 210 #define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 211 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 212 #define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 213 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 214 #define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 215 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 216 #define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 217 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 218 #define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 219 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 220 #define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 221 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 222 #define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 223 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 224 #define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 227 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 228 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 229 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 230 #define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 231 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 232 #define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 233 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 234 #define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 235 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 236 #define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 237 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 238 #define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 239 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 240 #define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 241 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 242 #define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 243 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 244 #define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 247 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 248 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 249 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 250 #define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 251 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 252 #define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 253 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 254 #define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 255 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 256 #define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 257 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 258 #define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 259 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 260 #define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 261 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 262 #define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 263 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 264 #define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 267 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 268 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 269 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 270 #define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 271 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 272 #define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 273 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 274 #define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 275 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 276 #define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 277 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 278 #define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 279 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 280 #define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 281 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 282 #define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 283 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 284 #define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 287 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 288 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 289 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 290 #define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 291 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 292 #define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 293 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 294 #define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 295 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 296 #define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 297 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 298 #define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 299 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 300 #define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 301 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 302 #define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 303 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 304 #define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /* Register: AMLI_RAMPRI_SPIS1 */
sahilmgandhi 18:6a4db94011d3 307 /* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 310 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 311 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 312 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 313 #define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 314 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 315 #define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 316 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 317 #define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 318 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 319 #define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 320 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 321 #define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 322 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 323 #define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 324 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 325 #define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 326 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 327 #define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 330 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 331 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 332 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 333 #define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 334 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 335 #define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 336 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 337 #define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 338 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 339 #define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 340 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 341 #define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 342 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 343 #define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 344 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 345 #define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 350 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 351 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 352 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 353 #define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 354 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 355 #define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 357 #define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 371 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 380 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 381 #define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 382 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 383 #define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 384 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 385 #define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 386 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 387 #define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 391 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 397 #define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 398 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 399 #define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 400 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 401 #define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 402 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 403 #define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 404 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 405 #define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 406 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 407 #define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 410 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 411 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 412 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 413 #define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 414 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 415 #define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 416 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 417 #define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 418 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 419 #define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 420 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 421 #define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 422 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 423 #define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 424 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 425 #define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 426 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 427 #define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 430 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 431 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 432 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 433 #define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 434 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 435 #define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 436 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 437 #define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 438 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 439 #define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 440 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 441 #define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 442 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 443 #define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 444 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 445 #define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 446 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 447 #define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 450 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 451 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 452 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 453 #define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 454 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 455 #define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 456 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 457 #define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 458 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 459 #define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 460 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 461 #define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 462 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 463 #define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 464 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 465 #define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 466 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 467 #define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 /* Register: AMLI_RAMPRI_RADIO */
sahilmgandhi 18:6a4db94011d3 470 /* Description: AHB bus master priority register for RADIO */
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 473 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 474 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 475 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 476 #define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 477 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 478 #define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 479 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 480 #define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 481 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 482 #define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 483 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 484 #define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 485 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 486 #define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 487 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 488 #define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 489 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 490 #define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 493 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 494 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 495 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 496 #define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 497 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 498 #define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 499 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 500 #define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 501 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 502 #define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 503 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 504 #define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 505 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 506 #define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 507 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 508 #define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 509 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 510 #define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 513 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 514 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 515 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 516 #define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 517 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 518 #define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 519 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 520 #define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 521 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 522 #define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 523 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 524 #define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 525 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 526 #define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 527 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 528 #define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 529 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 530 #define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 533 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 534 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 535 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 536 #define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 537 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 538 #define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 539 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 540 #define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 541 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 542 #define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 543 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 544 #define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 545 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 546 #define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 547 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 548 #define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 549 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 550 #define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 553 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 554 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 555 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 556 #define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 557 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 558 #define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 559 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 560 #define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 561 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 562 #define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 563 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 564 #define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 565 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 566 #define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 567 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 568 #define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 569 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 570 #define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 573 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 574 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 575 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 576 #define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 577 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 578 #define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 579 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 580 #define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 581 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 582 #define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 583 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 584 #define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 585 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 586 #define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 587 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 588 #define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 589 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 590 #define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 593 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 594 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 595 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 596 #define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 597 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 598 #define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 599 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 600 #define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 601 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 602 #define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 603 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 604 #define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 605 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 606 #define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 607 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 608 #define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 609 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 610 #define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 613 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 614 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 615 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 616 #define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 617 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 618 #define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 619 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 620 #define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 621 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 622 #define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 623 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 624 #define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 625 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 626 #define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 627 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 628 #define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 629 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 630 #define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632 /* Register: AMLI_RAMPRI_ECB */
sahilmgandhi 18:6a4db94011d3 633 /* Description: AHB bus master priority register for ECB */
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 636 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 637 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 638 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 639 #define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 640 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 641 #define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 642 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 643 #define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 644 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 645 #define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 646 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 647 #define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 648 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 649 #define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 650 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 651 #define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 652 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 653 #define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 656 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 657 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 658 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 659 #define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 660 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 661 #define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 662 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 663 #define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 664 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 665 #define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 666 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 667 #define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 668 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 669 #define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 670 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 671 #define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 672 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 673 #define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 676 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 677 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 678 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 679 #define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 680 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 681 #define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 682 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 683 #define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 684 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 685 #define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 686 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 687 #define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 688 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 689 #define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 690 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 691 #define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 692 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 693 #define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 696 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 697 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 698 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 699 #define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 700 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 701 #define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 702 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 703 #define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 704 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 705 #define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 706 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 707 #define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 708 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 709 #define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 710 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 711 #define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 712 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 713 #define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 716 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 717 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 718 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 719 #define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 720 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 721 #define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 722 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 723 #define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 724 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 725 #define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 726 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 727 #define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 728 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 729 #define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 730 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 731 #define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 732 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 733 #define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 736 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 737 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 738 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 739 #define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 740 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 741 #define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 742 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 743 #define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 744 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 745 #define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 746 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 747 #define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 748 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 749 #define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 750 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 751 #define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 752 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 753 #define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 756 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 757 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 758 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 759 #define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 760 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 761 #define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 762 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 763 #define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 764 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 765 #define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 766 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 767 #define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 768 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 769 #define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 770 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 771 #define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 772 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 773 #define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 774
sahilmgandhi 18:6a4db94011d3 775 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 776 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 777 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 778 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 779 #define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 780 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 781 #define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 782 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 783 #define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 784 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 785 #define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 786 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 787 #define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 788 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 789 #define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 790 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 791 #define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 792 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 793 #define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 /* Register: AMLI_RAMPRI_CCM */
sahilmgandhi 18:6a4db94011d3 796 /* Description: AHB bus master priority register for CCM */
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 799 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 800 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 801 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 802 #define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 803 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 804 #define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 805 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 806 #define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 807 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 808 #define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 809 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 810 #define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 811 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 812 #define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 813 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 814 #define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 815 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 816 #define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 819 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 820 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 821 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 822 #define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 823 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 824 #define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 825 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 826 #define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 827 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 828 #define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 829 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 830 #define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 831 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 832 #define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 833 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 834 #define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 835 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 836 #define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 837
sahilmgandhi 18:6a4db94011d3 838 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 839 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 840 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 841 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 842 #define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 843 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 844 #define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 845 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 846 #define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 847 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 848 #define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 849 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 850 #define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 851 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 852 #define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 853 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 854 #define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 855 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 856 #define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 859 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 860 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 861 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 862 #define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 863 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 864 #define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 865 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 866 #define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 867 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 868 #define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 869 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 870 #define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 871 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 872 #define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 873 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 874 #define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 875 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 876 #define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 877
sahilmgandhi 18:6a4db94011d3 878 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 879 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 880 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 881 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 882 #define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 883 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 884 #define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 885 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 886 #define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 887 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 888 #define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 889 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 890 #define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 891 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 892 #define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 893 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 894 #define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 895 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 896 #define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 897
sahilmgandhi 18:6a4db94011d3 898 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 899 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 900 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 901 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 902 #define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 903 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 904 #define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 905 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 906 #define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 907 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 908 #define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 909 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 910 #define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 911 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 912 #define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 913 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 914 #define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 915 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 916 #define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 919 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 920 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 921 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 922 #define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 923 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 924 #define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 925 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 926 #define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 927 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 928 #define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 929 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 930 #define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 931 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 932 #define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 933 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 934 #define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 935 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 936 #define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 937
sahilmgandhi 18:6a4db94011d3 938 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 939 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 940 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 941 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 942 #define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 943 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 944 #define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 945 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 946 #define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 947 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 948 #define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 949 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 950 #define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 951 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 952 #define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 953 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 954 #define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 955 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 956 #define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958 /* Register: AMLI_RAMPRI_AAR */
sahilmgandhi 18:6a4db94011d3 959 /* Description: AHB bus master priority register for AAR */
sahilmgandhi 18:6a4db94011d3 960
sahilmgandhi 18:6a4db94011d3 961 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 962 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 963 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 964 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 965 #define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 966 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 967 #define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 968 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 969 #define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 970 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 971 #define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 972 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 973 #define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 974 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 975 #define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 976 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 977 #define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 978 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 979 #define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 982 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 983 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 984 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 985 #define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 986 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 987 #define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 988 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 989 #define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 990 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 991 #define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 992 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 993 #define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 994 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 995 #define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 996 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 997 #define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 998 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 999 #define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1000
sahilmgandhi 18:6a4db94011d3 1001 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1002 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1003 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1004 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1005 #define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1006 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1007 #define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1008 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1009 #define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1010 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1011 #define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1012 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1013 #define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1014 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1015 #define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1016 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1017 #define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1018 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1019 #define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 1022 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1023 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1024 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1025 #define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1026 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1027 #define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1028 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1029 #define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1030 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1031 #define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1032 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1033 #define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1034 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1035 #define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1036 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1037 #define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1038 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1039 #define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 1042 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1043 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1044 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1045 #define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1046 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1047 #define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1048 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1049 #define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1050 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1051 #define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1052 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1053 #define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1054 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1055 #define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1056 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1057 #define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1058 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1059 #define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1060
sahilmgandhi 18:6a4db94011d3 1061 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 1062 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1063 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1064 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1065 #define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1066 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1067 #define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1068 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1069 #define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1070 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1071 #define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1072 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1073 #define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1074 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1075 #define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1076 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1077 #define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1078 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1079 #define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1080
sahilmgandhi 18:6a4db94011d3 1081 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 1082 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1083 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1084 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1085 #define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1086 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1087 #define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1088 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1089 #define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1090 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1091 #define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1092 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1093 #define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1094 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1095 #define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1096 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1097 #define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1098 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1099 #define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1100
sahilmgandhi 18:6a4db94011d3 1101 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 1102 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1103 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1104 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1105 #define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1106 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1107 #define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1108 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1109 #define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1110 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1111 #define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1112 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1113 #define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1114 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1115 #define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1116 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1117 #define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1118 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1119 #define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1120
sahilmgandhi 18:6a4db94011d3 1121 /* Register: AMLI_RAMPRI_SAADC */
sahilmgandhi 18:6a4db94011d3 1122 /* Description: AHB bus master priority register for SAADC */
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 1125 #define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1126 #define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1127 #define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1128 #define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1129 #define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1130 #define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1131 #define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1132 #define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1133 #define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1134 #define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1135 #define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1136 #define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1137 #define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1138 #define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1139 #define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1140 #define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1141 #define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1142 #define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1143
sahilmgandhi 18:6a4db94011d3 1144 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 1145 #define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1146 #define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1147 #define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1148 #define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1149 #define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1150 #define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1151 #define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1152 #define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1153 #define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1154 #define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1155 #define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1156 #define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1157 #define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1158 #define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1159 #define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1160 #define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1161 #define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1162 #define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1165 #define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1166 #define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1167 #define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1168 #define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1169 #define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1170 #define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1171 #define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1172 #define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1173 #define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1174 #define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1175 #define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1176 #define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1177 #define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1178 #define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1179 #define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1180 #define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1181 #define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1182 #define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 1185 #define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1186 #define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1187 #define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1188 #define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1189 #define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1190 #define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1191 #define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1192 #define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1193 #define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1194 #define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1195 #define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1196 #define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1197 #define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1198 #define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1199 #define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1200 #define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1201 #define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1202 #define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 1205 #define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1206 #define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1207 #define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1208 #define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1209 #define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1210 #define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1211 #define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1212 #define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1213 #define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1214 #define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1215 #define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1216 #define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1217 #define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1218 #define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1219 #define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1220 #define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1221 #define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1222 #define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 1225 #define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1226 #define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1227 #define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1228 #define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1229 #define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1230 #define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1231 #define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1232 #define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1233 #define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1234 #define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1235 #define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1236 #define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1237 #define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1238 #define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1239 #define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1240 #define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1241 #define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1242 #define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 1245 #define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1246 #define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1247 #define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1248 #define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1249 #define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1250 #define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1251 #define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1252 #define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1253 #define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1254 #define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1255 #define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1256 #define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1257 #define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1258 #define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1259 #define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1260 #define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1261 #define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1262 #define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1263
sahilmgandhi 18:6a4db94011d3 1264 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 1265 #define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1266 #define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1267 #define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1268 #define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1269 #define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1270 #define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1271 #define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1272 #define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1273 #define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1274 #define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1275 #define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1276 #define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1277 #define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1278 #define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1279 #define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1280 #define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1281 #define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1282 #define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1283
sahilmgandhi 18:6a4db94011d3 1284 /* Register: AMLI_RAMPRI_UARTE */
sahilmgandhi 18:6a4db94011d3 1285 /* Description: AHB bus master priority register for UARTE */
sahilmgandhi 18:6a4db94011d3 1286
sahilmgandhi 18:6a4db94011d3 1287 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 1288 #define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1289 #define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1290 #define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1291 #define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1292 #define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1293 #define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1294 #define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1295 #define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1296 #define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1297 #define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1298 #define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1299 #define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1300 #define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1301 #define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1302 #define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1303 #define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1304 #define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1305 #define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1306
sahilmgandhi 18:6a4db94011d3 1307 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 1308 #define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1309 #define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1310 #define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1311 #define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1312 #define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1313 #define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1314 #define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1315 #define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1316 #define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1317 #define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1318 #define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1319 #define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1320 #define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1321 #define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1322 #define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1323 #define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1324 #define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1325 #define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1326
sahilmgandhi 18:6a4db94011d3 1327 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1328 #define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1329 #define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1330 #define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1331 #define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1332 #define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1333 #define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1334 #define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1335 #define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1336 #define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1337 #define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1338 #define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1339 #define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1340 #define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1341 #define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1342 #define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1343 #define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1344 #define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1345 #define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 1348 #define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1349 #define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1350 #define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1351 #define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1352 #define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1353 #define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1354 #define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1355 #define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1356 #define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1357 #define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1358 #define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1359 #define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1360 #define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1361 #define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1362 #define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1363 #define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1364 #define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1365 #define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1366
sahilmgandhi 18:6a4db94011d3 1367 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 1368 #define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1369 #define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1370 #define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1371 #define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1372 #define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1373 #define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1374 #define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1375 #define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1376 #define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1377 #define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1378 #define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1379 #define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1380 #define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1381 #define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1382 #define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1383 #define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1384 #define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1385 #define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1386
sahilmgandhi 18:6a4db94011d3 1387 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 1388 #define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1389 #define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1390 #define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1391 #define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1392 #define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1393 #define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1394 #define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1395 #define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1396 #define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1397 #define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1398 #define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1399 #define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1400 #define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1401 #define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1402 #define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1403 #define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1404 #define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1405 #define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1406
sahilmgandhi 18:6a4db94011d3 1407 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 1408 #define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1409 #define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1410 #define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1411 #define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1412 #define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1413 #define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1414 #define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1415 #define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1416 #define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1417 #define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1418 #define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1419 #define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1420 #define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1421 #define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1422 #define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1423 #define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1424 #define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1425 #define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1426
sahilmgandhi 18:6a4db94011d3 1427 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 1428 #define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1429 #define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1430 #define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1431 #define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1432 #define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1433 #define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1434 #define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1435 #define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1436 #define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1437 #define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1438 #define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1439 #define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1440 #define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1441 #define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1442 #define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1443 #define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1444 #define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1445 #define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1446
sahilmgandhi 18:6a4db94011d3 1447 /* Register: AMLI_RAMPRI_SERIAL0 */
sahilmgandhi 18:6a4db94011d3 1448 /* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */
sahilmgandhi 18:6a4db94011d3 1449
sahilmgandhi 18:6a4db94011d3 1450 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 1451 #define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1452 #define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1453 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1454 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1455 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1456 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1457 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1458 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1459 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1460 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1461 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1462 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1463 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1464 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1465 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1466 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1467 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1468 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1469
sahilmgandhi 18:6a4db94011d3 1470 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 1471 #define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1472 #define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1473 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1474 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1475 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1476 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1477 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1478 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1479 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1480 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1481 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1482 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1483 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1484 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1485 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1486 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1487 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1488 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1489
sahilmgandhi 18:6a4db94011d3 1490 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1491 #define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1492 #define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1493 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1494 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1495 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1496 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1497 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1498 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1499 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1500 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1501 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1502 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1503 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1504 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1505 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1506 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1507 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1508 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1509
sahilmgandhi 18:6a4db94011d3 1510 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 1511 #define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1512 #define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1513 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1514 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1515 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1516 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1517 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1518 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1519 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1520 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1521 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1522 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1523 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1524 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1525 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1526 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1527 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1528 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1529
sahilmgandhi 18:6a4db94011d3 1530 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 1531 #define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1532 #define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1533 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1534 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1535 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1536 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1537 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1538 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1539 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1540 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1541 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1542 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1543 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1544 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1545 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1546 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1547 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1548 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1549
sahilmgandhi 18:6a4db94011d3 1550 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 1551 #define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1552 #define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1553 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1554 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1555 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1556 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1557 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1558 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1559 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1560 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1561 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1562 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1563 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1564 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1565 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1566 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1567 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1568 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1569
sahilmgandhi 18:6a4db94011d3 1570 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 1571 #define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1572 #define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1573 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1574 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1575 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1576 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1577 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1578 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1579 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1580 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1581 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1582 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1583 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1584 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1585 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1586 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1587 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1588 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1589
sahilmgandhi 18:6a4db94011d3 1590 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 1591 #define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1592 #define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1593 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1594 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1595 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1596 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1597 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1598 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1599 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1600 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1601 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1602 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1603 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1604 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1605 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1606 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1607 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1608 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1609
sahilmgandhi 18:6a4db94011d3 1610 /* Register: AMLI_RAMPRI_SERIAL2 */
sahilmgandhi 18:6a4db94011d3 1611 /* Description: AHB bus master priority register for SPIM2 and SPIS2 */
sahilmgandhi 18:6a4db94011d3 1612
sahilmgandhi 18:6a4db94011d3 1613 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 1614 #define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1615 #define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1616 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1617 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1618 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1619 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1620 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1621 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1622 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1623 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1624 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1625 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1626 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1627 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1628 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1629 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1630 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1631 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1632
sahilmgandhi 18:6a4db94011d3 1633 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 1634 #define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1635 #define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1636 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1637 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1638 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1639 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1640 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1641 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1642 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1643 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1644 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1645 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1646 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1647 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1648 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1649 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1650 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1651 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1652
sahilmgandhi 18:6a4db94011d3 1653 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1654 #define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1655 #define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1656 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1657 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1658 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1659 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1660 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1661 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1662 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1663 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1664 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1665 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1666 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1667 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1668 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1669 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1670 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1671 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1672
sahilmgandhi 18:6a4db94011d3 1673 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 1674 #define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1675 #define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1676 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1677 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1678 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1679 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1680 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1681 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1682 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1683 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1684 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1685 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1686 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1687 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1688 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1689 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1690 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1691 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1692
sahilmgandhi 18:6a4db94011d3 1693 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 1694 #define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1695 #define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1696 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1697 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1698 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1699 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1700 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1701 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1702 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1703 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1704 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1705 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1706 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1707 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1708 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1709 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1710 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1711 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1712
sahilmgandhi 18:6a4db94011d3 1713 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 1714 #define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1715 #define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1716 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1717 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1718 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1719 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1720 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1721 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1722 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1723 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1724 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1725 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1726 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1727 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1728 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1729 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1730 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1731 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1732
sahilmgandhi 18:6a4db94011d3 1733 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 1734 #define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1735 #define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1736 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1737 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1738 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1739 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1740 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1741 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1742 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1743 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1744 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1745 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1746 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1747 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1748 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1749 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1750 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1751 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1752
sahilmgandhi 18:6a4db94011d3 1753 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 1754 #define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1755 #define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1756 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1757 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1758 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1759 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1760 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1761 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1762 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1763 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1764 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1765 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1766 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1767 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1768 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1769 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1770 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1771 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1772
sahilmgandhi 18:6a4db94011d3 1773 /* Register: AMLI_RAMPRI_NFCT */
sahilmgandhi 18:6a4db94011d3 1774 /* Description: AHB bus master priority register for NFCT */
sahilmgandhi 18:6a4db94011d3 1775
sahilmgandhi 18:6a4db94011d3 1776 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 1777 #define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1778 #define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1779 #define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1780 #define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1781 #define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1782 #define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1783 #define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1784 #define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1785 #define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1786 #define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1787 #define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1788 #define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1789 #define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1790 #define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1791 #define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1792 #define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1793 #define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1794 #define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1795
sahilmgandhi 18:6a4db94011d3 1796 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 1797 #define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1798 #define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1799 #define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1800 #define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1801 #define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1802 #define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1803 #define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1804 #define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1805 #define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1806 #define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1807 #define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1808 #define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1809 #define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1810 #define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1811 #define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1812 #define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1813 #define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1814 #define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1815
sahilmgandhi 18:6a4db94011d3 1816 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1817 #define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1818 #define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1819 #define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1820 #define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1821 #define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1822 #define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1823 #define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1824 #define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1825 #define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1826 #define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1827 #define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1828 #define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1829 #define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1830 #define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1831 #define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1832 #define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1833 #define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1834 #define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1835
sahilmgandhi 18:6a4db94011d3 1836 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 1837 #define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1838 #define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 1839 #define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1840 #define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1841 #define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1842 #define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1843 #define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1844 #define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1845 #define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1846 #define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1847 #define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1848 #define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1849 #define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1850 #define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1851 #define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1852 #define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1853 #define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1854 #define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1855
sahilmgandhi 18:6a4db94011d3 1856 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 1857 #define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1858 #define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 1859 #define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1860 #define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1861 #define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1862 #define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1863 #define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1864 #define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1865 #define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1866 #define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1867 #define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1868 #define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1869 #define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1870 #define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1871 #define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1872 #define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1873 #define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1874 #define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1875
sahilmgandhi 18:6a4db94011d3 1876 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 1877 #define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1878 #define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 1879 #define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1880 #define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1881 #define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1882 #define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1883 #define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1884 #define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1885 #define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1886 #define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1887 #define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1888 #define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1889 #define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1890 #define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1891 #define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1892 #define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1893 #define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1894 #define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1895
sahilmgandhi 18:6a4db94011d3 1896 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 1897 #define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1898 #define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 1899 #define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1900 #define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1901 #define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1902 #define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1903 #define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1904 #define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1905 #define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1906 #define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1907 #define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1908 #define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1909 #define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1910 #define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1911 #define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1912 #define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1913 #define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1914 #define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1915
sahilmgandhi 18:6a4db94011d3 1916 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 1917 #define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1918 #define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 1919 #define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1920 #define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1921 #define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1922 #define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1923 #define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1924 #define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1925 #define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1926 #define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1927 #define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1928 #define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1929 #define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1930 #define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1931 #define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1932 #define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1933 #define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1934 #define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1935
sahilmgandhi 18:6a4db94011d3 1936 /* Register: AMLI_RAMPRI_I2S */
sahilmgandhi 18:6a4db94011d3 1937 /* Description: AHB bus master priority register for I2S */
sahilmgandhi 18:6a4db94011d3 1938
sahilmgandhi 18:6a4db94011d3 1939 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 1940 #define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1941 #define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 1942 #define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1943 #define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1944 #define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1945 #define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1946 #define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1947 #define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1948 #define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1949 #define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1950 #define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1951 #define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1952 #define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1953 #define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1954 #define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1955 #define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1956 #define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1957 #define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1958
sahilmgandhi 18:6a4db94011d3 1959 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 1960 #define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1961 #define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 1962 #define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1963 #define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1964 #define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1965 #define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1966 #define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1967 #define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1968 #define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1969 #define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1970 #define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1971 #define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1972 #define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1973 #define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1974 #define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1975 #define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1976 #define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1977 #define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1978
sahilmgandhi 18:6a4db94011d3 1979 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 1980 #define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1981 #define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 1982 #define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 1983 #define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 1984 #define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 1985 #define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 1986 #define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 1987 #define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 1988 #define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 1989 #define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 1990 #define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 1991 #define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 1992 #define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 1993 #define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 1994 #define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 1995 #define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 1996 #define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 1997 #define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 1998
sahilmgandhi 18:6a4db94011d3 1999 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 2000 #define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 2001 #define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 2002 #define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2003 #define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2004 #define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2005 #define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2006 #define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2007 #define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2008 #define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2009 #define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2010 #define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2011 #define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2012 #define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2013 #define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2014 #define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2015 #define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2016 #define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2017 #define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2018
sahilmgandhi 18:6a4db94011d3 2019 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 2020 #define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 2021 #define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 2022 #define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2023 #define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2024 #define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2025 #define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2026 #define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2027 #define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2028 #define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2029 #define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2030 #define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2031 #define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2032 #define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2033 #define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2034 #define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2035 #define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2036 #define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2037 #define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2038
sahilmgandhi 18:6a4db94011d3 2039 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 2040 #define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 2041 #define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 2042 #define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2043 #define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2044 #define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2045 #define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2046 #define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2047 #define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2048 #define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2049 #define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2050 #define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2051 #define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2052 #define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2053 #define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2054 #define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2055 #define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2056 #define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2057 #define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2058
sahilmgandhi 18:6a4db94011d3 2059 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 2060 #define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 2061 #define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 2062 #define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2063 #define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2064 #define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2065 #define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2066 #define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2067 #define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2068 #define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2069 #define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2070 #define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2071 #define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2072 #define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2073 #define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2074 #define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2075 #define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2076 #define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2077 #define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2078
sahilmgandhi 18:6a4db94011d3 2079 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 2080 #define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 2081 #define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 2082 #define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2083 #define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2084 #define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2085 #define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2086 #define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2087 #define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2088 #define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2089 #define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2090 #define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2091 #define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2092 #define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2093 #define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2094 #define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2095 #define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2096 #define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2097 #define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2098
sahilmgandhi 18:6a4db94011d3 2099 /* Register: AMLI_RAMPRI_PDM */
sahilmgandhi 18:6a4db94011d3 2100 /* Description: AHB bus master priority register for PDM */
sahilmgandhi 18:6a4db94011d3 2101
sahilmgandhi 18:6a4db94011d3 2102 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 2103 #define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 2104 #define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 2105 #define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2106 #define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2107 #define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2108 #define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2109 #define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2110 #define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2111 #define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2112 #define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2113 #define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2114 #define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2115 #define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2116 #define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2117 #define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2118 #define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2119 #define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2120 #define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2121
sahilmgandhi 18:6a4db94011d3 2122 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 2123 #define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 2124 #define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 2125 #define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2126 #define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2127 #define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2128 #define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2129 #define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2130 #define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2131 #define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2132 #define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2133 #define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2134 #define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2135 #define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2136 #define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2137 #define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2138 #define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2139 #define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2140 #define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2141
sahilmgandhi 18:6a4db94011d3 2142 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 2143 #define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 2144 #define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 2145 #define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2146 #define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2147 #define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2148 #define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2149 #define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2150 #define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2151 #define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2152 #define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2153 #define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2154 #define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2155 #define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2156 #define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2157 #define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2158 #define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2159 #define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2160 #define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2161
sahilmgandhi 18:6a4db94011d3 2162 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 2163 #define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 2164 #define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 2165 #define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2166 #define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2167 #define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2168 #define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2169 #define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2170 #define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2171 #define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2172 #define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2173 #define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2174 #define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2175 #define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2176 #define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2177 #define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2178 #define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2179 #define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2180 #define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2181
sahilmgandhi 18:6a4db94011d3 2182 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 2183 #define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 2184 #define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 2185 #define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2186 #define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2187 #define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2188 #define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2189 #define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2190 #define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2191 #define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2192 #define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2193 #define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2194 #define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2195 #define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2196 #define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2197 #define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2198 #define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2199 #define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2200 #define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2201
sahilmgandhi 18:6a4db94011d3 2202 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 2203 #define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 2204 #define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 2205 #define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2206 #define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2207 #define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2208 #define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2209 #define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2210 #define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2211 #define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2212 #define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2213 #define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2214 #define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2215 #define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2216 #define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2217 #define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2218 #define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2219 #define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2220 #define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2221
sahilmgandhi 18:6a4db94011d3 2222 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 2223 #define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 2224 #define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 2225 #define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2226 #define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2227 #define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2228 #define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2229 #define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2230 #define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2231 #define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2232 #define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2233 #define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2234 #define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2235 #define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2236 #define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2237 #define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2238 #define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2239 #define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2240 #define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2241
sahilmgandhi 18:6a4db94011d3 2242 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 2243 #define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 2244 #define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 2245 #define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2246 #define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2247 #define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2248 #define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2249 #define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2250 #define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2251 #define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2252 #define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2253 #define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2254 #define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2255 #define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2256 #define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2257 #define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2258 #define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2259 #define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2260 #define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2261
sahilmgandhi 18:6a4db94011d3 2262 /* Register: AMLI_RAMPRI_PWM */
sahilmgandhi 18:6a4db94011d3 2263 /* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */
sahilmgandhi 18:6a4db94011d3 2264
sahilmgandhi 18:6a4db94011d3 2265 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
sahilmgandhi 18:6a4db94011d3 2266 #define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 2267 #define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 2268 #define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2269 #define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2270 #define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2271 #define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2272 #define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2273 #define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2274 #define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2275 #define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2276 #define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2277 #define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2278 #define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2279 #define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2280 #define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2281 #define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2282 #define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2283 #define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2284
sahilmgandhi 18:6a4db94011d3 2285 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
sahilmgandhi 18:6a4db94011d3 2286 #define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 2287 #define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 2288 #define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2289 #define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2290 #define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2291 #define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2292 #define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2293 #define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2294 #define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2295 #define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2296 #define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2297 #define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2298 #define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2299 #define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2300 #define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2301 #define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2302 #define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2303 #define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2304
sahilmgandhi 18:6a4db94011d3 2305 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
sahilmgandhi 18:6a4db94011d3 2306 #define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 2307 #define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 2308 #define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2309 #define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2310 #define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2311 #define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2312 #define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2313 #define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2314 #define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2315 #define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2316 #define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2317 #define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2318 #define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2319 #define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2320 #define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2321 #define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2322 #define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2323 #define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2324
sahilmgandhi 18:6a4db94011d3 2325 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
sahilmgandhi 18:6a4db94011d3 2326 #define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 2327 #define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 2328 #define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2329 #define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2330 #define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2331 #define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2332 #define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2333 #define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2334 #define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2335 #define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2336 #define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2337 #define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2338 #define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2339 #define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2340 #define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2341 #define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2342 #define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2343 #define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2344
sahilmgandhi 18:6a4db94011d3 2345 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
sahilmgandhi 18:6a4db94011d3 2346 #define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 2347 #define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 2348 #define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2349 #define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2350 #define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2351 #define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2352 #define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2353 #define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2354 #define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2355 #define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2356 #define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2357 #define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2358 #define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2359 #define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2360 #define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2361 #define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2362 #define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2363 #define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2364
sahilmgandhi 18:6a4db94011d3 2365 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
sahilmgandhi 18:6a4db94011d3 2366 #define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 2367 #define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 2368 #define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2369 #define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2370 #define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2371 #define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2372 #define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2373 #define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2374 #define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2375 #define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2376 #define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2377 #define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2378 #define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2379 #define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2380 #define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2381 #define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2382 #define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2383 #define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2384
sahilmgandhi 18:6a4db94011d3 2385 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
sahilmgandhi 18:6a4db94011d3 2386 #define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 2387 #define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 2388 #define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2389 #define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2390 #define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2391 #define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2392 #define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2393 #define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2394 #define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2395 #define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2396 #define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2397 #define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2398 #define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2399 #define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2400 #define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2401 #define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2402 #define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2403 #define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2404
sahilmgandhi 18:6a4db94011d3 2405 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
sahilmgandhi 18:6a4db94011d3 2406 #define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 2407 #define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 2408 #define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */
sahilmgandhi 18:6a4db94011d3 2409 #define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */
sahilmgandhi 18:6a4db94011d3 2410 #define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */
sahilmgandhi 18:6a4db94011d3 2411 #define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */
sahilmgandhi 18:6a4db94011d3 2412 #define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */
sahilmgandhi 18:6a4db94011d3 2413 #define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */
sahilmgandhi 18:6a4db94011d3 2414 #define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */
sahilmgandhi 18:6a4db94011d3 2415 #define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */
sahilmgandhi 18:6a4db94011d3 2416 #define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */
sahilmgandhi 18:6a4db94011d3 2417 #define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */
sahilmgandhi 18:6a4db94011d3 2418 #define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */
sahilmgandhi 18:6a4db94011d3 2419 #define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */
sahilmgandhi 18:6a4db94011d3 2420 #define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */
sahilmgandhi 18:6a4db94011d3 2421 #define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */
sahilmgandhi 18:6a4db94011d3 2422 #define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */
sahilmgandhi 18:6a4db94011d3 2423 #define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */
sahilmgandhi 18:6a4db94011d3 2424
sahilmgandhi 18:6a4db94011d3 2425
sahilmgandhi 18:6a4db94011d3 2426 /* Peripheral: BPROT */
sahilmgandhi 18:6a4db94011d3 2427 /* Description: Block Protect */
sahilmgandhi 18:6a4db94011d3 2428
sahilmgandhi 18:6a4db94011d3 2429 /* Register: BPROT_CONFIG0 */
sahilmgandhi 18:6a4db94011d3 2430 /* Description: Block protect configuration register 0 */
sahilmgandhi 18:6a4db94011d3 2431
sahilmgandhi 18:6a4db94011d3 2432 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2433 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
sahilmgandhi 18:6a4db94011d3 2434 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
sahilmgandhi 18:6a4db94011d3 2435 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2436 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2437
sahilmgandhi 18:6a4db94011d3 2438 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2439 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
sahilmgandhi 18:6a4db94011d3 2440 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
sahilmgandhi 18:6a4db94011d3 2441 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2442 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2443
sahilmgandhi 18:6a4db94011d3 2444 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2445 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
sahilmgandhi 18:6a4db94011d3 2446 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
sahilmgandhi 18:6a4db94011d3 2447 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2448 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2449
sahilmgandhi 18:6a4db94011d3 2450 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2451 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
sahilmgandhi 18:6a4db94011d3 2452 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
sahilmgandhi 18:6a4db94011d3 2453 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2454 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2455
sahilmgandhi 18:6a4db94011d3 2456 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2457 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
sahilmgandhi 18:6a4db94011d3 2458 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
sahilmgandhi 18:6a4db94011d3 2459 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2460 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2461
sahilmgandhi 18:6a4db94011d3 2462 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2463 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
sahilmgandhi 18:6a4db94011d3 2464 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
sahilmgandhi 18:6a4db94011d3 2465 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2466 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2467
sahilmgandhi 18:6a4db94011d3 2468 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2469 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
sahilmgandhi 18:6a4db94011d3 2470 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
sahilmgandhi 18:6a4db94011d3 2471 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2472 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2473
sahilmgandhi 18:6a4db94011d3 2474 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2475 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
sahilmgandhi 18:6a4db94011d3 2476 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
sahilmgandhi 18:6a4db94011d3 2477 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2478 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2479
sahilmgandhi 18:6a4db94011d3 2480 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2481 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
sahilmgandhi 18:6a4db94011d3 2482 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
sahilmgandhi 18:6a4db94011d3 2483 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2484 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2485
sahilmgandhi 18:6a4db94011d3 2486 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2487 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
sahilmgandhi 18:6a4db94011d3 2488 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
sahilmgandhi 18:6a4db94011d3 2489 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2490 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2491
sahilmgandhi 18:6a4db94011d3 2492 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2493 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
sahilmgandhi 18:6a4db94011d3 2494 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
sahilmgandhi 18:6a4db94011d3 2495 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2496 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2497
sahilmgandhi 18:6a4db94011d3 2498 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2499 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
sahilmgandhi 18:6a4db94011d3 2500 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
sahilmgandhi 18:6a4db94011d3 2501 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2502 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2503
sahilmgandhi 18:6a4db94011d3 2504 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2505 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
sahilmgandhi 18:6a4db94011d3 2506 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
sahilmgandhi 18:6a4db94011d3 2507 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2508 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2509
sahilmgandhi 18:6a4db94011d3 2510 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2511 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
sahilmgandhi 18:6a4db94011d3 2512 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
sahilmgandhi 18:6a4db94011d3 2513 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2514 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2515
sahilmgandhi 18:6a4db94011d3 2516 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2517 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
sahilmgandhi 18:6a4db94011d3 2518 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
sahilmgandhi 18:6a4db94011d3 2519 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2520 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2521
sahilmgandhi 18:6a4db94011d3 2522 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2523 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
sahilmgandhi 18:6a4db94011d3 2524 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
sahilmgandhi 18:6a4db94011d3 2525 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2526 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2527
sahilmgandhi 18:6a4db94011d3 2528 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2529 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
sahilmgandhi 18:6a4db94011d3 2530 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
sahilmgandhi 18:6a4db94011d3 2531 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2532 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2533
sahilmgandhi 18:6a4db94011d3 2534 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2535 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
sahilmgandhi 18:6a4db94011d3 2536 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
sahilmgandhi 18:6a4db94011d3 2537 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2538 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2539
sahilmgandhi 18:6a4db94011d3 2540 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2541 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
sahilmgandhi 18:6a4db94011d3 2542 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
sahilmgandhi 18:6a4db94011d3 2543 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2544 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2545
sahilmgandhi 18:6a4db94011d3 2546 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2547 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
sahilmgandhi 18:6a4db94011d3 2548 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
sahilmgandhi 18:6a4db94011d3 2549 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2550 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2551
sahilmgandhi 18:6a4db94011d3 2552 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2553 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
sahilmgandhi 18:6a4db94011d3 2554 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
sahilmgandhi 18:6a4db94011d3 2555 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2556 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2557
sahilmgandhi 18:6a4db94011d3 2558 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2559 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
sahilmgandhi 18:6a4db94011d3 2560 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
sahilmgandhi 18:6a4db94011d3 2561 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2562 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2563
sahilmgandhi 18:6a4db94011d3 2564 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2565 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
sahilmgandhi 18:6a4db94011d3 2566 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
sahilmgandhi 18:6a4db94011d3 2567 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2568 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2569
sahilmgandhi 18:6a4db94011d3 2570 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2571 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
sahilmgandhi 18:6a4db94011d3 2572 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
sahilmgandhi 18:6a4db94011d3 2573 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2574 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2575
sahilmgandhi 18:6a4db94011d3 2576 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2577 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
sahilmgandhi 18:6a4db94011d3 2578 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
sahilmgandhi 18:6a4db94011d3 2579 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2580 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2581
sahilmgandhi 18:6a4db94011d3 2582 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2583 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
sahilmgandhi 18:6a4db94011d3 2584 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
sahilmgandhi 18:6a4db94011d3 2585 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2586 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2587
sahilmgandhi 18:6a4db94011d3 2588 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2589 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
sahilmgandhi 18:6a4db94011d3 2590 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
sahilmgandhi 18:6a4db94011d3 2591 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2592 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2593
sahilmgandhi 18:6a4db94011d3 2594 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2595 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
sahilmgandhi 18:6a4db94011d3 2596 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
sahilmgandhi 18:6a4db94011d3 2597 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2598 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2599
sahilmgandhi 18:6a4db94011d3 2600 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2601 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
sahilmgandhi 18:6a4db94011d3 2602 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
sahilmgandhi 18:6a4db94011d3 2603 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2604 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2605
sahilmgandhi 18:6a4db94011d3 2606 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2607 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
sahilmgandhi 18:6a4db94011d3 2608 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
sahilmgandhi 18:6a4db94011d3 2609 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2610 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2611
sahilmgandhi 18:6a4db94011d3 2612 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2613 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
sahilmgandhi 18:6a4db94011d3 2614 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
sahilmgandhi 18:6a4db94011d3 2615 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2616 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2617
sahilmgandhi 18:6a4db94011d3 2618 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2619 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
sahilmgandhi 18:6a4db94011d3 2620 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
sahilmgandhi 18:6a4db94011d3 2621 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2622 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
sahilmgandhi 18:6a4db94011d3 2623
sahilmgandhi 18:6a4db94011d3 2624 /* Register: BPROT_CONFIG1 */
sahilmgandhi 18:6a4db94011d3 2625 /* Description: Block protect configuration register 1 */
sahilmgandhi 18:6a4db94011d3 2626
sahilmgandhi 18:6a4db94011d3 2627 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2628 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
sahilmgandhi 18:6a4db94011d3 2629 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
sahilmgandhi 18:6a4db94011d3 2630 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2631 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2632
sahilmgandhi 18:6a4db94011d3 2633 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2634 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
sahilmgandhi 18:6a4db94011d3 2635 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
sahilmgandhi 18:6a4db94011d3 2636 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2637 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2638
sahilmgandhi 18:6a4db94011d3 2639 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2640 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
sahilmgandhi 18:6a4db94011d3 2641 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
sahilmgandhi 18:6a4db94011d3 2642 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2643 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2644
sahilmgandhi 18:6a4db94011d3 2645 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2646 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
sahilmgandhi 18:6a4db94011d3 2647 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
sahilmgandhi 18:6a4db94011d3 2648 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2649 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2650
sahilmgandhi 18:6a4db94011d3 2651 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2652 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
sahilmgandhi 18:6a4db94011d3 2653 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
sahilmgandhi 18:6a4db94011d3 2654 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2655 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2656
sahilmgandhi 18:6a4db94011d3 2657 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2658 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
sahilmgandhi 18:6a4db94011d3 2659 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
sahilmgandhi 18:6a4db94011d3 2660 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2661 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2662
sahilmgandhi 18:6a4db94011d3 2663 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2664 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
sahilmgandhi 18:6a4db94011d3 2665 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
sahilmgandhi 18:6a4db94011d3 2666 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2667 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2668
sahilmgandhi 18:6a4db94011d3 2669 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2670 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
sahilmgandhi 18:6a4db94011d3 2671 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
sahilmgandhi 18:6a4db94011d3 2672 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2673 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2674
sahilmgandhi 18:6a4db94011d3 2675 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2676 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
sahilmgandhi 18:6a4db94011d3 2677 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
sahilmgandhi 18:6a4db94011d3 2678 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2679 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2680
sahilmgandhi 18:6a4db94011d3 2681 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2682 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
sahilmgandhi 18:6a4db94011d3 2683 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
sahilmgandhi 18:6a4db94011d3 2684 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2685 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2686
sahilmgandhi 18:6a4db94011d3 2687 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2688 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
sahilmgandhi 18:6a4db94011d3 2689 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
sahilmgandhi 18:6a4db94011d3 2690 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2691 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2692
sahilmgandhi 18:6a4db94011d3 2693 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2694 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
sahilmgandhi 18:6a4db94011d3 2695 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
sahilmgandhi 18:6a4db94011d3 2696 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2697 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2698
sahilmgandhi 18:6a4db94011d3 2699 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2700 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
sahilmgandhi 18:6a4db94011d3 2701 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
sahilmgandhi 18:6a4db94011d3 2702 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2703 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2704
sahilmgandhi 18:6a4db94011d3 2705 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2706 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
sahilmgandhi 18:6a4db94011d3 2707 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
sahilmgandhi 18:6a4db94011d3 2708 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2709 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2710
sahilmgandhi 18:6a4db94011d3 2711 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2712 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
sahilmgandhi 18:6a4db94011d3 2713 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
sahilmgandhi 18:6a4db94011d3 2714 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2715 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2716
sahilmgandhi 18:6a4db94011d3 2717 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2718 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
sahilmgandhi 18:6a4db94011d3 2719 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
sahilmgandhi 18:6a4db94011d3 2720 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2721 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2722
sahilmgandhi 18:6a4db94011d3 2723 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2724 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
sahilmgandhi 18:6a4db94011d3 2725 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
sahilmgandhi 18:6a4db94011d3 2726 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2727 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2728
sahilmgandhi 18:6a4db94011d3 2729 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2730 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
sahilmgandhi 18:6a4db94011d3 2731 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
sahilmgandhi 18:6a4db94011d3 2732 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2733 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2734
sahilmgandhi 18:6a4db94011d3 2735 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2736 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
sahilmgandhi 18:6a4db94011d3 2737 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
sahilmgandhi 18:6a4db94011d3 2738 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2739 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2740
sahilmgandhi 18:6a4db94011d3 2741 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2742 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
sahilmgandhi 18:6a4db94011d3 2743 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
sahilmgandhi 18:6a4db94011d3 2744 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2745 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2746
sahilmgandhi 18:6a4db94011d3 2747 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2748 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
sahilmgandhi 18:6a4db94011d3 2749 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
sahilmgandhi 18:6a4db94011d3 2750 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2751 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2752
sahilmgandhi 18:6a4db94011d3 2753 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2754 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
sahilmgandhi 18:6a4db94011d3 2755 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
sahilmgandhi 18:6a4db94011d3 2756 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2757 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2758
sahilmgandhi 18:6a4db94011d3 2759 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2760 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
sahilmgandhi 18:6a4db94011d3 2761 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
sahilmgandhi 18:6a4db94011d3 2762 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2763 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2764
sahilmgandhi 18:6a4db94011d3 2765 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2766 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
sahilmgandhi 18:6a4db94011d3 2767 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
sahilmgandhi 18:6a4db94011d3 2768 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2769 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2770
sahilmgandhi 18:6a4db94011d3 2771 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2772 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
sahilmgandhi 18:6a4db94011d3 2773 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
sahilmgandhi 18:6a4db94011d3 2774 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2775 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2776
sahilmgandhi 18:6a4db94011d3 2777 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2778 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
sahilmgandhi 18:6a4db94011d3 2779 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
sahilmgandhi 18:6a4db94011d3 2780 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2781 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2782
sahilmgandhi 18:6a4db94011d3 2783 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2784 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
sahilmgandhi 18:6a4db94011d3 2785 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
sahilmgandhi 18:6a4db94011d3 2786 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2787 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2788
sahilmgandhi 18:6a4db94011d3 2789 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2790 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
sahilmgandhi 18:6a4db94011d3 2791 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
sahilmgandhi 18:6a4db94011d3 2792 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2793 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2794
sahilmgandhi 18:6a4db94011d3 2795 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2796 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
sahilmgandhi 18:6a4db94011d3 2797 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
sahilmgandhi 18:6a4db94011d3 2798 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2799 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2800
sahilmgandhi 18:6a4db94011d3 2801 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2802 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
sahilmgandhi 18:6a4db94011d3 2803 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
sahilmgandhi 18:6a4db94011d3 2804 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2805 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2806
sahilmgandhi 18:6a4db94011d3 2807 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2808 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
sahilmgandhi 18:6a4db94011d3 2809 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
sahilmgandhi 18:6a4db94011d3 2810 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2811 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2812
sahilmgandhi 18:6a4db94011d3 2813 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2814 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
sahilmgandhi 18:6a4db94011d3 2815 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
sahilmgandhi 18:6a4db94011d3 2816 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2817 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2818
sahilmgandhi 18:6a4db94011d3 2819 /* Register: BPROT_DISABLEINDEBUG */
sahilmgandhi 18:6a4db94011d3 2820 /* Description: Disable protection mechanism in debug interface mode */
sahilmgandhi 18:6a4db94011d3 2821
sahilmgandhi 18:6a4db94011d3 2822 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
sahilmgandhi 18:6a4db94011d3 2823 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
sahilmgandhi 18:6a4db94011d3 2824 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
sahilmgandhi 18:6a4db94011d3 2825 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
sahilmgandhi 18:6a4db94011d3 2826 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
sahilmgandhi 18:6a4db94011d3 2827
sahilmgandhi 18:6a4db94011d3 2828 /* Register: BPROT_CONFIG2 */
sahilmgandhi 18:6a4db94011d3 2829 /* Description: Block protect configuration register 2 */
sahilmgandhi 18:6a4db94011d3 2830
sahilmgandhi 18:6a4db94011d3 2831 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2832 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
sahilmgandhi 18:6a4db94011d3 2833 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
sahilmgandhi 18:6a4db94011d3 2834 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2835 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2836
sahilmgandhi 18:6a4db94011d3 2837 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2838 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
sahilmgandhi 18:6a4db94011d3 2839 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
sahilmgandhi 18:6a4db94011d3 2840 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2841 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2842
sahilmgandhi 18:6a4db94011d3 2843 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2844 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
sahilmgandhi 18:6a4db94011d3 2845 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
sahilmgandhi 18:6a4db94011d3 2846 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2847 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2848
sahilmgandhi 18:6a4db94011d3 2849 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2850 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
sahilmgandhi 18:6a4db94011d3 2851 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
sahilmgandhi 18:6a4db94011d3 2852 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2853 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2854
sahilmgandhi 18:6a4db94011d3 2855 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2856 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
sahilmgandhi 18:6a4db94011d3 2857 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
sahilmgandhi 18:6a4db94011d3 2858 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2859 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2860
sahilmgandhi 18:6a4db94011d3 2861 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2862 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
sahilmgandhi 18:6a4db94011d3 2863 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
sahilmgandhi 18:6a4db94011d3 2864 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2865 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2866
sahilmgandhi 18:6a4db94011d3 2867 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2868 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
sahilmgandhi 18:6a4db94011d3 2869 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
sahilmgandhi 18:6a4db94011d3 2870 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2871 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2872
sahilmgandhi 18:6a4db94011d3 2873 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2874 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
sahilmgandhi 18:6a4db94011d3 2875 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
sahilmgandhi 18:6a4db94011d3 2876 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2877 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2878
sahilmgandhi 18:6a4db94011d3 2879 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2880 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
sahilmgandhi 18:6a4db94011d3 2881 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
sahilmgandhi 18:6a4db94011d3 2882 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2883 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2884
sahilmgandhi 18:6a4db94011d3 2885 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2886 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
sahilmgandhi 18:6a4db94011d3 2887 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
sahilmgandhi 18:6a4db94011d3 2888 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2889 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2890
sahilmgandhi 18:6a4db94011d3 2891 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2892 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
sahilmgandhi 18:6a4db94011d3 2893 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
sahilmgandhi 18:6a4db94011d3 2894 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2895 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2896
sahilmgandhi 18:6a4db94011d3 2897 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2898 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
sahilmgandhi 18:6a4db94011d3 2899 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
sahilmgandhi 18:6a4db94011d3 2900 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2901 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2902
sahilmgandhi 18:6a4db94011d3 2903 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2904 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
sahilmgandhi 18:6a4db94011d3 2905 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
sahilmgandhi 18:6a4db94011d3 2906 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2907 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2908
sahilmgandhi 18:6a4db94011d3 2909 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2910 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
sahilmgandhi 18:6a4db94011d3 2911 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
sahilmgandhi 18:6a4db94011d3 2912 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2913 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2914
sahilmgandhi 18:6a4db94011d3 2915 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2916 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
sahilmgandhi 18:6a4db94011d3 2917 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
sahilmgandhi 18:6a4db94011d3 2918 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2919 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2920
sahilmgandhi 18:6a4db94011d3 2921 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2922 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
sahilmgandhi 18:6a4db94011d3 2923 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
sahilmgandhi 18:6a4db94011d3 2924 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2925 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2926
sahilmgandhi 18:6a4db94011d3 2927 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2928 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
sahilmgandhi 18:6a4db94011d3 2929 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
sahilmgandhi 18:6a4db94011d3 2930 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2931 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2932
sahilmgandhi 18:6a4db94011d3 2933 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2934 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
sahilmgandhi 18:6a4db94011d3 2935 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
sahilmgandhi 18:6a4db94011d3 2936 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2937 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2938
sahilmgandhi 18:6a4db94011d3 2939 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2940 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
sahilmgandhi 18:6a4db94011d3 2941 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
sahilmgandhi 18:6a4db94011d3 2942 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2943 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2944
sahilmgandhi 18:6a4db94011d3 2945 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2946 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
sahilmgandhi 18:6a4db94011d3 2947 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
sahilmgandhi 18:6a4db94011d3 2948 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2949 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2950
sahilmgandhi 18:6a4db94011d3 2951 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2952 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
sahilmgandhi 18:6a4db94011d3 2953 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
sahilmgandhi 18:6a4db94011d3 2954 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2955 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2956
sahilmgandhi 18:6a4db94011d3 2957 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2958 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
sahilmgandhi 18:6a4db94011d3 2959 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
sahilmgandhi 18:6a4db94011d3 2960 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2961 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2962
sahilmgandhi 18:6a4db94011d3 2963 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2964 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
sahilmgandhi 18:6a4db94011d3 2965 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
sahilmgandhi 18:6a4db94011d3 2966 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2967 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2968
sahilmgandhi 18:6a4db94011d3 2969 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2970 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
sahilmgandhi 18:6a4db94011d3 2971 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
sahilmgandhi 18:6a4db94011d3 2972 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2973 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2974
sahilmgandhi 18:6a4db94011d3 2975 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2976 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
sahilmgandhi 18:6a4db94011d3 2977 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
sahilmgandhi 18:6a4db94011d3 2978 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2979 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2980
sahilmgandhi 18:6a4db94011d3 2981 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2982 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
sahilmgandhi 18:6a4db94011d3 2983 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
sahilmgandhi 18:6a4db94011d3 2984 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2985 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2986
sahilmgandhi 18:6a4db94011d3 2987 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2988 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
sahilmgandhi 18:6a4db94011d3 2989 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
sahilmgandhi 18:6a4db94011d3 2990 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2991 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2992
sahilmgandhi 18:6a4db94011d3 2993 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 2994 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
sahilmgandhi 18:6a4db94011d3 2995 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
sahilmgandhi 18:6a4db94011d3 2996 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 2997 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 2998
sahilmgandhi 18:6a4db94011d3 2999 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3000 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
sahilmgandhi 18:6a4db94011d3 3001 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
sahilmgandhi 18:6a4db94011d3 3002 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3003 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3004
sahilmgandhi 18:6a4db94011d3 3005 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3006 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
sahilmgandhi 18:6a4db94011d3 3007 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
sahilmgandhi 18:6a4db94011d3 3008 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3009 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3010
sahilmgandhi 18:6a4db94011d3 3011 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3012 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
sahilmgandhi 18:6a4db94011d3 3013 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
sahilmgandhi 18:6a4db94011d3 3014 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3015 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3016
sahilmgandhi 18:6a4db94011d3 3017 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3018 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
sahilmgandhi 18:6a4db94011d3 3019 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
sahilmgandhi 18:6a4db94011d3 3020 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3021 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3022
sahilmgandhi 18:6a4db94011d3 3023 /* Register: BPROT_CONFIG3 */
sahilmgandhi 18:6a4db94011d3 3024 /* Description: Block protect configuration register 3 */
sahilmgandhi 18:6a4db94011d3 3025
sahilmgandhi 18:6a4db94011d3 3026 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3027 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
sahilmgandhi 18:6a4db94011d3 3028 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
sahilmgandhi 18:6a4db94011d3 3029 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3030 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3031
sahilmgandhi 18:6a4db94011d3 3032 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3033 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
sahilmgandhi 18:6a4db94011d3 3034 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
sahilmgandhi 18:6a4db94011d3 3035 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3036 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3037
sahilmgandhi 18:6a4db94011d3 3038 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3039 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
sahilmgandhi 18:6a4db94011d3 3040 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
sahilmgandhi 18:6a4db94011d3 3041 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3042 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3043
sahilmgandhi 18:6a4db94011d3 3044 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3045 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
sahilmgandhi 18:6a4db94011d3 3046 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
sahilmgandhi 18:6a4db94011d3 3047 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3048 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3049
sahilmgandhi 18:6a4db94011d3 3050 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3051 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
sahilmgandhi 18:6a4db94011d3 3052 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
sahilmgandhi 18:6a4db94011d3 3053 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3054 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3055
sahilmgandhi 18:6a4db94011d3 3056 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3057 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
sahilmgandhi 18:6a4db94011d3 3058 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
sahilmgandhi 18:6a4db94011d3 3059 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3060 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3061
sahilmgandhi 18:6a4db94011d3 3062 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3063 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
sahilmgandhi 18:6a4db94011d3 3064 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
sahilmgandhi 18:6a4db94011d3 3065 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3066 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3067
sahilmgandhi 18:6a4db94011d3 3068 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3069 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
sahilmgandhi 18:6a4db94011d3 3070 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
sahilmgandhi 18:6a4db94011d3 3071 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3072 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3073
sahilmgandhi 18:6a4db94011d3 3074 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3075 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
sahilmgandhi 18:6a4db94011d3 3076 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
sahilmgandhi 18:6a4db94011d3 3077 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3078 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3079
sahilmgandhi 18:6a4db94011d3 3080 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3081 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
sahilmgandhi 18:6a4db94011d3 3082 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
sahilmgandhi 18:6a4db94011d3 3083 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3084 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3085
sahilmgandhi 18:6a4db94011d3 3086 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3087 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
sahilmgandhi 18:6a4db94011d3 3088 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
sahilmgandhi 18:6a4db94011d3 3089 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3090 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3091
sahilmgandhi 18:6a4db94011d3 3092 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3093 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
sahilmgandhi 18:6a4db94011d3 3094 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
sahilmgandhi 18:6a4db94011d3 3095 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3096 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3097
sahilmgandhi 18:6a4db94011d3 3098 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3099 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
sahilmgandhi 18:6a4db94011d3 3100 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
sahilmgandhi 18:6a4db94011d3 3101 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3102 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3103
sahilmgandhi 18:6a4db94011d3 3104 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3105 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
sahilmgandhi 18:6a4db94011d3 3106 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
sahilmgandhi 18:6a4db94011d3 3107 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3108 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3109
sahilmgandhi 18:6a4db94011d3 3110 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3111 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
sahilmgandhi 18:6a4db94011d3 3112 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
sahilmgandhi 18:6a4db94011d3 3113 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3114 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3115
sahilmgandhi 18:6a4db94011d3 3116 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3117 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
sahilmgandhi 18:6a4db94011d3 3118 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
sahilmgandhi 18:6a4db94011d3 3119 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3120 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3121
sahilmgandhi 18:6a4db94011d3 3122 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3123 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
sahilmgandhi 18:6a4db94011d3 3124 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
sahilmgandhi 18:6a4db94011d3 3125 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3126 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3127
sahilmgandhi 18:6a4db94011d3 3128 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3129 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
sahilmgandhi 18:6a4db94011d3 3130 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
sahilmgandhi 18:6a4db94011d3 3131 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3132 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3133
sahilmgandhi 18:6a4db94011d3 3134 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3135 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
sahilmgandhi 18:6a4db94011d3 3136 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
sahilmgandhi 18:6a4db94011d3 3137 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3138 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3139
sahilmgandhi 18:6a4db94011d3 3140 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3141 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
sahilmgandhi 18:6a4db94011d3 3142 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
sahilmgandhi 18:6a4db94011d3 3143 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3144 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3145
sahilmgandhi 18:6a4db94011d3 3146 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3147 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
sahilmgandhi 18:6a4db94011d3 3148 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
sahilmgandhi 18:6a4db94011d3 3149 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3150 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3151
sahilmgandhi 18:6a4db94011d3 3152 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3153 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
sahilmgandhi 18:6a4db94011d3 3154 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
sahilmgandhi 18:6a4db94011d3 3155 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3156 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3157
sahilmgandhi 18:6a4db94011d3 3158 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3159 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
sahilmgandhi 18:6a4db94011d3 3160 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
sahilmgandhi 18:6a4db94011d3 3161 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3162 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3163
sahilmgandhi 18:6a4db94011d3 3164 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3165 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
sahilmgandhi 18:6a4db94011d3 3166 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
sahilmgandhi 18:6a4db94011d3 3167 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3168 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3169
sahilmgandhi 18:6a4db94011d3 3170 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3171 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
sahilmgandhi 18:6a4db94011d3 3172 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
sahilmgandhi 18:6a4db94011d3 3173 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3174 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3175
sahilmgandhi 18:6a4db94011d3 3176 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3177 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
sahilmgandhi 18:6a4db94011d3 3178 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
sahilmgandhi 18:6a4db94011d3 3179 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3180 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3181
sahilmgandhi 18:6a4db94011d3 3182 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3183 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
sahilmgandhi 18:6a4db94011d3 3184 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
sahilmgandhi 18:6a4db94011d3 3185 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3186 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3187
sahilmgandhi 18:6a4db94011d3 3188 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3189 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
sahilmgandhi 18:6a4db94011d3 3190 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
sahilmgandhi 18:6a4db94011d3 3191 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3192 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3193
sahilmgandhi 18:6a4db94011d3 3194 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3195 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
sahilmgandhi 18:6a4db94011d3 3196 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
sahilmgandhi 18:6a4db94011d3 3197 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3198 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3199
sahilmgandhi 18:6a4db94011d3 3200 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3201 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
sahilmgandhi 18:6a4db94011d3 3202 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
sahilmgandhi 18:6a4db94011d3 3203 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3204 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3205
sahilmgandhi 18:6a4db94011d3 3206 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3207 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
sahilmgandhi 18:6a4db94011d3 3208 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
sahilmgandhi 18:6a4db94011d3 3209 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3210 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3211
sahilmgandhi 18:6a4db94011d3 3212 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
sahilmgandhi 18:6a4db94011d3 3213 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
sahilmgandhi 18:6a4db94011d3 3214 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
sahilmgandhi 18:6a4db94011d3 3215 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
sahilmgandhi 18:6a4db94011d3 3216 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
sahilmgandhi 18:6a4db94011d3 3217
sahilmgandhi 18:6a4db94011d3 3218
sahilmgandhi 18:6a4db94011d3 3219 /* Peripheral: CCM */
sahilmgandhi 18:6a4db94011d3 3220 /* Description: AES CCM Mode Encryption */
sahilmgandhi 18:6a4db94011d3 3221
sahilmgandhi 18:6a4db94011d3 3222 /* Register: CCM_SHORTS */
sahilmgandhi 18:6a4db94011d3 3223 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 3224
sahilmgandhi 18:6a4db94011d3 3225 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
sahilmgandhi 18:6a4db94011d3 3226 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
sahilmgandhi 18:6a4db94011d3 3227 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
sahilmgandhi 18:6a4db94011d3 3228 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 3229 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 3230
sahilmgandhi 18:6a4db94011d3 3231 /* Register: CCM_INTENSET */
sahilmgandhi 18:6a4db94011d3 3232 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 3233
sahilmgandhi 18:6a4db94011d3 3234 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 3235 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 3236 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 3237 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3238 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3239 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3240
sahilmgandhi 18:6a4db94011d3 3241 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
sahilmgandhi 18:6a4db94011d3 3242 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 3243 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 3244 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3245 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3246 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3247
sahilmgandhi 18:6a4db94011d3 3248 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
sahilmgandhi 18:6a4db94011d3 3249 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 3250 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 3251 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3252 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3253 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3254
sahilmgandhi 18:6a4db94011d3 3255 /* Register: CCM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 3256 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 3257
sahilmgandhi 18:6a4db94011d3 3258 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 3259 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 3260 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 3261 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3262 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3263 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3264
sahilmgandhi 18:6a4db94011d3 3265 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
sahilmgandhi 18:6a4db94011d3 3266 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 3267 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 3268 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3269 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3270 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3271
sahilmgandhi 18:6a4db94011d3 3272 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
sahilmgandhi 18:6a4db94011d3 3273 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 3274 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 3275 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3276 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3277 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3278
sahilmgandhi 18:6a4db94011d3 3279 /* Register: CCM_MICSTATUS */
sahilmgandhi 18:6a4db94011d3 3280 /* Description: MIC check result */
sahilmgandhi 18:6a4db94011d3 3281
sahilmgandhi 18:6a4db94011d3 3282 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
sahilmgandhi 18:6a4db94011d3 3283 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
sahilmgandhi 18:6a4db94011d3 3284 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
sahilmgandhi 18:6a4db94011d3 3285 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
sahilmgandhi 18:6a4db94011d3 3286 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
sahilmgandhi 18:6a4db94011d3 3287
sahilmgandhi 18:6a4db94011d3 3288 /* Register: CCM_ENABLE */
sahilmgandhi 18:6a4db94011d3 3289 /* Description: Enable */
sahilmgandhi 18:6a4db94011d3 3290
sahilmgandhi 18:6a4db94011d3 3291 /* Bits 1..0 : Enable or disable CCM */
sahilmgandhi 18:6a4db94011d3 3292 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 3293 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 3294 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3295 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3296
sahilmgandhi 18:6a4db94011d3 3297 /* Register: CCM_MODE */
sahilmgandhi 18:6a4db94011d3 3298 /* Description: Operation mode */
sahilmgandhi 18:6a4db94011d3 3299
sahilmgandhi 18:6a4db94011d3 3300 /* Bit 24 : Packet length configuration */
sahilmgandhi 18:6a4db94011d3 3301 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
sahilmgandhi 18:6a4db94011d3 3302 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
sahilmgandhi 18:6a4db94011d3 3303 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
sahilmgandhi 18:6a4db94011d3 3304 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
sahilmgandhi 18:6a4db94011d3 3305
sahilmgandhi 18:6a4db94011d3 3306 /* Bit 16 : Data rate that the CCM shall run in synch with */
sahilmgandhi 18:6a4db94011d3 3307 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
sahilmgandhi 18:6a4db94011d3 3308 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
sahilmgandhi 18:6a4db94011d3 3309 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
sahilmgandhi 18:6a4db94011d3 3310 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
sahilmgandhi 18:6a4db94011d3 3311
sahilmgandhi 18:6a4db94011d3 3312 /* Bit 0 : The mode of operation to be used */
sahilmgandhi 18:6a4db94011d3 3313 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 3314 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 3315 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
sahilmgandhi 18:6a4db94011d3 3316 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
sahilmgandhi 18:6a4db94011d3 3317
sahilmgandhi 18:6a4db94011d3 3318 /* Register: CCM_CNFPTR */
sahilmgandhi 18:6a4db94011d3 3319 /* Description: Pointer to data structure holding AES key and NONCE vector */
sahilmgandhi 18:6a4db94011d3 3320
sahilmgandhi 18:6a4db94011d3 3321 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
sahilmgandhi 18:6a4db94011d3 3322 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
sahilmgandhi 18:6a4db94011d3 3323 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
sahilmgandhi 18:6a4db94011d3 3324
sahilmgandhi 18:6a4db94011d3 3325 /* Register: CCM_INPTR */
sahilmgandhi 18:6a4db94011d3 3326 /* Description: Input pointer */
sahilmgandhi 18:6a4db94011d3 3327
sahilmgandhi 18:6a4db94011d3 3328 /* Bits 31..0 : Input pointer */
sahilmgandhi 18:6a4db94011d3 3329 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
sahilmgandhi 18:6a4db94011d3 3330 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
sahilmgandhi 18:6a4db94011d3 3331
sahilmgandhi 18:6a4db94011d3 3332 /* Register: CCM_OUTPTR */
sahilmgandhi 18:6a4db94011d3 3333 /* Description: Output pointer */
sahilmgandhi 18:6a4db94011d3 3334
sahilmgandhi 18:6a4db94011d3 3335 /* Bits 31..0 : Output pointer */
sahilmgandhi 18:6a4db94011d3 3336 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
sahilmgandhi 18:6a4db94011d3 3337 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
sahilmgandhi 18:6a4db94011d3 3338
sahilmgandhi 18:6a4db94011d3 3339 /* Register: CCM_SCRATCHPTR */
sahilmgandhi 18:6a4db94011d3 3340 /* Description: Pointer to data area used for temporary storage */
sahilmgandhi 18:6a4db94011d3 3341
sahilmgandhi 18:6a4db94011d3 3342 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
sahilmgandhi 18:6a4db94011d3 3343 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
sahilmgandhi 18:6a4db94011d3 3344 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
sahilmgandhi 18:6a4db94011d3 3345
sahilmgandhi 18:6a4db94011d3 3346
sahilmgandhi 18:6a4db94011d3 3347 /* Peripheral: CLOCK */
sahilmgandhi 18:6a4db94011d3 3348 /* Description: Clock control */
sahilmgandhi 18:6a4db94011d3 3349
sahilmgandhi 18:6a4db94011d3 3350 /* Register: CLOCK_INTENSET */
sahilmgandhi 18:6a4db94011d3 3351 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 3352
sahilmgandhi 18:6a4db94011d3 3353 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
sahilmgandhi 18:6a4db94011d3 3354 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
sahilmgandhi 18:6a4db94011d3 3355 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
sahilmgandhi 18:6a4db94011d3 3356 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3357 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3358 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3359
sahilmgandhi 18:6a4db94011d3 3360 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
sahilmgandhi 18:6a4db94011d3 3361 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 3362 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 3363 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3364 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3365 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3366
sahilmgandhi 18:6a4db94011d3 3367 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
sahilmgandhi 18:6a4db94011d3 3368 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3369 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3370 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3371 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3372 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3373
sahilmgandhi 18:6a4db94011d3 3374 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
sahilmgandhi 18:6a4db94011d3 3375 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3376 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3377 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3378 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3379 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3380
sahilmgandhi 18:6a4db94011d3 3381 /* Register: CLOCK_INTENCLR */
sahilmgandhi 18:6a4db94011d3 3382 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 3383
sahilmgandhi 18:6a4db94011d3 3384 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
sahilmgandhi 18:6a4db94011d3 3385 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
sahilmgandhi 18:6a4db94011d3 3386 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
sahilmgandhi 18:6a4db94011d3 3387 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3388 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3389 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3390
sahilmgandhi 18:6a4db94011d3 3391 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
sahilmgandhi 18:6a4db94011d3 3392 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 3393 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 3394 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3395 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3396 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3397
sahilmgandhi 18:6a4db94011d3 3398 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
sahilmgandhi 18:6a4db94011d3 3399 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3400 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3401 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3402 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3403 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3404
sahilmgandhi 18:6a4db94011d3 3405 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
sahilmgandhi 18:6a4db94011d3 3406 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3407 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 3408 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3409 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3410 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3411
sahilmgandhi 18:6a4db94011d3 3412 /* Register: CLOCK_HFCLKRUN */
sahilmgandhi 18:6a4db94011d3 3413 /* Description: Status indicating that HFCLKSTART task has been triggered */
sahilmgandhi 18:6a4db94011d3 3414
sahilmgandhi 18:6a4db94011d3 3415 /* Bit 0 : HFCLKSTART task triggered or not */
sahilmgandhi 18:6a4db94011d3 3416 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 3417 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 3418 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
sahilmgandhi 18:6a4db94011d3 3419 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
sahilmgandhi 18:6a4db94011d3 3420
sahilmgandhi 18:6a4db94011d3 3421 /* Register: CLOCK_HFCLKSTAT */
sahilmgandhi 18:6a4db94011d3 3422 /* Description: HFCLK status */
sahilmgandhi 18:6a4db94011d3 3423
sahilmgandhi 18:6a4db94011d3 3424 /* Bit 16 : HFCLK state */
sahilmgandhi 18:6a4db94011d3 3425 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
sahilmgandhi 18:6a4db94011d3 3426 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
sahilmgandhi 18:6a4db94011d3 3427 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
sahilmgandhi 18:6a4db94011d3 3428 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
sahilmgandhi 18:6a4db94011d3 3429
sahilmgandhi 18:6a4db94011d3 3430 /* Bit 0 : Source of HFCLK */
sahilmgandhi 18:6a4db94011d3 3431 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 3432 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 3433 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
sahilmgandhi 18:6a4db94011d3 3434 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
sahilmgandhi 18:6a4db94011d3 3435
sahilmgandhi 18:6a4db94011d3 3436 /* Register: CLOCK_LFCLKRUN */
sahilmgandhi 18:6a4db94011d3 3437 /* Description: Status indicating that LFCLKSTART task has been triggered */
sahilmgandhi 18:6a4db94011d3 3438
sahilmgandhi 18:6a4db94011d3 3439 /* Bit 0 : LFCLKSTART task triggered or not */
sahilmgandhi 18:6a4db94011d3 3440 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 3441 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 3442 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
sahilmgandhi 18:6a4db94011d3 3443 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
sahilmgandhi 18:6a4db94011d3 3444
sahilmgandhi 18:6a4db94011d3 3445 /* Register: CLOCK_LFCLKSTAT */
sahilmgandhi 18:6a4db94011d3 3446 /* Description: LFCLK status */
sahilmgandhi 18:6a4db94011d3 3447
sahilmgandhi 18:6a4db94011d3 3448 /* Bit 16 : LFCLK state */
sahilmgandhi 18:6a4db94011d3 3449 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
sahilmgandhi 18:6a4db94011d3 3450 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
sahilmgandhi 18:6a4db94011d3 3451 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
sahilmgandhi 18:6a4db94011d3 3452 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
sahilmgandhi 18:6a4db94011d3 3453
sahilmgandhi 18:6a4db94011d3 3454 /* Bits 1..0 : Source of LFCLK */
sahilmgandhi 18:6a4db94011d3 3455 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 3456 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 3457 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
sahilmgandhi 18:6a4db94011d3 3458 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
sahilmgandhi 18:6a4db94011d3 3459 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
sahilmgandhi 18:6a4db94011d3 3460
sahilmgandhi 18:6a4db94011d3 3461 /* Register: CLOCK_LFCLKSRCCOPY */
sahilmgandhi 18:6a4db94011d3 3462 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
sahilmgandhi 18:6a4db94011d3 3463
sahilmgandhi 18:6a4db94011d3 3464 /* Bits 1..0 : Clock source */
sahilmgandhi 18:6a4db94011d3 3465 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 3466 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 3467 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
sahilmgandhi 18:6a4db94011d3 3468 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
sahilmgandhi 18:6a4db94011d3 3469 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
sahilmgandhi 18:6a4db94011d3 3470
sahilmgandhi 18:6a4db94011d3 3471 /* Register: CLOCK_LFCLKSRC */
sahilmgandhi 18:6a4db94011d3 3472 /* Description: Clock source for the LFCLK */
sahilmgandhi 18:6a4db94011d3 3473
sahilmgandhi 18:6a4db94011d3 3474 /* Bits 1..0 : Clock source */
sahilmgandhi 18:6a4db94011d3 3475 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 3476 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 3477 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
sahilmgandhi 18:6a4db94011d3 3478 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
sahilmgandhi 18:6a4db94011d3 3479 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
sahilmgandhi 18:6a4db94011d3 3480
sahilmgandhi 18:6a4db94011d3 3481 /* Register: CLOCK_CTIV */
sahilmgandhi 18:6a4db94011d3 3482 /* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
sahilmgandhi 18:6a4db94011d3 3483
sahilmgandhi 18:6a4db94011d3 3484 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
sahilmgandhi 18:6a4db94011d3 3485 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
sahilmgandhi 18:6a4db94011d3 3486 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
sahilmgandhi 18:6a4db94011d3 3487
sahilmgandhi 18:6a4db94011d3 3488 /* Register: CLOCK_TRACECONFIG */
sahilmgandhi 18:6a4db94011d3 3489 /* Description: Clocking options for the Trace Port debug interface */
sahilmgandhi 18:6a4db94011d3 3490
sahilmgandhi 18:6a4db94011d3 3491 /* Bits 17..16 : Pin multiplexing of trace signals. */
sahilmgandhi 18:6a4db94011d3 3492 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
sahilmgandhi 18:6a4db94011d3 3493 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
sahilmgandhi 18:6a4db94011d3 3494 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
sahilmgandhi 18:6a4db94011d3 3495 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
sahilmgandhi 18:6a4db94011d3 3496 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
sahilmgandhi 18:6a4db94011d3 3497
sahilmgandhi 18:6a4db94011d3 3498 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
sahilmgandhi 18:6a4db94011d3 3499 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
sahilmgandhi 18:6a4db94011d3 3500 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
sahilmgandhi 18:6a4db94011d3 3501 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
sahilmgandhi 18:6a4db94011d3 3502 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
sahilmgandhi 18:6a4db94011d3 3503 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
sahilmgandhi 18:6a4db94011d3 3504 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
sahilmgandhi 18:6a4db94011d3 3505
sahilmgandhi 18:6a4db94011d3 3506
sahilmgandhi 18:6a4db94011d3 3507 /* Peripheral: COMP */
sahilmgandhi 18:6a4db94011d3 3508 /* Description: Comparator */
sahilmgandhi 18:6a4db94011d3 3509
sahilmgandhi 18:6a4db94011d3 3510 /* Register: COMP_SHORTS */
sahilmgandhi 18:6a4db94011d3 3511 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 3512
sahilmgandhi 18:6a4db94011d3 3513 /* Bit 4 : Shortcut between CROSS event and STOP task */
sahilmgandhi 18:6a4db94011d3 3514 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
sahilmgandhi 18:6a4db94011d3 3515 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
sahilmgandhi 18:6a4db94011d3 3516 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 3517 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 3518
sahilmgandhi 18:6a4db94011d3 3519 /* Bit 3 : Shortcut between UP event and STOP task */
sahilmgandhi 18:6a4db94011d3 3520 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
sahilmgandhi 18:6a4db94011d3 3521 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
sahilmgandhi 18:6a4db94011d3 3522 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 3523 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 3524
sahilmgandhi 18:6a4db94011d3 3525 /* Bit 2 : Shortcut between DOWN event and STOP task */
sahilmgandhi 18:6a4db94011d3 3526 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
sahilmgandhi 18:6a4db94011d3 3527 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
sahilmgandhi 18:6a4db94011d3 3528 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 3529 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 3530
sahilmgandhi 18:6a4db94011d3 3531 /* Bit 1 : Shortcut between READY event and STOP task */
sahilmgandhi 18:6a4db94011d3 3532 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
sahilmgandhi 18:6a4db94011d3 3533 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
sahilmgandhi 18:6a4db94011d3 3534 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 3535 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 3536
sahilmgandhi 18:6a4db94011d3 3537 /* Bit 0 : Shortcut between READY event and SAMPLE task */
sahilmgandhi 18:6a4db94011d3 3538 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 3539 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 3540 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 3541 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 3542
sahilmgandhi 18:6a4db94011d3 3543 /* Register: COMP_INTEN */
sahilmgandhi 18:6a4db94011d3 3544 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 3545
sahilmgandhi 18:6a4db94011d3 3546 /* Bit 3 : Enable or disable interrupt for CROSS event */
sahilmgandhi 18:6a4db94011d3 3547 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 3548 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 3549 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3550 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3551
sahilmgandhi 18:6a4db94011d3 3552 /* Bit 2 : Enable or disable interrupt for UP event */
sahilmgandhi 18:6a4db94011d3 3553 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 3554 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 3555 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3556 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3557
sahilmgandhi 18:6a4db94011d3 3558 /* Bit 1 : Enable or disable interrupt for DOWN event */
sahilmgandhi 18:6a4db94011d3 3559 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 3560 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 3561 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3562 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3563
sahilmgandhi 18:6a4db94011d3 3564 /* Bit 0 : Enable or disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 3565 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 3566 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 3567 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3568 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3569
sahilmgandhi 18:6a4db94011d3 3570 /* Register: COMP_INTENSET */
sahilmgandhi 18:6a4db94011d3 3571 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 3572
sahilmgandhi 18:6a4db94011d3 3573 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
sahilmgandhi 18:6a4db94011d3 3574 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 3575 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 3576 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3577 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3578 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3579
sahilmgandhi 18:6a4db94011d3 3580 /* Bit 2 : Write '1' to Enable interrupt for UP event */
sahilmgandhi 18:6a4db94011d3 3581 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 3582 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 3583 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3584 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3585 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3586
sahilmgandhi 18:6a4db94011d3 3587 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
sahilmgandhi 18:6a4db94011d3 3588 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 3589 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 3590 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3591 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3592 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3593
sahilmgandhi 18:6a4db94011d3 3594 /* Bit 0 : Write '1' to Enable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 3595 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 3596 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 3597 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3598 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3599 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3600
sahilmgandhi 18:6a4db94011d3 3601 /* Register: COMP_INTENCLR */
sahilmgandhi 18:6a4db94011d3 3602 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 3603
sahilmgandhi 18:6a4db94011d3 3604 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
sahilmgandhi 18:6a4db94011d3 3605 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 3606 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 3607 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3608 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3609 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3610
sahilmgandhi 18:6a4db94011d3 3611 /* Bit 2 : Write '1' to Disable interrupt for UP event */
sahilmgandhi 18:6a4db94011d3 3612 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 3613 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 3614 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3615 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3616 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3617
sahilmgandhi 18:6a4db94011d3 3618 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
sahilmgandhi 18:6a4db94011d3 3619 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 3620 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 3621 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3622 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3623 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3624
sahilmgandhi 18:6a4db94011d3 3625 /* Bit 0 : Write '1' to Disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 3626 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 3627 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 3628 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3629 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3630 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3631
sahilmgandhi 18:6a4db94011d3 3632 /* Register: COMP_RESULT */
sahilmgandhi 18:6a4db94011d3 3633 /* Description: Compare result */
sahilmgandhi 18:6a4db94011d3 3634
sahilmgandhi 18:6a4db94011d3 3635 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
sahilmgandhi 18:6a4db94011d3 3636 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
sahilmgandhi 18:6a4db94011d3 3637 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
sahilmgandhi 18:6a4db94011d3 3638 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
sahilmgandhi 18:6a4db94011d3 3639 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
sahilmgandhi 18:6a4db94011d3 3640
sahilmgandhi 18:6a4db94011d3 3641 /* Register: COMP_ENABLE */
sahilmgandhi 18:6a4db94011d3 3642 /* Description: COMP enable */
sahilmgandhi 18:6a4db94011d3 3643
sahilmgandhi 18:6a4db94011d3 3644 /* Bits 1..0 : Enable or disable COMP */
sahilmgandhi 18:6a4db94011d3 3645 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 3646 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 3647 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3648 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3649
sahilmgandhi 18:6a4db94011d3 3650 /* Register: COMP_PSEL */
sahilmgandhi 18:6a4db94011d3 3651 /* Description: Pin select */
sahilmgandhi 18:6a4db94011d3 3652
sahilmgandhi 18:6a4db94011d3 3653 /* Bits 2..0 : Analog pin select */
sahilmgandhi 18:6a4db94011d3 3654 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
sahilmgandhi 18:6a4db94011d3 3655 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
sahilmgandhi 18:6a4db94011d3 3656 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3657 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3658 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3659 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3660 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3661 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3662 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3663 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
sahilmgandhi 18:6a4db94011d3 3664
sahilmgandhi 18:6a4db94011d3 3665 /* Register: COMP_REFSEL */
sahilmgandhi 18:6a4db94011d3 3666 /* Description: Reference source select */
sahilmgandhi 18:6a4db94011d3 3667
sahilmgandhi 18:6a4db94011d3 3668 /* Bits 2..0 : Reference select */
sahilmgandhi 18:6a4db94011d3 3669 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 3670 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 3671 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
sahilmgandhi 18:6a4db94011d3 3672 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
sahilmgandhi 18:6a4db94011d3 3673 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
sahilmgandhi 18:6a4db94011d3 3674 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
sahilmgandhi 18:6a4db94011d3 3675 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
sahilmgandhi 18:6a4db94011d3 3676
sahilmgandhi 18:6a4db94011d3 3677 /* Register: COMP_EXTREFSEL */
sahilmgandhi 18:6a4db94011d3 3678 /* Description: External reference select */
sahilmgandhi 18:6a4db94011d3 3679
sahilmgandhi 18:6a4db94011d3 3680 /* Bit 0 : External analog reference select */
sahilmgandhi 18:6a4db94011d3 3681 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 3682 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 3683 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
sahilmgandhi 18:6a4db94011d3 3684 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
sahilmgandhi 18:6a4db94011d3 3685
sahilmgandhi 18:6a4db94011d3 3686 /* Register: COMP_TH */
sahilmgandhi 18:6a4db94011d3 3687 /* Description: Threshold configuration for hysteresis unit */
sahilmgandhi 18:6a4db94011d3 3688
sahilmgandhi 18:6a4db94011d3 3689 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
sahilmgandhi 18:6a4db94011d3 3690 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
sahilmgandhi 18:6a4db94011d3 3691 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
sahilmgandhi 18:6a4db94011d3 3692
sahilmgandhi 18:6a4db94011d3 3693 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
sahilmgandhi 18:6a4db94011d3 3694 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
sahilmgandhi 18:6a4db94011d3 3695 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
sahilmgandhi 18:6a4db94011d3 3696
sahilmgandhi 18:6a4db94011d3 3697 /* Register: COMP_MODE */
sahilmgandhi 18:6a4db94011d3 3698 /* Description: Mode configuration */
sahilmgandhi 18:6a4db94011d3 3699
sahilmgandhi 18:6a4db94011d3 3700 /* Bit 8 : Main operation mode */
sahilmgandhi 18:6a4db94011d3 3701 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
sahilmgandhi 18:6a4db94011d3 3702 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
sahilmgandhi 18:6a4db94011d3 3703 #define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
sahilmgandhi 18:6a4db94011d3 3704 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
sahilmgandhi 18:6a4db94011d3 3705
sahilmgandhi 18:6a4db94011d3 3706 /* Bits 1..0 : Speed and power mode */
sahilmgandhi 18:6a4db94011d3 3707 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
sahilmgandhi 18:6a4db94011d3 3708 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
sahilmgandhi 18:6a4db94011d3 3709 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
sahilmgandhi 18:6a4db94011d3 3710 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
sahilmgandhi 18:6a4db94011d3 3711 #define COMP_MODE_SP_High (2UL) /*!< High speed mode */
sahilmgandhi 18:6a4db94011d3 3712
sahilmgandhi 18:6a4db94011d3 3713 /* Register: COMP_HYST */
sahilmgandhi 18:6a4db94011d3 3714 /* Description: Comparator hysteresis enable */
sahilmgandhi 18:6a4db94011d3 3715
sahilmgandhi 18:6a4db94011d3 3716 /* Bit 0 : Comparator hysteresis */
sahilmgandhi 18:6a4db94011d3 3717 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
sahilmgandhi 18:6a4db94011d3 3718 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
sahilmgandhi 18:6a4db94011d3 3719 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
sahilmgandhi 18:6a4db94011d3 3720 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
sahilmgandhi 18:6a4db94011d3 3721
sahilmgandhi 18:6a4db94011d3 3722 /* Register: COMP_ISOURCE */
sahilmgandhi 18:6a4db94011d3 3723 /* Description: Current source select on analog input */
sahilmgandhi 18:6a4db94011d3 3724
sahilmgandhi 18:6a4db94011d3 3725 /* Bits 1..0 : Comparator hysteresis */
sahilmgandhi 18:6a4db94011d3 3726 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
sahilmgandhi 18:6a4db94011d3 3727 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
sahilmgandhi 18:6a4db94011d3 3728 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
sahilmgandhi 18:6a4db94011d3 3729 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
sahilmgandhi 18:6a4db94011d3 3730 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
sahilmgandhi 18:6a4db94011d3 3731 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
sahilmgandhi 18:6a4db94011d3 3732
sahilmgandhi 18:6a4db94011d3 3733
sahilmgandhi 18:6a4db94011d3 3734 /* Peripheral: ECB */
sahilmgandhi 18:6a4db94011d3 3735 /* Description: AES ECB Mode Encryption */
sahilmgandhi 18:6a4db94011d3 3736
sahilmgandhi 18:6a4db94011d3 3737 /* Register: ECB_INTENSET */
sahilmgandhi 18:6a4db94011d3 3738 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 3739
sahilmgandhi 18:6a4db94011d3 3740 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
sahilmgandhi 18:6a4db94011d3 3741 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 3742 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 3743 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3744 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3745 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3746
sahilmgandhi 18:6a4db94011d3 3747 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
sahilmgandhi 18:6a4db94011d3 3748 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 3749 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 3750 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3751 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3752 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3753
sahilmgandhi 18:6a4db94011d3 3754 /* Register: ECB_INTENCLR */
sahilmgandhi 18:6a4db94011d3 3755 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 3756
sahilmgandhi 18:6a4db94011d3 3757 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
sahilmgandhi 18:6a4db94011d3 3758 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 3759 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 3760 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3761 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3762 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3763
sahilmgandhi 18:6a4db94011d3 3764 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
sahilmgandhi 18:6a4db94011d3 3765 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 3766 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 3767 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3768 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3769 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3770
sahilmgandhi 18:6a4db94011d3 3771 /* Register: ECB_ECBDATAPTR */
sahilmgandhi 18:6a4db94011d3 3772 /* Description: ECB block encrypt memory pointers */
sahilmgandhi 18:6a4db94011d3 3773
sahilmgandhi 18:6a4db94011d3 3774 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
sahilmgandhi 18:6a4db94011d3 3775 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
sahilmgandhi 18:6a4db94011d3 3776 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
sahilmgandhi 18:6a4db94011d3 3777
sahilmgandhi 18:6a4db94011d3 3778
sahilmgandhi 18:6a4db94011d3 3779 /* Peripheral: EGU */
sahilmgandhi 18:6a4db94011d3 3780 /* Description: Event Generator Unit 0 */
sahilmgandhi 18:6a4db94011d3 3781
sahilmgandhi 18:6a4db94011d3 3782 /* Register: EGU_INTEN */
sahilmgandhi 18:6a4db94011d3 3783 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 3784
sahilmgandhi 18:6a4db94011d3 3785 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
sahilmgandhi 18:6a4db94011d3 3786 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
sahilmgandhi 18:6a4db94011d3 3787 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
sahilmgandhi 18:6a4db94011d3 3788 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3789 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3790
sahilmgandhi 18:6a4db94011d3 3791 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
sahilmgandhi 18:6a4db94011d3 3792 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
sahilmgandhi 18:6a4db94011d3 3793 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
sahilmgandhi 18:6a4db94011d3 3794 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3795 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3796
sahilmgandhi 18:6a4db94011d3 3797 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
sahilmgandhi 18:6a4db94011d3 3798 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
sahilmgandhi 18:6a4db94011d3 3799 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
sahilmgandhi 18:6a4db94011d3 3800 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3801 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3802
sahilmgandhi 18:6a4db94011d3 3803 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
sahilmgandhi 18:6a4db94011d3 3804 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
sahilmgandhi 18:6a4db94011d3 3805 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
sahilmgandhi 18:6a4db94011d3 3806 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3807 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3808
sahilmgandhi 18:6a4db94011d3 3809 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
sahilmgandhi 18:6a4db94011d3 3810 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
sahilmgandhi 18:6a4db94011d3 3811 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
sahilmgandhi 18:6a4db94011d3 3812 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3813 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3814
sahilmgandhi 18:6a4db94011d3 3815 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
sahilmgandhi 18:6a4db94011d3 3816 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
sahilmgandhi 18:6a4db94011d3 3817 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
sahilmgandhi 18:6a4db94011d3 3818 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3819 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3820
sahilmgandhi 18:6a4db94011d3 3821 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
sahilmgandhi 18:6a4db94011d3 3822 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
sahilmgandhi 18:6a4db94011d3 3823 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
sahilmgandhi 18:6a4db94011d3 3824 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3825 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3826
sahilmgandhi 18:6a4db94011d3 3827 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
sahilmgandhi 18:6a4db94011d3 3828 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
sahilmgandhi 18:6a4db94011d3 3829 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
sahilmgandhi 18:6a4db94011d3 3830 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3831 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3832
sahilmgandhi 18:6a4db94011d3 3833 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
sahilmgandhi 18:6a4db94011d3 3834 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
sahilmgandhi 18:6a4db94011d3 3835 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
sahilmgandhi 18:6a4db94011d3 3836 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3837 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3838
sahilmgandhi 18:6a4db94011d3 3839 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
sahilmgandhi 18:6a4db94011d3 3840 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
sahilmgandhi 18:6a4db94011d3 3841 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
sahilmgandhi 18:6a4db94011d3 3842 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3843 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3844
sahilmgandhi 18:6a4db94011d3 3845 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
sahilmgandhi 18:6a4db94011d3 3846 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
sahilmgandhi 18:6a4db94011d3 3847 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
sahilmgandhi 18:6a4db94011d3 3848 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3849 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3850
sahilmgandhi 18:6a4db94011d3 3851 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
sahilmgandhi 18:6a4db94011d3 3852 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
sahilmgandhi 18:6a4db94011d3 3853 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
sahilmgandhi 18:6a4db94011d3 3854 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3855 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3856
sahilmgandhi 18:6a4db94011d3 3857 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
sahilmgandhi 18:6a4db94011d3 3858 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
sahilmgandhi 18:6a4db94011d3 3859 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
sahilmgandhi 18:6a4db94011d3 3860 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3861 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3862
sahilmgandhi 18:6a4db94011d3 3863 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
sahilmgandhi 18:6a4db94011d3 3864 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
sahilmgandhi 18:6a4db94011d3 3865 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
sahilmgandhi 18:6a4db94011d3 3866 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3867 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3868
sahilmgandhi 18:6a4db94011d3 3869 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
sahilmgandhi 18:6a4db94011d3 3870 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
sahilmgandhi 18:6a4db94011d3 3871 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
sahilmgandhi 18:6a4db94011d3 3872 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3873 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3874
sahilmgandhi 18:6a4db94011d3 3875 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
sahilmgandhi 18:6a4db94011d3 3876 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
sahilmgandhi 18:6a4db94011d3 3877 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
sahilmgandhi 18:6a4db94011d3 3878 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 3879 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3880
sahilmgandhi 18:6a4db94011d3 3881 /* Register: EGU_INTENSET */
sahilmgandhi 18:6a4db94011d3 3882 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 3883
sahilmgandhi 18:6a4db94011d3 3884 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
sahilmgandhi 18:6a4db94011d3 3885 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
sahilmgandhi 18:6a4db94011d3 3886 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
sahilmgandhi 18:6a4db94011d3 3887 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3888 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3889 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3890
sahilmgandhi 18:6a4db94011d3 3891 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
sahilmgandhi 18:6a4db94011d3 3892 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
sahilmgandhi 18:6a4db94011d3 3893 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
sahilmgandhi 18:6a4db94011d3 3894 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3895 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3896 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3897
sahilmgandhi 18:6a4db94011d3 3898 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
sahilmgandhi 18:6a4db94011d3 3899 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
sahilmgandhi 18:6a4db94011d3 3900 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
sahilmgandhi 18:6a4db94011d3 3901 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3902 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3903 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3904
sahilmgandhi 18:6a4db94011d3 3905 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
sahilmgandhi 18:6a4db94011d3 3906 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
sahilmgandhi 18:6a4db94011d3 3907 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
sahilmgandhi 18:6a4db94011d3 3908 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3909 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3910 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3911
sahilmgandhi 18:6a4db94011d3 3912 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
sahilmgandhi 18:6a4db94011d3 3913 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
sahilmgandhi 18:6a4db94011d3 3914 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
sahilmgandhi 18:6a4db94011d3 3915 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3916 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3917 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3918
sahilmgandhi 18:6a4db94011d3 3919 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
sahilmgandhi 18:6a4db94011d3 3920 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
sahilmgandhi 18:6a4db94011d3 3921 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
sahilmgandhi 18:6a4db94011d3 3922 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3923 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3924 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3925
sahilmgandhi 18:6a4db94011d3 3926 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
sahilmgandhi 18:6a4db94011d3 3927 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
sahilmgandhi 18:6a4db94011d3 3928 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
sahilmgandhi 18:6a4db94011d3 3929 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3930 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3931 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3932
sahilmgandhi 18:6a4db94011d3 3933 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
sahilmgandhi 18:6a4db94011d3 3934 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
sahilmgandhi 18:6a4db94011d3 3935 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
sahilmgandhi 18:6a4db94011d3 3936 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3937 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3938 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3939
sahilmgandhi 18:6a4db94011d3 3940 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
sahilmgandhi 18:6a4db94011d3 3941 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
sahilmgandhi 18:6a4db94011d3 3942 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
sahilmgandhi 18:6a4db94011d3 3943 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3944 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3945 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3946
sahilmgandhi 18:6a4db94011d3 3947 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
sahilmgandhi 18:6a4db94011d3 3948 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
sahilmgandhi 18:6a4db94011d3 3949 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
sahilmgandhi 18:6a4db94011d3 3950 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3951 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3952 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3953
sahilmgandhi 18:6a4db94011d3 3954 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
sahilmgandhi 18:6a4db94011d3 3955 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
sahilmgandhi 18:6a4db94011d3 3956 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
sahilmgandhi 18:6a4db94011d3 3957 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3958 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3959 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3960
sahilmgandhi 18:6a4db94011d3 3961 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
sahilmgandhi 18:6a4db94011d3 3962 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
sahilmgandhi 18:6a4db94011d3 3963 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
sahilmgandhi 18:6a4db94011d3 3964 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3965 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3966 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3967
sahilmgandhi 18:6a4db94011d3 3968 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
sahilmgandhi 18:6a4db94011d3 3969 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
sahilmgandhi 18:6a4db94011d3 3970 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
sahilmgandhi 18:6a4db94011d3 3971 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3972 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3973 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3974
sahilmgandhi 18:6a4db94011d3 3975 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
sahilmgandhi 18:6a4db94011d3 3976 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
sahilmgandhi 18:6a4db94011d3 3977 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
sahilmgandhi 18:6a4db94011d3 3978 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3979 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3980 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3981
sahilmgandhi 18:6a4db94011d3 3982 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
sahilmgandhi 18:6a4db94011d3 3983 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
sahilmgandhi 18:6a4db94011d3 3984 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
sahilmgandhi 18:6a4db94011d3 3985 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3986 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3987 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3988
sahilmgandhi 18:6a4db94011d3 3989 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
sahilmgandhi 18:6a4db94011d3 3990 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
sahilmgandhi 18:6a4db94011d3 3991 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
sahilmgandhi 18:6a4db94011d3 3992 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 3993 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 3994 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 3995
sahilmgandhi 18:6a4db94011d3 3996 /* Register: EGU_INTENCLR */
sahilmgandhi 18:6a4db94011d3 3997 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 3998
sahilmgandhi 18:6a4db94011d3 3999 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
sahilmgandhi 18:6a4db94011d3 4000 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
sahilmgandhi 18:6a4db94011d3 4001 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
sahilmgandhi 18:6a4db94011d3 4002 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4003 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4004 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4005
sahilmgandhi 18:6a4db94011d3 4006 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
sahilmgandhi 18:6a4db94011d3 4007 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
sahilmgandhi 18:6a4db94011d3 4008 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
sahilmgandhi 18:6a4db94011d3 4009 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4010 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4011 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4012
sahilmgandhi 18:6a4db94011d3 4013 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
sahilmgandhi 18:6a4db94011d3 4014 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
sahilmgandhi 18:6a4db94011d3 4015 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
sahilmgandhi 18:6a4db94011d3 4016 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4017 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4018 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4019
sahilmgandhi 18:6a4db94011d3 4020 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
sahilmgandhi 18:6a4db94011d3 4021 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
sahilmgandhi 18:6a4db94011d3 4022 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
sahilmgandhi 18:6a4db94011d3 4023 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4024 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4025 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4026
sahilmgandhi 18:6a4db94011d3 4027 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
sahilmgandhi 18:6a4db94011d3 4028 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
sahilmgandhi 18:6a4db94011d3 4029 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
sahilmgandhi 18:6a4db94011d3 4030 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4031 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4032 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4033
sahilmgandhi 18:6a4db94011d3 4034 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
sahilmgandhi 18:6a4db94011d3 4035 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
sahilmgandhi 18:6a4db94011d3 4036 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
sahilmgandhi 18:6a4db94011d3 4037 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4038 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4039 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4040
sahilmgandhi 18:6a4db94011d3 4041 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
sahilmgandhi 18:6a4db94011d3 4042 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
sahilmgandhi 18:6a4db94011d3 4043 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
sahilmgandhi 18:6a4db94011d3 4044 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4045 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4046 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4047
sahilmgandhi 18:6a4db94011d3 4048 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
sahilmgandhi 18:6a4db94011d3 4049 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
sahilmgandhi 18:6a4db94011d3 4050 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
sahilmgandhi 18:6a4db94011d3 4051 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4052 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4053 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4054
sahilmgandhi 18:6a4db94011d3 4055 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
sahilmgandhi 18:6a4db94011d3 4056 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
sahilmgandhi 18:6a4db94011d3 4057 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
sahilmgandhi 18:6a4db94011d3 4058 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4059 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4060 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4061
sahilmgandhi 18:6a4db94011d3 4062 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
sahilmgandhi 18:6a4db94011d3 4063 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
sahilmgandhi 18:6a4db94011d3 4064 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
sahilmgandhi 18:6a4db94011d3 4065 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4066 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4067 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4068
sahilmgandhi 18:6a4db94011d3 4069 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
sahilmgandhi 18:6a4db94011d3 4070 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
sahilmgandhi 18:6a4db94011d3 4071 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
sahilmgandhi 18:6a4db94011d3 4072 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4073 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4074 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4075
sahilmgandhi 18:6a4db94011d3 4076 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
sahilmgandhi 18:6a4db94011d3 4077 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
sahilmgandhi 18:6a4db94011d3 4078 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
sahilmgandhi 18:6a4db94011d3 4079 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4080 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4081 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4082
sahilmgandhi 18:6a4db94011d3 4083 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
sahilmgandhi 18:6a4db94011d3 4084 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
sahilmgandhi 18:6a4db94011d3 4085 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
sahilmgandhi 18:6a4db94011d3 4086 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4087 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4088 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4089
sahilmgandhi 18:6a4db94011d3 4090 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
sahilmgandhi 18:6a4db94011d3 4091 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
sahilmgandhi 18:6a4db94011d3 4092 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
sahilmgandhi 18:6a4db94011d3 4093 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4094 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4095 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4096
sahilmgandhi 18:6a4db94011d3 4097 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
sahilmgandhi 18:6a4db94011d3 4098 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
sahilmgandhi 18:6a4db94011d3 4099 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
sahilmgandhi 18:6a4db94011d3 4100 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4101 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4102 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4103
sahilmgandhi 18:6a4db94011d3 4104 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
sahilmgandhi 18:6a4db94011d3 4105 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
sahilmgandhi 18:6a4db94011d3 4106 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
sahilmgandhi 18:6a4db94011d3 4107 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4108 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4109 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4110
sahilmgandhi 18:6a4db94011d3 4111
sahilmgandhi 18:6a4db94011d3 4112 /* Peripheral: FICR */
sahilmgandhi 18:6a4db94011d3 4113 /* Description: Factory Information Configuration Registers */
sahilmgandhi 18:6a4db94011d3 4114
sahilmgandhi 18:6a4db94011d3 4115 /* Register: FICR_CODEPAGESIZE */
sahilmgandhi 18:6a4db94011d3 4116 /* Description: Code memory page size */
sahilmgandhi 18:6a4db94011d3 4117
sahilmgandhi 18:6a4db94011d3 4118 /* Bits 31..0 : Code memory page size */
sahilmgandhi 18:6a4db94011d3 4119 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
sahilmgandhi 18:6a4db94011d3 4120 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
sahilmgandhi 18:6a4db94011d3 4121
sahilmgandhi 18:6a4db94011d3 4122 /* Register: FICR_CODESIZE */
sahilmgandhi 18:6a4db94011d3 4123 /* Description: Code memory size */
sahilmgandhi 18:6a4db94011d3 4124
sahilmgandhi 18:6a4db94011d3 4125 /* Bits 31..0 : Code memory size in number of pages */
sahilmgandhi 18:6a4db94011d3 4126 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
sahilmgandhi 18:6a4db94011d3 4127 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
sahilmgandhi 18:6a4db94011d3 4128
sahilmgandhi 18:6a4db94011d3 4129 /* Register: FICR_DEVICEID */
sahilmgandhi 18:6a4db94011d3 4130 /* Description: Description collection[0]: Device identifier */
sahilmgandhi 18:6a4db94011d3 4131
sahilmgandhi 18:6a4db94011d3 4132 /* Bits 31..0 : 64 bit unique device identifier */
sahilmgandhi 18:6a4db94011d3 4133 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
sahilmgandhi 18:6a4db94011d3 4134 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
sahilmgandhi 18:6a4db94011d3 4135
sahilmgandhi 18:6a4db94011d3 4136 /* Register: FICR_ER */
sahilmgandhi 18:6a4db94011d3 4137 /* Description: Description collection[0]: Encryption Root, word 0 */
sahilmgandhi 18:6a4db94011d3 4138
sahilmgandhi 18:6a4db94011d3 4139 /* Bits 31..0 : Encryption Root, word n */
sahilmgandhi 18:6a4db94011d3 4140 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
sahilmgandhi 18:6a4db94011d3 4141 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
sahilmgandhi 18:6a4db94011d3 4142
sahilmgandhi 18:6a4db94011d3 4143 /* Register: FICR_IR */
sahilmgandhi 18:6a4db94011d3 4144 /* Description: Description collection[0]: Identity Root, word 0 */
sahilmgandhi 18:6a4db94011d3 4145
sahilmgandhi 18:6a4db94011d3 4146 /* Bits 31..0 : Identity Root, word n */
sahilmgandhi 18:6a4db94011d3 4147 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
sahilmgandhi 18:6a4db94011d3 4148 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
sahilmgandhi 18:6a4db94011d3 4149
sahilmgandhi 18:6a4db94011d3 4150 /* Register: FICR_DEVICEADDRTYPE */
sahilmgandhi 18:6a4db94011d3 4151 /* Description: Device address type */
sahilmgandhi 18:6a4db94011d3 4152
sahilmgandhi 18:6a4db94011d3 4153 /* Bit 0 : Device address type */
sahilmgandhi 18:6a4db94011d3 4154 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
sahilmgandhi 18:6a4db94011d3 4155 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
sahilmgandhi 18:6a4db94011d3 4156 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
sahilmgandhi 18:6a4db94011d3 4157 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
sahilmgandhi 18:6a4db94011d3 4158
sahilmgandhi 18:6a4db94011d3 4159 /* Register: FICR_DEVICEADDR */
sahilmgandhi 18:6a4db94011d3 4160 /* Description: Description collection[0]: Device address 0 */
sahilmgandhi 18:6a4db94011d3 4161
sahilmgandhi 18:6a4db94011d3 4162 /* Bits 31..0 : 48 bit device address */
sahilmgandhi 18:6a4db94011d3 4163 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
sahilmgandhi 18:6a4db94011d3 4164 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
sahilmgandhi 18:6a4db94011d3 4165
sahilmgandhi 18:6a4db94011d3 4166 /* Register: FICR_INFO_PART */
sahilmgandhi 18:6a4db94011d3 4167 /* Description: Part code */
sahilmgandhi 18:6a4db94011d3 4168
sahilmgandhi 18:6a4db94011d3 4169 /* Bits 31..0 : Part code */
sahilmgandhi 18:6a4db94011d3 4170 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
sahilmgandhi 18:6a4db94011d3 4171 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
sahilmgandhi 18:6a4db94011d3 4172 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
sahilmgandhi 18:6a4db94011d3 4173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 4174
sahilmgandhi 18:6a4db94011d3 4175 /* Register: FICR_INFO_VARIANT */
sahilmgandhi 18:6a4db94011d3 4176 /* Description: Part Variant, Hardware version and Production configuration */
sahilmgandhi 18:6a4db94011d3 4177
sahilmgandhi 18:6a4db94011d3 4178 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
sahilmgandhi 18:6a4db94011d3 4179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
sahilmgandhi 18:6a4db94011d3 4180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
sahilmgandhi 18:6a4db94011d3 4181 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
sahilmgandhi 18:6a4db94011d3 4182 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
sahilmgandhi 18:6a4db94011d3 4183 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
sahilmgandhi 18:6a4db94011d3 4184 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
sahilmgandhi 18:6a4db94011d3 4185 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 4186
sahilmgandhi 18:6a4db94011d3 4187 /* Register: FICR_INFO_PACKAGE */
sahilmgandhi 18:6a4db94011d3 4188 /* Description: Package option */
sahilmgandhi 18:6a4db94011d3 4189
sahilmgandhi 18:6a4db94011d3 4190 /* Bits 31..0 : Package option */
sahilmgandhi 18:6a4db94011d3 4191 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
sahilmgandhi 18:6a4db94011d3 4192 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
sahilmgandhi 18:6a4db94011d3 4193 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
sahilmgandhi 18:6a4db94011d3 4194 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
sahilmgandhi 18:6a4db94011d3 4195 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 4196
sahilmgandhi 18:6a4db94011d3 4197 /* Register: FICR_INFO_RAM */
sahilmgandhi 18:6a4db94011d3 4198 /* Description: RAM variant */
sahilmgandhi 18:6a4db94011d3 4199
sahilmgandhi 18:6a4db94011d3 4200 /* Bits 31..0 : RAM variant */
sahilmgandhi 18:6a4db94011d3 4201 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
sahilmgandhi 18:6a4db94011d3 4202 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
sahilmgandhi 18:6a4db94011d3 4203 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
sahilmgandhi 18:6a4db94011d3 4204 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
sahilmgandhi 18:6a4db94011d3 4205 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
sahilmgandhi 18:6a4db94011d3 4206 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 4207
sahilmgandhi 18:6a4db94011d3 4208 /* Register: FICR_INFO_FLASH */
sahilmgandhi 18:6a4db94011d3 4209 /* Description: Flash variant */
sahilmgandhi 18:6a4db94011d3 4210
sahilmgandhi 18:6a4db94011d3 4211 /* Bits 31..0 : Flash variant */
sahilmgandhi 18:6a4db94011d3 4212 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
sahilmgandhi 18:6a4db94011d3 4213 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
sahilmgandhi 18:6a4db94011d3 4214 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
sahilmgandhi 18:6a4db94011d3 4215 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
sahilmgandhi 18:6a4db94011d3 4216 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
sahilmgandhi 18:6a4db94011d3 4217 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 4218
sahilmgandhi 18:6a4db94011d3 4219 /* Register: FICR_TEMP_A0 */
sahilmgandhi 18:6a4db94011d3 4220 /* Description: Slope definition A0. */
sahilmgandhi 18:6a4db94011d3 4221
sahilmgandhi 18:6a4db94011d3 4222 /* Bits 11..0 : A (slope definition) register. */
sahilmgandhi 18:6a4db94011d3 4223 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
sahilmgandhi 18:6a4db94011d3 4224 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
sahilmgandhi 18:6a4db94011d3 4225
sahilmgandhi 18:6a4db94011d3 4226 /* Register: FICR_TEMP_A1 */
sahilmgandhi 18:6a4db94011d3 4227 /* Description: Slope definition A1. */
sahilmgandhi 18:6a4db94011d3 4228
sahilmgandhi 18:6a4db94011d3 4229 /* Bits 11..0 : A (slope definition) register. */
sahilmgandhi 18:6a4db94011d3 4230 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
sahilmgandhi 18:6a4db94011d3 4231 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
sahilmgandhi 18:6a4db94011d3 4232
sahilmgandhi 18:6a4db94011d3 4233 /* Register: FICR_TEMP_A2 */
sahilmgandhi 18:6a4db94011d3 4234 /* Description: Slope definition A2. */
sahilmgandhi 18:6a4db94011d3 4235
sahilmgandhi 18:6a4db94011d3 4236 /* Bits 11..0 : A (slope definition) register. */
sahilmgandhi 18:6a4db94011d3 4237 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
sahilmgandhi 18:6a4db94011d3 4238 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
sahilmgandhi 18:6a4db94011d3 4239
sahilmgandhi 18:6a4db94011d3 4240 /* Register: FICR_TEMP_A3 */
sahilmgandhi 18:6a4db94011d3 4241 /* Description: Slope definition A3. */
sahilmgandhi 18:6a4db94011d3 4242
sahilmgandhi 18:6a4db94011d3 4243 /* Bits 11..0 : A (slope definition) register. */
sahilmgandhi 18:6a4db94011d3 4244 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
sahilmgandhi 18:6a4db94011d3 4245 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
sahilmgandhi 18:6a4db94011d3 4246
sahilmgandhi 18:6a4db94011d3 4247 /* Register: FICR_TEMP_A4 */
sahilmgandhi 18:6a4db94011d3 4248 /* Description: Slope definition A4. */
sahilmgandhi 18:6a4db94011d3 4249
sahilmgandhi 18:6a4db94011d3 4250 /* Bits 11..0 : A (slope definition) register. */
sahilmgandhi 18:6a4db94011d3 4251 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
sahilmgandhi 18:6a4db94011d3 4252 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
sahilmgandhi 18:6a4db94011d3 4253
sahilmgandhi 18:6a4db94011d3 4254 /* Register: FICR_TEMP_A5 */
sahilmgandhi 18:6a4db94011d3 4255 /* Description: Slope definition A5. */
sahilmgandhi 18:6a4db94011d3 4256
sahilmgandhi 18:6a4db94011d3 4257 /* Bits 11..0 : A (slope definition) register. */
sahilmgandhi 18:6a4db94011d3 4258 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
sahilmgandhi 18:6a4db94011d3 4259 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
sahilmgandhi 18:6a4db94011d3 4260
sahilmgandhi 18:6a4db94011d3 4261 /* Register: FICR_TEMP_B0 */
sahilmgandhi 18:6a4db94011d3 4262 /* Description: y-intercept B0. */
sahilmgandhi 18:6a4db94011d3 4263
sahilmgandhi 18:6a4db94011d3 4264 /* Bits 13..0 : B (y-intercept) */
sahilmgandhi 18:6a4db94011d3 4265 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
sahilmgandhi 18:6a4db94011d3 4266 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
sahilmgandhi 18:6a4db94011d3 4267
sahilmgandhi 18:6a4db94011d3 4268 /* Register: FICR_TEMP_B1 */
sahilmgandhi 18:6a4db94011d3 4269 /* Description: y-intercept B1. */
sahilmgandhi 18:6a4db94011d3 4270
sahilmgandhi 18:6a4db94011d3 4271 /* Bits 13..0 : B (y-intercept) */
sahilmgandhi 18:6a4db94011d3 4272 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
sahilmgandhi 18:6a4db94011d3 4273 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
sahilmgandhi 18:6a4db94011d3 4274
sahilmgandhi 18:6a4db94011d3 4275 /* Register: FICR_TEMP_B2 */
sahilmgandhi 18:6a4db94011d3 4276 /* Description: y-intercept B2. */
sahilmgandhi 18:6a4db94011d3 4277
sahilmgandhi 18:6a4db94011d3 4278 /* Bits 13..0 : B (y-intercept) */
sahilmgandhi 18:6a4db94011d3 4279 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
sahilmgandhi 18:6a4db94011d3 4280 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
sahilmgandhi 18:6a4db94011d3 4281
sahilmgandhi 18:6a4db94011d3 4282 /* Register: FICR_TEMP_B3 */
sahilmgandhi 18:6a4db94011d3 4283 /* Description: y-intercept B3. */
sahilmgandhi 18:6a4db94011d3 4284
sahilmgandhi 18:6a4db94011d3 4285 /* Bits 13..0 : B (y-intercept) */
sahilmgandhi 18:6a4db94011d3 4286 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
sahilmgandhi 18:6a4db94011d3 4287 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
sahilmgandhi 18:6a4db94011d3 4288
sahilmgandhi 18:6a4db94011d3 4289 /* Register: FICR_TEMP_B4 */
sahilmgandhi 18:6a4db94011d3 4290 /* Description: y-intercept B4. */
sahilmgandhi 18:6a4db94011d3 4291
sahilmgandhi 18:6a4db94011d3 4292 /* Bits 13..0 : B (y-intercept) */
sahilmgandhi 18:6a4db94011d3 4293 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
sahilmgandhi 18:6a4db94011d3 4294 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
sahilmgandhi 18:6a4db94011d3 4295
sahilmgandhi 18:6a4db94011d3 4296 /* Register: FICR_TEMP_B5 */
sahilmgandhi 18:6a4db94011d3 4297 /* Description: y-intercept B5. */
sahilmgandhi 18:6a4db94011d3 4298
sahilmgandhi 18:6a4db94011d3 4299 /* Bits 13..0 : B (y-intercept) */
sahilmgandhi 18:6a4db94011d3 4300 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
sahilmgandhi 18:6a4db94011d3 4301 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
sahilmgandhi 18:6a4db94011d3 4302
sahilmgandhi 18:6a4db94011d3 4303 /* Register: FICR_TEMP_T0 */
sahilmgandhi 18:6a4db94011d3 4304 /* Description: Segment end T0. */
sahilmgandhi 18:6a4db94011d3 4305
sahilmgandhi 18:6a4db94011d3 4306 /* Bits 7..0 : T (segment end)register. */
sahilmgandhi 18:6a4db94011d3 4307 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
sahilmgandhi 18:6a4db94011d3 4308 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
sahilmgandhi 18:6a4db94011d3 4309
sahilmgandhi 18:6a4db94011d3 4310 /* Register: FICR_TEMP_T1 */
sahilmgandhi 18:6a4db94011d3 4311 /* Description: Segment end T1. */
sahilmgandhi 18:6a4db94011d3 4312
sahilmgandhi 18:6a4db94011d3 4313 /* Bits 7..0 : T (segment end)register. */
sahilmgandhi 18:6a4db94011d3 4314 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
sahilmgandhi 18:6a4db94011d3 4315 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
sahilmgandhi 18:6a4db94011d3 4316
sahilmgandhi 18:6a4db94011d3 4317 /* Register: FICR_TEMP_T2 */
sahilmgandhi 18:6a4db94011d3 4318 /* Description: Segment end T2. */
sahilmgandhi 18:6a4db94011d3 4319
sahilmgandhi 18:6a4db94011d3 4320 /* Bits 7..0 : T (segment end)register. */
sahilmgandhi 18:6a4db94011d3 4321 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
sahilmgandhi 18:6a4db94011d3 4322 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
sahilmgandhi 18:6a4db94011d3 4323
sahilmgandhi 18:6a4db94011d3 4324 /* Register: FICR_TEMP_T3 */
sahilmgandhi 18:6a4db94011d3 4325 /* Description: Segment end T3. */
sahilmgandhi 18:6a4db94011d3 4326
sahilmgandhi 18:6a4db94011d3 4327 /* Bits 7..0 : T (segment end)register. */
sahilmgandhi 18:6a4db94011d3 4328 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
sahilmgandhi 18:6a4db94011d3 4329 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
sahilmgandhi 18:6a4db94011d3 4330
sahilmgandhi 18:6a4db94011d3 4331 /* Register: FICR_TEMP_T4 */
sahilmgandhi 18:6a4db94011d3 4332 /* Description: Segment end T4. */
sahilmgandhi 18:6a4db94011d3 4333
sahilmgandhi 18:6a4db94011d3 4334 /* Bits 7..0 : T (segment end)register. */
sahilmgandhi 18:6a4db94011d3 4335 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
sahilmgandhi 18:6a4db94011d3 4336 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
sahilmgandhi 18:6a4db94011d3 4337
sahilmgandhi 18:6a4db94011d3 4338 /* Register: FICR_NFC_TAGHEADER0 */
sahilmgandhi 18:6a4db94011d3 4339 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 4340
sahilmgandhi 18:6a4db94011d3 4341 /* Bits 31..24 : Unique identifier byte 3 */
sahilmgandhi 18:6a4db94011d3 4342 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
sahilmgandhi 18:6a4db94011d3 4343 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
sahilmgandhi 18:6a4db94011d3 4344
sahilmgandhi 18:6a4db94011d3 4345 /* Bits 23..16 : Unique identifier byte 2 */
sahilmgandhi 18:6a4db94011d3 4346 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
sahilmgandhi 18:6a4db94011d3 4347 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
sahilmgandhi 18:6a4db94011d3 4348
sahilmgandhi 18:6a4db94011d3 4349 /* Bits 15..8 : Unique identifier byte 1 */
sahilmgandhi 18:6a4db94011d3 4350 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
sahilmgandhi 18:6a4db94011d3 4351 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
sahilmgandhi 18:6a4db94011d3 4352
sahilmgandhi 18:6a4db94011d3 4353 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
sahilmgandhi 18:6a4db94011d3 4354 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
sahilmgandhi 18:6a4db94011d3 4355 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
sahilmgandhi 18:6a4db94011d3 4356
sahilmgandhi 18:6a4db94011d3 4357 /* Register: FICR_NFC_TAGHEADER1 */
sahilmgandhi 18:6a4db94011d3 4358 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 4359
sahilmgandhi 18:6a4db94011d3 4360 /* Bits 31..24 : Unique identifier byte 7 */
sahilmgandhi 18:6a4db94011d3 4361 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
sahilmgandhi 18:6a4db94011d3 4362 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
sahilmgandhi 18:6a4db94011d3 4363
sahilmgandhi 18:6a4db94011d3 4364 /* Bits 23..16 : Unique identifier byte 6 */
sahilmgandhi 18:6a4db94011d3 4365 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
sahilmgandhi 18:6a4db94011d3 4366 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
sahilmgandhi 18:6a4db94011d3 4367
sahilmgandhi 18:6a4db94011d3 4368 /* Bits 15..8 : Unique identifier byte 5 */
sahilmgandhi 18:6a4db94011d3 4369 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
sahilmgandhi 18:6a4db94011d3 4370 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
sahilmgandhi 18:6a4db94011d3 4371
sahilmgandhi 18:6a4db94011d3 4372 /* Bits 7..0 : Unique identifier byte 4 */
sahilmgandhi 18:6a4db94011d3 4373 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
sahilmgandhi 18:6a4db94011d3 4374 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
sahilmgandhi 18:6a4db94011d3 4375
sahilmgandhi 18:6a4db94011d3 4376 /* Register: FICR_NFC_TAGHEADER2 */
sahilmgandhi 18:6a4db94011d3 4377 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 4378
sahilmgandhi 18:6a4db94011d3 4379 /* Bits 31..24 : Unique identifier byte 11 */
sahilmgandhi 18:6a4db94011d3 4380 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
sahilmgandhi 18:6a4db94011d3 4381 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
sahilmgandhi 18:6a4db94011d3 4382
sahilmgandhi 18:6a4db94011d3 4383 /* Bits 23..16 : Unique identifier byte 10 */
sahilmgandhi 18:6a4db94011d3 4384 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
sahilmgandhi 18:6a4db94011d3 4385 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
sahilmgandhi 18:6a4db94011d3 4386
sahilmgandhi 18:6a4db94011d3 4387 /* Bits 15..8 : Unique identifier byte 9 */
sahilmgandhi 18:6a4db94011d3 4388 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
sahilmgandhi 18:6a4db94011d3 4389 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
sahilmgandhi 18:6a4db94011d3 4390
sahilmgandhi 18:6a4db94011d3 4391 /* Bits 7..0 : Unique identifier byte 8 */
sahilmgandhi 18:6a4db94011d3 4392 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
sahilmgandhi 18:6a4db94011d3 4393 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
sahilmgandhi 18:6a4db94011d3 4394
sahilmgandhi 18:6a4db94011d3 4395 /* Register: FICR_NFC_TAGHEADER3 */
sahilmgandhi 18:6a4db94011d3 4396 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 4397
sahilmgandhi 18:6a4db94011d3 4398 /* Bits 31..24 : Unique identifier byte 15 */
sahilmgandhi 18:6a4db94011d3 4399 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
sahilmgandhi 18:6a4db94011d3 4400 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
sahilmgandhi 18:6a4db94011d3 4401
sahilmgandhi 18:6a4db94011d3 4402 /* Bits 23..16 : Unique identifier byte 14 */
sahilmgandhi 18:6a4db94011d3 4403 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
sahilmgandhi 18:6a4db94011d3 4404 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
sahilmgandhi 18:6a4db94011d3 4405
sahilmgandhi 18:6a4db94011d3 4406 /* Bits 15..8 : Unique identifier byte 13 */
sahilmgandhi 18:6a4db94011d3 4407 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
sahilmgandhi 18:6a4db94011d3 4408 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
sahilmgandhi 18:6a4db94011d3 4409
sahilmgandhi 18:6a4db94011d3 4410 /* Bits 7..0 : Unique identifier byte 12 */
sahilmgandhi 18:6a4db94011d3 4411 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
sahilmgandhi 18:6a4db94011d3 4412 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
sahilmgandhi 18:6a4db94011d3 4413
sahilmgandhi 18:6a4db94011d3 4414
sahilmgandhi 18:6a4db94011d3 4415 /* Peripheral: GPIOTE */
sahilmgandhi 18:6a4db94011d3 4416 /* Description: GPIO Tasks and Events */
sahilmgandhi 18:6a4db94011d3 4417
sahilmgandhi 18:6a4db94011d3 4418 /* Register: GPIOTE_INTENSET */
sahilmgandhi 18:6a4db94011d3 4419 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 4420
sahilmgandhi 18:6a4db94011d3 4421 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
sahilmgandhi 18:6a4db94011d3 4422 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
sahilmgandhi 18:6a4db94011d3 4423 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
sahilmgandhi 18:6a4db94011d3 4424 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4425 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4426 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4427
sahilmgandhi 18:6a4db94011d3 4428 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
sahilmgandhi 18:6a4db94011d3 4429 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
sahilmgandhi 18:6a4db94011d3 4430 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
sahilmgandhi 18:6a4db94011d3 4431 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4432 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4433 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4434
sahilmgandhi 18:6a4db94011d3 4435 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
sahilmgandhi 18:6a4db94011d3 4436 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
sahilmgandhi 18:6a4db94011d3 4437 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
sahilmgandhi 18:6a4db94011d3 4438 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4439 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4440 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4441
sahilmgandhi 18:6a4db94011d3 4442 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
sahilmgandhi 18:6a4db94011d3 4443 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
sahilmgandhi 18:6a4db94011d3 4444 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
sahilmgandhi 18:6a4db94011d3 4445 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4446 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4447 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4448
sahilmgandhi 18:6a4db94011d3 4449 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
sahilmgandhi 18:6a4db94011d3 4450 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
sahilmgandhi 18:6a4db94011d3 4451 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
sahilmgandhi 18:6a4db94011d3 4452 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4453 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4454 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4455
sahilmgandhi 18:6a4db94011d3 4456 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
sahilmgandhi 18:6a4db94011d3 4457 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
sahilmgandhi 18:6a4db94011d3 4458 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
sahilmgandhi 18:6a4db94011d3 4459 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4460 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4461 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4462
sahilmgandhi 18:6a4db94011d3 4463 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
sahilmgandhi 18:6a4db94011d3 4464 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
sahilmgandhi 18:6a4db94011d3 4465 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
sahilmgandhi 18:6a4db94011d3 4466 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4467 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4468 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4469
sahilmgandhi 18:6a4db94011d3 4470 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
sahilmgandhi 18:6a4db94011d3 4471 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
sahilmgandhi 18:6a4db94011d3 4472 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
sahilmgandhi 18:6a4db94011d3 4473 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4474 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4475 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4476
sahilmgandhi 18:6a4db94011d3 4477 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
sahilmgandhi 18:6a4db94011d3 4478 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
sahilmgandhi 18:6a4db94011d3 4479 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
sahilmgandhi 18:6a4db94011d3 4480 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4481 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4482 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4483
sahilmgandhi 18:6a4db94011d3 4484 /* Register: GPIOTE_INTENCLR */
sahilmgandhi 18:6a4db94011d3 4485 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 4486
sahilmgandhi 18:6a4db94011d3 4487 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
sahilmgandhi 18:6a4db94011d3 4488 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
sahilmgandhi 18:6a4db94011d3 4489 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
sahilmgandhi 18:6a4db94011d3 4490 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4491 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4492 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4493
sahilmgandhi 18:6a4db94011d3 4494 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
sahilmgandhi 18:6a4db94011d3 4495 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
sahilmgandhi 18:6a4db94011d3 4496 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
sahilmgandhi 18:6a4db94011d3 4497 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4498 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4499 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4500
sahilmgandhi 18:6a4db94011d3 4501 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
sahilmgandhi 18:6a4db94011d3 4502 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
sahilmgandhi 18:6a4db94011d3 4503 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
sahilmgandhi 18:6a4db94011d3 4504 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4505 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4506 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4507
sahilmgandhi 18:6a4db94011d3 4508 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
sahilmgandhi 18:6a4db94011d3 4509 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
sahilmgandhi 18:6a4db94011d3 4510 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
sahilmgandhi 18:6a4db94011d3 4511 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4512 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4513 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4514
sahilmgandhi 18:6a4db94011d3 4515 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
sahilmgandhi 18:6a4db94011d3 4516 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
sahilmgandhi 18:6a4db94011d3 4517 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
sahilmgandhi 18:6a4db94011d3 4518 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4519 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4520 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4521
sahilmgandhi 18:6a4db94011d3 4522 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
sahilmgandhi 18:6a4db94011d3 4523 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
sahilmgandhi 18:6a4db94011d3 4524 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
sahilmgandhi 18:6a4db94011d3 4525 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4526 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4527 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4528
sahilmgandhi 18:6a4db94011d3 4529 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
sahilmgandhi 18:6a4db94011d3 4530 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
sahilmgandhi 18:6a4db94011d3 4531 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
sahilmgandhi 18:6a4db94011d3 4532 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4533 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4534 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4535
sahilmgandhi 18:6a4db94011d3 4536 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
sahilmgandhi 18:6a4db94011d3 4537 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
sahilmgandhi 18:6a4db94011d3 4538 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
sahilmgandhi 18:6a4db94011d3 4539 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4540 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4541 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4542
sahilmgandhi 18:6a4db94011d3 4543 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
sahilmgandhi 18:6a4db94011d3 4544 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
sahilmgandhi 18:6a4db94011d3 4545 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
sahilmgandhi 18:6a4db94011d3 4546 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4547 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4548 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4549
sahilmgandhi 18:6a4db94011d3 4550 /* Register: GPIOTE_CONFIG */
sahilmgandhi 18:6a4db94011d3 4551 /* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
sahilmgandhi 18:6a4db94011d3 4552
sahilmgandhi 18:6a4db94011d3 4553 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
sahilmgandhi 18:6a4db94011d3 4554 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
sahilmgandhi 18:6a4db94011d3 4555 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
sahilmgandhi 18:6a4db94011d3 4556 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
sahilmgandhi 18:6a4db94011d3 4557 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
sahilmgandhi 18:6a4db94011d3 4558
sahilmgandhi 18:6a4db94011d3 4559 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
sahilmgandhi 18:6a4db94011d3 4560 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
sahilmgandhi 18:6a4db94011d3 4561 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
sahilmgandhi 18:6a4db94011d3 4562 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
sahilmgandhi 18:6a4db94011d3 4563 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
sahilmgandhi 18:6a4db94011d3 4564 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
sahilmgandhi 18:6a4db94011d3 4565 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
sahilmgandhi 18:6a4db94011d3 4566
sahilmgandhi 18:6a4db94011d3 4567 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
sahilmgandhi 18:6a4db94011d3 4568 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
sahilmgandhi 18:6a4db94011d3 4569 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
sahilmgandhi 18:6a4db94011d3 4570
sahilmgandhi 18:6a4db94011d3 4571 /* Bits 1..0 : Mode */
sahilmgandhi 18:6a4db94011d3 4572 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 4573 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 4574 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
sahilmgandhi 18:6a4db94011d3 4575 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
sahilmgandhi 18:6a4db94011d3 4576 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
sahilmgandhi 18:6a4db94011d3 4577
sahilmgandhi 18:6a4db94011d3 4578
sahilmgandhi 18:6a4db94011d3 4579 /* Peripheral: I2S */
sahilmgandhi 18:6a4db94011d3 4580 /* Description: Inter-IC Sound */
sahilmgandhi 18:6a4db94011d3 4581
sahilmgandhi 18:6a4db94011d3 4582 /* Register: I2S_INTEN */
sahilmgandhi 18:6a4db94011d3 4583 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 4584
sahilmgandhi 18:6a4db94011d3 4585 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
sahilmgandhi 18:6a4db94011d3 4586 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4587 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4588 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4589 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4590
sahilmgandhi 18:6a4db94011d3 4591 /* Bit 2 : Enable or disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 4592 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 4593 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 4594 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4595 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4596
sahilmgandhi 18:6a4db94011d3 4597 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
sahilmgandhi 18:6a4db94011d3 4598 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4599 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4600 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4601 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4602
sahilmgandhi 18:6a4db94011d3 4603 /* Register: I2S_INTENSET */
sahilmgandhi 18:6a4db94011d3 4604 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 4605
sahilmgandhi 18:6a4db94011d3 4606 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
sahilmgandhi 18:6a4db94011d3 4607 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4608 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4609 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4610 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4611 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4612
sahilmgandhi 18:6a4db94011d3 4613 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 4614 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 4615 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 4616 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4617 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4618 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4619
sahilmgandhi 18:6a4db94011d3 4620 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
sahilmgandhi 18:6a4db94011d3 4621 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4622 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4623 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4624 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4625 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4626
sahilmgandhi 18:6a4db94011d3 4627 /* Register: I2S_INTENCLR */
sahilmgandhi 18:6a4db94011d3 4628 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 4629
sahilmgandhi 18:6a4db94011d3 4630 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
sahilmgandhi 18:6a4db94011d3 4631 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4632 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4633 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4634 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4635 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4636
sahilmgandhi 18:6a4db94011d3 4637 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 4638 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 4639 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 4640 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4641 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4642 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4643
sahilmgandhi 18:6a4db94011d3 4644 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
sahilmgandhi 18:6a4db94011d3 4645 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4646 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
sahilmgandhi 18:6a4db94011d3 4647 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4648 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4649 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4650
sahilmgandhi 18:6a4db94011d3 4651 /* Register: I2S_ENABLE */
sahilmgandhi 18:6a4db94011d3 4652 /* Description: Enable I2S module. */
sahilmgandhi 18:6a4db94011d3 4653
sahilmgandhi 18:6a4db94011d3 4654 /* Bit 0 : Enable I2S module. */
sahilmgandhi 18:6a4db94011d3 4655 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 4656 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 4657 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4658 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4659
sahilmgandhi 18:6a4db94011d3 4660 /* Register: I2S_CONFIG_MODE */
sahilmgandhi 18:6a4db94011d3 4661 /* Description: I2S mode. */
sahilmgandhi 18:6a4db94011d3 4662
sahilmgandhi 18:6a4db94011d3 4663 /* Bit 0 : I2S mode. */
sahilmgandhi 18:6a4db94011d3 4664 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 4665 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 4666 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
sahilmgandhi 18:6a4db94011d3 4667 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
sahilmgandhi 18:6a4db94011d3 4668
sahilmgandhi 18:6a4db94011d3 4669 /* Register: I2S_CONFIG_RXEN */
sahilmgandhi 18:6a4db94011d3 4670 /* Description: Reception (RX) enable. */
sahilmgandhi 18:6a4db94011d3 4671
sahilmgandhi 18:6a4db94011d3 4672 /* Bit 0 : Reception (RX) enable. */
sahilmgandhi 18:6a4db94011d3 4673 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
sahilmgandhi 18:6a4db94011d3 4674 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
sahilmgandhi 18:6a4db94011d3 4675 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
sahilmgandhi 18:6a4db94011d3 4676 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 4677
sahilmgandhi 18:6a4db94011d3 4678 /* Register: I2S_CONFIG_TXEN */
sahilmgandhi 18:6a4db94011d3 4679 /* Description: Transmission (TX) enable. */
sahilmgandhi 18:6a4db94011d3 4680
sahilmgandhi 18:6a4db94011d3 4681 /* Bit 0 : Transmission (TX) enable. */
sahilmgandhi 18:6a4db94011d3 4682 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
sahilmgandhi 18:6a4db94011d3 4683 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
sahilmgandhi 18:6a4db94011d3 4684 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
sahilmgandhi 18:6a4db94011d3 4685 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
sahilmgandhi 18:6a4db94011d3 4686
sahilmgandhi 18:6a4db94011d3 4687 /* Register: I2S_CONFIG_MCKEN */
sahilmgandhi 18:6a4db94011d3 4688 /* Description: Master clock generator enable. */
sahilmgandhi 18:6a4db94011d3 4689
sahilmgandhi 18:6a4db94011d3 4690 /* Bit 0 : Master clock generator enable. */
sahilmgandhi 18:6a4db94011d3 4691 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
sahilmgandhi 18:6a4db94011d3 4692 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
sahilmgandhi 18:6a4db94011d3 4693 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
sahilmgandhi 18:6a4db94011d3 4694 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
sahilmgandhi 18:6a4db94011d3 4695
sahilmgandhi 18:6a4db94011d3 4696 /* Register: I2S_CONFIG_MCKFREQ */
sahilmgandhi 18:6a4db94011d3 4697 /* Description: Master clock generator frequency. */
sahilmgandhi 18:6a4db94011d3 4698
sahilmgandhi 18:6a4db94011d3 4699 /* Bits 31..0 : Master clock generator frequency. */
sahilmgandhi 18:6a4db94011d3 4700 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
sahilmgandhi 18:6a4db94011d3 4701 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
sahilmgandhi 18:6a4db94011d3 4702 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
sahilmgandhi 18:6a4db94011d3 4703 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
sahilmgandhi 18:6a4db94011d3 4704 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
sahilmgandhi 18:6a4db94011d3 4705 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
sahilmgandhi 18:6a4db94011d3 4706 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
sahilmgandhi 18:6a4db94011d3 4707 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
sahilmgandhi 18:6a4db94011d3 4708 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
sahilmgandhi 18:6a4db94011d3 4709 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
sahilmgandhi 18:6a4db94011d3 4710 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
sahilmgandhi 18:6a4db94011d3 4711 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
sahilmgandhi 18:6a4db94011d3 4712 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
sahilmgandhi 18:6a4db94011d3 4713 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
sahilmgandhi 18:6a4db94011d3 4714 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
sahilmgandhi 18:6a4db94011d3 4715 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
sahilmgandhi 18:6a4db94011d3 4716 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
sahilmgandhi 18:6a4db94011d3 4717 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
sahilmgandhi 18:6a4db94011d3 4718 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
sahilmgandhi 18:6a4db94011d3 4719 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
sahilmgandhi 18:6a4db94011d3 4720
sahilmgandhi 18:6a4db94011d3 4721 /* Register: I2S_CONFIG_RATIO */
sahilmgandhi 18:6a4db94011d3 4722 /* Description: MCK / LRCK ratio. */
sahilmgandhi 18:6a4db94011d3 4723
sahilmgandhi 18:6a4db94011d3 4724 /* Bits 3..0 : MCK / LRCK ratio. */
sahilmgandhi 18:6a4db94011d3 4725 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
sahilmgandhi 18:6a4db94011d3 4726 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
sahilmgandhi 18:6a4db94011d3 4727 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
sahilmgandhi 18:6a4db94011d3 4728 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
sahilmgandhi 18:6a4db94011d3 4729 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
sahilmgandhi 18:6a4db94011d3 4730 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
sahilmgandhi 18:6a4db94011d3 4731 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
sahilmgandhi 18:6a4db94011d3 4732 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
sahilmgandhi 18:6a4db94011d3 4733 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
sahilmgandhi 18:6a4db94011d3 4734 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
sahilmgandhi 18:6a4db94011d3 4735 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
sahilmgandhi 18:6a4db94011d3 4736
sahilmgandhi 18:6a4db94011d3 4737 /* Register: I2S_CONFIG_SWIDTH */
sahilmgandhi 18:6a4db94011d3 4738 /* Description: Sample width. */
sahilmgandhi 18:6a4db94011d3 4739
sahilmgandhi 18:6a4db94011d3 4740 /* Bits 1..0 : Sample width. */
sahilmgandhi 18:6a4db94011d3 4741 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
sahilmgandhi 18:6a4db94011d3 4742 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
sahilmgandhi 18:6a4db94011d3 4743 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
sahilmgandhi 18:6a4db94011d3 4744 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
sahilmgandhi 18:6a4db94011d3 4745 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
sahilmgandhi 18:6a4db94011d3 4746
sahilmgandhi 18:6a4db94011d3 4747 /* Register: I2S_CONFIG_ALIGN */
sahilmgandhi 18:6a4db94011d3 4748 /* Description: Alignment of sample within a frame. */
sahilmgandhi 18:6a4db94011d3 4749
sahilmgandhi 18:6a4db94011d3 4750 /* Bit 0 : Alignment of sample within a frame. */
sahilmgandhi 18:6a4db94011d3 4751 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
sahilmgandhi 18:6a4db94011d3 4752 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
sahilmgandhi 18:6a4db94011d3 4753 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
sahilmgandhi 18:6a4db94011d3 4754 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
sahilmgandhi 18:6a4db94011d3 4755
sahilmgandhi 18:6a4db94011d3 4756 /* Register: I2S_CONFIG_FORMAT */
sahilmgandhi 18:6a4db94011d3 4757 /* Description: Frame format. */
sahilmgandhi 18:6a4db94011d3 4758
sahilmgandhi 18:6a4db94011d3 4759 /* Bit 0 : Frame format. */
sahilmgandhi 18:6a4db94011d3 4760 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
sahilmgandhi 18:6a4db94011d3 4761 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
sahilmgandhi 18:6a4db94011d3 4762 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
sahilmgandhi 18:6a4db94011d3 4763 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
sahilmgandhi 18:6a4db94011d3 4764
sahilmgandhi 18:6a4db94011d3 4765 /* Register: I2S_CONFIG_CHANNELS */
sahilmgandhi 18:6a4db94011d3 4766 /* Description: Enable channels. */
sahilmgandhi 18:6a4db94011d3 4767
sahilmgandhi 18:6a4db94011d3 4768 /* Bits 1..0 : Enable channels. */
sahilmgandhi 18:6a4db94011d3 4769 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
sahilmgandhi 18:6a4db94011d3 4770 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
sahilmgandhi 18:6a4db94011d3 4771 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
sahilmgandhi 18:6a4db94011d3 4772 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
sahilmgandhi 18:6a4db94011d3 4773 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
sahilmgandhi 18:6a4db94011d3 4774
sahilmgandhi 18:6a4db94011d3 4775 /* Register: I2S_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 4776 /* Description: Receive buffer RAM start address. */
sahilmgandhi 18:6a4db94011d3 4777
sahilmgandhi 18:6a4db94011d3 4778 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
sahilmgandhi 18:6a4db94011d3 4779 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 4780 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 4781
sahilmgandhi 18:6a4db94011d3 4782 /* Register: I2S_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 4783 /* Description: Transmit buffer RAM start address. */
sahilmgandhi 18:6a4db94011d3 4784
sahilmgandhi 18:6a4db94011d3 4785 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
sahilmgandhi 18:6a4db94011d3 4786 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 4787 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 4788
sahilmgandhi 18:6a4db94011d3 4789 /* Register: I2S_RXTXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 4790 /* Description: Size of RXD and TXD buffers. */
sahilmgandhi 18:6a4db94011d3 4791
sahilmgandhi 18:6a4db94011d3 4792 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
sahilmgandhi 18:6a4db94011d3 4793 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 4794 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 4795
sahilmgandhi 18:6a4db94011d3 4796 /* Register: I2S_PSEL_MCK */
sahilmgandhi 18:6a4db94011d3 4797 /* Description: Pin select for MCK signal. */
sahilmgandhi 18:6a4db94011d3 4798
sahilmgandhi 18:6a4db94011d3 4799 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 4800 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4801 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4802 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 4803 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 4804
sahilmgandhi 18:6a4db94011d3 4805 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 4806 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 4807 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 4808
sahilmgandhi 18:6a4db94011d3 4809 /* Register: I2S_PSEL_SCK */
sahilmgandhi 18:6a4db94011d3 4810 /* Description: Pin select for SCK signal. */
sahilmgandhi 18:6a4db94011d3 4811
sahilmgandhi 18:6a4db94011d3 4812 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 4813 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4814 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4815 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 4816 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 4817
sahilmgandhi 18:6a4db94011d3 4818 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 4819 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 4820 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 4821
sahilmgandhi 18:6a4db94011d3 4822 /* Register: I2S_PSEL_LRCK */
sahilmgandhi 18:6a4db94011d3 4823 /* Description: Pin select for LRCK signal. */
sahilmgandhi 18:6a4db94011d3 4824
sahilmgandhi 18:6a4db94011d3 4825 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 4826 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4827 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4828 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 4829 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 4830
sahilmgandhi 18:6a4db94011d3 4831 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 4832 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 4833 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 4834
sahilmgandhi 18:6a4db94011d3 4835 /* Register: I2S_PSEL_SDIN */
sahilmgandhi 18:6a4db94011d3 4836 /* Description: Pin select for SDIN signal. */
sahilmgandhi 18:6a4db94011d3 4837
sahilmgandhi 18:6a4db94011d3 4838 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 4839 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4840 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4841 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 4842 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 4843
sahilmgandhi 18:6a4db94011d3 4844 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 4845 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 4846 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 4847
sahilmgandhi 18:6a4db94011d3 4848 /* Register: I2S_PSEL_SDOUT */
sahilmgandhi 18:6a4db94011d3 4849 /* Description: Pin select for SDOUT signal. */
sahilmgandhi 18:6a4db94011d3 4850
sahilmgandhi 18:6a4db94011d3 4851 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 4852 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4853 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 4854 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 4855 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 4856
sahilmgandhi 18:6a4db94011d3 4857 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 4858 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 4859 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 4860
sahilmgandhi 18:6a4db94011d3 4861
sahilmgandhi 18:6a4db94011d3 4862 /* Peripheral: LPCOMP */
sahilmgandhi 18:6a4db94011d3 4863 /* Description: Low Power Comparator */
sahilmgandhi 18:6a4db94011d3 4864
sahilmgandhi 18:6a4db94011d3 4865 /* Register: LPCOMP_SHORTS */
sahilmgandhi 18:6a4db94011d3 4866 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 4867
sahilmgandhi 18:6a4db94011d3 4868 /* Bit 4 : Shortcut between CROSS event and STOP task */
sahilmgandhi 18:6a4db94011d3 4869 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
sahilmgandhi 18:6a4db94011d3 4870 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
sahilmgandhi 18:6a4db94011d3 4871 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 4872 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 4873
sahilmgandhi 18:6a4db94011d3 4874 /* Bit 3 : Shortcut between UP event and STOP task */
sahilmgandhi 18:6a4db94011d3 4875 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
sahilmgandhi 18:6a4db94011d3 4876 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
sahilmgandhi 18:6a4db94011d3 4877 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 4878 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 4879
sahilmgandhi 18:6a4db94011d3 4880 /* Bit 2 : Shortcut between DOWN event and STOP task */
sahilmgandhi 18:6a4db94011d3 4881 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
sahilmgandhi 18:6a4db94011d3 4882 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
sahilmgandhi 18:6a4db94011d3 4883 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 4884 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 4885
sahilmgandhi 18:6a4db94011d3 4886 /* Bit 1 : Shortcut between READY event and STOP task */
sahilmgandhi 18:6a4db94011d3 4887 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
sahilmgandhi 18:6a4db94011d3 4888 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
sahilmgandhi 18:6a4db94011d3 4889 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 4890 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 4891
sahilmgandhi 18:6a4db94011d3 4892 /* Bit 0 : Shortcut between READY event and SAMPLE task */
sahilmgandhi 18:6a4db94011d3 4893 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 4894 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 4895 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 4896 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 4897
sahilmgandhi 18:6a4db94011d3 4898 /* Register: LPCOMP_INTENSET */
sahilmgandhi 18:6a4db94011d3 4899 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 4900
sahilmgandhi 18:6a4db94011d3 4901 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
sahilmgandhi 18:6a4db94011d3 4902 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 4903 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 4904 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4905 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4906 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4907
sahilmgandhi 18:6a4db94011d3 4908 /* Bit 2 : Write '1' to Enable interrupt for UP event */
sahilmgandhi 18:6a4db94011d3 4909 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 4910 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 4911 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4912 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4913 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4914
sahilmgandhi 18:6a4db94011d3 4915 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
sahilmgandhi 18:6a4db94011d3 4916 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 4917 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 4918 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4919 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4920 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4921
sahilmgandhi 18:6a4db94011d3 4922 /* Bit 0 : Write '1' to Enable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 4923 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 4924 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 4925 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4926 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4927 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4928
sahilmgandhi 18:6a4db94011d3 4929 /* Register: LPCOMP_INTENCLR */
sahilmgandhi 18:6a4db94011d3 4930 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 4931
sahilmgandhi 18:6a4db94011d3 4932 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
sahilmgandhi 18:6a4db94011d3 4933 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 4934 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 4935 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4936 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4937 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4938
sahilmgandhi 18:6a4db94011d3 4939 /* Bit 2 : Write '1' to Disable interrupt for UP event */
sahilmgandhi 18:6a4db94011d3 4940 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 4941 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 4942 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4943 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4944 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4945
sahilmgandhi 18:6a4db94011d3 4946 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
sahilmgandhi 18:6a4db94011d3 4947 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 4948 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 4949 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4950 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4951 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4952
sahilmgandhi 18:6a4db94011d3 4953 /* Bit 0 : Write '1' to Disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 4954 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 4955 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 4956 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 4957 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 4958 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4959
sahilmgandhi 18:6a4db94011d3 4960 /* Register: LPCOMP_RESULT */
sahilmgandhi 18:6a4db94011d3 4961 /* Description: Compare result */
sahilmgandhi 18:6a4db94011d3 4962
sahilmgandhi 18:6a4db94011d3 4963 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
sahilmgandhi 18:6a4db94011d3 4964 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
sahilmgandhi 18:6a4db94011d3 4965 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
sahilmgandhi 18:6a4db94011d3 4966 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
sahilmgandhi 18:6a4db94011d3 4967 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
sahilmgandhi 18:6a4db94011d3 4968
sahilmgandhi 18:6a4db94011d3 4969 /* Register: LPCOMP_ENABLE */
sahilmgandhi 18:6a4db94011d3 4970 /* Description: Enable LPCOMP */
sahilmgandhi 18:6a4db94011d3 4971
sahilmgandhi 18:6a4db94011d3 4972 /* Bits 1..0 : Enable or disable LPCOMP */
sahilmgandhi 18:6a4db94011d3 4973 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 4974 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 4975 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 4976 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 4977
sahilmgandhi 18:6a4db94011d3 4978 /* Register: LPCOMP_PSEL */
sahilmgandhi 18:6a4db94011d3 4979 /* Description: Input pin select */
sahilmgandhi 18:6a4db94011d3 4980
sahilmgandhi 18:6a4db94011d3 4981 /* Bits 2..0 : Analog pin select */
sahilmgandhi 18:6a4db94011d3 4982 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
sahilmgandhi 18:6a4db94011d3 4983 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
sahilmgandhi 18:6a4db94011d3 4984 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4985 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4986 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4987 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4988 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4989 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4990 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4991 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
sahilmgandhi 18:6a4db94011d3 4992
sahilmgandhi 18:6a4db94011d3 4993 /* Register: LPCOMP_REFSEL */
sahilmgandhi 18:6a4db94011d3 4994 /* Description: Reference select */
sahilmgandhi 18:6a4db94011d3 4995
sahilmgandhi 18:6a4db94011d3 4996 /* Bits 3..0 : Reference select */
sahilmgandhi 18:6a4db94011d3 4997 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 4998 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 4999 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5000 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5001 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5002 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5003 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5004 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5005 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
sahilmgandhi 18:6a4db94011d3 5006 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
sahilmgandhi 18:6a4db94011d3 5007 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5008 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5009 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5010 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5011 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5012 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5013 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5014 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
sahilmgandhi 18:6a4db94011d3 5015
sahilmgandhi 18:6a4db94011d3 5016 /* Register: LPCOMP_EXTREFSEL */
sahilmgandhi 18:6a4db94011d3 5017 /* Description: External reference select */
sahilmgandhi 18:6a4db94011d3 5018
sahilmgandhi 18:6a4db94011d3 5019 /* Bit 0 : External analog reference select */
sahilmgandhi 18:6a4db94011d3 5020 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 5021 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 5022 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
sahilmgandhi 18:6a4db94011d3 5023 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
sahilmgandhi 18:6a4db94011d3 5024
sahilmgandhi 18:6a4db94011d3 5025 /* Register: LPCOMP_ANADETECT */
sahilmgandhi 18:6a4db94011d3 5026 /* Description: Analog detect configuration */
sahilmgandhi 18:6a4db94011d3 5027
sahilmgandhi 18:6a4db94011d3 5028 /* Bits 1..0 : Analog detect configuration */
sahilmgandhi 18:6a4db94011d3 5029 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
sahilmgandhi 18:6a4db94011d3 5030 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
sahilmgandhi 18:6a4db94011d3 5031 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
sahilmgandhi 18:6a4db94011d3 5032 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
sahilmgandhi 18:6a4db94011d3 5033 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
sahilmgandhi 18:6a4db94011d3 5034
sahilmgandhi 18:6a4db94011d3 5035 /* Register: LPCOMP_HYST */
sahilmgandhi 18:6a4db94011d3 5036 /* Description: Comparator hysteresis enable */
sahilmgandhi 18:6a4db94011d3 5037
sahilmgandhi 18:6a4db94011d3 5038 /* Bit 0 : Comparator hysteresis enable */
sahilmgandhi 18:6a4db94011d3 5039 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
sahilmgandhi 18:6a4db94011d3 5040 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
sahilmgandhi 18:6a4db94011d3 5041 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
sahilmgandhi 18:6a4db94011d3 5042 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
sahilmgandhi 18:6a4db94011d3 5043
sahilmgandhi 18:6a4db94011d3 5044
sahilmgandhi 18:6a4db94011d3 5045 /* Peripheral: MWU */
sahilmgandhi 18:6a4db94011d3 5046 /* Description: Memory Watch Unit */
sahilmgandhi 18:6a4db94011d3 5047
sahilmgandhi 18:6a4db94011d3 5048 /* Register: MWU_INTEN */
sahilmgandhi 18:6a4db94011d3 5049 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 5050
sahilmgandhi 18:6a4db94011d3 5051 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5052 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5053 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5054 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5055 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5056
sahilmgandhi 18:6a4db94011d3 5057 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5058 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5059 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5060 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5061 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5062
sahilmgandhi 18:6a4db94011d3 5063 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5064 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5065 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5066 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5067 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5068
sahilmgandhi 18:6a4db94011d3 5069 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5070 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5071 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5072 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5073 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5074
sahilmgandhi 18:6a4db94011d3 5075 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
sahilmgandhi 18:6a4db94011d3 5076 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5077 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5078 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5079 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5080
sahilmgandhi 18:6a4db94011d3 5081 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
sahilmgandhi 18:6a4db94011d3 5082 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5083 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5084 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5085 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5086
sahilmgandhi 18:6a4db94011d3 5087 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
sahilmgandhi 18:6a4db94011d3 5088 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5089 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5090 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5091 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5092
sahilmgandhi 18:6a4db94011d3 5093 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
sahilmgandhi 18:6a4db94011d3 5094 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5095 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5096 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5097 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5098
sahilmgandhi 18:6a4db94011d3 5099 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5100 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5101 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5102 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5103 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5104
sahilmgandhi 18:6a4db94011d3 5105 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5106 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5107 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5108 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5109 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5110
sahilmgandhi 18:6a4db94011d3 5111 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5112 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5113 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5114 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5115 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5116
sahilmgandhi 18:6a4db94011d3 5117 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5118 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5119 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5120 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5121 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5122
sahilmgandhi 18:6a4db94011d3 5123 /* Register: MWU_INTENSET */
sahilmgandhi 18:6a4db94011d3 5124 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 5125
sahilmgandhi 18:6a4db94011d3 5126 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5127 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5128 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5129 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5130 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5131 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5132
sahilmgandhi 18:6a4db94011d3 5133 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5134 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5135 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5136 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5137 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5138 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5139
sahilmgandhi 18:6a4db94011d3 5140 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5141 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5142 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5143 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5144 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5145 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5146
sahilmgandhi 18:6a4db94011d3 5147 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5148 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5149 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5150 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5151 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5152 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5153
sahilmgandhi 18:6a4db94011d3 5154 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
sahilmgandhi 18:6a4db94011d3 5155 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5156 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5157 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5158 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5159 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5160
sahilmgandhi 18:6a4db94011d3 5161 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
sahilmgandhi 18:6a4db94011d3 5162 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5163 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5164 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5165 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5166 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5167
sahilmgandhi 18:6a4db94011d3 5168 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
sahilmgandhi 18:6a4db94011d3 5169 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5170 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5171 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5172 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5173 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5174
sahilmgandhi 18:6a4db94011d3 5175 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
sahilmgandhi 18:6a4db94011d3 5176 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5177 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5178 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5179 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5180 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5181
sahilmgandhi 18:6a4db94011d3 5182 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5183 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5184 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5185 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5186 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5187 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5188
sahilmgandhi 18:6a4db94011d3 5189 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5190 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5191 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5192 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5193 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5194 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5195
sahilmgandhi 18:6a4db94011d3 5196 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5197 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5198 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5199 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5200 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5201 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5202
sahilmgandhi 18:6a4db94011d3 5203 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5204 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5205 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5206 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5207 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5208 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5209
sahilmgandhi 18:6a4db94011d3 5210 /* Register: MWU_INTENCLR */
sahilmgandhi 18:6a4db94011d3 5211 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 5212
sahilmgandhi 18:6a4db94011d3 5213 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5214 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5215 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5216 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5217 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5218 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5219
sahilmgandhi 18:6a4db94011d3 5220 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5221 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5222 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5223 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5224 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5225 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5226
sahilmgandhi 18:6a4db94011d3 5227 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5228 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5229 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5230 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5231 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5232 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5233
sahilmgandhi 18:6a4db94011d3 5234 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5235 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5236 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5237 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5238 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5239 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5240
sahilmgandhi 18:6a4db94011d3 5241 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
sahilmgandhi 18:6a4db94011d3 5242 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5243 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5244 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5245 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5246 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5247
sahilmgandhi 18:6a4db94011d3 5248 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
sahilmgandhi 18:6a4db94011d3 5249 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5250 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5251 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5252 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5253 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5254
sahilmgandhi 18:6a4db94011d3 5255 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
sahilmgandhi 18:6a4db94011d3 5256 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5257 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5258 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5259 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5260 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5261
sahilmgandhi 18:6a4db94011d3 5262 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
sahilmgandhi 18:6a4db94011d3 5263 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5264 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5265 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5266 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5267 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5268
sahilmgandhi 18:6a4db94011d3 5269 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5270 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5271 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5272 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5273 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5274 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5275
sahilmgandhi 18:6a4db94011d3 5276 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5277 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5278 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5279 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5280 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5281 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5282
sahilmgandhi 18:6a4db94011d3 5283 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5284 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5285 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5286 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5287 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5288 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5289
sahilmgandhi 18:6a4db94011d3 5290 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5291 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5292 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5293 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5294 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5295 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5296
sahilmgandhi 18:6a4db94011d3 5297 /* Register: MWU_NMIEN */
sahilmgandhi 18:6a4db94011d3 5298 /* Description: Enable or disable non-maskable interrupt */
sahilmgandhi 18:6a4db94011d3 5299
sahilmgandhi 18:6a4db94011d3 5300 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5301 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5302 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5303 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5304 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5305
sahilmgandhi 18:6a4db94011d3 5306 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5307 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5308 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5309 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5310 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5311
sahilmgandhi 18:6a4db94011d3 5312 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5313 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5314 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5315 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5316 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5317
sahilmgandhi 18:6a4db94011d3 5318 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5319 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5320 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5321 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5322 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5323
sahilmgandhi 18:6a4db94011d3 5324 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
sahilmgandhi 18:6a4db94011d3 5325 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5326 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5327 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5328 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5329
sahilmgandhi 18:6a4db94011d3 5330 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
sahilmgandhi 18:6a4db94011d3 5331 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5332 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5333 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5334 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5335
sahilmgandhi 18:6a4db94011d3 5336 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
sahilmgandhi 18:6a4db94011d3 5337 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5338 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5339 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5340 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5341
sahilmgandhi 18:6a4db94011d3 5342 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
sahilmgandhi 18:6a4db94011d3 5343 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5344 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5345 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5346 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5347
sahilmgandhi 18:6a4db94011d3 5348 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5349 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5350 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5351 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5352 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5353
sahilmgandhi 18:6a4db94011d3 5354 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5355 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5356 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5357 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5358 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5359
sahilmgandhi 18:6a4db94011d3 5360 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5361 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5362 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5363 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5364 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5365
sahilmgandhi 18:6a4db94011d3 5366 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5367 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5368 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5369 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5370 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5371
sahilmgandhi 18:6a4db94011d3 5372 /* Register: MWU_NMIENSET */
sahilmgandhi 18:6a4db94011d3 5373 /* Description: Enable non-maskable interrupt */
sahilmgandhi 18:6a4db94011d3 5374
sahilmgandhi 18:6a4db94011d3 5375 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5376 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5377 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5378 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5379 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5380 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5381
sahilmgandhi 18:6a4db94011d3 5382 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5383 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5384 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5385 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5386 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5387 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5388
sahilmgandhi 18:6a4db94011d3 5389 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5390 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5391 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5392 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5393 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5394 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5395
sahilmgandhi 18:6a4db94011d3 5396 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5397 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5398 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5399 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5400 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5401 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5402
sahilmgandhi 18:6a4db94011d3 5403 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
sahilmgandhi 18:6a4db94011d3 5404 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5405 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5406 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5407 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5408 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5409
sahilmgandhi 18:6a4db94011d3 5410 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
sahilmgandhi 18:6a4db94011d3 5411 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5412 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5413 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5414 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5415 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5416
sahilmgandhi 18:6a4db94011d3 5417 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
sahilmgandhi 18:6a4db94011d3 5418 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5419 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5420 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5421 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5422 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5423
sahilmgandhi 18:6a4db94011d3 5424 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
sahilmgandhi 18:6a4db94011d3 5425 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5426 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5427 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5428 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5429 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5430
sahilmgandhi 18:6a4db94011d3 5431 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5432 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5433 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5434 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5435 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5436 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5437
sahilmgandhi 18:6a4db94011d3 5438 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5439 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5440 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5441 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5442 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5443 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5444
sahilmgandhi 18:6a4db94011d3 5445 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5446 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5447 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5448 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5449 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5450 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5451
sahilmgandhi 18:6a4db94011d3 5452 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5453 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5454 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5455 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5456 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5457 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 5458
sahilmgandhi 18:6a4db94011d3 5459 /* Register: MWU_NMIENCLR */
sahilmgandhi 18:6a4db94011d3 5460 /* Description: Disable non-maskable interrupt */
sahilmgandhi 18:6a4db94011d3 5461
sahilmgandhi 18:6a4db94011d3 5462 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5463 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5464 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5465 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5466 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5467 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5468
sahilmgandhi 18:6a4db94011d3 5469 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5470 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5471 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5472 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5473 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5474 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5475
sahilmgandhi 18:6a4db94011d3 5476 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5477 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5478 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5479 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5480 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5481 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5482
sahilmgandhi 18:6a4db94011d3 5483 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5484 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5485 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5486 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5487 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5488 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5489
sahilmgandhi 18:6a4db94011d3 5490 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
sahilmgandhi 18:6a4db94011d3 5491 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5492 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
sahilmgandhi 18:6a4db94011d3 5493 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5494 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5495 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5496
sahilmgandhi 18:6a4db94011d3 5497 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
sahilmgandhi 18:6a4db94011d3 5498 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5499 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
sahilmgandhi 18:6a4db94011d3 5500 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5501 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5502 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5503
sahilmgandhi 18:6a4db94011d3 5504 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
sahilmgandhi 18:6a4db94011d3 5505 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5506 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
sahilmgandhi 18:6a4db94011d3 5507 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5508 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5509 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5510
sahilmgandhi 18:6a4db94011d3 5511 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
sahilmgandhi 18:6a4db94011d3 5512 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5513 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
sahilmgandhi 18:6a4db94011d3 5514 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5515 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5516 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5517
sahilmgandhi 18:6a4db94011d3 5518 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
sahilmgandhi 18:6a4db94011d3 5519 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5520 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
sahilmgandhi 18:6a4db94011d3 5521 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5522 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5523 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5524
sahilmgandhi 18:6a4db94011d3 5525 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
sahilmgandhi 18:6a4db94011d3 5526 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5527 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
sahilmgandhi 18:6a4db94011d3 5528 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5529 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5530 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5531
sahilmgandhi 18:6a4db94011d3 5532 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
sahilmgandhi 18:6a4db94011d3 5533 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5534 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
sahilmgandhi 18:6a4db94011d3 5535 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5536 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5537 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5538
sahilmgandhi 18:6a4db94011d3 5539 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
sahilmgandhi 18:6a4db94011d3 5540 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5541 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
sahilmgandhi 18:6a4db94011d3 5542 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 5543 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 5544 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 5545
sahilmgandhi 18:6a4db94011d3 5546 /* Register: MWU_PERREGION_SUBSTATWA */
sahilmgandhi 18:6a4db94011d3 5547 /* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
sahilmgandhi 18:6a4db94011d3 5548
sahilmgandhi 18:6a4db94011d3 5549 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5550 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
sahilmgandhi 18:6a4db94011d3 5551 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
sahilmgandhi 18:6a4db94011d3 5552 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5553 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5554
sahilmgandhi 18:6a4db94011d3 5555 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5556 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
sahilmgandhi 18:6a4db94011d3 5557 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
sahilmgandhi 18:6a4db94011d3 5558 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5559 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5560
sahilmgandhi 18:6a4db94011d3 5561 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5562 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
sahilmgandhi 18:6a4db94011d3 5563 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
sahilmgandhi 18:6a4db94011d3 5564 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5565 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5566
sahilmgandhi 18:6a4db94011d3 5567 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5568 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
sahilmgandhi 18:6a4db94011d3 5569 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
sahilmgandhi 18:6a4db94011d3 5570 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5571 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5572
sahilmgandhi 18:6a4db94011d3 5573 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5574 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
sahilmgandhi 18:6a4db94011d3 5575 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
sahilmgandhi 18:6a4db94011d3 5576 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5577 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5578
sahilmgandhi 18:6a4db94011d3 5579 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5580 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
sahilmgandhi 18:6a4db94011d3 5581 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
sahilmgandhi 18:6a4db94011d3 5582 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5583 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5584
sahilmgandhi 18:6a4db94011d3 5585 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5586 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
sahilmgandhi 18:6a4db94011d3 5587 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
sahilmgandhi 18:6a4db94011d3 5588 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5589 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5590
sahilmgandhi 18:6a4db94011d3 5591 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5592 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
sahilmgandhi 18:6a4db94011d3 5593 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
sahilmgandhi 18:6a4db94011d3 5594 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5595 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5596
sahilmgandhi 18:6a4db94011d3 5597 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5598 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
sahilmgandhi 18:6a4db94011d3 5599 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
sahilmgandhi 18:6a4db94011d3 5600 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5601 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5602
sahilmgandhi 18:6a4db94011d3 5603 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5604 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
sahilmgandhi 18:6a4db94011d3 5605 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
sahilmgandhi 18:6a4db94011d3 5606 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5607 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5608
sahilmgandhi 18:6a4db94011d3 5609 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5610 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
sahilmgandhi 18:6a4db94011d3 5611 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
sahilmgandhi 18:6a4db94011d3 5612 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5613 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5614
sahilmgandhi 18:6a4db94011d3 5615 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5616 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
sahilmgandhi 18:6a4db94011d3 5617 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
sahilmgandhi 18:6a4db94011d3 5618 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5619 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5620
sahilmgandhi 18:6a4db94011d3 5621 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5622 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
sahilmgandhi 18:6a4db94011d3 5623 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
sahilmgandhi 18:6a4db94011d3 5624 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5625 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5626
sahilmgandhi 18:6a4db94011d3 5627 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5628 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
sahilmgandhi 18:6a4db94011d3 5629 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
sahilmgandhi 18:6a4db94011d3 5630 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5631 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5632
sahilmgandhi 18:6a4db94011d3 5633 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5634 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
sahilmgandhi 18:6a4db94011d3 5635 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
sahilmgandhi 18:6a4db94011d3 5636 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5637 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5638
sahilmgandhi 18:6a4db94011d3 5639 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5640 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
sahilmgandhi 18:6a4db94011d3 5641 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
sahilmgandhi 18:6a4db94011d3 5642 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5643 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5644
sahilmgandhi 18:6a4db94011d3 5645 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5646 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
sahilmgandhi 18:6a4db94011d3 5647 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
sahilmgandhi 18:6a4db94011d3 5648 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5649 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5650
sahilmgandhi 18:6a4db94011d3 5651 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5652 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
sahilmgandhi 18:6a4db94011d3 5653 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
sahilmgandhi 18:6a4db94011d3 5654 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5655 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5656
sahilmgandhi 18:6a4db94011d3 5657 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5658 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
sahilmgandhi 18:6a4db94011d3 5659 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
sahilmgandhi 18:6a4db94011d3 5660 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5661 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5662
sahilmgandhi 18:6a4db94011d3 5663 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5664 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
sahilmgandhi 18:6a4db94011d3 5665 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
sahilmgandhi 18:6a4db94011d3 5666 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5667 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5668
sahilmgandhi 18:6a4db94011d3 5669 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5670 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
sahilmgandhi 18:6a4db94011d3 5671 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
sahilmgandhi 18:6a4db94011d3 5672 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5673 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5674
sahilmgandhi 18:6a4db94011d3 5675 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5676 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
sahilmgandhi 18:6a4db94011d3 5677 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
sahilmgandhi 18:6a4db94011d3 5678 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5679 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5680
sahilmgandhi 18:6a4db94011d3 5681 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5682 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
sahilmgandhi 18:6a4db94011d3 5683 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
sahilmgandhi 18:6a4db94011d3 5684 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5685 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5686
sahilmgandhi 18:6a4db94011d3 5687 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5688 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
sahilmgandhi 18:6a4db94011d3 5689 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
sahilmgandhi 18:6a4db94011d3 5690 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5691 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5692
sahilmgandhi 18:6a4db94011d3 5693 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5694 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
sahilmgandhi 18:6a4db94011d3 5695 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
sahilmgandhi 18:6a4db94011d3 5696 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5697 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5698
sahilmgandhi 18:6a4db94011d3 5699 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5700 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
sahilmgandhi 18:6a4db94011d3 5701 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
sahilmgandhi 18:6a4db94011d3 5702 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5703 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5704
sahilmgandhi 18:6a4db94011d3 5705 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5706 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
sahilmgandhi 18:6a4db94011d3 5707 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
sahilmgandhi 18:6a4db94011d3 5708 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5709 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5710
sahilmgandhi 18:6a4db94011d3 5711 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5712 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
sahilmgandhi 18:6a4db94011d3 5713 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
sahilmgandhi 18:6a4db94011d3 5714 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5715 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5716
sahilmgandhi 18:6a4db94011d3 5717 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5718 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
sahilmgandhi 18:6a4db94011d3 5719 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
sahilmgandhi 18:6a4db94011d3 5720 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5721 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5722
sahilmgandhi 18:6a4db94011d3 5723 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5724 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
sahilmgandhi 18:6a4db94011d3 5725 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
sahilmgandhi 18:6a4db94011d3 5726 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5727 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5728
sahilmgandhi 18:6a4db94011d3 5729 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5730 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
sahilmgandhi 18:6a4db94011d3 5731 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
sahilmgandhi 18:6a4db94011d3 5732 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5733 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5734
sahilmgandhi 18:6a4db94011d3 5735 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5736 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
sahilmgandhi 18:6a4db94011d3 5737 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
sahilmgandhi 18:6a4db94011d3 5738 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5739 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5740
sahilmgandhi 18:6a4db94011d3 5741 /* Register: MWU_PERREGION_SUBSTATRA */
sahilmgandhi 18:6a4db94011d3 5742 /* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
sahilmgandhi 18:6a4db94011d3 5743
sahilmgandhi 18:6a4db94011d3 5744 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5745 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
sahilmgandhi 18:6a4db94011d3 5746 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
sahilmgandhi 18:6a4db94011d3 5747 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5748 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5749
sahilmgandhi 18:6a4db94011d3 5750 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5751 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
sahilmgandhi 18:6a4db94011d3 5752 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
sahilmgandhi 18:6a4db94011d3 5753 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5754 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5755
sahilmgandhi 18:6a4db94011d3 5756 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5757 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
sahilmgandhi 18:6a4db94011d3 5758 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
sahilmgandhi 18:6a4db94011d3 5759 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5760 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5761
sahilmgandhi 18:6a4db94011d3 5762 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5763 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
sahilmgandhi 18:6a4db94011d3 5764 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
sahilmgandhi 18:6a4db94011d3 5765 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5766 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5767
sahilmgandhi 18:6a4db94011d3 5768 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5769 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
sahilmgandhi 18:6a4db94011d3 5770 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
sahilmgandhi 18:6a4db94011d3 5771 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5772 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5773
sahilmgandhi 18:6a4db94011d3 5774 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5775 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
sahilmgandhi 18:6a4db94011d3 5776 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
sahilmgandhi 18:6a4db94011d3 5777 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5778 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5779
sahilmgandhi 18:6a4db94011d3 5780 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5781 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
sahilmgandhi 18:6a4db94011d3 5782 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
sahilmgandhi 18:6a4db94011d3 5783 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5784 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5785
sahilmgandhi 18:6a4db94011d3 5786 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5787 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
sahilmgandhi 18:6a4db94011d3 5788 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
sahilmgandhi 18:6a4db94011d3 5789 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5790 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5791
sahilmgandhi 18:6a4db94011d3 5792 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5793 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
sahilmgandhi 18:6a4db94011d3 5794 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
sahilmgandhi 18:6a4db94011d3 5795 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5796 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5797
sahilmgandhi 18:6a4db94011d3 5798 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5799 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
sahilmgandhi 18:6a4db94011d3 5800 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
sahilmgandhi 18:6a4db94011d3 5801 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5802 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5803
sahilmgandhi 18:6a4db94011d3 5804 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5805 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
sahilmgandhi 18:6a4db94011d3 5806 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
sahilmgandhi 18:6a4db94011d3 5807 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5808 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5809
sahilmgandhi 18:6a4db94011d3 5810 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5811 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
sahilmgandhi 18:6a4db94011d3 5812 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
sahilmgandhi 18:6a4db94011d3 5813 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5814 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5815
sahilmgandhi 18:6a4db94011d3 5816 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5817 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
sahilmgandhi 18:6a4db94011d3 5818 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
sahilmgandhi 18:6a4db94011d3 5819 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5820 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5821
sahilmgandhi 18:6a4db94011d3 5822 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5823 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
sahilmgandhi 18:6a4db94011d3 5824 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
sahilmgandhi 18:6a4db94011d3 5825 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5826 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5827
sahilmgandhi 18:6a4db94011d3 5828 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5829 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
sahilmgandhi 18:6a4db94011d3 5830 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
sahilmgandhi 18:6a4db94011d3 5831 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5832 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5833
sahilmgandhi 18:6a4db94011d3 5834 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5835 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
sahilmgandhi 18:6a4db94011d3 5836 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
sahilmgandhi 18:6a4db94011d3 5837 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5838 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5839
sahilmgandhi 18:6a4db94011d3 5840 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5841 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
sahilmgandhi 18:6a4db94011d3 5842 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
sahilmgandhi 18:6a4db94011d3 5843 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5844 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5845
sahilmgandhi 18:6a4db94011d3 5846 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5847 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
sahilmgandhi 18:6a4db94011d3 5848 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
sahilmgandhi 18:6a4db94011d3 5849 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5850 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5851
sahilmgandhi 18:6a4db94011d3 5852 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5853 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
sahilmgandhi 18:6a4db94011d3 5854 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
sahilmgandhi 18:6a4db94011d3 5855 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5856 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5857
sahilmgandhi 18:6a4db94011d3 5858 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5859 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
sahilmgandhi 18:6a4db94011d3 5860 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
sahilmgandhi 18:6a4db94011d3 5861 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5862 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5863
sahilmgandhi 18:6a4db94011d3 5864 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5865 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
sahilmgandhi 18:6a4db94011d3 5866 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
sahilmgandhi 18:6a4db94011d3 5867 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5868 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5869
sahilmgandhi 18:6a4db94011d3 5870 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5871 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
sahilmgandhi 18:6a4db94011d3 5872 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
sahilmgandhi 18:6a4db94011d3 5873 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5874 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5875
sahilmgandhi 18:6a4db94011d3 5876 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5877 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
sahilmgandhi 18:6a4db94011d3 5878 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
sahilmgandhi 18:6a4db94011d3 5879 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5880 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5881
sahilmgandhi 18:6a4db94011d3 5882 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5883 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
sahilmgandhi 18:6a4db94011d3 5884 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
sahilmgandhi 18:6a4db94011d3 5885 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5886 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5887
sahilmgandhi 18:6a4db94011d3 5888 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5889 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
sahilmgandhi 18:6a4db94011d3 5890 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
sahilmgandhi 18:6a4db94011d3 5891 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5892 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5893
sahilmgandhi 18:6a4db94011d3 5894 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5895 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
sahilmgandhi 18:6a4db94011d3 5896 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
sahilmgandhi 18:6a4db94011d3 5897 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5898 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5899
sahilmgandhi 18:6a4db94011d3 5900 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5901 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
sahilmgandhi 18:6a4db94011d3 5902 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
sahilmgandhi 18:6a4db94011d3 5903 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5904 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5905
sahilmgandhi 18:6a4db94011d3 5906 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5907 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
sahilmgandhi 18:6a4db94011d3 5908 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
sahilmgandhi 18:6a4db94011d3 5909 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5910 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5911
sahilmgandhi 18:6a4db94011d3 5912 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5913 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
sahilmgandhi 18:6a4db94011d3 5914 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
sahilmgandhi 18:6a4db94011d3 5915 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5916 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5917
sahilmgandhi 18:6a4db94011d3 5918 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5919 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
sahilmgandhi 18:6a4db94011d3 5920 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
sahilmgandhi 18:6a4db94011d3 5921 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5922 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5923
sahilmgandhi 18:6a4db94011d3 5924 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5925 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
sahilmgandhi 18:6a4db94011d3 5926 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
sahilmgandhi 18:6a4db94011d3 5927 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5928 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5929
sahilmgandhi 18:6a4db94011d3 5930 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 5931 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
sahilmgandhi 18:6a4db94011d3 5932 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
sahilmgandhi 18:6a4db94011d3 5933 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5934 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
sahilmgandhi 18:6a4db94011d3 5935
sahilmgandhi 18:6a4db94011d3 5936 /* Register: MWU_REGIONEN */
sahilmgandhi 18:6a4db94011d3 5937 /* Description: Enable/disable regions watch */
sahilmgandhi 18:6a4db94011d3 5938
sahilmgandhi 18:6a4db94011d3 5939 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
sahilmgandhi 18:6a4db94011d3 5940 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
sahilmgandhi 18:6a4db94011d3 5941 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
sahilmgandhi 18:6a4db94011d3 5942 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5943 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5944
sahilmgandhi 18:6a4db94011d3 5945 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
sahilmgandhi 18:6a4db94011d3 5946 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
sahilmgandhi 18:6a4db94011d3 5947 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
sahilmgandhi 18:6a4db94011d3 5948 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5949 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5950
sahilmgandhi 18:6a4db94011d3 5951 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
sahilmgandhi 18:6a4db94011d3 5952 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
sahilmgandhi 18:6a4db94011d3 5953 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
sahilmgandhi 18:6a4db94011d3 5954 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5955 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5956
sahilmgandhi 18:6a4db94011d3 5957 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
sahilmgandhi 18:6a4db94011d3 5958 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
sahilmgandhi 18:6a4db94011d3 5959 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
sahilmgandhi 18:6a4db94011d3 5960 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5961 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 5962
sahilmgandhi 18:6a4db94011d3 5963 /* Bit 7 : Enable/disable read access watch in region[3] */
sahilmgandhi 18:6a4db94011d3 5964 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
sahilmgandhi 18:6a4db94011d3 5965 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
sahilmgandhi 18:6a4db94011d3 5966 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 5967 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 5968
sahilmgandhi 18:6a4db94011d3 5969 /* Bit 6 : Enable/disable write access watch in region[3] */
sahilmgandhi 18:6a4db94011d3 5970 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
sahilmgandhi 18:6a4db94011d3 5971 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
sahilmgandhi 18:6a4db94011d3 5972 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 5973 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 5974
sahilmgandhi 18:6a4db94011d3 5975 /* Bit 5 : Enable/disable read access watch in region[2] */
sahilmgandhi 18:6a4db94011d3 5976 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
sahilmgandhi 18:6a4db94011d3 5977 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
sahilmgandhi 18:6a4db94011d3 5978 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 5979 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 5980
sahilmgandhi 18:6a4db94011d3 5981 /* Bit 4 : Enable/disable write access watch in region[2] */
sahilmgandhi 18:6a4db94011d3 5982 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
sahilmgandhi 18:6a4db94011d3 5983 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
sahilmgandhi 18:6a4db94011d3 5984 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 5985 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 5986
sahilmgandhi 18:6a4db94011d3 5987 /* Bit 3 : Enable/disable read access watch in region[1] */
sahilmgandhi 18:6a4db94011d3 5988 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
sahilmgandhi 18:6a4db94011d3 5989 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
sahilmgandhi 18:6a4db94011d3 5990 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 5991 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 5992
sahilmgandhi 18:6a4db94011d3 5993 /* Bit 2 : Enable/disable write access watch in region[1] */
sahilmgandhi 18:6a4db94011d3 5994 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
sahilmgandhi 18:6a4db94011d3 5995 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
sahilmgandhi 18:6a4db94011d3 5996 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 5997 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 5998
sahilmgandhi 18:6a4db94011d3 5999 /* Bit 1 : Enable/disable read access watch in region[0] */
sahilmgandhi 18:6a4db94011d3 6000 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6001 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6002 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6003 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6004
sahilmgandhi 18:6a4db94011d3 6005 /* Bit 0 : Enable/disable write access watch in region[0] */
sahilmgandhi 18:6a4db94011d3 6006 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6007 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6008 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6009 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6010
sahilmgandhi 18:6a4db94011d3 6011 /* Register: MWU_REGIONENSET */
sahilmgandhi 18:6a4db94011d3 6012 /* Description: Enable regions watch */
sahilmgandhi 18:6a4db94011d3 6013
sahilmgandhi 18:6a4db94011d3 6014 /* Bit 27 : Enable read access watch in PREGION[1] */
sahilmgandhi 18:6a4db94011d3 6015 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6016 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6017 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6018 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6019 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6020
sahilmgandhi 18:6a4db94011d3 6021 /* Bit 26 : Enable write access watch in PREGION[1] */
sahilmgandhi 18:6a4db94011d3 6022 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6023 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6024 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6025 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6026 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6027
sahilmgandhi 18:6a4db94011d3 6028 /* Bit 25 : Enable read access watch in PREGION[0] */
sahilmgandhi 18:6a4db94011d3 6029 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6030 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6031 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6032 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6033 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6034
sahilmgandhi 18:6a4db94011d3 6035 /* Bit 24 : Enable write access watch in PREGION[0] */
sahilmgandhi 18:6a4db94011d3 6036 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6037 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6038 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6039 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6040 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6041
sahilmgandhi 18:6a4db94011d3 6042 /* Bit 7 : Enable read access watch in region[3] */
sahilmgandhi 18:6a4db94011d3 6043 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
sahilmgandhi 18:6a4db94011d3 6044 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
sahilmgandhi 18:6a4db94011d3 6045 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6046 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6047 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6048
sahilmgandhi 18:6a4db94011d3 6049 /* Bit 6 : Enable write access watch in region[3] */
sahilmgandhi 18:6a4db94011d3 6050 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
sahilmgandhi 18:6a4db94011d3 6051 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
sahilmgandhi 18:6a4db94011d3 6052 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6053 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6054 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6055
sahilmgandhi 18:6a4db94011d3 6056 /* Bit 5 : Enable read access watch in region[2] */
sahilmgandhi 18:6a4db94011d3 6057 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
sahilmgandhi 18:6a4db94011d3 6058 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
sahilmgandhi 18:6a4db94011d3 6059 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6060 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6061 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6062
sahilmgandhi 18:6a4db94011d3 6063 /* Bit 4 : Enable write access watch in region[2] */
sahilmgandhi 18:6a4db94011d3 6064 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
sahilmgandhi 18:6a4db94011d3 6065 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
sahilmgandhi 18:6a4db94011d3 6066 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6067 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6068 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6069
sahilmgandhi 18:6a4db94011d3 6070 /* Bit 3 : Enable read access watch in region[1] */
sahilmgandhi 18:6a4db94011d3 6071 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6072 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6073 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6074 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6075 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6076
sahilmgandhi 18:6a4db94011d3 6077 /* Bit 2 : Enable write access watch in region[1] */
sahilmgandhi 18:6a4db94011d3 6078 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6079 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6080 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6081 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6082 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6083
sahilmgandhi 18:6a4db94011d3 6084 /* Bit 1 : Enable read access watch in region[0] */
sahilmgandhi 18:6a4db94011d3 6085 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6086 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6087 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6088 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6089 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6090
sahilmgandhi 18:6a4db94011d3 6091 /* Bit 0 : Enable write access watch in region[0] */
sahilmgandhi 18:6a4db94011d3 6092 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6093 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6094 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6095 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6096 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6097
sahilmgandhi 18:6a4db94011d3 6098 /* Register: MWU_REGIONENCLR */
sahilmgandhi 18:6a4db94011d3 6099 /* Description: Disable regions watch */
sahilmgandhi 18:6a4db94011d3 6100
sahilmgandhi 18:6a4db94011d3 6101 /* Bit 27 : Disable read access watch in PREGION[1] */
sahilmgandhi 18:6a4db94011d3 6102 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6103 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6104 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6105 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6106 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6107
sahilmgandhi 18:6a4db94011d3 6108 /* Bit 26 : Disable write access watch in PREGION[1] */
sahilmgandhi 18:6a4db94011d3 6109 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6110 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6111 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6112 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6113 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6114
sahilmgandhi 18:6a4db94011d3 6115 /* Bit 25 : Disable read access watch in PREGION[0] */
sahilmgandhi 18:6a4db94011d3 6116 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6117 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6118 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6119 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6120 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6121
sahilmgandhi 18:6a4db94011d3 6122 /* Bit 24 : Disable write access watch in PREGION[0] */
sahilmgandhi 18:6a4db94011d3 6123 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6124 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6125 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
sahilmgandhi 18:6a4db94011d3 6126 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
sahilmgandhi 18:6a4db94011d3 6127 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
sahilmgandhi 18:6a4db94011d3 6128
sahilmgandhi 18:6a4db94011d3 6129 /* Bit 7 : Disable read access watch in region[3] */
sahilmgandhi 18:6a4db94011d3 6130 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
sahilmgandhi 18:6a4db94011d3 6131 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
sahilmgandhi 18:6a4db94011d3 6132 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6133 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6134 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6135
sahilmgandhi 18:6a4db94011d3 6136 /* Bit 6 : Disable write access watch in region[3] */
sahilmgandhi 18:6a4db94011d3 6137 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
sahilmgandhi 18:6a4db94011d3 6138 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
sahilmgandhi 18:6a4db94011d3 6139 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6140 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6141 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6142
sahilmgandhi 18:6a4db94011d3 6143 /* Bit 5 : Disable read access watch in region[2] */
sahilmgandhi 18:6a4db94011d3 6144 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
sahilmgandhi 18:6a4db94011d3 6145 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
sahilmgandhi 18:6a4db94011d3 6146 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6147 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6148 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6149
sahilmgandhi 18:6a4db94011d3 6150 /* Bit 4 : Disable write access watch in region[2] */
sahilmgandhi 18:6a4db94011d3 6151 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
sahilmgandhi 18:6a4db94011d3 6152 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
sahilmgandhi 18:6a4db94011d3 6153 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6154 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6155 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6156
sahilmgandhi 18:6a4db94011d3 6157 /* Bit 3 : Disable read access watch in region[1] */
sahilmgandhi 18:6a4db94011d3 6158 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6159 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
sahilmgandhi 18:6a4db94011d3 6160 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6161 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6162 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6163
sahilmgandhi 18:6a4db94011d3 6164 /* Bit 2 : Disable write access watch in region[1] */
sahilmgandhi 18:6a4db94011d3 6165 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6166 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
sahilmgandhi 18:6a4db94011d3 6167 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6168 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6169 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6170
sahilmgandhi 18:6a4db94011d3 6171 /* Bit 1 : Disable read access watch in region[0] */
sahilmgandhi 18:6a4db94011d3 6172 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6173 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
sahilmgandhi 18:6a4db94011d3 6174 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6175 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6176 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
sahilmgandhi 18:6a4db94011d3 6177
sahilmgandhi 18:6a4db94011d3 6178 /* Bit 0 : Disable write access watch in region[0] */
sahilmgandhi 18:6a4db94011d3 6179 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6180 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
sahilmgandhi 18:6a4db94011d3 6181 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
sahilmgandhi 18:6a4db94011d3 6182 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
sahilmgandhi 18:6a4db94011d3 6183 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
sahilmgandhi 18:6a4db94011d3 6184
sahilmgandhi 18:6a4db94011d3 6185 /* Register: MWU_REGION_START */
sahilmgandhi 18:6a4db94011d3 6186 /* Description: Description cluster[0]: Start address for region 0 */
sahilmgandhi 18:6a4db94011d3 6187
sahilmgandhi 18:6a4db94011d3 6188 /* Bits 31..0 : Start address for region */
sahilmgandhi 18:6a4db94011d3 6189 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
sahilmgandhi 18:6a4db94011d3 6190 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
sahilmgandhi 18:6a4db94011d3 6191
sahilmgandhi 18:6a4db94011d3 6192 /* Register: MWU_REGION_END */
sahilmgandhi 18:6a4db94011d3 6193 /* Description: Description cluster[0]: End address of region 0 */
sahilmgandhi 18:6a4db94011d3 6194
sahilmgandhi 18:6a4db94011d3 6195 /* Bits 31..0 : End address of region. */
sahilmgandhi 18:6a4db94011d3 6196 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 6197 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 6198
sahilmgandhi 18:6a4db94011d3 6199 /* Register: MWU_PREGION_START */
sahilmgandhi 18:6a4db94011d3 6200 /* Description: Description cluster[0]: Reserved for future use */
sahilmgandhi 18:6a4db94011d3 6201
sahilmgandhi 18:6a4db94011d3 6202 /* Bits 31..0 : Reserved for future use */
sahilmgandhi 18:6a4db94011d3 6203 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
sahilmgandhi 18:6a4db94011d3 6204 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
sahilmgandhi 18:6a4db94011d3 6205
sahilmgandhi 18:6a4db94011d3 6206 /* Register: MWU_PREGION_END */
sahilmgandhi 18:6a4db94011d3 6207 /* Description: Description cluster[0]: Reserved for future use */
sahilmgandhi 18:6a4db94011d3 6208
sahilmgandhi 18:6a4db94011d3 6209 /* Bits 31..0 : Reserved for future use */
sahilmgandhi 18:6a4db94011d3 6210 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 6211 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 6212
sahilmgandhi 18:6a4db94011d3 6213 /* Register: MWU_PREGION_SUBS */
sahilmgandhi 18:6a4db94011d3 6214 /* Description: Description cluster[0]: Subregions of region 0 */
sahilmgandhi 18:6a4db94011d3 6215
sahilmgandhi 18:6a4db94011d3 6216 /* Bit 31 : Include or exclude subregion 31 in region */
sahilmgandhi 18:6a4db94011d3 6217 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
sahilmgandhi 18:6a4db94011d3 6218 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
sahilmgandhi 18:6a4db94011d3 6219 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6220 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6221
sahilmgandhi 18:6a4db94011d3 6222 /* Bit 30 : Include or exclude subregion 30 in region */
sahilmgandhi 18:6a4db94011d3 6223 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
sahilmgandhi 18:6a4db94011d3 6224 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
sahilmgandhi 18:6a4db94011d3 6225 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6226 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6227
sahilmgandhi 18:6a4db94011d3 6228 /* Bit 29 : Include or exclude subregion 29 in region */
sahilmgandhi 18:6a4db94011d3 6229 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
sahilmgandhi 18:6a4db94011d3 6230 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
sahilmgandhi 18:6a4db94011d3 6231 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6232 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6233
sahilmgandhi 18:6a4db94011d3 6234 /* Bit 28 : Include or exclude subregion 28 in region */
sahilmgandhi 18:6a4db94011d3 6235 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
sahilmgandhi 18:6a4db94011d3 6236 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
sahilmgandhi 18:6a4db94011d3 6237 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6238 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6239
sahilmgandhi 18:6a4db94011d3 6240 /* Bit 27 : Include or exclude subregion 27 in region */
sahilmgandhi 18:6a4db94011d3 6241 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
sahilmgandhi 18:6a4db94011d3 6242 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
sahilmgandhi 18:6a4db94011d3 6243 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6244 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6245
sahilmgandhi 18:6a4db94011d3 6246 /* Bit 26 : Include or exclude subregion 26 in region */
sahilmgandhi 18:6a4db94011d3 6247 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
sahilmgandhi 18:6a4db94011d3 6248 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
sahilmgandhi 18:6a4db94011d3 6249 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6250 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6251
sahilmgandhi 18:6a4db94011d3 6252 /* Bit 25 : Include or exclude subregion 25 in region */
sahilmgandhi 18:6a4db94011d3 6253 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
sahilmgandhi 18:6a4db94011d3 6254 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
sahilmgandhi 18:6a4db94011d3 6255 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6256 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6257
sahilmgandhi 18:6a4db94011d3 6258 /* Bit 24 : Include or exclude subregion 24 in region */
sahilmgandhi 18:6a4db94011d3 6259 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
sahilmgandhi 18:6a4db94011d3 6260 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
sahilmgandhi 18:6a4db94011d3 6261 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6262 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6263
sahilmgandhi 18:6a4db94011d3 6264 /* Bit 23 : Include or exclude subregion 23 in region */
sahilmgandhi 18:6a4db94011d3 6265 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
sahilmgandhi 18:6a4db94011d3 6266 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
sahilmgandhi 18:6a4db94011d3 6267 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6268 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6269
sahilmgandhi 18:6a4db94011d3 6270 /* Bit 22 : Include or exclude subregion 22 in region */
sahilmgandhi 18:6a4db94011d3 6271 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
sahilmgandhi 18:6a4db94011d3 6272 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
sahilmgandhi 18:6a4db94011d3 6273 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6274 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6275
sahilmgandhi 18:6a4db94011d3 6276 /* Bit 21 : Include or exclude subregion 21 in region */
sahilmgandhi 18:6a4db94011d3 6277 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
sahilmgandhi 18:6a4db94011d3 6278 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
sahilmgandhi 18:6a4db94011d3 6279 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6280 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6281
sahilmgandhi 18:6a4db94011d3 6282 /* Bit 20 : Include or exclude subregion 20 in region */
sahilmgandhi 18:6a4db94011d3 6283 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
sahilmgandhi 18:6a4db94011d3 6284 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
sahilmgandhi 18:6a4db94011d3 6285 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6286 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6287
sahilmgandhi 18:6a4db94011d3 6288 /* Bit 19 : Include or exclude subregion 19 in region */
sahilmgandhi 18:6a4db94011d3 6289 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
sahilmgandhi 18:6a4db94011d3 6290 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
sahilmgandhi 18:6a4db94011d3 6291 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6292 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6293
sahilmgandhi 18:6a4db94011d3 6294 /* Bit 18 : Include or exclude subregion 18 in region */
sahilmgandhi 18:6a4db94011d3 6295 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
sahilmgandhi 18:6a4db94011d3 6296 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
sahilmgandhi 18:6a4db94011d3 6297 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6298 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6299
sahilmgandhi 18:6a4db94011d3 6300 /* Bit 17 : Include or exclude subregion 17 in region */
sahilmgandhi 18:6a4db94011d3 6301 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
sahilmgandhi 18:6a4db94011d3 6302 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
sahilmgandhi 18:6a4db94011d3 6303 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6304 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6305
sahilmgandhi 18:6a4db94011d3 6306 /* Bit 16 : Include or exclude subregion 16 in region */
sahilmgandhi 18:6a4db94011d3 6307 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
sahilmgandhi 18:6a4db94011d3 6308 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
sahilmgandhi 18:6a4db94011d3 6309 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6310 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6311
sahilmgandhi 18:6a4db94011d3 6312 /* Bit 15 : Include or exclude subregion 15 in region */
sahilmgandhi 18:6a4db94011d3 6313 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
sahilmgandhi 18:6a4db94011d3 6314 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
sahilmgandhi 18:6a4db94011d3 6315 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6316 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6317
sahilmgandhi 18:6a4db94011d3 6318 /* Bit 14 : Include or exclude subregion 14 in region */
sahilmgandhi 18:6a4db94011d3 6319 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
sahilmgandhi 18:6a4db94011d3 6320 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
sahilmgandhi 18:6a4db94011d3 6321 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6322 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6323
sahilmgandhi 18:6a4db94011d3 6324 /* Bit 13 : Include or exclude subregion 13 in region */
sahilmgandhi 18:6a4db94011d3 6325 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
sahilmgandhi 18:6a4db94011d3 6326 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
sahilmgandhi 18:6a4db94011d3 6327 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6328 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6329
sahilmgandhi 18:6a4db94011d3 6330 /* Bit 12 : Include or exclude subregion 12 in region */
sahilmgandhi 18:6a4db94011d3 6331 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
sahilmgandhi 18:6a4db94011d3 6332 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
sahilmgandhi 18:6a4db94011d3 6333 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6334 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6335
sahilmgandhi 18:6a4db94011d3 6336 /* Bit 11 : Include or exclude subregion 11 in region */
sahilmgandhi 18:6a4db94011d3 6337 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
sahilmgandhi 18:6a4db94011d3 6338 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
sahilmgandhi 18:6a4db94011d3 6339 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6340 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6341
sahilmgandhi 18:6a4db94011d3 6342 /* Bit 10 : Include or exclude subregion 10 in region */
sahilmgandhi 18:6a4db94011d3 6343 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
sahilmgandhi 18:6a4db94011d3 6344 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
sahilmgandhi 18:6a4db94011d3 6345 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6346 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6347
sahilmgandhi 18:6a4db94011d3 6348 /* Bit 9 : Include or exclude subregion 9 in region */
sahilmgandhi 18:6a4db94011d3 6349 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
sahilmgandhi 18:6a4db94011d3 6350 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
sahilmgandhi 18:6a4db94011d3 6351 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6352 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6353
sahilmgandhi 18:6a4db94011d3 6354 /* Bit 8 : Include or exclude subregion 8 in region */
sahilmgandhi 18:6a4db94011d3 6355 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
sahilmgandhi 18:6a4db94011d3 6356 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
sahilmgandhi 18:6a4db94011d3 6357 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6358 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6359
sahilmgandhi 18:6a4db94011d3 6360 /* Bit 7 : Include or exclude subregion 7 in region */
sahilmgandhi 18:6a4db94011d3 6361 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
sahilmgandhi 18:6a4db94011d3 6362 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
sahilmgandhi 18:6a4db94011d3 6363 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6364 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6365
sahilmgandhi 18:6a4db94011d3 6366 /* Bit 6 : Include or exclude subregion 6 in region */
sahilmgandhi 18:6a4db94011d3 6367 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
sahilmgandhi 18:6a4db94011d3 6368 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
sahilmgandhi 18:6a4db94011d3 6369 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6370 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6371
sahilmgandhi 18:6a4db94011d3 6372 /* Bit 5 : Include or exclude subregion 5 in region */
sahilmgandhi 18:6a4db94011d3 6373 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
sahilmgandhi 18:6a4db94011d3 6374 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
sahilmgandhi 18:6a4db94011d3 6375 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6376 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6377
sahilmgandhi 18:6a4db94011d3 6378 /* Bit 4 : Include or exclude subregion 4 in region */
sahilmgandhi 18:6a4db94011d3 6379 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
sahilmgandhi 18:6a4db94011d3 6380 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
sahilmgandhi 18:6a4db94011d3 6381 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6382 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6383
sahilmgandhi 18:6a4db94011d3 6384 /* Bit 3 : Include or exclude subregion 3 in region */
sahilmgandhi 18:6a4db94011d3 6385 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
sahilmgandhi 18:6a4db94011d3 6386 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
sahilmgandhi 18:6a4db94011d3 6387 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6388 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6389
sahilmgandhi 18:6a4db94011d3 6390 /* Bit 2 : Include or exclude subregion 2 in region */
sahilmgandhi 18:6a4db94011d3 6391 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
sahilmgandhi 18:6a4db94011d3 6392 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
sahilmgandhi 18:6a4db94011d3 6393 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6394 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6395
sahilmgandhi 18:6a4db94011d3 6396 /* Bit 1 : Include or exclude subregion 1 in region */
sahilmgandhi 18:6a4db94011d3 6397 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
sahilmgandhi 18:6a4db94011d3 6398 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
sahilmgandhi 18:6a4db94011d3 6399 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6400 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6401
sahilmgandhi 18:6a4db94011d3 6402 /* Bit 0 : Include or exclude subregion 0 in region */
sahilmgandhi 18:6a4db94011d3 6403 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
sahilmgandhi 18:6a4db94011d3 6404 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
sahilmgandhi 18:6a4db94011d3 6405 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 6406 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 6407
sahilmgandhi 18:6a4db94011d3 6408
sahilmgandhi 18:6a4db94011d3 6409 /* Peripheral: NFCT */
sahilmgandhi 18:6a4db94011d3 6410 /* Description: NFC-A compatible radio */
sahilmgandhi 18:6a4db94011d3 6411
sahilmgandhi 18:6a4db94011d3 6412 /* Register: NFCT_SHORTS */
sahilmgandhi 18:6a4db94011d3 6413 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 6414
sahilmgandhi 18:6a4db94011d3 6415 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
sahilmgandhi 18:6a4db94011d3 6416 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
sahilmgandhi 18:6a4db94011d3 6417 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
sahilmgandhi 18:6a4db94011d3 6418 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 6419 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 6420
sahilmgandhi 18:6a4db94011d3 6421 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
sahilmgandhi 18:6a4db94011d3 6422 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
sahilmgandhi 18:6a4db94011d3 6423 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
sahilmgandhi 18:6a4db94011d3 6424 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 6425 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 6426
sahilmgandhi 18:6a4db94011d3 6427 /* Register: NFCT_INTEN */
sahilmgandhi 18:6a4db94011d3 6428 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 6429
sahilmgandhi 18:6a4db94011d3 6430 /* Bit 20 : Enable or disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 6431 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 6432 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 6433 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6434 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6435
sahilmgandhi 18:6a4db94011d3 6436 /* Bit 19 : Enable or disable interrupt for SELECTED event */
sahilmgandhi 18:6a4db94011d3 6437 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
sahilmgandhi 18:6a4db94011d3 6438 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
sahilmgandhi 18:6a4db94011d3 6439 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6440 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6441
sahilmgandhi 18:6a4db94011d3 6442 /* Bit 18 : Enable or disable interrupt for COLLISION event */
sahilmgandhi 18:6a4db94011d3 6443 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
sahilmgandhi 18:6a4db94011d3 6444 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
sahilmgandhi 18:6a4db94011d3 6445 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6446 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6447
sahilmgandhi 18:6a4db94011d3 6448 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
sahilmgandhi 18:6a4db94011d3 6449 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
sahilmgandhi 18:6a4db94011d3 6450 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
sahilmgandhi 18:6a4db94011d3 6451 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6452 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6453
sahilmgandhi 18:6a4db94011d3 6454 /* Bit 12 : Enable or disable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 6455 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 6456 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 6457 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6458 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6459
sahilmgandhi 18:6a4db94011d3 6460 /* Bit 11 : Enable or disable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 6461 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 6462 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 6463 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6464 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6465
sahilmgandhi 18:6a4db94011d3 6466 /* Bit 10 : Enable or disable interrupt for RXERROR event */
sahilmgandhi 18:6a4db94011d3 6467 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
sahilmgandhi 18:6a4db94011d3 6468 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
sahilmgandhi 18:6a4db94011d3 6469 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6470 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6471
sahilmgandhi 18:6a4db94011d3 6472 /* Bit 7 : Enable or disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 6473 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6474 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6475 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6476 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6477
sahilmgandhi 18:6a4db94011d3 6478 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
sahilmgandhi 18:6a4db94011d3 6479 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6480 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6481 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6482 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6483
sahilmgandhi 18:6a4db94011d3 6484 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
sahilmgandhi 18:6a4db94011d3 6485 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6486 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6487 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6488 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6489
sahilmgandhi 18:6a4db94011d3 6490 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
sahilmgandhi 18:6a4db94011d3 6491 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6492 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6493 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6494 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6495
sahilmgandhi 18:6a4db94011d3 6496 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
sahilmgandhi 18:6a4db94011d3 6497 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6498 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6499 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6500 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6501
sahilmgandhi 18:6a4db94011d3 6502 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
sahilmgandhi 18:6a4db94011d3 6503 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
sahilmgandhi 18:6a4db94011d3 6504 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
sahilmgandhi 18:6a4db94011d3 6505 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6506 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6507
sahilmgandhi 18:6a4db94011d3 6508 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
sahilmgandhi 18:6a4db94011d3 6509 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
sahilmgandhi 18:6a4db94011d3 6510 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
sahilmgandhi 18:6a4db94011d3 6511 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6512 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6513
sahilmgandhi 18:6a4db94011d3 6514 /* Bit 0 : Enable or disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 6515 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 6516 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 6517 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6518 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6519
sahilmgandhi 18:6a4db94011d3 6520 /* Register: NFCT_INTENSET */
sahilmgandhi 18:6a4db94011d3 6521 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 6522
sahilmgandhi 18:6a4db94011d3 6523 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 6524 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 6525 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 6526 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6527 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6528 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6529
sahilmgandhi 18:6a4db94011d3 6530 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
sahilmgandhi 18:6a4db94011d3 6531 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
sahilmgandhi 18:6a4db94011d3 6532 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
sahilmgandhi 18:6a4db94011d3 6533 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6534 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6535 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6536
sahilmgandhi 18:6a4db94011d3 6537 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
sahilmgandhi 18:6a4db94011d3 6538 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
sahilmgandhi 18:6a4db94011d3 6539 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
sahilmgandhi 18:6a4db94011d3 6540 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6541 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6542 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6543
sahilmgandhi 18:6a4db94011d3 6544 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
sahilmgandhi 18:6a4db94011d3 6545 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
sahilmgandhi 18:6a4db94011d3 6546 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
sahilmgandhi 18:6a4db94011d3 6547 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6548 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6549 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6550
sahilmgandhi 18:6a4db94011d3 6551 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 6552 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 6553 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 6554 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6555 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6556 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6557
sahilmgandhi 18:6a4db94011d3 6558 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 6559 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 6560 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 6561 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6562 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6563 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6564
sahilmgandhi 18:6a4db94011d3 6565 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
sahilmgandhi 18:6a4db94011d3 6566 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
sahilmgandhi 18:6a4db94011d3 6567 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
sahilmgandhi 18:6a4db94011d3 6568 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6569 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6570 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6571
sahilmgandhi 18:6a4db94011d3 6572 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 6573 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6574 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6575 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6576 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6577 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6578
sahilmgandhi 18:6a4db94011d3 6579 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
sahilmgandhi 18:6a4db94011d3 6580 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6581 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6582 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6583 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6584 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6585
sahilmgandhi 18:6a4db94011d3 6586 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
sahilmgandhi 18:6a4db94011d3 6587 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6588 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6589 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6590 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6591 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6592
sahilmgandhi 18:6a4db94011d3 6593 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
sahilmgandhi 18:6a4db94011d3 6594 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6595 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6596 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6597 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6598 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6599
sahilmgandhi 18:6a4db94011d3 6600 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
sahilmgandhi 18:6a4db94011d3 6601 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6602 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6603 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6604 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6605 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6606
sahilmgandhi 18:6a4db94011d3 6607 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
sahilmgandhi 18:6a4db94011d3 6608 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
sahilmgandhi 18:6a4db94011d3 6609 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
sahilmgandhi 18:6a4db94011d3 6610 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6611 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6612 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6613
sahilmgandhi 18:6a4db94011d3 6614 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
sahilmgandhi 18:6a4db94011d3 6615 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
sahilmgandhi 18:6a4db94011d3 6616 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
sahilmgandhi 18:6a4db94011d3 6617 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6618 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6619 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6620
sahilmgandhi 18:6a4db94011d3 6621 /* Bit 0 : Write '1' to Enable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 6622 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 6623 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 6624 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6625 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6626 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6627
sahilmgandhi 18:6a4db94011d3 6628 /* Register: NFCT_INTENCLR */
sahilmgandhi 18:6a4db94011d3 6629 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 6630
sahilmgandhi 18:6a4db94011d3 6631 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 6632 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 6633 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 6634 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6635 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6636 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6637
sahilmgandhi 18:6a4db94011d3 6638 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
sahilmgandhi 18:6a4db94011d3 6639 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
sahilmgandhi 18:6a4db94011d3 6640 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
sahilmgandhi 18:6a4db94011d3 6641 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6642 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6643 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6644
sahilmgandhi 18:6a4db94011d3 6645 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
sahilmgandhi 18:6a4db94011d3 6646 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
sahilmgandhi 18:6a4db94011d3 6647 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
sahilmgandhi 18:6a4db94011d3 6648 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6649 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6650 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6651
sahilmgandhi 18:6a4db94011d3 6652 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
sahilmgandhi 18:6a4db94011d3 6653 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
sahilmgandhi 18:6a4db94011d3 6654 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
sahilmgandhi 18:6a4db94011d3 6655 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6656 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6657 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6658
sahilmgandhi 18:6a4db94011d3 6659 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 6660 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 6661 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 6662 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6663 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6664 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6665
sahilmgandhi 18:6a4db94011d3 6666 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 6667 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 6668 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 6669 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6670 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6671 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6672
sahilmgandhi 18:6a4db94011d3 6673 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
sahilmgandhi 18:6a4db94011d3 6674 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
sahilmgandhi 18:6a4db94011d3 6675 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
sahilmgandhi 18:6a4db94011d3 6676 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6677 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6678 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6679
sahilmgandhi 18:6a4db94011d3 6680 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 6681 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6682 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6683 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6684 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6685 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6686
sahilmgandhi 18:6a4db94011d3 6687 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
sahilmgandhi 18:6a4db94011d3 6688 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6689 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6690 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6691 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6692 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6693
sahilmgandhi 18:6a4db94011d3 6694 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
sahilmgandhi 18:6a4db94011d3 6695 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6696 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6697 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6698 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6699 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6700
sahilmgandhi 18:6a4db94011d3 6701 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
sahilmgandhi 18:6a4db94011d3 6702 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6703 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
sahilmgandhi 18:6a4db94011d3 6704 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6705 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6706 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6707
sahilmgandhi 18:6a4db94011d3 6708 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
sahilmgandhi 18:6a4db94011d3 6709 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6710 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
sahilmgandhi 18:6a4db94011d3 6711 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6712 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6713 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6714
sahilmgandhi 18:6a4db94011d3 6715 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
sahilmgandhi 18:6a4db94011d3 6716 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
sahilmgandhi 18:6a4db94011d3 6717 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
sahilmgandhi 18:6a4db94011d3 6718 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6719 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6720 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6721
sahilmgandhi 18:6a4db94011d3 6722 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
sahilmgandhi 18:6a4db94011d3 6723 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
sahilmgandhi 18:6a4db94011d3 6724 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
sahilmgandhi 18:6a4db94011d3 6725 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6726 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6727 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6728
sahilmgandhi 18:6a4db94011d3 6729 /* Bit 0 : Write '1' to Disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 6730 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 6731 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 6732 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 6733 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 6734 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 6735
sahilmgandhi 18:6a4db94011d3 6736 /* Register: NFCT_ERRORSTATUS */
sahilmgandhi 18:6a4db94011d3 6737 /* Description: NFC Error Status register */
sahilmgandhi 18:6a4db94011d3 6738
sahilmgandhi 18:6a4db94011d3 6739 /* Bit 3 : Field level is too low at min load resistance */
sahilmgandhi 18:6a4db94011d3 6740 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
sahilmgandhi 18:6a4db94011d3 6741 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
sahilmgandhi 18:6a4db94011d3 6742
sahilmgandhi 18:6a4db94011d3 6743 /* Bit 2 : Field level is too high at max load resistance */
sahilmgandhi 18:6a4db94011d3 6744 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
sahilmgandhi 18:6a4db94011d3 6745 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
sahilmgandhi 18:6a4db94011d3 6746
sahilmgandhi 18:6a4db94011d3 6747 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
sahilmgandhi 18:6a4db94011d3 6748 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 6749 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 6750
sahilmgandhi 18:6a4db94011d3 6751 /* Register: NFCT_FRAMESTATUS_RX */
sahilmgandhi 18:6a4db94011d3 6752 /* Description: Result of last incoming frames */
sahilmgandhi 18:6a4db94011d3 6753
sahilmgandhi 18:6a4db94011d3 6754 /* Bit 3 : Overrun detected */
sahilmgandhi 18:6a4db94011d3 6755 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 6756 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 6757 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
sahilmgandhi 18:6a4db94011d3 6758 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
sahilmgandhi 18:6a4db94011d3 6759
sahilmgandhi 18:6a4db94011d3 6760 /* Bit 2 : Parity status of received frame */
sahilmgandhi 18:6a4db94011d3 6761 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
sahilmgandhi 18:6a4db94011d3 6762 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
sahilmgandhi 18:6a4db94011d3 6763 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
sahilmgandhi 18:6a4db94011d3 6764 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
sahilmgandhi 18:6a4db94011d3 6765
sahilmgandhi 18:6a4db94011d3 6766 /* Bit 0 : No valid End of Frame detected */
sahilmgandhi 18:6a4db94011d3 6767 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
sahilmgandhi 18:6a4db94011d3 6768 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
sahilmgandhi 18:6a4db94011d3 6769 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
sahilmgandhi 18:6a4db94011d3 6770 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
sahilmgandhi 18:6a4db94011d3 6771
sahilmgandhi 18:6a4db94011d3 6772 /* Register: NFCT_CURRENTLOADCTRL */
sahilmgandhi 18:6a4db94011d3 6773 /* Description: Current value driven to the NFC Load Control */
sahilmgandhi 18:6a4db94011d3 6774
sahilmgandhi 18:6a4db94011d3 6775 /* Bits 5..0 : Current value driven to the NFC Load Control */
sahilmgandhi 18:6a4db94011d3 6776 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
sahilmgandhi 18:6a4db94011d3 6777 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
sahilmgandhi 18:6a4db94011d3 6778
sahilmgandhi 18:6a4db94011d3 6779 /* Register: NFCT_FIELDPRESENT */
sahilmgandhi 18:6a4db94011d3 6780 /* Description: Indicates the presence or not of a valid field */
sahilmgandhi 18:6a4db94011d3 6781
sahilmgandhi 18:6a4db94011d3 6782 /* Bit 1 : Indicates if the low level has locked to the field */
sahilmgandhi 18:6a4db94011d3 6783 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
sahilmgandhi 18:6a4db94011d3 6784 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
sahilmgandhi 18:6a4db94011d3 6785 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
sahilmgandhi 18:6a4db94011d3 6786 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
sahilmgandhi 18:6a4db94011d3 6787
sahilmgandhi 18:6a4db94011d3 6788 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
sahilmgandhi 18:6a4db94011d3 6789 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
sahilmgandhi 18:6a4db94011d3 6790 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
sahilmgandhi 18:6a4db94011d3 6791 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
sahilmgandhi 18:6a4db94011d3 6792 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
sahilmgandhi 18:6a4db94011d3 6793
sahilmgandhi 18:6a4db94011d3 6794 /* Register: NFCT_FRAMEDELAYMIN */
sahilmgandhi 18:6a4db94011d3 6795 /* Description: Minimum frame delay */
sahilmgandhi 18:6a4db94011d3 6796
sahilmgandhi 18:6a4db94011d3 6797 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
sahilmgandhi 18:6a4db94011d3 6798 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
sahilmgandhi 18:6a4db94011d3 6799 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
sahilmgandhi 18:6a4db94011d3 6800
sahilmgandhi 18:6a4db94011d3 6801 /* Register: NFCT_FRAMEDELAYMAX */
sahilmgandhi 18:6a4db94011d3 6802 /* Description: Maximum frame delay */
sahilmgandhi 18:6a4db94011d3 6803
sahilmgandhi 18:6a4db94011d3 6804 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
sahilmgandhi 18:6a4db94011d3 6805 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
sahilmgandhi 18:6a4db94011d3 6806 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
sahilmgandhi 18:6a4db94011d3 6807
sahilmgandhi 18:6a4db94011d3 6808 /* Register: NFCT_FRAMEDELAYMODE */
sahilmgandhi 18:6a4db94011d3 6809 /* Description: Configuration register for the Frame Delay Timer */
sahilmgandhi 18:6a4db94011d3 6810
sahilmgandhi 18:6a4db94011d3 6811 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
sahilmgandhi 18:6a4db94011d3 6812 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
sahilmgandhi 18:6a4db94011d3 6813 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
sahilmgandhi 18:6a4db94011d3 6814 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
sahilmgandhi 18:6a4db94011d3 6815 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
sahilmgandhi 18:6a4db94011d3 6816 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
sahilmgandhi 18:6a4db94011d3 6817 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
sahilmgandhi 18:6a4db94011d3 6818
sahilmgandhi 18:6a4db94011d3 6819 /* Register: NFCT_PACKETPTR */
sahilmgandhi 18:6a4db94011d3 6820 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
sahilmgandhi 18:6a4db94011d3 6821
sahilmgandhi 18:6a4db94011d3 6822 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
sahilmgandhi 18:6a4db94011d3 6823 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 6824 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 6825
sahilmgandhi 18:6a4db94011d3 6826 /* Register: NFCT_MAXLEN */
sahilmgandhi 18:6a4db94011d3 6827 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
sahilmgandhi 18:6a4db94011d3 6828
sahilmgandhi 18:6a4db94011d3 6829 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
sahilmgandhi 18:6a4db94011d3 6830 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
sahilmgandhi 18:6a4db94011d3 6831 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
sahilmgandhi 18:6a4db94011d3 6832
sahilmgandhi 18:6a4db94011d3 6833 /* Register: NFCT_TXD_FRAMECONFIG */
sahilmgandhi 18:6a4db94011d3 6834 /* Description: Configuration of outgoing frames */
sahilmgandhi 18:6a4db94011d3 6835
sahilmgandhi 18:6a4db94011d3 6836 /* Bit 4 : CRC mode for outgoing frames */
sahilmgandhi 18:6a4db94011d3 6837 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
sahilmgandhi 18:6a4db94011d3 6838 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
sahilmgandhi 18:6a4db94011d3 6839 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
sahilmgandhi 18:6a4db94011d3 6840 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
sahilmgandhi 18:6a4db94011d3 6841
sahilmgandhi 18:6a4db94011d3 6842 /* Bit 2 : Adding SoF or not in TX frames */
sahilmgandhi 18:6a4db94011d3 6843 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
sahilmgandhi 18:6a4db94011d3 6844 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
sahilmgandhi 18:6a4db94011d3 6845 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
sahilmgandhi 18:6a4db94011d3 6846 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
sahilmgandhi 18:6a4db94011d3 6847
sahilmgandhi 18:6a4db94011d3 6848 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
sahilmgandhi 18:6a4db94011d3 6849 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
sahilmgandhi 18:6a4db94011d3 6850 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
sahilmgandhi 18:6a4db94011d3 6851 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
sahilmgandhi 18:6a4db94011d3 6852 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
sahilmgandhi 18:6a4db94011d3 6853
sahilmgandhi 18:6a4db94011d3 6854 /* Bit 0 : Adding parity or not in the frame */
sahilmgandhi 18:6a4db94011d3 6855 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6856 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6857 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
sahilmgandhi 18:6a4db94011d3 6858 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
sahilmgandhi 18:6a4db94011d3 6859
sahilmgandhi 18:6a4db94011d3 6860 /* Register: NFCT_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 6861 /* Description: Size of outgoing frame */
sahilmgandhi 18:6a4db94011d3 6862
sahilmgandhi 18:6a4db94011d3 6863 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
sahilmgandhi 18:6a4db94011d3 6864 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
sahilmgandhi 18:6a4db94011d3 6865 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
sahilmgandhi 18:6a4db94011d3 6866
sahilmgandhi 18:6a4db94011d3 6867 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
sahilmgandhi 18:6a4db94011d3 6868 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
sahilmgandhi 18:6a4db94011d3 6869 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
sahilmgandhi 18:6a4db94011d3 6870
sahilmgandhi 18:6a4db94011d3 6871 /* Register: NFCT_RXD_FRAMECONFIG */
sahilmgandhi 18:6a4db94011d3 6872 /* Description: Configuration of incoming frames */
sahilmgandhi 18:6a4db94011d3 6873
sahilmgandhi 18:6a4db94011d3 6874 /* Bit 4 : CRC mode for incoming frames */
sahilmgandhi 18:6a4db94011d3 6875 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
sahilmgandhi 18:6a4db94011d3 6876 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
sahilmgandhi 18:6a4db94011d3 6877 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
sahilmgandhi 18:6a4db94011d3 6878 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
sahilmgandhi 18:6a4db94011d3 6879
sahilmgandhi 18:6a4db94011d3 6880 /* Bit 2 : SoF expected or not in RX frames */
sahilmgandhi 18:6a4db94011d3 6881 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
sahilmgandhi 18:6a4db94011d3 6882 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
sahilmgandhi 18:6a4db94011d3 6883 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
sahilmgandhi 18:6a4db94011d3 6884 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
sahilmgandhi 18:6a4db94011d3 6885
sahilmgandhi 18:6a4db94011d3 6886 /* Bit 0 : Parity expected or not in RX frame */
sahilmgandhi 18:6a4db94011d3 6887 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6888 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6889 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
sahilmgandhi 18:6a4db94011d3 6890 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
sahilmgandhi 18:6a4db94011d3 6891
sahilmgandhi 18:6a4db94011d3 6892 /* Register: NFCT_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 6893 /* Description: Size of last incoming frame */
sahilmgandhi 18:6a4db94011d3 6894
sahilmgandhi 18:6a4db94011d3 6895 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
sahilmgandhi 18:6a4db94011d3 6896 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
sahilmgandhi 18:6a4db94011d3 6897 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
sahilmgandhi 18:6a4db94011d3 6898
sahilmgandhi 18:6a4db94011d3 6899 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
sahilmgandhi 18:6a4db94011d3 6900 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
sahilmgandhi 18:6a4db94011d3 6901 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
sahilmgandhi 18:6a4db94011d3 6902
sahilmgandhi 18:6a4db94011d3 6903 /* Register: NFCT_NFCID1_LAST */
sahilmgandhi 18:6a4db94011d3 6904 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
sahilmgandhi 18:6a4db94011d3 6905
sahilmgandhi 18:6a4db94011d3 6906 /* Bits 31..24 : NFCID1 byte W */
sahilmgandhi 18:6a4db94011d3 6907 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
sahilmgandhi 18:6a4db94011d3 6908 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
sahilmgandhi 18:6a4db94011d3 6909
sahilmgandhi 18:6a4db94011d3 6910 /* Bits 23..16 : NFCID1 byte X */
sahilmgandhi 18:6a4db94011d3 6911 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
sahilmgandhi 18:6a4db94011d3 6912 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
sahilmgandhi 18:6a4db94011d3 6913
sahilmgandhi 18:6a4db94011d3 6914 /* Bits 15..8 : NFCID1 byte Y */
sahilmgandhi 18:6a4db94011d3 6915 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
sahilmgandhi 18:6a4db94011d3 6916 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
sahilmgandhi 18:6a4db94011d3 6917
sahilmgandhi 18:6a4db94011d3 6918 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
sahilmgandhi 18:6a4db94011d3 6919 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
sahilmgandhi 18:6a4db94011d3 6920 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
sahilmgandhi 18:6a4db94011d3 6921
sahilmgandhi 18:6a4db94011d3 6922 /* Register: NFCT_NFCID1_2ND_LAST */
sahilmgandhi 18:6a4db94011d3 6923 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
sahilmgandhi 18:6a4db94011d3 6924
sahilmgandhi 18:6a4db94011d3 6925 /* Bits 23..16 : NFCID1 byte T */
sahilmgandhi 18:6a4db94011d3 6926 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
sahilmgandhi 18:6a4db94011d3 6927 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
sahilmgandhi 18:6a4db94011d3 6928
sahilmgandhi 18:6a4db94011d3 6929 /* Bits 15..8 : NFCID1 byte U */
sahilmgandhi 18:6a4db94011d3 6930 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
sahilmgandhi 18:6a4db94011d3 6931 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
sahilmgandhi 18:6a4db94011d3 6932
sahilmgandhi 18:6a4db94011d3 6933 /* Bits 7..0 : NFCID1 byte V */
sahilmgandhi 18:6a4db94011d3 6934 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
sahilmgandhi 18:6a4db94011d3 6935 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
sahilmgandhi 18:6a4db94011d3 6936
sahilmgandhi 18:6a4db94011d3 6937 /* Register: NFCT_NFCID1_3RD_LAST */
sahilmgandhi 18:6a4db94011d3 6938 /* Description: Third last NFCID1 part (10 bytes ID) */
sahilmgandhi 18:6a4db94011d3 6939
sahilmgandhi 18:6a4db94011d3 6940 /* Bits 23..16 : NFCID1 byte Q */
sahilmgandhi 18:6a4db94011d3 6941 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
sahilmgandhi 18:6a4db94011d3 6942 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
sahilmgandhi 18:6a4db94011d3 6943
sahilmgandhi 18:6a4db94011d3 6944 /* Bits 15..8 : NFCID1 byte R */
sahilmgandhi 18:6a4db94011d3 6945 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
sahilmgandhi 18:6a4db94011d3 6946 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
sahilmgandhi 18:6a4db94011d3 6947
sahilmgandhi 18:6a4db94011d3 6948 /* Bits 7..0 : NFCID1 byte S */
sahilmgandhi 18:6a4db94011d3 6949 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
sahilmgandhi 18:6a4db94011d3 6950 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
sahilmgandhi 18:6a4db94011d3 6951
sahilmgandhi 18:6a4db94011d3 6952 /* Register: NFCT_SENSRES */
sahilmgandhi 18:6a4db94011d3 6953 /* Description: NFC-A SENS_RES auto-response settings */
sahilmgandhi 18:6a4db94011d3 6954
sahilmgandhi 18:6a4db94011d3 6955 /* Bits 15..12 : Reserved for future use. Shall be 0. */
sahilmgandhi 18:6a4db94011d3 6956 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
sahilmgandhi 18:6a4db94011d3 6957 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
sahilmgandhi 18:6a4db94011d3 6958
sahilmgandhi 18:6a4db94011d3 6959 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
sahilmgandhi 18:6a4db94011d3 6960 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
sahilmgandhi 18:6a4db94011d3 6961 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
sahilmgandhi 18:6a4db94011d3 6962
sahilmgandhi 18:6a4db94011d3 6963 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
sahilmgandhi 18:6a4db94011d3 6964 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
sahilmgandhi 18:6a4db94011d3 6965 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
sahilmgandhi 18:6a4db94011d3 6966 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
sahilmgandhi 18:6a4db94011d3 6967 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
sahilmgandhi 18:6a4db94011d3 6968 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
sahilmgandhi 18:6a4db94011d3 6969
sahilmgandhi 18:6a4db94011d3 6970 /* Bit 5 : Reserved for future use. Shall be 0. */
sahilmgandhi 18:6a4db94011d3 6971 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
sahilmgandhi 18:6a4db94011d3 6972 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
sahilmgandhi 18:6a4db94011d3 6973
sahilmgandhi 18:6a4db94011d3 6974 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
sahilmgandhi 18:6a4db94011d3 6975 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
sahilmgandhi 18:6a4db94011d3 6976 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
sahilmgandhi 18:6a4db94011d3 6977 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
sahilmgandhi 18:6a4db94011d3 6978 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
sahilmgandhi 18:6a4db94011d3 6979 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
sahilmgandhi 18:6a4db94011d3 6980 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
sahilmgandhi 18:6a4db94011d3 6981 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
sahilmgandhi 18:6a4db94011d3 6982 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
sahilmgandhi 18:6a4db94011d3 6983
sahilmgandhi 18:6a4db94011d3 6984 /* Register: NFCT_SELRES */
sahilmgandhi 18:6a4db94011d3 6985 /* Description: NFC-A SEL_RES auto-response settings */
sahilmgandhi 18:6a4db94011d3 6986
sahilmgandhi 18:6a4db94011d3 6987 /* Bit 7 : Reserved for future use. Shall be 0. */
sahilmgandhi 18:6a4db94011d3 6988 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
sahilmgandhi 18:6a4db94011d3 6989 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
sahilmgandhi 18:6a4db94011d3 6990
sahilmgandhi 18:6a4db94011d3 6991 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
sahilmgandhi 18:6a4db94011d3 6992 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
sahilmgandhi 18:6a4db94011d3 6993 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
sahilmgandhi 18:6a4db94011d3 6994
sahilmgandhi 18:6a4db94011d3 6995 /* Bits 4..3 : Reserved for future use. Shall be 0. */
sahilmgandhi 18:6a4db94011d3 6996 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
sahilmgandhi 18:6a4db94011d3 6997 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
sahilmgandhi 18:6a4db94011d3 6998
sahilmgandhi 18:6a4db94011d3 6999 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
sahilmgandhi 18:6a4db94011d3 7000 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
sahilmgandhi 18:6a4db94011d3 7001 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
sahilmgandhi 18:6a4db94011d3 7002 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
sahilmgandhi 18:6a4db94011d3 7003 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
sahilmgandhi 18:6a4db94011d3 7004
sahilmgandhi 18:6a4db94011d3 7005 /* Bits 1..0 : Reserved for future use. Shall be 0. */
sahilmgandhi 18:6a4db94011d3 7006 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
sahilmgandhi 18:6a4db94011d3 7007 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
sahilmgandhi 18:6a4db94011d3 7008
sahilmgandhi 18:6a4db94011d3 7009
sahilmgandhi 18:6a4db94011d3 7010 /* Peripheral: NVMC */
sahilmgandhi 18:6a4db94011d3 7011 /* Description: Non Volatile Memory Controller */
sahilmgandhi 18:6a4db94011d3 7012
sahilmgandhi 18:6a4db94011d3 7013 /* Register: NVMC_READY */
sahilmgandhi 18:6a4db94011d3 7014 /* Description: Ready flag */
sahilmgandhi 18:6a4db94011d3 7015
sahilmgandhi 18:6a4db94011d3 7016 /* Bit 0 : NVMC is ready or busy */
sahilmgandhi 18:6a4db94011d3 7017 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 7018 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 7019 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
sahilmgandhi 18:6a4db94011d3 7020 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
sahilmgandhi 18:6a4db94011d3 7021
sahilmgandhi 18:6a4db94011d3 7022 /* Register: NVMC_CONFIG */
sahilmgandhi 18:6a4db94011d3 7023 /* Description: Configuration register */
sahilmgandhi 18:6a4db94011d3 7024
sahilmgandhi 18:6a4db94011d3 7025 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
sahilmgandhi 18:6a4db94011d3 7026 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
sahilmgandhi 18:6a4db94011d3 7027 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
sahilmgandhi 18:6a4db94011d3 7028 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
sahilmgandhi 18:6a4db94011d3 7029 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
sahilmgandhi 18:6a4db94011d3 7030 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
sahilmgandhi 18:6a4db94011d3 7031
sahilmgandhi 18:6a4db94011d3 7032 /* Register: NVMC_ERASEPAGE */
sahilmgandhi 18:6a4db94011d3 7033 /* Description: Register for erasing a page in Code area */
sahilmgandhi 18:6a4db94011d3 7034
sahilmgandhi 18:6a4db94011d3 7035 /* Bits 31..0 : Register for starting erase of a page in Code area */
sahilmgandhi 18:6a4db94011d3 7036 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
sahilmgandhi 18:6a4db94011d3 7037 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
sahilmgandhi 18:6a4db94011d3 7038
sahilmgandhi 18:6a4db94011d3 7039 /* Register: NVMC_ERASEPCR1 */
sahilmgandhi 18:6a4db94011d3 7040 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
sahilmgandhi 18:6a4db94011d3 7041
sahilmgandhi 18:6a4db94011d3 7042 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
sahilmgandhi 18:6a4db94011d3 7043 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
sahilmgandhi 18:6a4db94011d3 7044 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
sahilmgandhi 18:6a4db94011d3 7045
sahilmgandhi 18:6a4db94011d3 7046 /* Register: NVMC_ERASEALL */
sahilmgandhi 18:6a4db94011d3 7047 /* Description: Register for erasing all non-volatile user memory */
sahilmgandhi 18:6a4db94011d3 7048
sahilmgandhi 18:6a4db94011d3 7049 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
sahilmgandhi 18:6a4db94011d3 7050 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
sahilmgandhi 18:6a4db94011d3 7051 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
sahilmgandhi 18:6a4db94011d3 7052 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
sahilmgandhi 18:6a4db94011d3 7053 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
sahilmgandhi 18:6a4db94011d3 7054
sahilmgandhi 18:6a4db94011d3 7055 /* Register: NVMC_ERASEPCR0 */
sahilmgandhi 18:6a4db94011d3 7056 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
sahilmgandhi 18:6a4db94011d3 7057
sahilmgandhi 18:6a4db94011d3 7058 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
sahilmgandhi 18:6a4db94011d3 7059 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
sahilmgandhi 18:6a4db94011d3 7060 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
sahilmgandhi 18:6a4db94011d3 7061
sahilmgandhi 18:6a4db94011d3 7062 /* Register: NVMC_ERASEUICR */
sahilmgandhi 18:6a4db94011d3 7063 /* Description: Register for erasing User Information Configuration Registers */
sahilmgandhi 18:6a4db94011d3 7064
sahilmgandhi 18:6a4db94011d3 7065 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
sahilmgandhi 18:6a4db94011d3 7066 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
sahilmgandhi 18:6a4db94011d3 7067 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
sahilmgandhi 18:6a4db94011d3 7068 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
sahilmgandhi 18:6a4db94011d3 7069 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
sahilmgandhi 18:6a4db94011d3 7070
sahilmgandhi 18:6a4db94011d3 7071 /* Register: NVMC_ICACHECNF */
sahilmgandhi 18:6a4db94011d3 7072 /* Description: I-Code cache configuration register. */
sahilmgandhi 18:6a4db94011d3 7073
sahilmgandhi 18:6a4db94011d3 7074 /* Bit 8 : Cache profiling enable */
sahilmgandhi 18:6a4db94011d3 7075 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
sahilmgandhi 18:6a4db94011d3 7076 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
sahilmgandhi 18:6a4db94011d3 7077 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
sahilmgandhi 18:6a4db94011d3 7078 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
sahilmgandhi 18:6a4db94011d3 7079
sahilmgandhi 18:6a4db94011d3 7080 /* Bit 0 : Cache enable */
sahilmgandhi 18:6a4db94011d3 7081 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
sahilmgandhi 18:6a4db94011d3 7082 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
sahilmgandhi 18:6a4db94011d3 7083 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
sahilmgandhi 18:6a4db94011d3 7084 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
sahilmgandhi 18:6a4db94011d3 7085
sahilmgandhi 18:6a4db94011d3 7086 /* Register: NVMC_IHIT */
sahilmgandhi 18:6a4db94011d3 7087 /* Description: I-Code cache hit counter. */
sahilmgandhi 18:6a4db94011d3 7088
sahilmgandhi 18:6a4db94011d3 7089 /* Bits 31..0 : Number of cache hits */
sahilmgandhi 18:6a4db94011d3 7090 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
sahilmgandhi 18:6a4db94011d3 7091 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
sahilmgandhi 18:6a4db94011d3 7092
sahilmgandhi 18:6a4db94011d3 7093 /* Register: NVMC_IMISS */
sahilmgandhi 18:6a4db94011d3 7094 /* Description: I-Code cache miss counter. */
sahilmgandhi 18:6a4db94011d3 7095
sahilmgandhi 18:6a4db94011d3 7096 /* Bits 31..0 : Number of cache misses */
sahilmgandhi 18:6a4db94011d3 7097 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
sahilmgandhi 18:6a4db94011d3 7098 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
sahilmgandhi 18:6a4db94011d3 7099
sahilmgandhi 18:6a4db94011d3 7100
sahilmgandhi 18:6a4db94011d3 7101 /* Peripheral: GPIO */
sahilmgandhi 18:6a4db94011d3 7102 /* Description: GPIO Port 1 */
sahilmgandhi 18:6a4db94011d3 7103
sahilmgandhi 18:6a4db94011d3 7104 /* Register: GPIO_OUT */
sahilmgandhi 18:6a4db94011d3 7105 /* Description: Write GPIO port */
sahilmgandhi 18:6a4db94011d3 7106
sahilmgandhi 18:6a4db94011d3 7107 /* Bit 31 : P0.31 pin */
sahilmgandhi 18:6a4db94011d3 7108 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7109 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7110 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7111 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7112
sahilmgandhi 18:6a4db94011d3 7113 /* Bit 30 : P0.30 pin */
sahilmgandhi 18:6a4db94011d3 7114 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7115 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7116 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7117 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7118
sahilmgandhi 18:6a4db94011d3 7119 /* Bit 29 : P0.29 pin */
sahilmgandhi 18:6a4db94011d3 7120 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7121 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7122 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7123 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7124
sahilmgandhi 18:6a4db94011d3 7125 /* Bit 28 : P0.28 pin */
sahilmgandhi 18:6a4db94011d3 7126 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7127 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7128 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7129 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7130
sahilmgandhi 18:6a4db94011d3 7131 /* Bit 27 : P0.27 pin */
sahilmgandhi 18:6a4db94011d3 7132 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7133 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7134 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7135 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7136
sahilmgandhi 18:6a4db94011d3 7137 /* Bit 26 : P0.26 pin */
sahilmgandhi 18:6a4db94011d3 7138 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7139 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7140 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7141 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7142
sahilmgandhi 18:6a4db94011d3 7143 /* Bit 25 : P0.25 pin */
sahilmgandhi 18:6a4db94011d3 7144 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7145 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7146 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7147 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7148
sahilmgandhi 18:6a4db94011d3 7149 /* Bit 24 : P0.24 pin */
sahilmgandhi 18:6a4db94011d3 7150 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7151 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7152 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7153 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7154
sahilmgandhi 18:6a4db94011d3 7155 /* Bit 23 : P0.23 pin */
sahilmgandhi 18:6a4db94011d3 7156 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7157 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7158 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7159 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7160
sahilmgandhi 18:6a4db94011d3 7161 /* Bit 22 : P0.22 pin */
sahilmgandhi 18:6a4db94011d3 7162 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7163 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7164 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7165 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7166
sahilmgandhi 18:6a4db94011d3 7167 /* Bit 21 : P0.21 pin */
sahilmgandhi 18:6a4db94011d3 7168 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7169 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7170 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7171 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7172
sahilmgandhi 18:6a4db94011d3 7173 /* Bit 20 : P0.20 pin */
sahilmgandhi 18:6a4db94011d3 7174 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7175 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7176 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7177 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7178
sahilmgandhi 18:6a4db94011d3 7179 /* Bit 19 : P0.19 pin */
sahilmgandhi 18:6a4db94011d3 7180 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7181 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7182 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7183 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7184
sahilmgandhi 18:6a4db94011d3 7185 /* Bit 18 : P0.18 pin */
sahilmgandhi 18:6a4db94011d3 7186 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7187 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7188 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7189 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7190
sahilmgandhi 18:6a4db94011d3 7191 /* Bit 17 : P0.17 pin */
sahilmgandhi 18:6a4db94011d3 7192 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7193 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7194 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7195 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7196
sahilmgandhi 18:6a4db94011d3 7197 /* Bit 16 : P0.16 pin */
sahilmgandhi 18:6a4db94011d3 7198 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7199 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7200 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7201 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7202
sahilmgandhi 18:6a4db94011d3 7203 /* Bit 15 : P0.15 pin */
sahilmgandhi 18:6a4db94011d3 7204 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7205 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7206 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7207 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7208
sahilmgandhi 18:6a4db94011d3 7209 /* Bit 14 : P0.14 pin */
sahilmgandhi 18:6a4db94011d3 7210 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7211 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7212 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7213 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7214
sahilmgandhi 18:6a4db94011d3 7215 /* Bit 13 : P0.13 pin */
sahilmgandhi 18:6a4db94011d3 7216 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7217 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7218 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7219 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7220
sahilmgandhi 18:6a4db94011d3 7221 /* Bit 12 : P0.12 pin */
sahilmgandhi 18:6a4db94011d3 7222 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7223 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7224 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7225 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7226
sahilmgandhi 18:6a4db94011d3 7227 /* Bit 11 : P0.11 pin */
sahilmgandhi 18:6a4db94011d3 7228 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7229 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7230 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7231 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7232
sahilmgandhi 18:6a4db94011d3 7233 /* Bit 10 : P0.10 pin */
sahilmgandhi 18:6a4db94011d3 7234 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7235 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7236 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7237 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7238
sahilmgandhi 18:6a4db94011d3 7239 /* Bit 9 : P0.9 pin */
sahilmgandhi 18:6a4db94011d3 7240 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7241 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7242 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7243 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7244
sahilmgandhi 18:6a4db94011d3 7245 /* Bit 8 : P0.8 pin */
sahilmgandhi 18:6a4db94011d3 7246 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7247 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7248 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7249 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7250
sahilmgandhi 18:6a4db94011d3 7251 /* Bit 7 : P0.7 pin */
sahilmgandhi 18:6a4db94011d3 7252 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7253 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7254 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7255 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7256
sahilmgandhi 18:6a4db94011d3 7257 /* Bit 6 : P0.6 pin */
sahilmgandhi 18:6a4db94011d3 7258 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7259 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7260 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7261 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7262
sahilmgandhi 18:6a4db94011d3 7263 /* Bit 5 : P0.5 pin */
sahilmgandhi 18:6a4db94011d3 7264 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7265 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7266 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7267 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7268
sahilmgandhi 18:6a4db94011d3 7269 /* Bit 4 : P0.4 pin */
sahilmgandhi 18:6a4db94011d3 7270 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7271 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7272 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7273 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7274
sahilmgandhi 18:6a4db94011d3 7275 /* Bit 3 : P0.3 pin */
sahilmgandhi 18:6a4db94011d3 7276 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7277 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7278 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7279 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7280
sahilmgandhi 18:6a4db94011d3 7281 /* Bit 2 : P0.2 pin */
sahilmgandhi 18:6a4db94011d3 7282 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7283 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7284 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7285 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7286
sahilmgandhi 18:6a4db94011d3 7287 /* Bit 1 : P0.1 pin */
sahilmgandhi 18:6a4db94011d3 7288 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7289 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7290 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7291 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7292
sahilmgandhi 18:6a4db94011d3 7293 /* Bit 0 : P0.0 pin */
sahilmgandhi 18:6a4db94011d3 7294 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7295 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7296 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
sahilmgandhi 18:6a4db94011d3 7297 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
sahilmgandhi 18:6a4db94011d3 7298
sahilmgandhi 18:6a4db94011d3 7299 /* Register: GPIO_OUTSET */
sahilmgandhi 18:6a4db94011d3 7300 /* Description: Set individual bits in GPIO port */
sahilmgandhi 18:6a4db94011d3 7301
sahilmgandhi 18:6a4db94011d3 7302 /* Bit 31 : P0.31 pin */
sahilmgandhi 18:6a4db94011d3 7303 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7304 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7305 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7306 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7307 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7308
sahilmgandhi 18:6a4db94011d3 7309 /* Bit 30 : P0.30 pin */
sahilmgandhi 18:6a4db94011d3 7310 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7311 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7312 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7313 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7314 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7315
sahilmgandhi 18:6a4db94011d3 7316 /* Bit 29 : P0.29 pin */
sahilmgandhi 18:6a4db94011d3 7317 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7318 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7319 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7320 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7321 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7322
sahilmgandhi 18:6a4db94011d3 7323 /* Bit 28 : P0.28 pin */
sahilmgandhi 18:6a4db94011d3 7324 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7325 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7326 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7327 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7328 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7329
sahilmgandhi 18:6a4db94011d3 7330 /* Bit 27 : P0.27 pin */
sahilmgandhi 18:6a4db94011d3 7331 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7332 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7333 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7334 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7335 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7336
sahilmgandhi 18:6a4db94011d3 7337 /* Bit 26 : P0.26 pin */
sahilmgandhi 18:6a4db94011d3 7338 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7339 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7340 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7341 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7342 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7343
sahilmgandhi 18:6a4db94011d3 7344 /* Bit 25 : P0.25 pin */
sahilmgandhi 18:6a4db94011d3 7345 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7346 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7347 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7348 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7349 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7350
sahilmgandhi 18:6a4db94011d3 7351 /* Bit 24 : P0.24 pin */
sahilmgandhi 18:6a4db94011d3 7352 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7353 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7354 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7355 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7356 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7357
sahilmgandhi 18:6a4db94011d3 7358 /* Bit 23 : P0.23 pin */
sahilmgandhi 18:6a4db94011d3 7359 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7360 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7361 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7362 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7363 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7364
sahilmgandhi 18:6a4db94011d3 7365 /* Bit 22 : P0.22 pin */
sahilmgandhi 18:6a4db94011d3 7366 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7367 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7368 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7369 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7370 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7371
sahilmgandhi 18:6a4db94011d3 7372 /* Bit 21 : P0.21 pin */
sahilmgandhi 18:6a4db94011d3 7373 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7374 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7375 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7376 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7377 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7378
sahilmgandhi 18:6a4db94011d3 7379 /* Bit 20 : P0.20 pin */
sahilmgandhi 18:6a4db94011d3 7380 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7381 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7382 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7383 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7384 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7385
sahilmgandhi 18:6a4db94011d3 7386 /* Bit 19 : P0.19 pin */
sahilmgandhi 18:6a4db94011d3 7387 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7388 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7389 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7390 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7391 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7392
sahilmgandhi 18:6a4db94011d3 7393 /* Bit 18 : P0.18 pin */
sahilmgandhi 18:6a4db94011d3 7394 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7395 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7396 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7397 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7398 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7399
sahilmgandhi 18:6a4db94011d3 7400 /* Bit 17 : P0.17 pin */
sahilmgandhi 18:6a4db94011d3 7401 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7402 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7403 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7404 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7405 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7406
sahilmgandhi 18:6a4db94011d3 7407 /* Bit 16 : P0.16 pin */
sahilmgandhi 18:6a4db94011d3 7408 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7409 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7410 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7411 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7412 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7413
sahilmgandhi 18:6a4db94011d3 7414 /* Bit 15 : P0.15 pin */
sahilmgandhi 18:6a4db94011d3 7415 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7416 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7417 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7418 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7419 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7420
sahilmgandhi 18:6a4db94011d3 7421 /* Bit 14 : P0.14 pin */
sahilmgandhi 18:6a4db94011d3 7422 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7423 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7424 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7425 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7426 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7427
sahilmgandhi 18:6a4db94011d3 7428 /* Bit 13 : P0.13 pin */
sahilmgandhi 18:6a4db94011d3 7429 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7430 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7431 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7432 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7433 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7434
sahilmgandhi 18:6a4db94011d3 7435 /* Bit 12 : P0.12 pin */
sahilmgandhi 18:6a4db94011d3 7436 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7437 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7438 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7439 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7440 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7441
sahilmgandhi 18:6a4db94011d3 7442 /* Bit 11 : P0.11 pin */
sahilmgandhi 18:6a4db94011d3 7443 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7444 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7445 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7446 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7447 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7448
sahilmgandhi 18:6a4db94011d3 7449 /* Bit 10 : P0.10 pin */
sahilmgandhi 18:6a4db94011d3 7450 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7451 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7452 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7453 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7454 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7455
sahilmgandhi 18:6a4db94011d3 7456 /* Bit 9 : P0.9 pin */
sahilmgandhi 18:6a4db94011d3 7457 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7458 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7459 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7460 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7461 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7462
sahilmgandhi 18:6a4db94011d3 7463 /* Bit 8 : P0.8 pin */
sahilmgandhi 18:6a4db94011d3 7464 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7465 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7466 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7467 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7468 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7469
sahilmgandhi 18:6a4db94011d3 7470 /* Bit 7 : P0.7 pin */
sahilmgandhi 18:6a4db94011d3 7471 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7472 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7473 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7474 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7475 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7476
sahilmgandhi 18:6a4db94011d3 7477 /* Bit 6 : P0.6 pin */
sahilmgandhi 18:6a4db94011d3 7478 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7479 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7480 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7481 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7482 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7483
sahilmgandhi 18:6a4db94011d3 7484 /* Bit 5 : P0.5 pin */
sahilmgandhi 18:6a4db94011d3 7485 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7486 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7487 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7488 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7489 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7490
sahilmgandhi 18:6a4db94011d3 7491 /* Bit 4 : P0.4 pin */
sahilmgandhi 18:6a4db94011d3 7492 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7493 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7494 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7495 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7496 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7497
sahilmgandhi 18:6a4db94011d3 7498 /* Bit 3 : P0.3 pin */
sahilmgandhi 18:6a4db94011d3 7499 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7500 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7501 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7502 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7503 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7504
sahilmgandhi 18:6a4db94011d3 7505 /* Bit 2 : P0.2 pin */
sahilmgandhi 18:6a4db94011d3 7506 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7507 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7508 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7509 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7510 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7511
sahilmgandhi 18:6a4db94011d3 7512 /* Bit 1 : P0.1 pin */
sahilmgandhi 18:6a4db94011d3 7513 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7514 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7515 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7516 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7517 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7518
sahilmgandhi 18:6a4db94011d3 7519 /* Bit 0 : P0.0 pin */
sahilmgandhi 18:6a4db94011d3 7520 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7521 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7522 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7523 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7524 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7525
sahilmgandhi 18:6a4db94011d3 7526 /* Register: GPIO_OUTCLR */
sahilmgandhi 18:6a4db94011d3 7527 /* Description: Clear individual bits in GPIO port */
sahilmgandhi 18:6a4db94011d3 7528
sahilmgandhi 18:6a4db94011d3 7529 /* Bit 31 : P0.31 pin */
sahilmgandhi 18:6a4db94011d3 7530 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7531 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7532 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7533 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7534 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7535
sahilmgandhi 18:6a4db94011d3 7536 /* Bit 30 : P0.30 pin */
sahilmgandhi 18:6a4db94011d3 7537 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7538 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7539 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7540 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7541 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7542
sahilmgandhi 18:6a4db94011d3 7543 /* Bit 29 : P0.29 pin */
sahilmgandhi 18:6a4db94011d3 7544 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7545 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7546 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7547 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7548 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7549
sahilmgandhi 18:6a4db94011d3 7550 /* Bit 28 : P0.28 pin */
sahilmgandhi 18:6a4db94011d3 7551 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7552 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7553 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7554 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7555 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7556
sahilmgandhi 18:6a4db94011d3 7557 /* Bit 27 : P0.27 pin */
sahilmgandhi 18:6a4db94011d3 7558 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7559 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7560 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7561 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7562 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7563
sahilmgandhi 18:6a4db94011d3 7564 /* Bit 26 : P0.26 pin */
sahilmgandhi 18:6a4db94011d3 7565 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7566 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7567 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7568 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7569 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7570
sahilmgandhi 18:6a4db94011d3 7571 /* Bit 25 : P0.25 pin */
sahilmgandhi 18:6a4db94011d3 7572 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7573 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7574 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7575 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7576 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7577
sahilmgandhi 18:6a4db94011d3 7578 /* Bit 24 : P0.24 pin */
sahilmgandhi 18:6a4db94011d3 7579 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7580 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7581 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7582 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7583 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7584
sahilmgandhi 18:6a4db94011d3 7585 /* Bit 23 : P0.23 pin */
sahilmgandhi 18:6a4db94011d3 7586 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7587 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7588 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7589 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7590 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7591
sahilmgandhi 18:6a4db94011d3 7592 /* Bit 22 : P0.22 pin */
sahilmgandhi 18:6a4db94011d3 7593 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7594 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7595 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7596 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7597 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7598
sahilmgandhi 18:6a4db94011d3 7599 /* Bit 21 : P0.21 pin */
sahilmgandhi 18:6a4db94011d3 7600 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7601 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7602 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7603 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7604 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7605
sahilmgandhi 18:6a4db94011d3 7606 /* Bit 20 : P0.20 pin */
sahilmgandhi 18:6a4db94011d3 7607 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7608 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7609 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7610 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7611 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7612
sahilmgandhi 18:6a4db94011d3 7613 /* Bit 19 : P0.19 pin */
sahilmgandhi 18:6a4db94011d3 7614 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7615 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7616 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7617 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7618 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7619
sahilmgandhi 18:6a4db94011d3 7620 /* Bit 18 : P0.18 pin */
sahilmgandhi 18:6a4db94011d3 7621 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7622 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7623 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7624 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7625 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7626
sahilmgandhi 18:6a4db94011d3 7627 /* Bit 17 : P0.17 pin */
sahilmgandhi 18:6a4db94011d3 7628 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7629 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7630 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7631 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7632 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7633
sahilmgandhi 18:6a4db94011d3 7634 /* Bit 16 : P0.16 pin */
sahilmgandhi 18:6a4db94011d3 7635 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7636 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7637 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7638 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7639 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7640
sahilmgandhi 18:6a4db94011d3 7641 /* Bit 15 : P0.15 pin */
sahilmgandhi 18:6a4db94011d3 7642 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7643 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7644 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7645 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7646 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7647
sahilmgandhi 18:6a4db94011d3 7648 /* Bit 14 : P0.14 pin */
sahilmgandhi 18:6a4db94011d3 7649 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7650 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7651 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7652 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7653 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7654
sahilmgandhi 18:6a4db94011d3 7655 /* Bit 13 : P0.13 pin */
sahilmgandhi 18:6a4db94011d3 7656 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7657 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7658 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7659 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7660 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7661
sahilmgandhi 18:6a4db94011d3 7662 /* Bit 12 : P0.12 pin */
sahilmgandhi 18:6a4db94011d3 7663 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7664 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7665 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7666 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7667 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7668
sahilmgandhi 18:6a4db94011d3 7669 /* Bit 11 : P0.11 pin */
sahilmgandhi 18:6a4db94011d3 7670 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7671 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7672 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7673 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7674 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7675
sahilmgandhi 18:6a4db94011d3 7676 /* Bit 10 : P0.10 pin */
sahilmgandhi 18:6a4db94011d3 7677 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7678 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7679 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7680 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7681 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7682
sahilmgandhi 18:6a4db94011d3 7683 /* Bit 9 : P0.9 pin */
sahilmgandhi 18:6a4db94011d3 7684 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7685 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7686 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7687 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7688 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7689
sahilmgandhi 18:6a4db94011d3 7690 /* Bit 8 : P0.8 pin */
sahilmgandhi 18:6a4db94011d3 7691 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7692 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7693 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7694 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7695 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7696
sahilmgandhi 18:6a4db94011d3 7697 /* Bit 7 : P0.7 pin */
sahilmgandhi 18:6a4db94011d3 7698 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7699 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7700 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7701 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7702 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7703
sahilmgandhi 18:6a4db94011d3 7704 /* Bit 6 : P0.6 pin */
sahilmgandhi 18:6a4db94011d3 7705 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7706 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7707 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7708 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7709 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7710
sahilmgandhi 18:6a4db94011d3 7711 /* Bit 5 : P0.5 pin */
sahilmgandhi 18:6a4db94011d3 7712 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7713 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7714 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7715 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7716 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7717
sahilmgandhi 18:6a4db94011d3 7718 /* Bit 4 : P0.4 pin */
sahilmgandhi 18:6a4db94011d3 7719 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7720 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7721 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7722 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7723 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7724
sahilmgandhi 18:6a4db94011d3 7725 /* Bit 3 : P0.3 pin */
sahilmgandhi 18:6a4db94011d3 7726 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7727 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7728 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7729 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7730 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7731
sahilmgandhi 18:6a4db94011d3 7732 /* Bit 2 : P0.2 pin */
sahilmgandhi 18:6a4db94011d3 7733 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7734 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7735 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7736 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7737 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7738
sahilmgandhi 18:6a4db94011d3 7739 /* Bit 1 : P0.1 pin */
sahilmgandhi 18:6a4db94011d3 7740 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7741 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7742 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7743 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7744 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7745
sahilmgandhi 18:6a4db94011d3 7746 /* Bit 0 : P0.0 pin */
sahilmgandhi 18:6a4db94011d3 7747 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7748 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7749 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
sahilmgandhi 18:6a4db94011d3 7750 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
sahilmgandhi 18:6a4db94011d3 7751 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 7752
sahilmgandhi 18:6a4db94011d3 7753 /* Register: GPIO_IN */
sahilmgandhi 18:6a4db94011d3 7754 /* Description: Read GPIO port */
sahilmgandhi 18:6a4db94011d3 7755
sahilmgandhi 18:6a4db94011d3 7756 /* Bit 31 : P0.31 pin */
sahilmgandhi 18:6a4db94011d3 7757 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7758 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7759 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7760 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7761
sahilmgandhi 18:6a4db94011d3 7762 /* Bit 30 : P0.30 pin */
sahilmgandhi 18:6a4db94011d3 7763 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7764 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7765 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7766 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7767
sahilmgandhi 18:6a4db94011d3 7768 /* Bit 29 : P0.29 pin */
sahilmgandhi 18:6a4db94011d3 7769 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7770 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7771 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7772 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7773
sahilmgandhi 18:6a4db94011d3 7774 /* Bit 28 : P0.28 pin */
sahilmgandhi 18:6a4db94011d3 7775 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7776 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7777 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7778 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7779
sahilmgandhi 18:6a4db94011d3 7780 /* Bit 27 : P0.27 pin */
sahilmgandhi 18:6a4db94011d3 7781 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7782 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7783 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7784 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7785
sahilmgandhi 18:6a4db94011d3 7786 /* Bit 26 : P0.26 pin */
sahilmgandhi 18:6a4db94011d3 7787 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7788 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7789 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7790 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7791
sahilmgandhi 18:6a4db94011d3 7792 /* Bit 25 : P0.25 pin */
sahilmgandhi 18:6a4db94011d3 7793 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7794 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7795 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7796 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7797
sahilmgandhi 18:6a4db94011d3 7798 /* Bit 24 : P0.24 pin */
sahilmgandhi 18:6a4db94011d3 7799 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7800 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7801 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7802 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7803
sahilmgandhi 18:6a4db94011d3 7804 /* Bit 23 : P0.23 pin */
sahilmgandhi 18:6a4db94011d3 7805 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7806 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 7807 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7808 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7809
sahilmgandhi 18:6a4db94011d3 7810 /* Bit 22 : P0.22 pin */
sahilmgandhi 18:6a4db94011d3 7811 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7812 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 7813 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7814 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7815
sahilmgandhi 18:6a4db94011d3 7816 /* Bit 21 : P0.21 pin */
sahilmgandhi 18:6a4db94011d3 7817 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7818 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 7819 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7820 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7821
sahilmgandhi 18:6a4db94011d3 7822 /* Bit 20 : P0.20 pin */
sahilmgandhi 18:6a4db94011d3 7823 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7824 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 7825 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7826 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7827
sahilmgandhi 18:6a4db94011d3 7828 /* Bit 19 : P0.19 pin */
sahilmgandhi 18:6a4db94011d3 7829 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7830 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 7831 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7832 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7833
sahilmgandhi 18:6a4db94011d3 7834 /* Bit 18 : P0.18 pin */
sahilmgandhi 18:6a4db94011d3 7835 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7836 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 7837 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7838 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7839
sahilmgandhi 18:6a4db94011d3 7840 /* Bit 17 : P0.17 pin */
sahilmgandhi 18:6a4db94011d3 7841 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7842 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 7843 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7844 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7845
sahilmgandhi 18:6a4db94011d3 7846 /* Bit 16 : P0.16 pin */
sahilmgandhi 18:6a4db94011d3 7847 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7848 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 7849 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7850 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7851
sahilmgandhi 18:6a4db94011d3 7852 /* Bit 15 : P0.15 pin */
sahilmgandhi 18:6a4db94011d3 7853 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7854 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 7855 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7856 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7857
sahilmgandhi 18:6a4db94011d3 7858 /* Bit 14 : P0.14 pin */
sahilmgandhi 18:6a4db94011d3 7859 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7860 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 7861 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7862 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7863
sahilmgandhi 18:6a4db94011d3 7864 /* Bit 13 : P0.13 pin */
sahilmgandhi 18:6a4db94011d3 7865 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7866 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 7867 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7868 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7869
sahilmgandhi 18:6a4db94011d3 7870 /* Bit 12 : P0.12 pin */
sahilmgandhi 18:6a4db94011d3 7871 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7872 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 7873 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7874 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7875
sahilmgandhi 18:6a4db94011d3 7876 /* Bit 11 : P0.11 pin */
sahilmgandhi 18:6a4db94011d3 7877 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7878 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 7879 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7880 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7881
sahilmgandhi 18:6a4db94011d3 7882 /* Bit 10 : P0.10 pin */
sahilmgandhi 18:6a4db94011d3 7883 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7884 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 7885 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7886 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7887
sahilmgandhi 18:6a4db94011d3 7888 /* Bit 9 : P0.9 pin */
sahilmgandhi 18:6a4db94011d3 7889 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7890 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 7891 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7892 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7893
sahilmgandhi 18:6a4db94011d3 7894 /* Bit 8 : P0.8 pin */
sahilmgandhi 18:6a4db94011d3 7895 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7896 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 7897 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7898 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7899
sahilmgandhi 18:6a4db94011d3 7900 /* Bit 7 : P0.7 pin */
sahilmgandhi 18:6a4db94011d3 7901 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7902 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 7903 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7904 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7905
sahilmgandhi 18:6a4db94011d3 7906 /* Bit 6 : P0.6 pin */
sahilmgandhi 18:6a4db94011d3 7907 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7908 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 7909 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7910 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7911
sahilmgandhi 18:6a4db94011d3 7912 /* Bit 5 : P0.5 pin */
sahilmgandhi 18:6a4db94011d3 7913 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7914 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 7915 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7916 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7917
sahilmgandhi 18:6a4db94011d3 7918 /* Bit 4 : P0.4 pin */
sahilmgandhi 18:6a4db94011d3 7919 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7920 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 7921 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7922 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7923
sahilmgandhi 18:6a4db94011d3 7924 /* Bit 3 : P0.3 pin */
sahilmgandhi 18:6a4db94011d3 7925 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7926 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 7927 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7928 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7929
sahilmgandhi 18:6a4db94011d3 7930 /* Bit 2 : P0.2 pin */
sahilmgandhi 18:6a4db94011d3 7931 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7932 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 7933 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7934 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7935
sahilmgandhi 18:6a4db94011d3 7936 /* Bit 1 : P0.1 pin */
sahilmgandhi 18:6a4db94011d3 7937 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7938 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 7939 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7940 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7941
sahilmgandhi 18:6a4db94011d3 7942 /* Bit 0 : P0.0 pin */
sahilmgandhi 18:6a4db94011d3 7943 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7944 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 7945 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
sahilmgandhi 18:6a4db94011d3 7946 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
sahilmgandhi 18:6a4db94011d3 7947
sahilmgandhi 18:6a4db94011d3 7948 /* Register: GPIO_DIR */
sahilmgandhi 18:6a4db94011d3 7949 /* Description: Direction of GPIO pins */
sahilmgandhi 18:6a4db94011d3 7950
sahilmgandhi 18:6a4db94011d3 7951 /* Bit 31 : P0.31 pin */
sahilmgandhi 18:6a4db94011d3 7952 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7953 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 7954 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7955 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7956
sahilmgandhi 18:6a4db94011d3 7957 /* Bit 30 : P0.30 pin */
sahilmgandhi 18:6a4db94011d3 7958 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7959 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 7960 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7961 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7962
sahilmgandhi 18:6a4db94011d3 7963 /* Bit 29 : P0.29 pin */
sahilmgandhi 18:6a4db94011d3 7964 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7965 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 7966 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7967 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7968
sahilmgandhi 18:6a4db94011d3 7969 /* Bit 28 : P0.28 pin */
sahilmgandhi 18:6a4db94011d3 7970 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7971 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 7972 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7973 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7974
sahilmgandhi 18:6a4db94011d3 7975 /* Bit 27 : P0.27 pin */
sahilmgandhi 18:6a4db94011d3 7976 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7977 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 7978 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7979 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7980
sahilmgandhi 18:6a4db94011d3 7981 /* Bit 26 : P0.26 pin */
sahilmgandhi 18:6a4db94011d3 7982 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7983 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 7984 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7985 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7986
sahilmgandhi 18:6a4db94011d3 7987 /* Bit 25 : P0.25 pin */
sahilmgandhi 18:6a4db94011d3 7988 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7989 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 7990 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7991 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7992
sahilmgandhi 18:6a4db94011d3 7993 /* Bit 24 : P0.24 pin */
sahilmgandhi 18:6a4db94011d3 7994 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7995 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 7996 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 7997 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 7998
sahilmgandhi 18:6a4db94011d3 7999 /* Bit 23 : P0.23 pin */
sahilmgandhi 18:6a4db94011d3 8000 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8001 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8002 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8003 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8004
sahilmgandhi 18:6a4db94011d3 8005 /* Bit 22 : P0.22 pin */
sahilmgandhi 18:6a4db94011d3 8006 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8007 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8008 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8009 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8010
sahilmgandhi 18:6a4db94011d3 8011 /* Bit 21 : P0.21 pin */
sahilmgandhi 18:6a4db94011d3 8012 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8013 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8014 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8015 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8016
sahilmgandhi 18:6a4db94011d3 8017 /* Bit 20 : P0.20 pin */
sahilmgandhi 18:6a4db94011d3 8018 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8019 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8020 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8021 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8022
sahilmgandhi 18:6a4db94011d3 8023 /* Bit 19 : P0.19 pin */
sahilmgandhi 18:6a4db94011d3 8024 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8025 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8026 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8027 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8028
sahilmgandhi 18:6a4db94011d3 8029 /* Bit 18 : P0.18 pin */
sahilmgandhi 18:6a4db94011d3 8030 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8031 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8032 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8033 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8034
sahilmgandhi 18:6a4db94011d3 8035 /* Bit 17 : P0.17 pin */
sahilmgandhi 18:6a4db94011d3 8036 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8037 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8038 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8039 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8040
sahilmgandhi 18:6a4db94011d3 8041 /* Bit 16 : P0.16 pin */
sahilmgandhi 18:6a4db94011d3 8042 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8043 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8044 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8045 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8046
sahilmgandhi 18:6a4db94011d3 8047 /* Bit 15 : P0.15 pin */
sahilmgandhi 18:6a4db94011d3 8048 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8049 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8050 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8051 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8052
sahilmgandhi 18:6a4db94011d3 8053 /* Bit 14 : P0.14 pin */
sahilmgandhi 18:6a4db94011d3 8054 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8055 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8056 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8057 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8058
sahilmgandhi 18:6a4db94011d3 8059 /* Bit 13 : P0.13 pin */
sahilmgandhi 18:6a4db94011d3 8060 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8061 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8062 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8063 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8064
sahilmgandhi 18:6a4db94011d3 8065 /* Bit 12 : P0.12 pin */
sahilmgandhi 18:6a4db94011d3 8066 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8067 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8068 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8069 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8070
sahilmgandhi 18:6a4db94011d3 8071 /* Bit 11 : P0.11 pin */
sahilmgandhi 18:6a4db94011d3 8072 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8073 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8074 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8075 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8076
sahilmgandhi 18:6a4db94011d3 8077 /* Bit 10 : P0.10 pin */
sahilmgandhi 18:6a4db94011d3 8078 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8079 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8080 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8081 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8082
sahilmgandhi 18:6a4db94011d3 8083 /* Bit 9 : P0.9 pin */
sahilmgandhi 18:6a4db94011d3 8084 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8085 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8086 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8087 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8088
sahilmgandhi 18:6a4db94011d3 8089 /* Bit 8 : P0.8 pin */
sahilmgandhi 18:6a4db94011d3 8090 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8091 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8092 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8093 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8094
sahilmgandhi 18:6a4db94011d3 8095 /* Bit 7 : P0.7 pin */
sahilmgandhi 18:6a4db94011d3 8096 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8097 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8098 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8099 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8100
sahilmgandhi 18:6a4db94011d3 8101 /* Bit 6 : P0.6 pin */
sahilmgandhi 18:6a4db94011d3 8102 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8103 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8104 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8105 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8106
sahilmgandhi 18:6a4db94011d3 8107 /* Bit 5 : P0.5 pin */
sahilmgandhi 18:6a4db94011d3 8108 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8109 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8110 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8111 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8112
sahilmgandhi 18:6a4db94011d3 8113 /* Bit 4 : P0.4 pin */
sahilmgandhi 18:6a4db94011d3 8114 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8115 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8116 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8117 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8118
sahilmgandhi 18:6a4db94011d3 8119 /* Bit 3 : P0.3 pin */
sahilmgandhi 18:6a4db94011d3 8120 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8121 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8122 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8123 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8124
sahilmgandhi 18:6a4db94011d3 8125 /* Bit 2 : P0.2 pin */
sahilmgandhi 18:6a4db94011d3 8126 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8127 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8128 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8129 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8130
sahilmgandhi 18:6a4db94011d3 8131 /* Bit 1 : P0.1 pin */
sahilmgandhi 18:6a4db94011d3 8132 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8133 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8134 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8135 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8136
sahilmgandhi 18:6a4db94011d3 8137 /* Bit 0 : P0.0 pin */
sahilmgandhi 18:6a4db94011d3 8138 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8139 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8140 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
sahilmgandhi 18:6a4db94011d3 8141 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
sahilmgandhi 18:6a4db94011d3 8142
sahilmgandhi 18:6a4db94011d3 8143 /* Register: GPIO_DIRSET */
sahilmgandhi 18:6a4db94011d3 8144 /* Description: DIR set register */
sahilmgandhi 18:6a4db94011d3 8145
sahilmgandhi 18:6a4db94011d3 8146 /* Bit 31 : Set as output pin 31 */
sahilmgandhi 18:6a4db94011d3 8147 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 8148 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 8149 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8150 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8151 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8152
sahilmgandhi 18:6a4db94011d3 8153 /* Bit 30 : Set as output pin 30 */
sahilmgandhi 18:6a4db94011d3 8154 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 8155 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 8156 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8157 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8158 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8159
sahilmgandhi 18:6a4db94011d3 8160 /* Bit 29 : Set as output pin 29 */
sahilmgandhi 18:6a4db94011d3 8161 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 8162 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 8163 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8164 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8165 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8166
sahilmgandhi 18:6a4db94011d3 8167 /* Bit 28 : Set as output pin 28 */
sahilmgandhi 18:6a4db94011d3 8168 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 8169 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 8170 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8171 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8172 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8173
sahilmgandhi 18:6a4db94011d3 8174 /* Bit 27 : Set as output pin 27 */
sahilmgandhi 18:6a4db94011d3 8175 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 8176 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 8177 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8178 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8179 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8180
sahilmgandhi 18:6a4db94011d3 8181 /* Bit 26 : Set as output pin 26 */
sahilmgandhi 18:6a4db94011d3 8182 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 8183 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 8184 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8185 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8186 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8187
sahilmgandhi 18:6a4db94011d3 8188 /* Bit 25 : Set as output pin 25 */
sahilmgandhi 18:6a4db94011d3 8189 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 8190 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 8191 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8192 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8193 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8194
sahilmgandhi 18:6a4db94011d3 8195 /* Bit 24 : Set as output pin 24 */
sahilmgandhi 18:6a4db94011d3 8196 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 8197 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 8198 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8199 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8200 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8201
sahilmgandhi 18:6a4db94011d3 8202 /* Bit 23 : Set as output pin 23 */
sahilmgandhi 18:6a4db94011d3 8203 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8204 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8205 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8206 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8207 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8208
sahilmgandhi 18:6a4db94011d3 8209 /* Bit 22 : Set as output pin 22 */
sahilmgandhi 18:6a4db94011d3 8210 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8211 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8212 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8213 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8214 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8215
sahilmgandhi 18:6a4db94011d3 8216 /* Bit 21 : Set as output pin 21 */
sahilmgandhi 18:6a4db94011d3 8217 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8218 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8219 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8220 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8221 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8222
sahilmgandhi 18:6a4db94011d3 8223 /* Bit 20 : Set as output pin 20 */
sahilmgandhi 18:6a4db94011d3 8224 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8225 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8226 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8227 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8228 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8229
sahilmgandhi 18:6a4db94011d3 8230 /* Bit 19 : Set as output pin 19 */
sahilmgandhi 18:6a4db94011d3 8231 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8232 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8233 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8234 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8235 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8236
sahilmgandhi 18:6a4db94011d3 8237 /* Bit 18 : Set as output pin 18 */
sahilmgandhi 18:6a4db94011d3 8238 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8239 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8240 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8241 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8242 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8243
sahilmgandhi 18:6a4db94011d3 8244 /* Bit 17 : Set as output pin 17 */
sahilmgandhi 18:6a4db94011d3 8245 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8246 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8247 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8248 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8249 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8250
sahilmgandhi 18:6a4db94011d3 8251 /* Bit 16 : Set as output pin 16 */
sahilmgandhi 18:6a4db94011d3 8252 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8253 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8254 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8255 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8256 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8257
sahilmgandhi 18:6a4db94011d3 8258 /* Bit 15 : Set as output pin 15 */
sahilmgandhi 18:6a4db94011d3 8259 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8260 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8261 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8262 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8263 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8264
sahilmgandhi 18:6a4db94011d3 8265 /* Bit 14 : Set as output pin 14 */
sahilmgandhi 18:6a4db94011d3 8266 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8267 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8268 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8269 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8270 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8271
sahilmgandhi 18:6a4db94011d3 8272 /* Bit 13 : Set as output pin 13 */
sahilmgandhi 18:6a4db94011d3 8273 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8274 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8275 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8276 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8277 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8278
sahilmgandhi 18:6a4db94011d3 8279 /* Bit 12 : Set as output pin 12 */
sahilmgandhi 18:6a4db94011d3 8280 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8281 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8282 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8283 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8284 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8285
sahilmgandhi 18:6a4db94011d3 8286 /* Bit 11 : Set as output pin 11 */
sahilmgandhi 18:6a4db94011d3 8287 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8288 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8289 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8290 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8291 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8292
sahilmgandhi 18:6a4db94011d3 8293 /* Bit 10 : Set as output pin 10 */
sahilmgandhi 18:6a4db94011d3 8294 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8295 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8296 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8297 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8298 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8299
sahilmgandhi 18:6a4db94011d3 8300 /* Bit 9 : Set as output pin 9 */
sahilmgandhi 18:6a4db94011d3 8301 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8302 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8303 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8304 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8305 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8306
sahilmgandhi 18:6a4db94011d3 8307 /* Bit 8 : Set as output pin 8 */
sahilmgandhi 18:6a4db94011d3 8308 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8309 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8310 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8311 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8312 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8313
sahilmgandhi 18:6a4db94011d3 8314 /* Bit 7 : Set as output pin 7 */
sahilmgandhi 18:6a4db94011d3 8315 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8316 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8317 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8318 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8319 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8320
sahilmgandhi 18:6a4db94011d3 8321 /* Bit 6 : Set as output pin 6 */
sahilmgandhi 18:6a4db94011d3 8322 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8323 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8324 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8325 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8326 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8327
sahilmgandhi 18:6a4db94011d3 8328 /* Bit 5 : Set as output pin 5 */
sahilmgandhi 18:6a4db94011d3 8329 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8330 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8331 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8332 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8333 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8334
sahilmgandhi 18:6a4db94011d3 8335 /* Bit 4 : Set as output pin 4 */
sahilmgandhi 18:6a4db94011d3 8336 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8337 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8338 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8339 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8340 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8341
sahilmgandhi 18:6a4db94011d3 8342 /* Bit 3 : Set as output pin 3 */
sahilmgandhi 18:6a4db94011d3 8343 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8344 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8345 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8346 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8347 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8348
sahilmgandhi 18:6a4db94011d3 8349 /* Bit 2 : Set as output pin 2 */
sahilmgandhi 18:6a4db94011d3 8350 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8351 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8352 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8353 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8354 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8355
sahilmgandhi 18:6a4db94011d3 8356 /* Bit 1 : Set as output pin 1 */
sahilmgandhi 18:6a4db94011d3 8357 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8358 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8359 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8360 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8361 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8362
sahilmgandhi 18:6a4db94011d3 8363 /* Bit 0 : Set as output pin 0 */
sahilmgandhi 18:6a4db94011d3 8364 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8365 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8366 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8367 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8368 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8369
sahilmgandhi 18:6a4db94011d3 8370 /* Register: GPIO_DIRCLR */
sahilmgandhi 18:6a4db94011d3 8371 /* Description: DIR clear register */
sahilmgandhi 18:6a4db94011d3 8372
sahilmgandhi 18:6a4db94011d3 8373 /* Bit 31 : Set as input pin 31 */
sahilmgandhi 18:6a4db94011d3 8374 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 8375 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 8376 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8377 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8378 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8379
sahilmgandhi 18:6a4db94011d3 8380 /* Bit 30 : Set as input pin 30 */
sahilmgandhi 18:6a4db94011d3 8381 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 8382 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 8383 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8384 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8385 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8386
sahilmgandhi 18:6a4db94011d3 8387 /* Bit 29 : Set as input pin 29 */
sahilmgandhi 18:6a4db94011d3 8388 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 8389 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 8390 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8391 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8392 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8393
sahilmgandhi 18:6a4db94011d3 8394 /* Bit 28 : Set as input pin 28 */
sahilmgandhi 18:6a4db94011d3 8395 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 8396 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 8397 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8398 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8399 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8400
sahilmgandhi 18:6a4db94011d3 8401 /* Bit 27 : Set as input pin 27 */
sahilmgandhi 18:6a4db94011d3 8402 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 8403 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 8404 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8405 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8406 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8407
sahilmgandhi 18:6a4db94011d3 8408 /* Bit 26 : Set as input pin 26 */
sahilmgandhi 18:6a4db94011d3 8409 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 8410 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 8411 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8412 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8413 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8414
sahilmgandhi 18:6a4db94011d3 8415 /* Bit 25 : Set as input pin 25 */
sahilmgandhi 18:6a4db94011d3 8416 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 8417 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 8418 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8419 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8420 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8421
sahilmgandhi 18:6a4db94011d3 8422 /* Bit 24 : Set as input pin 24 */
sahilmgandhi 18:6a4db94011d3 8423 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 8424 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 8425 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8426 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8427 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8428
sahilmgandhi 18:6a4db94011d3 8429 /* Bit 23 : Set as input pin 23 */
sahilmgandhi 18:6a4db94011d3 8430 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8431 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8432 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8433 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8434 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8435
sahilmgandhi 18:6a4db94011d3 8436 /* Bit 22 : Set as input pin 22 */
sahilmgandhi 18:6a4db94011d3 8437 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8438 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8439 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8440 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8441 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8442
sahilmgandhi 18:6a4db94011d3 8443 /* Bit 21 : Set as input pin 21 */
sahilmgandhi 18:6a4db94011d3 8444 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8445 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8446 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8447 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8448 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8449
sahilmgandhi 18:6a4db94011d3 8450 /* Bit 20 : Set as input pin 20 */
sahilmgandhi 18:6a4db94011d3 8451 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8452 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8453 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8454 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8455 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8456
sahilmgandhi 18:6a4db94011d3 8457 /* Bit 19 : Set as input pin 19 */
sahilmgandhi 18:6a4db94011d3 8458 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8459 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8460 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8461 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8462 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8463
sahilmgandhi 18:6a4db94011d3 8464 /* Bit 18 : Set as input pin 18 */
sahilmgandhi 18:6a4db94011d3 8465 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8466 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8467 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8468 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8469 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8470
sahilmgandhi 18:6a4db94011d3 8471 /* Bit 17 : Set as input pin 17 */
sahilmgandhi 18:6a4db94011d3 8472 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8473 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8474 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8475 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8476 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8477
sahilmgandhi 18:6a4db94011d3 8478 /* Bit 16 : Set as input pin 16 */
sahilmgandhi 18:6a4db94011d3 8479 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8480 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8481 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8482 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8483 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8484
sahilmgandhi 18:6a4db94011d3 8485 /* Bit 15 : Set as input pin 15 */
sahilmgandhi 18:6a4db94011d3 8486 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8487 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8488 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8489 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8490 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8491
sahilmgandhi 18:6a4db94011d3 8492 /* Bit 14 : Set as input pin 14 */
sahilmgandhi 18:6a4db94011d3 8493 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8494 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8495 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8496 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8497 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8498
sahilmgandhi 18:6a4db94011d3 8499 /* Bit 13 : Set as input pin 13 */
sahilmgandhi 18:6a4db94011d3 8500 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8501 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8502 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8503 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8504 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8505
sahilmgandhi 18:6a4db94011d3 8506 /* Bit 12 : Set as input pin 12 */
sahilmgandhi 18:6a4db94011d3 8507 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8508 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8509 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8510 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8511 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8512
sahilmgandhi 18:6a4db94011d3 8513 /* Bit 11 : Set as input pin 11 */
sahilmgandhi 18:6a4db94011d3 8514 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8515 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8516 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8517 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8518 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8519
sahilmgandhi 18:6a4db94011d3 8520 /* Bit 10 : Set as input pin 10 */
sahilmgandhi 18:6a4db94011d3 8521 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8522 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8523 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8524 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8525 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8526
sahilmgandhi 18:6a4db94011d3 8527 /* Bit 9 : Set as input pin 9 */
sahilmgandhi 18:6a4db94011d3 8528 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8529 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8530 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8531 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8532 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8533
sahilmgandhi 18:6a4db94011d3 8534 /* Bit 8 : Set as input pin 8 */
sahilmgandhi 18:6a4db94011d3 8535 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8536 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8537 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8538 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8539 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8540
sahilmgandhi 18:6a4db94011d3 8541 /* Bit 7 : Set as input pin 7 */
sahilmgandhi 18:6a4db94011d3 8542 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8543 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8544 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8545 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8546 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8547
sahilmgandhi 18:6a4db94011d3 8548 /* Bit 6 : Set as input pin 6 */
sahilmgandhi 18:6a4db94011d3 8549 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8550 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8551 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8552 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8553 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8554
sahilmgandhi 18:6a4db94011d3 8555 /* Bit 5 : Set as input pin 5 */
sahilmgandhi 18:6a4db94011d3 8556 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8557 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8558 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8559 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8560 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8561
sahilmgandhi 18:6a4db94011d3 8562 /* Bit 4 : Set as input pin 4 */
sahilmgandhi 18:6a4db94011d3 8563 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8564 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8565 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8566 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8567 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8568
sahilmgandhi 18:6a4db94011d3 8569 /* Bit 3 : Set as input pin 3 */
sahilmgandhi 18:6a4db94011d3 8570 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8571 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8572 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8573 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8574 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8575
sahilmgandhi 18:6a4db94011d3 8576 /* Bit 2 : Set as input pin 2 */
sahilmgandhi 18:6a4db94011d3 8577 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8578 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8579 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8580 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8581 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8582
sahilmgandhi 18:6a4db94011d3 8583 /* Bit 1 : Set as input pin 1 */
sahilmgandhi 18:6a4db94011d3 8584 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8585 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8586 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8587 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8588 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8589
sahilmgandhi 18:6a4db94011d3 8590 /* Bit 0 : Set as input pin 0 */
sahilmgandhi 18:6a4db94011d3 8591 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8592 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8593 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
sahilmgandhi 18:6a4db94011d3 8594 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
sahilmgandhi 18:6a4db94011d3 8595 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
sahilmgandhi 18:6a4db94011d3 8596
sahilmgandhi 18:6a4db94011d3 8597 /* Register: GPIO_LATCH */
sahilmgandhi 18:6a4db94011d3 8598 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
sahilmgandhi 18:6a4db94011d3 8599
sahilmgandhi 18:6a4db94011d3 8600 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8601 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 8602 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 8603 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8604 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8605
sahilmgandhi 18:6a4db94011d3 8606 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8607 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 8608 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 8609 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8610 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8611
sahilmgandhi 18:6a4db94011d3 8612 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8613 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 8614 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 8615 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8616 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8617
sahilmgandhi 18:6a4db94011d3 8618 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8619 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 8620 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 8621 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8622 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8623
sahilmgandhi 18:6a4db94011d3 8624 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8625 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 8626 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 8627 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8628 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8629
sahilmgandhi 18:6a4db94011d3 8630 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8631 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 8632 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 8633 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8634 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8635
sahilmgandhi 18:6a4db94011d3 8636 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8637 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 8638 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 8639 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8640 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8641
sahilmgandhi 18:6a4db94011d3 8642 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8643 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 8644 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 8645 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8646 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8647
sahilmgandhi 18:6a4db94011d3 8648 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8649 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8650 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 8651 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8652 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8653
sahilmgandhi 18:6a4db94011d3 8654 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8655 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8656 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 8657 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8658 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8659
sahilmgandhi 18:6a4db94011d3 8660 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8661 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8662 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 8663 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8664 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8665
sahilmgandhi 18:6a4db94011d3 8666 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8667 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8668 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 8669 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8670 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8671
sahilmgandhi 18:6a4db94011d3 8672 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8673 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8674 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 8675 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8676 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8677
sahilmgandhi 18:6a4db94011d3 8678 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8679 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8680 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 8681 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8682 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8683
sahilmgandhi 18:6a4db94011d3 8684 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8685 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8686 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 8687 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8688 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8689
sahilmgandhi 18:6a4db94011d3 8690 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8691 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8692 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 8693 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8694 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8695
sahilmgandhi 18:6a4db94011d3 8696 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8697 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8698 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 8699 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8700 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8701
sahilmgandhi 18:6a4db94011d3 8702 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8703 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8704 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 8705 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8706 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8707
sahilmgandhi 18:6a4db94011d3 8708 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8709 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8710 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 8711 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8712 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8713
sahilmgandhi 18:6a4db94011d3 8714 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8715 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8716 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 8717 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8718 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8719
sahilmgandhi 18:6a4db94011d3 8720 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8721 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8722 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 8723 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8724 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8725
sahilmgandhi 18:6a4db94011d3 8726 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8727 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8728 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 8729 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8730 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8731
sahilmgandhi 18:6a4db94011d3 8732 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8733 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8734 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 8735 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8736 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8737
sahilmgandhi 18:6a4db94011d3 8738 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8739 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8740 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 8741 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8742 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8743
sahilmgandhi 18:6a4db94011d3 8744 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8745 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8746 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 8747 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8748 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8749
sahilmgandhi 18:6a4db94011d3 8750 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8751 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8752 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 8753 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8754 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8755
sahilmgandhi 18:6a4db94011d3 8756 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8757 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8758 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 8759 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8760 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8761
sahilmgandhi 18:6a4db94011d3 8762 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8763 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8764 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 8765 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8766 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8767
sahilmgandhi 18:6a4db94011d3 8768 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8769 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8770 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 8771 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8772 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8773
sahilmgandhi 18:6a4db94011d3 8774 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8775 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8776 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 8777 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8778 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8779
sahilmgandhi 18:6a4db94011d3 8780 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8781 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8782 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 8783 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8784 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8785
sahilmgandhi 18:6a4db94011d3 8786 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
sahilmgandhi 18:6a4db94011d3 8787 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8788 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 8789 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
sahilmgandhi 18:6a4db94011d3 8790 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
sahilmgandhi 18:6a4db94011d3 8791
sahilmgandhi 18:6a4db94011d3 8792 /* Register: GPIO_DETECTMODE */
sahilmgandhi 18:6a4db94011d3 8793 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
sahilmgandhi 18:6a4db94011d3 8794
sahilmgandhi 18:6a4db94011d3 8795 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
sahilmgandhi 18:6a4db94011d3 8796 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
sahilmgandhi 18:6a4db94011d3 8797 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
sahilmgandhi 18:6a4db94011d3 8798 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
sahilmgandhi 18:6a4db94011d3 8799 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
sahilmgandhi 18:6a4db94011d3 8800
sahilmgandhi 18:6a4db94011d3 8801 /* Register: GPIO_PIN_CNF */
sahilmgandhi 18:6a4db94011d3 8802 /* Description: Description collection[0]: Configuration of GPIO pins */
sahilmgandhi 18:6a4db94011d3 8803
sahilmgandhi 18:6a4db94011d3 8804 /* Bits 17..16 : Pin sensing mechanism */
sahilmgandhi 18:6a4db94011d3 8805 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
sahilmgandhi 18:6a4db94011d3 8806 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
sahilmgandhi 18:6a4db94011d3 8807 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 8808 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
sahilmgandhi 18:6a4db94011d3 8809 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
sahilmgandhi 18:6a4db94011d3 8810
sahilmgandhi 18:6a4db94011d3 8811 /* Bits 10..8 : Drive configuration */
sahilmgandhi 18:6a4db94011d3 8812 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
sahilmgandhi 18:6a4db94011d3 8813 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
sahilmgandhi 18:6a4db94011d3 8814 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
sahilmgandhi 18:6a4db94011d3 8815 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
sahilmgandhi 18:6a4db94011d3 8816 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
sahilmgandhi 18:6a4db94011d3 8817 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
sahilmgandhi 18:6a4db94011d3 8818 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
sahilmgandhi 18:6a4db94011d3 8819 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
sahilmgandhi 18:6a4db94011d3 8820 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
sahilmgandhi 18:6a4db94011d3 8821 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
sahilmgandhi 18:6a4db94011d3 8822
sahilmgandhi 18:6a4db94011d3 8823 /* Bits 3..2 : Pull configuration */
sahilmgandhi 18:6a4db94011d3 8824 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
sahilmgandhi 18:6a4db94011d3 8825 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
sahilmgandhi 18:6a4db94011d3 8826 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
sahilmgandhi 18:6a4db94011d3 8827 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
sahilmgandhi 18:6a4db94011d3 8828 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
sahilmgandhi 18:6a4db94011d3 8829
sahilmgandhi 18:6a4db94011d3 8830 /* Bit 1 : Connect or disconnect input buffer */
sahilmgandhi 18:6a4db94011d3 8831 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
sahilmgandhi 18:6a4db94011d3 8832 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
sahilmgandhi 18:6a4db94011d3 8833 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
sahilmgandhi 18:6a4db94011d3 8834 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
sahilmgandhi 18:6a4db94011d3 8835
sahilmgandhi 18:6a4db94011d3 8836 /* Bit 0 : Pin direction. Same physical register as DIR register */
sahilmgandhi 18:6a4db94011d3 8837 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
sahilmgandhi 18:6a4db94011d3 8838 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
sahilmgandhi 18:6a4db94011d3 8839 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
sahilmgandhi 18:6a4db94011d3 8840 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
sahilmgandhi 18:6a4db94011d3 8841
sahilmgandhi 18:6a4db94011d3 8842
sahilmgandhi 18:6a4db94011d3 8843 /* Peripheral: PDM */
sahilmgandhi 18:6a4db94011d3 8844 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
sahilmgandhi 18:6a4db94011d3 8845
sahilmgandhi 18:6a4db94011d3 8846 /* Register: PDM_INTEN */
sahilmgandhi 18:6a4db94011d3 8847 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 8848
sahilmgandhi 18:6a4db94011d3 8849 /* Bit 2 : Enable or disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 8850 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 8851 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 8852 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8853 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8854
sahilmgandhi 18:6a4db94011d3 8855 /* Bit 1 : Enable or disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 8856 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 8857 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 8858 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8859 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8860
sahilmgandhi 18:6a4db94011d3 8861 /* Bit 0 : Enable or disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 8862 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 8863 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 8864 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8865 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8866
sahilmgandhi 18:6a4db94011d3 8867 /* Register: PDM_INTENSET */
sahilmgandhi 18:6a4db94011d3 8868 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 8869
sahilmgandhi 18:6a4db94011d3 8870 /* Bit 2 : Write '1' to Enable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 8871 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 8872 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 8873 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 8874 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 8875 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8876
sahilmgandhi 18:6a4db94011d3 8877 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 8878 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 8879 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 8880 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 8881 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 8882 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8883
sahilmgandhi 18:6a4db94011d3 8884 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 8885 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 8886 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 8887 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 8888 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 8889 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8890
sahilmgandhi 18:6a4db94011d3 8891 /* Register: PDM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 8892 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 8893
sahilmgandhi 18:6a4db94011d3 8894 /* Bit 2 : Write '1' to Disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 8895 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 8896 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 8897 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 8898 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 8899 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8900
sahilmgandhi 18:6a4db94011d3 8901 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 8902 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 8903 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 8904 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 8905 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 8906 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8907
sahilmgandhi 18:6a4db94011d3 8908 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 8909 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 8910 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 8911 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 8912 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 8913 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8914
sahilmgandhi 18:6a4db94011d3 8915 /* Register: PDM_ENABLE */
sahilmgandhi 18:6a4db94011d3 8916 /* Description: PDM module enable register */
sahilmgandhi 18:6a4db94011d3 8917
sahilmgandhi 18:6a4db94011d3 8918 /* Bit 0 : Enable or disable PDM module */
sahilmgandhi 18:6a4db94011d3 8919 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 8920 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 8921 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 8922 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 8923
sahilmgandhi 18:6a4db94011d3 8924 /* Register: PDM_PDMCLKCTRL */
sahilmgandhi 18:6a4db94011d3 8925 /* Description: PDM clock generator control */
sahilmgandhi 18:6a4db94011d3 8926
sahilmgandhi 18:6a4db94011d3 8927 /* Bits 31..0 : PDM_CLK frequency */
sahilmgandhi 18:6a4db94011d3 8928 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
sahilmgandhi 18:6a4db94011d3 8929 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
sahilmgandhi 18:6a4db94011d3 8930 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
sahilmgandhi 18:6a4db94011d3 8931 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
sahilmgandhi 18:6a4db94011d3 8932 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
sahilmgandhi 18:6a4db94011d3 8933
sahilmgandhi 18:6a4db94011d3 8934 /* Register: PDM_MODE */
sahilmgandhi 18:6a4db94011d3 8935 /* Description: Defines the routing of the connected PDM microphones' signals */
sahilmgandhi 18:6a4db94011d3 8936
sahilmgandhi 18:6a4db94011d3 8937 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
sahilmgandhi 18:6a4db94011d3 8938 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
sahilmgandhi 18:6a4db94011d3 8939 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
sahilmgandhi 18:6a4db94011d3 8940 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
sahilmgandhi 18:6a4db94011d3 8941 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
sahilmgandhi 18:6a4db94011d3 8942
sahilmgandhi 18:6a4db94011d3 8943 /* Bit 0 : Mono or stereo operation */
sahilmgandhi 18:6a4db94011d3 8944 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
sahilmgandhi 18:6a4db94011d3 8945 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
sahilmgandhi 18:6a4db94011d3 8946 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
sahilmgandhi 18:6a4db94011d3 8947 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
sahilmgandhi 18:6a4db94011d3 8948
sahilmgandhi 18:6a4db94011d3 8949 /* Register: PDM_GAINL */
sahilmgandhi 18:6a4db94011d3 8950 /* Description: Left output gain adjustment */
sahilmgandhi 18:6a4db94011d3 8951
sahilmgandhi 18:6a4db94011d3 8952 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
sahilmgandhi 18:6a4db94011d3 8953 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
sahilmgandhi 18:6a4db94011d3 8954 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
sahilmgandhi 18:6a4db94011d3 8955 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
sahilmgandhi 18:6a4db94011d3 8956 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
sahilmgandhi 18:6a4db94011d3 8957 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
sahilmgandhi 18:6a4db94011d3 8958
sahilmgandhi 18:6a4db94011d3 8959 /* Register: PDM_GAINR */
sahilmgandhi 18:6a4db94011d3 8960 /* Description: Right output gain adjustment */
sahilmgandhi 18:6a4db94011d3 8961
sahilmgandhi 18:6a4db94011d3 8962 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
sahilmgandhi 18:6a4db94011d3 8963 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
sahilmgandhi 18:6a4db94011d3 8964 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
sahilmgandhi 18:6a4db94011d3 8965 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
sahilmgandhi 18:6a4db94011d3 8966 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
sahilmgandhi 18:6a4db94011d3 8967 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
sahilmgandhi 18:6a4db94011d3 8968
sahilmgandhi 18:6a4db94011d3 8969 /* Register: PDM_PSEL_CLK */
sahilmgandhi 18:6a4db94011d3 8970 /* Description: Pin number configuration for PDM CLK signal */
sahilmgandhi 18:6a4db94011d3 8971
sahilmgandhi 18:6a4db94011d3 8972 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 8973 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 8974 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 8975 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 8976 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 8977
sahilmgandhi 18:6a4db94011d3 8978 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 8979 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 8980 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 8981
sahilmgandhi 18:6a4db94011d3 8982 /* Register: PDM_PSEL_DIN */
sahilmgandhi 18:6a4db94011d3 8983 /* Description: Pin number configuration for PDM DIN signal */
sahilmgandhi 18:6a4db94011d3 8984
sahilmgandhi 18:6a4db94011d3 8985 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 8986 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 8987 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 8988 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 8989 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 8990
sahilmgandhi 18:6a4db94011d3 8991 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 8992 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 8993 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 8994
sahilmgandhi 18:6a4db94011d3 8995 /* Register: PDM_SAMPLE_PTR */
sahilmgandhi 18:6a4db94011d3 8996 /* Description: RAM address pointer to write samples to with EasyDMA */
sahilmgandhi 18:6a4db94011d3 8997
sahilmgandhi 18:6a4db94011d3 8998 /* Bits 31..0 : Address to write PDM samples to over DMA */
sahilmgandhi 18:6a4db94011d3 8999 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
sahilmgandhi 18:6a4db94011d3 9000 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
sahilmgandhi 18:6a4db94011d3 9001
sahilmgandhi 18:6a4db94011d3 9002 /* Register: PDM_SAMPLE_MAXCNT */
sahilmgandhi 18:6a4db94011d3 9003 /* Description: Number of samples to allocate memory for in EasyDMA mode */
sahilmgandhi 18:6a4db94011d3 9004
sahilmgandhi 18:6a4db94011d3 9005 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
sahilmgandhi 18:6a4db94011d3 9006 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
sahilmgandhi 18:6a4db94011d3 9007 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
sahilmgandhi 18:6a4db94011d3 9008
sahilmgandhi 18:6a4db94011d3 9009
sahilmgandhi 18:6a4db94011d3 9010 /* Peripheral: POWER */
sahilmgandhi 18:6a4db94011d3 9011 /* Description: Power control */
sahilmgandhi 18:6a4db94011d3 9012
sahilmgandhi 18:6a4db94011d3 9013 /* Register: POWER_INTENSET */
sahilmgandhi 18:6a4db94011d3 9014 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 9015
sahilmgandhi 18:6a4db94011d3 9016 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
sahilmgandhi 18:6a4db94011d3 9017 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
sahilmgandhi 18:6a4db94011d3 9018 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
sahilmgandhi 18:6a4db94011d3 9019 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 9020 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 9021 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 9022
sahilmgandhi 18:6a4db94011d3 9023 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
sahilmgandhi 18:6a4db94011d3 9024 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
sahilmgandhi 18:6a4db94011d3 9025 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
sahilmgandhi 18:6a4db94011d3 9026 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 9027 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 9028 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 9029
sahilmgandhi 18:6a4db94011d3 9030 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
sahilmgandhi 18:6a4db94011d3 9031 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 9032 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 9033 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 9034 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 9035 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 9036
sahilmgandhi 18:6a4db94011d3 9037 /* Register: POWER_INTENCLR */
sahilmgandhi 18:6a4db94011d3 9038 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 9039
sahilmgandhi 18:6a4db94011d3 9040 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
sahilmgandhi 18:6a4db94011d3 9041 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
sahilmgandhi 18:6a4db94011d3 9042 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
sahilmgandhi 18:6a4db94011d3 9043 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 9044 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 9045 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 9046
sahilmgandhi 18:6a4db94011d3 9047 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
sahilmgandhi 18:6a4db94011d3 9048 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
sahilmgandhi 18:6a4db94011d3 9049 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
sahilmgandhi 18:6a4db94011d3 9050 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 9051 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 9052 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 9053
sahilmgandhi 18:6a4db94011d3 9054 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
sahilmgandhi 18:6a4db94011d3 9055 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 9056 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 9057 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 9058 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 9059 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 9060
sahilmgandhi 18:6a4db94011d3 9061 /* Register: POWER_RESETREAS */
sahilmgandhi 18:6a4db94011d3 9062 /* Description: Reset reason */
sahilmgandhi 18:6a4db94011d3 9063
sahilmgandhi 18:6a4db94011d3 9064 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
sahilmgandhi 18:6a4db94011d3 9065 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
sahilmgandhi 18:6a4db94011d3 9066 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
sahilmgandhi 18:6a4db94011d3 9067 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9068 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9069
sahilmgandhi 18:6a4db94011d3 9070 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
sahilmgandhi 18:6a4db94011d3 9071 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
sahilmgandhi 18:6a4db94011d3 9072 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
sahilmgandhi 18:6a4db94011d3 9073 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9074 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9075
sahilmgandhi 18:6a4db94011d3 9076 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
sahilmgandhi 18:6a4db94011d3 9077 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
sahilmgandhi 18:6a4db94011d3 9078 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
sahilmgandhi 18:6a4db94011d3 9079 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9080 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9081
sahilmgandhi 18:6a4db94011d3 9082 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
sahilmgandhi 18:6a4db94011d3 9083 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
sahilmgandhi 18:6a4db94011d3 9084 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
sahilmgandhi 18:6a4db94011d3 9085 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9086 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9087
sahilmgandhi 18:6a4db94011d3 9088 /* Bit 3 : Reset from CPU lock-up detected */
sahilmgandhi 18:6a4db94011d3 9089 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
sahilmgandhi 18:6a4db94011d3 9090 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
sahilmgandhi 18:6a4db94011d3 9091 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9092 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9093
sahilmgandhi 18:6a4db94011d3 9094 /* Bit 2 : Reset from soft reset detected */
sahilmgandhi 18:6a4db94011d3 9095 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
sahilmgandhi 18:6a4db94011d3 9096 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
sahilmgandhi 18:6a4db94011d3 9097 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9098 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9099
sahilmgandhi 18:6a4db94011d3 9100 /* Bit 1 : Reset from watchdog detected */
sahilmgandhi 18:6a4db94011d3 9101 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
sahilmgandhi 18:6a4db94011d3 9102 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
sahilmgandhi 18:6a4db94011d3 9103 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9104 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9105
sahilmgandhi 18:6a4db94011d3 9106 /* Bit 0 : Reset from pin-reset detected */
sahilmgandhi 18:6a4db94011d3 9107 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
sahilmgandhi 18:6a4db94011d3 9108 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
sahilmgandhi 18:6a4db94011d3 9109 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
sahilmgandhi 18:6a4db94011d3 9110 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
sahilmgandhi 18:6a4db94011d3 9111
sahilmgandhi 18:6a4db94011d3 9112 /* Register: POWER_RAMSTATUS */
sahilmgandhi 18:6a4db94011d3 9113 /* Description: Deprecated register - RAM status register */
sahilmgandhi 18:6a4db94011d3 9114
sahilmgandhi 18:6a4db94011d3 9115 /* Bit 3 : RAM block 3 is on or off/powering up */
sahilmgandhi 18:6a4db94011d3 9116 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
sahilmgandhi 18:6a4db94011d3 9117 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
sahilmgandhi 18:6a4db94011d3 9118 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9119 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9120
sahilmgandhi 18:6a4db94011d3 9121 /* Bit 2 : RAM block 2 is on or off/powering up */
sahilmgandhi 18:6a4db94011d3 9122 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
sahilmgandhi 18:6a4db94011d3 9123 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
sahilmgandhi 18:6a4db94011d3 9124 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9125 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9126
sahilmgandhi 18:6a4db94011d3 9127 /* Bit 1 : RAM block 1 is on or off/powering up */
sahilmgandhi 18:6a4db94011d3 9128 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
sahilmgandhi 18:6a4db94011d3 9129 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
sahilmgandhi 18:6a4db94011d3 9130 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9131 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9132
sahilmgandhi 18:6a4db94011d3 9133 /* Bit 0 : RAM block 0 is on or off/powering up */
sahilmgandhi 18:6a4db94011d3 9134 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
sahilmgandhi 18:6a4db94011d3 9135 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
sahilmgandhi 18:6a4db94011d3 9136 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9137 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9138
sahilmgandhi 18:6a4db94011d3 9139 /* Register: POWER_SYSTEMOFF */
sahilmgandhi 18:6a4db94011d3 9140 /* Description: System OFF register */
sahilmgandhi 18:6a4db94011d3 9141
sahilmgandhi 18:6a4db94011d3 9142 /* Bit 0 : Enable System OFF mode */
sahilmgandhi 18:6a4db94011d3 9143 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
sahilmgandhi 18:6a4db94011d3 9144 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
sahilmgandhi 18:6a4db94011d3 9145 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
sahilmgandhi 18:6a4db94011d3 9146
sahilmgandhi 18:6a4db94011d3 9147 /* Register: POWER_POFCON */
sahilmgandhi 18:6a4db94011d3 9148 /* Description: Power failure comparator configuration */
sahilmgandhi 18:6a4db94011d3 9149
sahilmgandhi 18:6a4db94011d3 9150 /* Bits 4..1 : Power failure comparator threshold setting */
sahilmgandhi 18:6a4db94011d3 9151 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
sahilmgandhi 18:6a4db94011d3 9152 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
sahilmgandhi 18:6a4db94011d3 9153 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
sahilmgandhi 18:6a4db94011d3 9154 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
sahilmgandhi 18:6a4db94011d3 9155 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
sahilmgandhi 18:6a4db94011d3 9156 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
sahilmgandhi 18:6a4db94011d3 9157 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
sahilmgandhi 18:6a4db94011d3 9158 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
sahilmgandhi 18:6a4db94011d3 9159 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
sahilmgandhi 18:6a4db94011d3 9160 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
sahilmgandhi 18:6a4db94011d3 9161 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
sahilmgandhi 18:6a4db94011d3 9162 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
sahilmgandhi 18:6a4db94011d3 9163 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
sahilmgandhi 18:6a4db94011d3 9164 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
sahilmgandhi 18:6a4db94011d3 9165
sahilmgandhi 18:6a4db94011d3 9166 /* Bit 0 : Enable or disable power failure comparator */
sahilmgandhi 18:6a4db94011d3 9167 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
sahilmgandhi 18:6a4db94011d3 9168 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
sahilmgandhi 18:6a4db94011d3 9169 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 9170 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 9171
sahilmgandhi 18:6a4db94011d3 9172 /* Register: POWER_GPREGRET */
sahilmgandhi 18:6a4db94011d3 9173 /* Description: General purpose retention register */
sahilmgandhi 18:6a4db94011d3 9174
sahilmgandhi 18:6a4db94011d3 9175 /* Bits 7..0 : General purpose retention register */
sahilmgandhi 18:6a4db94011d3 9176 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
sahilmgandhi 18:6a4db94011d3 9177 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
sahilmgandhi 18:6a4db94011d3 9178
sahilmgandhi 18:6a4db94011d3 9179 /* Register: POWER_GPREGRET2 */
sahilmgandhi 18:6a4db94011d3 9180 /* Description: General purpose retention register */
sahilmgandhi 18:6a4db94011d3 9181
sahilmgandhi 18:6a4db94011d3 9182 /* Bits 7..0 : General purpose retention register */
sahilmgandhi 18:6a4db94011d3 9183 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
sahilmgandhi 18:6a4db94011d3 9184 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
sahilmgandhi 18:6a4db94011d3 9185
sahilmgandhi 18:6a4db94011d3 9186 /* Register: POWER_RAMON */
sahilmgandhi 18:6a4db94011d3 9187 /* Description: Deprecated register - RAM on/off register (this register is retained) */
sahilmgandhi 18:6a4db94011d3 9188
sahilmgandhi 18:6a4db94011d3 9189 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
sahilmgandhi 18:6a4db94011d3 9190 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
sahilmgandhi 18:6a4db94011d3 9191 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
sahilmgandhi 18:6a4db94011d3 9192 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9193 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9194
sahilmgandhi 18:6a4db94011d3 9195 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
sahilmgandhi 18:6a4db94011d3 9196 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
sahilmgandhi 18:6a4db94011d3 9197 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
sahilmgandhi 18:6a4db94011d3 9198 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9199 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9200
sahilmgandhi 18:6a4db94011d3 9201 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
sahilmgandhi 18:6a4db94011d3 9202 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
sahilmgandhi 18:6a4db94011d3 9203 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
sahilmgandhi 18:6a4db94011d3 9204 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9205 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9206
sahilmgandhi 18:6a4db94011d3 9207 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
sahilmgandhi 18:6a4db94011d3 9208 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
sahilmgandhi 18:6a4db94011d3 9209 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
sahilmgandhi 18:6a4db94011d3 9210 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9211 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9212
sahilmgandhi 18:6a4db94011d3 9213 /* Register: POWER_RAMONB */
sahilmgandhi 18:6a4db94011d3 9214 /* Description: Deprecated register - RAM on/off register (this register is retained) */
sahilmgandhi 18:6a4db94011d3 9215
sahilmgandhi 18:6a4db94011d3 9216 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
sahilmgandhi 18:6a4db94011d3 9217 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
sahilmgandhi 18:6a4db94011d3 9218 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
sahilmgandhi 18:6a4db94011d3 9219 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9220 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9221
sahilmgandhi 18:6a4db94011d3 9222 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
sahilmgandhi 18:6a4db94011d3 9223 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
sahilmgandhi 18:6a4db94011d3 9224 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
sahilmgandhi 18:6a4db94011d3 9225 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9226 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9227
sahilmgandhi 18:6a4db94011d3 9228 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
sahilmgandhi 18:6a4db94011d3 9229 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
sahilmgandhi 18:6a4db94011d3 9230 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
sahilmgandhi 18:6a4db94011d3 9231 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9232 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9233
sahilmgandhi 18:6a4db94011d3 9234 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
sahilmgandhi 18:6a4db94011d3 9235 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
sahilmgandhi 18:6a4db94011d3 9236 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
sahilmgandhi 18:6a4db94011d3 9237 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9238 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9239
sahilmgandhi 18:6a4db94011d3 9240 /* Register: POWER_DCDCEN */
sahilmgandhi 18:6a4db94011d3 9241 /* Description: DC/DC enable register */
sahilmgandhi 18:6a4db94011d3 9242
sahilmgandhi 18:6a4db94011d3 9243 /* Bit 0 : Enable or disable DC/DC converter */
sahilmgandhi 18:6a4db94011d3 9244 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
sahilmgandhi 18:6a4db94011d3 9245 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
sahilmgandhi 18:6a4db94011d3 9246 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 9247 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 9248
sahilmgandhi 18:6a4db94011d3 9249 /* Register: POWER_RAM_POWER */
sahilmgandhi 18:6a4db94011d3 9250 /* Description: Description cluster[0]: RAM0 power control register */
sahilmgandhi 18:6a4db94011d3 9251
sahilmgandhi 18:6a4db94011d3 9252 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
sahilmgandhi 18:6a4db94011d3 9253 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9254 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9255 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9256 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9257
sahilmgandhi 18:6a4db94011d3 9258 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
sahilmgandhi 18:6a4db94011d3 9259 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9260 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9261 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9262 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9263
sahilmgandhi 18:6a4db94011d3 9264 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
sahilmgandhi 18:6a4db94011d3 9265 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
sahilmgandhi 18:6a4db94011d3 9266 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
sahilmgandhi 18:6a4db94011d3 9267 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9268 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9269
sahilmgandhi 18:6a4db94011d3 9270 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
sahilmgandhi 18:6a4db94011d3 9271 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
sahilmgandhi 18:6a4db94011d3 9272 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
sahilmgandhi 18:6a4db94011d3 9273 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9274 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9275
sahilmgandhi 18:6a4db94011d3 9276 /* Register: POWER_RAM_POWERSET */
sahilmgandhi 18:6a4db94011d3 9277 /* Description: Description cluster[0]: RAM0 power control set register */
sahilmgandhi 18:6a4db94011d3 9278
sahilmgandhi 18:6a4db94011d3 9279 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
sahilmgandhi 18:6a4db94011d3 9280 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9281 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9282 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9283
sahilmgandhi 18:6a4db94011d3 9284 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
sahilmgandhi 18:6a4db94011d3 9285 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9286 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9287 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9288
sahilmgandhi 18:6a4db94011d3 9289 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
sahilmgandhi 18:6a4db94011d3 9290 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
sahilmgandhi 18:6a4db94011d3 9291 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
sahilmgandhi 18:6a4db94011d3 9292 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9293
sahilmgandhi 18:6a4db94011d3 9294 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
sahilmgandhi 18:6a4db94011d3 9295 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
sahilmgandhi 18:6a4db94011d3 9296 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
sahilmgandhi 18:6a4db94011d3 9297 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
sahilmgandhi 18:6a4db94011d3 9298
sahilmgandhi 18:6a4db94011d3 9299 /* Register: POWER_RAM_POWERCLR */
sahilmgandhi 18:6a4db94011d3 9300 /* Description: Description cluster[0]: RAM0 power control clear register */
sahilmgandhi 18:6a4db94011d3 9301
sahilmgandhi 18:6a4db94011d3 9302 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
sahilmgandhi 18:6a4db94011d3 9303 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9304 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9305 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9306
sahilmgandhi 18:6a4db94011d3 9307 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
sahilmgandhi 18:6a4db94011d3 9308 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9309 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
sahilmgandhi 18:6a4db94011d3 9310 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9311
sahilmgandhi 18:6a4db94011d3 9312 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
sahilmgandhi 18:6a4db94011d3 9313 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
sahilmgandhi 18:6a4db94011d3 9314 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
sahilmgandhi 18:6a4db94011d3 9315 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9316
sahilmgandhi 18:6a4db94011d3 9317 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
sahilmgandhi 18:6a4db94011d3 9318 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
sahilmgandhi 18:6a4db94011d3 9319 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
sahilmgandhi 18:6a4db94011d3 9320 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
sahilmgandhi 18:6a4db94011d3 9321
sahilmgandhi 18:6a4db94011d3 9322
sahilmgandhi 18:6a4db94011d3 9323 /* Peripheral: PPI */
sahilmgandhi 18:6a4db94011d3 9324 /* Description: Programmable Peripheral Interconnect */
sahilmgandhi 18:6a4db94011d3 9325
sahilmgandhi 18:6a4db94011d3 9326 /* Register: PPI_CHEN */
sahilmgandhi 18:6a4db94011d3 9327 /* Description: Channel enable register */
sahilmgandhi 18:6a4db94011d3 9328
sahilmgandhi 18:6a4db94011d3 9329 /* Bit 31 : Enable or disable channel 31 */
sahilmgandhi 18:6a4db94011d3 9330 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9331 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9332 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9333 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9334
sahilmgandhi 18:6a4db94011d3 9335 /* Bit 30 : Enable or disable channel 30 */
sahilmgandhi 18:6a4db94011d3 9336 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 9337 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 9338 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9339 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9340
sahilmgandhi 18:6a4db94011d3 9341 /* Bit 29 : Enable or disable channel 29 */
sahilmgandhi 18:6a4db94011d3 9342 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 9343 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 9344 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9345 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9346
sahilmgandhi 18:6a4db94011d3 9347 /* Bit 28 : Enable or disable channel 28 */
sahilmgandhi 18:6a4db94011d3 9348 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 9349 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 9350 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9351 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9352
sahilmgandhi 18:6a4db94011d3 9353 /* Bit 27 : Enable or disable channel 27 */
sahilmgandhi 18:6a4db94011d3 9354 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 9355 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 9356 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9357 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9358
sahilmgandhi 18:6a4db94011d3 9359 /* Bit 26 : Enable or disable channel 26 */
sahilmgandhi 18:6a4db94011d3 9360 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 9361 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 9362 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9363 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9364
sahilmgandhi 18:6a4db94011d3 9365 /* Bit 25 : Enable or disable channel 25 */
sahilmgandhi 18:6a4db94011d3 9366 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 9367 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 9368 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9369 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9370
sahilmgandhi 18:6a4db94011d3 9371 /* Bit 24 : Enable or disable channel 24 */
sahilmgandhi 18:6a4db94011d3 9372 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 9373 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 9374 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9375 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9376
sahilmgandhi 18:6a4db94011d3 9377 /* Bit 23 : Enable or disable channel 23 */
sahilmgandhi 18:6a4db94011d3 9378 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 9379 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 9380 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9381 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9382
sahilmgandhi 18:6a4db94011d3 9383 /* Bit 22 : Enable or disable channel 22 */
sahilmgandhi 18:6a4db94011d3 9384 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 9385 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 9386 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9387 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9388
sahilmgandhi 18:6a4db94011d3 9389 /* Bit 21 : Enable or disable channel 21 */
sahilmgandhi 18:6a4db94011d3 9390 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 9391 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 9392 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9393 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9394
sahilmgandhi 18:6a4db94011d3 9395 /* Bit 20 : Enable or disable channel 20 */
sahilmgandhi 18:6a4db94011d3 9396 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 9397 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 9398 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9399 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9400
sahilmgandhi 18:6a4db94011d3 9401 /* Bit 19 : Enable or disable channel 19 */
sahilmgandhi 18:6a4db94011d3 9402 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
sahilmgandhi 18:6a4db94011d3 9403 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
sahilmgandhi 18:6a4db94011d3 9404 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9405 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9406
sahilmgandhi 18:6a4db94011d3 9407 /* Bit 18 : Enable or disable channel 18 */
sahilmgandhi 18:6a4db94011d3 9408 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
sahilmgandhi 18:6a4db94011d3 9409 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
sahilmgandhi 18:6a4db94011d3 9410 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9411 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9412
sahilmgandhi 18:6a4db94011d3 9413 /* Bit 17 : Enable or disable channel 17 */
sahilmgandhi 18:6a4db94011d3 9414 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
sahilmgandhi 18:6a4db94011d3 9415 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
sahilmgandhi 18:6a4db94011d3 9416 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9417 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9418
sahilmgandhi 18:6a4db94011d3 9419 /* Bit 16 : Enable or disable channel 16 */
sahilmgandhi 18:6a4db94011d3 9420 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
sahilmgandhi 18:6a4db94011d3 9421 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
sahilmgandhi 18:6a4db94011d3 9422 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9423 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9424
sahilmgandhi 18:6a4db94011d3 9425 /* Bit 15 : Enable or disable channel 15 */
sahilmgandhi 18:6a4db94011d3 9426 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 9427 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 9428 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9429 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9430
sahilmgandhi 18:6a4db94011d3 9431 /* Bit 14 : Enable or disable channel 14 */
sahilmgandhi 18:6a4db94011d3 9432 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 9433 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 9434 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9435 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9436
sahilmgandhi 18:6a4db94011d3 9437 /* Bit 13 : Enable or disable channel 13 */
sahilmgandhi 18:6a4db94011d3 9438 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 9439 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 9440 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9441 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9442
sahilmgandhi 18:6a4db94011d3 9443 /* Bit 12 : Enable or disable channel 12 */
sahilmgandhi 18:6a4db94011d3 9444 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 9445 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 9446 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9447 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9448
sahilmgandhi 18:6a4db94011d3 9449 /* Bit 11 : Enable or disable channel 11 */
sahilmgandhi 18:6a4db94011d3 9450 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 9451 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 9452 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9453 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9454
sahilmgandhi 18:6a4db94011d3 9455 /* Bit 10 : Enable or disable channel 10 */
sahilmgandhi 18:6a4db94011d3 9456 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 9457 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 9458 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9459 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9460
sahilmgandhi 18:6a4db94011d3 9461 /* Bit 9 : Enable or disable channel 9 */
sahilmgandhi 18:6a4db94011d3 9462 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 9463 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 9464 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9465 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9466
sahilmgandhi 18:6a4db94011d3 9467 /* Bit 8 : Enable or disable channel 8 */
sahilmgandhi 18:6a4db94011d3 9468 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 9469 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 9470 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9471 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9472
sahilmgandhi 18:6a4db94011d3 9473 /* Bit 7 : Enable or disable channel 7 */
sahilmgandhi 18:6a4db94011d3 9474 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 9475 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 9476 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9477 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9478
sahilmgandhi 18:6a4db94011d3 9479 /* Bit 6 : Enable or disable channel 6 */
sahilmgandhi 18:6a4db94011d3 9480 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 9481 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 9482 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9483 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9484
sahilmgandhi 18:6a4db94011d3 9485 /* Bit 5 : Enable or disable channel 5 */
sahilmgandhi 18:6a4db94011d3 9486 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 9487 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 9488 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9489 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9490
sahilmgandhi 18:6a4db94011d3 9491 /* Bit 4 : Enable or disable channel 4 */
sahilmgandhi 18:6a4db94011d3 9492 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 9493 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 9494 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9495 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9496
sahilmgandhi 18:6a4db94011d3 9497 /* Bit 3 : Enable or disable channel 3 */
sahilmgandhi 18:6a4db94011d3 9498 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 9499 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 9500 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9501 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9502
sahilmgandhi 18:6a4db94011d3 9503 /* Bit 2 : Enable or disable channel 2 */
sahilmgandhi 18:6a4db94011d3 9504 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 9505 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 9506 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9507 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9508
sahilmgandhi 18:6a4db94011d3 9509 /* Bit 1 : Enable or disable channel 1 */
sahilmgandhi 18:6a4db94011d3 9510 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 9511 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 9512 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9513 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9514
sahilmgandhi 18:6a4db94011d3 9515 /* Bit 0 : Enable or disable channel 0 */
sahilmgandhi 18:6a4db94011d3 9516 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 9517 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 9518 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
sahilmgandhi 18:6a4db94011d3 9519 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
sahilmgandhi 18:6a4db94011d3 9520
sahilmgandhi 18:6a4db94011d3 9521 /* Register: PPI_CHENSET */
sahilmgandhi 18:6a4db94011d3 9522 /* Description: Channel enable set register */
sahilmgandhi 18:6a4db94011d3 9523
sahilmgandhi 18:6a4db94011d3 9524 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9525 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9526 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9527 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9528 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9529 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9530
sahilmgandhi 18:6a4db94011d3 9531 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9532 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 9533 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 9534 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9535 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9536 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9537
sahilmgandhi 18:6a4db94011d3 9538 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9539 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 9540 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 9541 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9542 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9543 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9544
sahilmgandhi 18:6a4db94011d3 9545 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9546 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 9547 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 9548 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9549 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9550 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9551
sahilmgandhi 18:6a4db94011d3 9552 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9553 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 9554 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 9555 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9556 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9557 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9558
sahilmgandhi 18:6a4db94011d3 9559 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9560 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 9561 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 9562 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9563 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9564 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9565
sahilmgandhi 18:6a4db94011d3 9566 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9567 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 9568 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 9569 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9570 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9571 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9572
sahilmgandhi 18:6a4db94011d3 9573 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9574 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 9575 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 9576 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9577 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9578 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9579
sahilmgandhi 18:6a4db94011d3 9580 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9581 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 9582 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 9583 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9584 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9585 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9586
sahilmgandhi 18:6a4db94011d3 9587 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9588 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 9589 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 9590 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9591 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9592 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9593
sahilmgandhi 18:6a4db94011d3 9594 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9595 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 9596 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 9597 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9598 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9599 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9600
sahilmgandhi 18:6a4db94011d3 9601 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9602 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 9603 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 9604 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9605 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9606 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9607
sahilmgandhi 18:6a4db94011d3 9608 /* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9609 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
sahilmgandhi 18:6a4db94011d3 9610 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
sahilmgandhi 18:6a4db94011d3 9611 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9612 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9613 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9614
sahilmgandhi 18:6a4db94011d3 9615 /* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9616 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
sahilmgandhi 18:6a4db94011d3 9617 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
sahilmgandhi 18:6a4db94011d3 9618 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9619 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9620 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9621
sahilmgandhi 18:6a4db94011d3 9622 /* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9623 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
sahilmgandhi 18:6a4db94011d3 9624 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
sahilmgandhi 18:6a4db94011d3 9625 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9626 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9627 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9628
sahilmgandhi 18:6a4db94011d3 9629 /* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9630 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
sahilmgandhi 18:6a4db94011d3 9631 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
sahilmgandhi 18:6a4db94011d3 9632 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9633 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9634 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9635
sahilmgandhi 18:6a4db94011d3 9636 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9637 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 9638 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 9639 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9640 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9641 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9642
sahilmgandhi 18:6a4db94011d3 9643 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9644 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 9645 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 9646 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9647 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9648 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9649
sahilmgandhi 18:6a4db94011d3 9650 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9651 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 9652 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 9653 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9654 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9655 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9656
sahilmgandhi 18:6a4db94011d3 9657 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9658 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 9659 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 9660 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9661 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9662 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9663
sahilmgandhi 18:6a4db94011d3 9664 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9665 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 9666 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 9667 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9668 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9669 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9670
sahilmgandhi 18:6a4db94011d3 9671 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9672 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 9673 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 9674 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9675 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9676 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9677
sahilmgandhi 18:6a4db94011d3 9678 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9679 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 9680 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 9681 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9682 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9683 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9684
sahilmgandhi 18:6a4db94011d3 9685 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9686 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 9687 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 9688 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9689 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9690 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9691
sahilmgandhi 18:6a4db94011d3 9692 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9693 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 9694 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 9695 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9696 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9697 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9698
sahilmgandhi 18:6a4db94011d3 9699 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9700 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 9701 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 9702 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9703 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9704 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9705
sahilmgandhi 18:6a4db94011d3 9706 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9707 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 9708 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 9709 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9710 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9711 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9712
sahilmgandhi 18:6a4db94011d3 9713 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9714 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 9715 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 9716 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9717 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9718 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9719
sahilmgandhi 18:6a4db94011d3 9720 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9721 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 9722 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 9723 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9724 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9725 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9726
sahilmgandhi 18:6a4db94011d3 9727 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9728 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 9729 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 9730 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9731 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9732 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9733
sahilmgandhi 18:6a4db94011d3 9734 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9735 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 9736 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 9737 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9738 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9739 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9740
sahilmgandhi 18:6a4db94011d3 9741 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9742 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 9743 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 9744 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9745 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9746 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
sahilmgandhi 18:6a4db94011d3 9747
sahilmgandhi 18:6a4db94011d3 9748 /* Register: PPI_CHENCLR */
sahilmgandhi 18:6a4db94011d3 9749 /* Description: Channel enable clear register */
sahilmgandhi 18:6a4db94011d3 9750
sahilmgandhi 18:6a4db94011d3 9751 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9752 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9753 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9754 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9755 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9756 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9757
sahilmgandhi 18:6a4db94011d3 9758 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9759 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 9760 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 9761 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9762 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9763 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9764
sahilmgandhi 18:6a4db94011d3 9765 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9766 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 9767 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 9768 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9769 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9770 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9771
sahilmgandhi 18:6a4db94011d3 9772 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9773 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 9774 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 9775 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9776 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9777 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9778
sahilmgandhi 18:6a4db94011d3 9779 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9780 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 9781 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 9782 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9783 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9784 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9785
sahilmgandhi 18:6a4db94011d3 9786 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9787 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 9788 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 9789 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9790 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9791 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9792
sahilmgandhi 18:6a4db94011d3 9793 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9794 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 9795 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 9796 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9797 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9798 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9799
sahilmgandhi 18:6a4db94011d3 9800 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9801 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 9802 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 9803 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9804 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9805 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9806
sahilmgandhi 18:6a4db94011d3 9807 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9808 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 9809 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 9810 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9811 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9812 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9813
sahilmgandhi 18:6a4db94011d3 9814 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9815 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 9816 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 9817 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9818 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9819 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9820
sahilmgandhi 18:6a4db94011d3 9821 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9822 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 9823 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 9824 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9825 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9826 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9827
sahilmgandhi 18:6a4db94011d3 9828 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9829 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 9830 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 9831 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9832 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9833 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9834
sahilmgandhi 18:6a4db94011d3 9835 /* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9836 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
sahilmgandhi 18:6a4db94011d3 9837 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
sahilmgandhi 18:6a4db94011d3 9838 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9839 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9840 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9841
sahilmgandhi 18:6a4db94011d3 9842 /* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9843 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
sahilmgandhi 18:6a4db94011d3 9844 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
sahilmgandhi 18:6a4db94011d3 9845 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9846 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9847 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9848
sahilmgandhi 18:6a4db94011d3 9849 /* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9850 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
sahilmgandhi 18:6a4db94011d3 9851 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
sahilmgandhi 18:6a4db94011d3 9852 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9853 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9854 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9855
sahilmgandhi 18:6a4db94011d3 9856 /* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9857 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
sahilmgandhi 18:6a4db94011d3 9858 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
sahilmgandhi 18:6a4db94011d3 9859 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9860 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9861 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9862
sahilmgandhi 18:6a4db94011d3 9863 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9864 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 9865 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 9866 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9867 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9868 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9869
sahilmgandhi 18:6a4db94011d3 9870 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9871 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 9872 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 9873 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9874 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9875 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9876
sahilmgandhi 18:6a4db94011d3 9877 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9878 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 9879 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 9880 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9881 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9882 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9883
sahilmgandhi 18:6a4db94011d3 9884 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9885 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 9886 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 9887 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9888 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9889 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9890
sahilmgandhi 18:6a4db94011d3 9891 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9892 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 9893 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 9894 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9895 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9896 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9897
sahilmgandhi 18:6a4db94011d3 9898 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9899 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 9900 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 9901 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9902 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9903 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9904
sahilmgandhi 18:6a4db94011d3 9905 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9906 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 9907 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 9908 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9909 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9910 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9911
sahilmgandhi 18:6a4db94011d3 9912 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9913 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 9914 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 9915 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9916 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9917 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9918
sahilmgandhi 18:6a4db94011d3 9919 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9920 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 9921 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 9922 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9923 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9924 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9925
sahilmgandhi 18:6a4db94011d3 9926 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9927 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 9928 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 9929 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9930 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9931 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9932
sahilmgandhi 18:6a4db94011d3 9933 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9934 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 9935 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 9936 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9937 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9938 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9939
sahilmgandhi 18:6a4db94011d3 9940 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9941 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 9942 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 9943 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9944 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9945 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9946
sahilmgandhi 18:6a4db94011d3 9947 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9948 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 9949 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 9950 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9951 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9952 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9953
sahilmgandhi 18:6a4db94011d3 9954 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9955 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 9956 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 9957 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9958 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9959 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9960
sahilmgandhi 18:6a4db94011d3 9961 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9962 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 9963 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 9964 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9965 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9966 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9967
sahilmgandhi 18:6a4db94011d3 9968 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
sahilmgandhi 18:6a4db94011d3 9969 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 9970 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 9971 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
sahilmgandhi 18:6a4db94011d3 9972 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
sahilmgandhi 18:6a4db94011d3 9973 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
sahilmgandhi 18:6a4db94011d3 9974
sahilmgandhi 18:6a4db94011d3 9975 /* Register: PPI_CH_EEP */
sahilmgandhi 18:6a4db94011d3 9976 /* Description: Description cluster[0]: Channel 0 event end-point */
sahilmgandhi 18:6a4db94011d3 9977
sahilmgandhi 18:6a4db94011d3 9978 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
sahilmgandhi 18:6a4db94011d3 9979 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
sahilmgandhi 18:6a4db94011d3 9980 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
sahilmgandhi 18:6a4db94011d3 9981
sahilmgandhi 18:6a4db94011d3 9982 /* Register: PPI_CH_TEP */
sahilmgandhi 18:6a4db94011d3 9983 /* Description: Description cluster[0]: Channel 0 task end-point */
sahilmgandhi 18:6a4db94011d3 9984
sahilmgandhi 18:6a4db94011d3 9985 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
sahilmgandhi 18:6a4db94011d3 9986 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
sahilmgandhi 18:6a4db94011d3 9987 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
sahilmgandhi 18:6a4db94011d3 9988
sahilmgandhi 18:6a4db94011d3 9989 /* Register: PPI_CHG */
sahilmgandhi 18:6a4db94011d3 9990 /* Description: Description collection[0]: Channel group 0 */
sahilmgandhi 18:6a4db94011d3 9991
sahilmgandhi 18:6a4db94011d3 9992 /* Bit 31 : Include or exclude channel 31 */
sahilmgandhi 18:6a4db94011d3 9993 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9994 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 9995 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 9996 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 9997
sahilmgandhi 18:6a4db94011d3 9998 /* Bit 30 : Include or exclude channel 30 */
sahilmgandhi 18:6a4db94011d3 9999 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 10000 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 10001 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10002 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10003
sahilmgandhi 18:6a4db94011d3 10004 /* Bit 29 : Include or exclude channel 29 */
sahilmgandhi 18:6a4db94011d3 10005 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 10006 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 10007 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10008 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10009
sahilmgandhi 18:6a4db94011d3 10010 /* Bit 28 : Include or exclude channel 28 */
sahilmgandhi 18:6a4db94011d3 10011 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 10012 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 10013 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10014 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10015
sahilmgandhi 18:6a4db94011d3 10016 /* Bit 27 : Include or exclude channel 27 */
sahilmgandhi 18:6a4db94011d3 10017 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 10018 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 10019 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10020 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10021
sahilmgandhi 18:6a4db94011d3 10022 /* Bit 26 : Include or exclude channel 26 */
sahilmgandhi 18:6a4db94011d3 10023 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 10024 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 10025 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10026 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10027
sahilmgandhi 18:6a4db94011d3 10028 /* Bit 25 : Include or exclude channel 25 */
sahilmgandhi 18:6a4db94011d3 10029 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 10030 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 10031 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10032 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10033
sahilmgandhi 18:6a4db94011d3 10034 /* Bit 24 : Include or exclude channel 24 */
sahilmgandhi 18:6a4db94011d3 10035 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 10036 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 10037 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10038 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10039
sahilmgandhi 18:6a4db94011d3 10040 /* Bit 23 : Include or exclude channel 23 */
sahilmgandhi 18:6a4db94011d3 10041 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 10042 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 10043 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10044 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10045
sahilmgandhi 18:6a4db94011d3 10046 /* Bit 22 : Include or exclude channel 22 */
sahilmgandhi 18:6a4db94011d3 10047 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 10048 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 10049 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10050 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10051
sahilmgandhi 18:6a4db94011d3 10052 /* Bit 21 : Include or exclude channel 21 */
sahilmgandhi 18:6a4db94011d3 10053 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 10054 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 10055 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10056 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10057
sahilmgandhi 18:6a4db94011d3 10058 /* Bit 20 : Include or exclude channel 20 */
sahilmgandhi 18:6a4db94011d3 10059 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 10060 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 10061 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10062 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10063
sahilmgandhi 18:6a4db94011d3 10064 /* Bit 19 : Include or exclude channel 19 */
sahilmgandhi 18:6a4db94011d3 10065 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
sahilmgandhi 18:6a4db94011d3 10066 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
sahilmgandhi 18:6a4db94011d3 10067 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10068 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10069
sahilmgandhi 18:6a4db94011d3 10070 /* Bit 18 : Include or exclude channel 18 */
sahilmgandhi 18:6a4db94011d3 10071 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
sahilmgandhi 18:6a4db94011d3 10072 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
sahilmgandhi 18:6a4db94011d3 10073 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10074 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10075
sahilmgandhi 18:6a4db94011d3 10076 /* Bit 17 : Include or exclude channel 17 */
sahilmgandhi 18:6a4db94011d3 10077 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
sahilmgandhi 18:6a4db94011d3 10078 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
sahilmgandhi 18:6a4db94011d3 10079 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10080 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10081
sahilmgandhi 18:6a4db94011d3 10082 /* Bit 16 : Include or exclude channel 16 */
sahilmgandhi 18:6a4db94011d3 10083 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
sahilmgandhi 18:6a4db94011d3 10084 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
sahilmgandhi 18:6a4db94011d3 10085 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10086 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10087
sahilmgandhi 18:6a4db94011d3 10088 /* Bit 15 : Include or exclude channel 15 */
sahilmgandhi 18:6a4db94011d3 10089 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 10090 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 10091 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10092 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10093
sahilmgandhi 18:6a4db94011d3 10094 /* Bit 14 : Include or exclude channel 14 */
sahilmgandhi 18:6a4db94011d3 10095 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 10096 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 10097 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10098 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10099
sahilmgandhi 18:6a4db94011d3 10100 /* Bit 13 : Include or exclude channel 13 */
sahilmgandhi 18:6a4db94011d3 10101 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 10102 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 10103 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10104 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10105
sahilmgandhi 18:6a4db94011d3 10106 /* Bit 12 : Include or exclude channel 12 */
sahilmgandhi 18:6a4db94011d3 10107 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 10108 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 10109 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10110 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10111
sahilmgandhi 18:6a4db94011d3 10112 /* Bit 11 : Include or exclude channel 11 */
sahilmgandhi 18:6a4db94011d3 10113 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 10114 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 10115 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10116 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10117
sahilmgandhi 18:6a4db94011d3 10118 /* Bit 10 : Include or exclude channel 10 */
sahilmgandhi 18:6a4db94011d3 10119 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 10120 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 10121 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10122 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10123
sahilmgandhi 18:6a4db94011d3 10124 /* Bit 9 : Include or exclude channel 9 */
sahilmgandhi 18:6a4db94011d3 10125 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 10126 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 10127 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10128 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10129
sahilmgandhi 18:6a4db94011d3 10130 /* Bit 8 : Include or exclude channel 8 */
sahilmgandhi 18:6a4db94011d3 10131 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 10132 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 10133 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10134 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10135
sahilmgandhi 18:6a4db94011d3 10136 /* Bit 7 : Include or exclude channel 7 */
sahilmgandhi 18:6a4db94011d3 10137 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 10138 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 10139 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10140 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10141
sahilmgandhi 18:6a4db94011d3 10142 /* Bit 6 : Include or exclude channel 6 */
sahilmgandhi 18:6a4db94011d3 10143 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 10144 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 10145 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10146 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10147
sahilmgandhi 18:6a4db94011d3 10148 /* Bit 5 : Include or exclude channel 5 */
sahilmgandhi 18:6a4db94011d3 10149 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 10150 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 10151 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10152 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10153
sahilmgandhi 18:6a4db94011d3 10154 /* Bit 4 : Include or exclude channel 4 */
sahilmgandhi 18:6a4db94011d3 10155 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 10156 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 10157 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10158 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10159
sahilmgandhi 18:6a4db94011d3 10160 /* Bit 3 : Include or exclude channel 3 */
sahilmgandhi 18:6a4db94011d3 10161 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 10162 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 10163 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10164 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10165
sahilmgandhi 18:6a4db94011d3 10166 /* Bit 2 : Include or exclude channel 2 */
sahilmgandhi 18:6a4db94011d3 10167 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 10168 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 10169 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10170 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10171
sahilmgandhi 18:6a4db94011d3 10172 /* Bit 1 : Include or exclude channel 1 */
sahilmgandhi 18:6a4db94011d3 10173 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 10174 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 10175 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10176 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10177
sahilmgandhi 18:6a4db94011d3 10178 /* Bit 0 : Include or exclude channel 0 */
sahilmgandhi 18:6a4db94011d3 10179 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 10180 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 10181 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
sahilmgandhi 18:6a4db94011d3 10182 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
sahilmgandhi 18:6a4db94011d3 10183
sahilmgandhi 18:6a4db94011d3 10184 /* Register: PPI_FORK_TEP */
sahilmgandhi 18:6a4db94011d3 10185 /* Description: Description cluster[0]: Channel 0 task end-point */
sahilmgandhi 18:6a4db94011d3 10186
sahilmgandhi 18:6a4db94011d3 10187 /* Bits 31..0 : Pointer to task register */
sahilmgandhi 18:6a4db94011d3 10188 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
sahilmgandhi 18:6a4db94011d3 10189 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
sahilmgandhi 18:6a4db94011d3 10190
sahilmgandhi 18:6a4db94011d3 10191
sahilmgandhi 18:6a4db94011d3 10192 /* Peripheral: PWM */
sahilmgandhi 18:6a4db94011d3 10193 /* Description: Pulse Width Modulation Unit 0 */
sahilmgandhi 18:6a4db94011d3 10194
sahilmgandhi 18:6a4db94011d3 10195 /* Register: PWM_SHORTS */
sahilmgandhi 18:6a4db94011d3 10196 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 10197
sahilmgandhi 18:6a4db94011d3 10198 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
sahilmgandhi 18:6a4db94011d3 10199 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
sahilmgandhi 18:6a4db94011d3 10200 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
sahilmgandhi 18:6a4db94011d3 10201 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10202 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10203
sahilmgandhi 18:6a4db94011d3 10204 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
sahilmgandhi 18:6a4db94011d3 10205 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
sahilmgandhi 18:6a4db94011d3 10206 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
sahilmgandhi 18:6a4db94011d3 10207 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10208 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10209
sahilmgandhi 18:6a4db94011d3 10210 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
sahilmgandhi 18:6a4db94011d3 10211 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
sahilmgandhi 18:6a4db94011d3 10212 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
sahilmgandhi 18:6a4db94011d3 10213 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10214 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10215
sahilmgandhi 18:6a4db94011d3 10216 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
sahilmgandhi 18:6a4db94011d3 10217 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
sahilmgandhi 18:6a4db94011d3 10218 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
sahilmgandhi 18:6a4db94011d3 10219 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10220 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10221
sahilmgandhi 18:6a4db94011d3 10222 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
sahilmgandhi 18:6a4db94011d3 10223 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
sahilmgandhi 18:6a4db94011d3 10224 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
sahilmgandhi 18:6a4db94011d3 10225 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10226 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10227
sahilmgandhi 18:6a4db94011d3 10228 /* Register: PWM_INTEN */
sahilmgandhi 18:6a4db94011d3 10229 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 10230
sahilmgandhi 18:6a4db94011d3 10231 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
sahilmgandhi 18:6a4db94011d3 10232 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
sahilmgandhi 18:6a4db94011d3 10233 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
sahilmgandhi 18:6a4db94011d3 10234 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10235 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10236
sahilmgandhi 18:6a4db94011d3 10237 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
sahilmgandhi 18:6a4db94011d3 10238 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
sahilmgandhi 18:6a4db94011d3 10239 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
sahilmgandhi 18:6a4db94011d3 10240 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10241 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10242
sahilmgandhi 18:6a4db94011d3 10243 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
sahilmgandhi 18:6a4db94011d3 10244 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
sahilmgandhi 18:6a4db94011d3 10245 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
sahilmgandhi 18:6a4db94011d3 10246 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10247 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10248
sahilmgandhi 18:6a4db94011d3 10249 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
sahilmgandhi 18:6a4db94011d3 10250 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
sahilmgandhi 18:6a4db94011d3 10251 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
sahilmgandhi 18:6a4db94011d3 10252 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10253 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10254
sahilmgandhi 18:6a4db94011d3 10255 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
sahilmgandhi 18:6a4db94011d3 10256 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
sahilmgandhi 18:6a4db94011d3 10257 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
sahilmgandhi 18:6a4db94011d3 10258 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10259 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10260
sahilmgandhi 18:6a4db94011d3 10261 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
sahilmgandhi 18:6a4db94011d3 10262 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
sahilmgandhi 18:6a4db94011d3 10263 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
sahilmgandhi 18:6a4db94011d3 10264 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10265 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10266
sahilmgandhi 18:6a4db94011d3 10267 /* Bit 1 : Enable or disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 10268 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10269 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10270 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10271 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10272
sahilmgandhi 18:6a4db94011d3 10273 /* Register: PWM_INTENSET */
sahilmgandhi 18:6a4db94011d3 10274 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 10275
sahilmgandhi 18:6a4db94011d3 10276 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
sahilmgandhi 18:6a4db94011d3 10277 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
sahilmgandhi 18:6a4db94011d3 10278 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
sahilmgandhi 18:6a4db94011d3 10279 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10280 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10281 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10282
sahilmgandhi 18:6a4db94011d3 10283 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
sahilmgandhi 18:6a4db94011d3 10284 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
sahilmgandhi 18:6a4db94011d3 10285 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
sahilmgandhi 18:6a4db94011d3 10286 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10287 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10288 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10289
sahilmgandhi 18:6a4db94011d3 10290 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
sahilmgandhi 18:6a4db94011d3 10291 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
sahilmgandhi 18:6a4db94011d3 10292 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
sahilmgandhi 18:6a4db94011d3 10293 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10294 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10295 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10296
sahilmgandhi 18:6a4db94011d3 10297 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
sahilmgandhi 18:6a4db94011d3 10298 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
sahilmgandhi 18:6a4db94011d3 10299 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
sahilmgandhi 18:6a4db94011d3 10300 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10301 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10302 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10303
sahilmgandhi 18:6a4db94011d3 10304 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
sahilmgandhi 18:6a4db94011d3 10305 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
sahilmgandhi 18:6a4db94011d3 10306 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
sahilmgandhi 18:6a4db94011d3 10307 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10308 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10309 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10310
sahilmgandhi 18:6a4db94011d3 10311 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
sahilmgandhi 18:6a4db94011d3 10312 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
sahilmgandhi 18:6a4db94011d3 10313 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
sahilmgandhi 18:6a4db94011d3 10314 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10315 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10316 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10317
sahilmgandhi 18:6a4db94011d3 10318 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 10319 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10320 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10321 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10322 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10323 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10324
sahilmgandhi 18:6a4db94011d3 10325 /* Register: PWM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 10326 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 10327
sahilmgandhi 18:6a4db94011d3 10328 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
sahilmgandhi 18:6a4db94011d3 10329 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
sahilmgandhi 18:6a4db94011d3 10330 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
sahilmgandhi 18:6a4db94011d3 10331 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10332 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10333 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10334
sahilmgandhi 18:6a4db94011d3 10335 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
sahilmgandhi 18:6a4db94011d3 10336 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
sahilmgandhi 18:6a4db94011d3 10337 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
sahilmgandhi 18:6a4db94011d3 10338 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10339 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10340 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10341
sahilmgandhi 18:6a4db94011d3 10342 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
sahilmgandhi 18:6a4db94011d3 10343 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
sahilmgandhi 18:6a4db94011d3 10344 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
sahilmgandhi 18:6a4db94011d3 10345 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10346 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10347 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10348
sahilmgandhi 18:6a4db94011d3 10349 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
sahilmgandhi 18:6a4db94011d3 10350 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
sahilmgandhi 18:6a4db94011d3 10351 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
sahilmgandhi 18:6a4db94011d3 10352 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10353 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10354 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10355
sahilmgandhi 18:6a4db94011d3 10356 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
sahilmgandhi 18:6a4db94011d3 10357 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
sahilmgandhi 18:6a4db94011d3 10358 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
sahilmgandhi 18:6a4db94011d3 10359 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10360 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10361 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10362
sahilmgandhi 18:6a4db94011d3 10363 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
sahilmgandhi 18:6a4db94011d3 10364 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
sahilmgandhi 18:6a4db94011d3 10365 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
sahilmgandhi 18:6a4db94011d3 10366 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10367 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10368 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10369
sahilmgandhi 18:6a4db94011d3 10370 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 10371 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10372 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10373 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10374 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10375 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10376
sahilmgandhi 18:6a4db94011d3 10377 /* Register: PWM_ENABLE */
sahilmgandhi 18:6a4db94011d3 10378 /* Description: PWM module enable register */
sahilmgandhi 18:6a4db94011d3 10379
sahilmgandhi 18:6a4db94011d3 10380 /* Bit 0 : Enable or disable PWM module */
sahilmgandhi 18:6a4db94011d3 10381 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 10382 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 10383 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 10384 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10385
sahilmgandhi 18:6a4db94011d3 10386 /* Register: PWM_MODE */
sahilmgandhi 18:6a4db94011d3 10387 /* Description: Selects operating mode of the wave counter */
sahilmgandhi 18:6a4db94011d3 10388
sahilmgandhi 18:6a4db94011d3 10389 /* Bit 0 : Selects up or up and down as wave counter mode */
sahilmgandhi 18:6a4db94011d3 10390 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
sahilmgandhi 18:6a4db94011d3 10391 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
sahilmgandhi 18:6a4db94011d3 10392 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
sahilmgandhi 18:6a4db94011d3 10393 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
sahilmgandhi 18:6a4db94011d3 10394
sahilmgandhi 18:6a4db94011d3 10395 /* Register: PWM_COUNTERTOP */
sahilmgandhi 18:6a4db94011d3 10396 /* Description: Value up to which the pulse generator counter counts */
sahilmgandhi 18:6a4db94011d3 10397
sahilmgandhi 18:6a4db94011d3 10398 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
sahilmgandhi 18:6a4db94011d3 10399 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
sahilmgandhi 18:6a4db94011d3 10400 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
sahilmgandhi 18:6a4db94011d3 10401
sahilmgandhi 18:6a4db94011d3 10402 /* Register: PWM_PRESCALER */
sahilmgandhi 18:6a4db94011d3 10403 /* Description: Configuration for PWM_CLK */
sahilmgandhi 18:6a4db94011d3 10404
sahilmgandhi 18:6a4db94011d3 10405 /* Bits 2..0 : Pre-scaler of PWM_CLK */
sahilmgandhi 18:6a4db94011d3 10406 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 10407 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 10408 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */
sahilmgandhi 18:6a4db94011d3 10409 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */
sahilmgandhi 18:6a4db94011d3 10410 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */
sahilmgandhi 18:6a4db94011d3 10411 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */
sahilmgandhi 18:6a4db94011d3 10412 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */
sahilmgandhi 18:6a4db94011d3 10413 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */
sahilmgandhi 18:6a4db94011d3 10414 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */
sahilmgandhi 18:6a4db94011d3 10415 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
sahilmgandhi 18:6a4db94011d3 10416
sahilmgandhi 18:6a4db94011d3 10417 /* Register: PWM_DECODER */
sahilmgandhi 18:6a4db94011d3 10418 /* Description: Configuration of the decoder */
sahilmgandhi 18:6a4db94011d3 10419
sahilmgandhi 18:6a4db94011d3 10420 /* Bit 8 : Selects source for advancing the active sequence */
sahilmgandhi 18:6a4db94011d3 10421 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 10422 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 10423 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
sahilmgandhi 18:6a4db94011d3 10424 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
sahilmgandhi 18:6a4db94011d3 10425
sahilmgandhi 18:6a4db94011d3 10426 /* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
sahilmgandhi 18:6a4db94011d3 10427 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
sahilmgandhi 18:6a4db94011d3 10428 #define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
sahilmgandhi 18:6a4db94011d3 10429 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
sahilmgandhi 18:6a4db94011d3 10430 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
sahilmgandhi 18:6a4db94011d3 10431 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
sahilmgandhi 18:6a4db94011d3 10432 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
sahilmgandhi 18:6a4db94011d3 10433
sahilmgandhi 18:6a4db94011d3 10434 /* Register: PWM_LOOP */
sahilmgandhi 18:6a4db94011d3 10435 /* Description: Amount of playback of a loop */
sahilmgandhi 18:6a4db94011d3 10436
sahilmgandhi 18:6a4db94011d3 10437 /* Bits 15..0 : Amount of playback of pattern cycles */
sahilmgandhi 18:6a4db94011d3 10438 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
sahilmgandhi 18:6a4db94011d3 10439 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
sahilmgandhi 18:6a4db94011d3 10440 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
sahilmgandhi 18:6a4db94011d3 10441
sahilmgandhi 18:6a4db94011d3 10442 /* Register: PWM_SEQ_PTR */
sahilmgandhi 18:6a4db94011d3 10443 /* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */
sahilmgandhi 18:6a4db94011d3 10444
sahilmgandhi 18:6a4db94011d3 10445 /* Bits 31..0 : Beginning address in Data RAM of sequence A */
sahilmgandhi 18:6a4db94011d3 10446 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 10447 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 10448
sahilmgandhi 18:6a4db94011d3 10449 /* Register: PWM_SEQ_CNT */
sahilmgandhi 18:6a4db94011d3 10450 /* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */
sahilmgandhi 18:6a4db94011d3 10451
sahilmgandhi 18:6a4db94011d3 10452 /* Bits 14..0 : Amount of values (duty cycles) in sequence A */
sahilmgandhi 18:6a4db94011d3 10453 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
sahilmgandhi 18:6a4db94011d3 10454 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
sahilmgandhi 18:6a4db94011d3 10455 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
sahilmgandhi 18:6a4db94011d3 10456
sahilmgandhi 18:6a4db94011d3 10457 /* Register: PWM_SEQ_REFRESH */
sahilmgandhi 18:6a4db94011d3 10458 /* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
sahilmgandhi 18:6a4db94011d3 10459
sahilmgandhi 18:6a4db94011d3 10460 /* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
sahilmgandhi 18:6a4db94011d3 10461 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
sahilmgandhi 18:6a4db94011d3 10462 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
sahilmgandhi 18:6a4db94011d3 10463 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
sahilmgandhi 18:6a4db94011d3 10464
sahilmgandhi 18:6a4db94011d3 10465 /* Register: PWM_SEQ_ENDDELAY */
sahilmgandhi 18:6a4db94011d3 10466 /* Description: Description cluster[0]: Time added after the sequence */
sahilmgandhi 18:6a4db94011d3 10467
sahilmgandhi 18:6a4db94011d3 10468 /* Bits 23..0 : Time added after the sequence in PWM periods */
sahilmgandhi 18:6a4db94011d3 10469 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
sahilmgandhi 18:6a4db94011d3 10470 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
sahilmgandhi 18:6a4db94011d3 10471
sahilmgandhi 18:6a4db94011d3 10472 /* Register: PWM_PSEL_OUT */
sahilmgandhi 18:6a4db94011d3 10473 /* Description: Description collection[0]: Output pin select for PWM channel 0 */
sahilmgandhi 18:6a4db94011d3 10474
sahilmgandhi 18:6a4db94011d3 10475 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 10476 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10477 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10478 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 10479 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 10480
sahilmgandhi 18:6a4db94011d3 10481 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 10482 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 10483 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 10484
sahilmgandhi 18:6a4db94011d3 10485
sahilmgandhi 18:6a4db94011d3 10486 /* Peripheral: QDEC */
sahilmgandhi 18:6a4db94011d3 10487 /* Description: Quadrature Decoder */
sahilmgandhi 18:6a4db94011d3 10488
sahilmgandhi 18:6a4db94011d3 10489 /* Register: QDEC_SHORTS */
sahilmgandhi 18:6a4db94011d3 10490 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 10491
sahilmgandhi 18:6a4db94011d3 10492 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
sahilmgandhi 18:6a4db94011d3 10493 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
sahilmgandhi 18:6a4db94011d3 10494 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
sahilmgandhi 18:6a4db94011d3 10495 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10496 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10497
sahilmgandhi 18:6a4db94011d3 10498 /* Bit 5 : Shortcut between DBLRDY event and STOP task */
sahilmgandhi 18:6a4db94011d3 10499 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 10500 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 10501 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10502 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10503
sahilmgandhi 18:6a4db94011d3 10504 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
sahilmgandhi 18:6a4db94011d3 10505 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
sahilmgandhi 18:6a4db94011d3 10506 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
sahilmgandhi 18:6a4db94011d3 10507 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10508 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10509
sahilmgandhi 18:6a4db94011d3 10510 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */
sahilmgandhi 18:6a4db94011d3 10511 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 10512 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 10513 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10514 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10515
sahilmgandhi 18:6a4db94011d3 10516 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
sahilmgandhi 18:6a4db94011d3 10517 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
sahilmgandhi 18:6a4db94011d3 10518 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
sahilmgandhi 18:6a4db94011d3 10519 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10520 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10521
sahilmgandhi 18:6a4db94011d3 10522 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
sahilmgandhi 18:6a4db94011d3 10523 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 10524 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 10525 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10526 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10527
sahilmgandhi 18:6a4db94011d3 10528 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
sahilmgandhi 18:6a4db94011d3 10529 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
sahilmgandhi 18:6a4db94011d3 10530 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
sahilmgandhi 18:6a4db94011d3 10531 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10532 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10533
sahilmgandhi 18:6a4db94011d3 10534 /* Register: QDEC_INTENSET */
sahilmgandhi 18:6a4db94011d3 10535 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 10536
sahilmgandhi 18:6a4db94011d3 10537 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 10538 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10539 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10540 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10541 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10542 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10543
sahilmgandhi 18:6a4db94011d3 10544 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
sahilmgandhi 18:6a4db94011d3 10545 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
sahilmgandhi 18:6a4db94011d3 10546 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
sahilmgandhi 18:6a4db94011d3 10547 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10548 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10549 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10550
sahilmgandhi 18:6a4db94011d3 10551 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
sahilmgandhi 18:6a4db94011d3 10552 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 10553 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 10554 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10555 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10556 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10557
sahilmgandhi 18:6a4db94011d3 10558 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
sahilmgandhi 18:6a4db94011d3 10559 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 10560 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 10561 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10562 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10563 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10564
sahilmgandhi 18:6a4db94011d3 10565 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
sahilmgandhi 18:6a4db94011d3 10566 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 10567 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 10568 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10569 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10570 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10571
sahilmgandhi 18:6a4db94011d3 10572 /* Register: QDEC_INTENCLR */
sahilmgandhi 18:6a4db94011d3 10573 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 10574
sahilmgandhi 18:6a4db94011d3 10575 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 10576 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10577 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 10578 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10579 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10580 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10581
sahilmgandhi 18:6a4db94011d3 10582 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
sahilmgandhi 18:6a4db94011d3 10583 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
sahilmgandhi 18:6a4db94011d3 10584 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
sahilmgandhi 18:6a4db94011d3 10585 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10586 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10587 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10588
sahilmgandhi 18:6a4db94011d3 10589 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
sahilmgandhi 18:6a4db94011d3 10590 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 10591 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 10592 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10593 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10594 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10595
sahilmgandhi 18:6a4db94011d3 10596 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
sahilmgandhi 18:6a4db94011d3 10597 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 10598 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 10599 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10600 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10601 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10602
sahilmgandhi 18:6a4db94011d3 10603 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
sahilmgandhi 18:6a4db94011d3 10604 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 10605 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 10606 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10607 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10608 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10609
sahilmgandhi 18:6a4db94011d3 10610 /* Register: QDEC_ENABLE */
sahilmgandhi 18:6a4db94011d3 10611 /* Description: Enable the quadrature decoder */
sahilmgandhi 18:6a4db94011d3 10612
sahilmgandhi 18:6a4db94011d3 10613 /* Bit 0 : Enable or disable the quadrature decoder */
sahilmgandhi 18:6a4db94011d3 10614 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 10615 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 10616 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10617 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10618
sahilmgandhi 18:6a4db94011d3 10619 /* Register: QDEC_LEDPOL */
sahilmgandhi 18:6a4db94011d3 10620 /* Description: LED output pin polarity */
sahilmgandhi 18:6a4db94011d3 10621
sahilmgandhi 18:6a4db94011d3 10622 /* Bit 0 : LED output pin polarity */
sahilmgandhi 18:6a4db94011d3 10623 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
sahilmgandhi 18:6a4db94011d3 10624 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
sahilmgandhi 18:6a4db94011d3 10625 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
sahilmgandhi 18:6a4db94011d3 10626 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
sahilmgandhi 18:6a4db94011d3 10627
sahilmgandhi 18:6a4db94011d3 10628 /* Register: QDEC_SAMPLEPER */
sahilmgandhi 18:6a4db94011d3 10629 /* Description: Sample period */
sahilmgandhi 18:6a4db94011d3 10630
sahilmgandhi 18:6a4db94011d3 10631 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
sahilmgandhi 18:6a4db94011d3 10632 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
sahilmgandhi 18:6a4db94011d3 10633 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
sahilmgandhi 18:6a4db94011d3 10634 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
sahilmgandhi 18:6a4db94011d3 10635 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
sahilmgandhi 18:6a4db94011d3 10636 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
sahilmgandhi 18:6a4db94011d3 10637 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
sahilmgandhi 18:6a4db94011d3 10638 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
sahilmgandhi 18:6a4db94011d3 10639 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
sahilmgandhi 18:6a4db94011d3 10640 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
sahilmgandhi 18:6a4db94011d3 10641 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
sahilmgandhi 18:6a4db94011d3 10642 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
sahilmgandhi 18:6a4db94011d3 10643 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
sahilmgandhi 18:6a4db94011d3 10644 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
sahilmgandhi 18:6a4db94011d3 10645
sahilmgandhi 18:6a4db94011d3 10646 /* Register: QDEC_SAMPLE */
sahilmgandhi 18:6a4db94011d3 10647 /* Description: Motion sample value */
sahilmgandhi 18:6a4db94011d3 10648
sahilmgandhi 18:6a4db94011d3 10649 /* Bits 31..0 : Last motion sample */
sahilmgandhi 18:6a4db94011d3 10650 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 10651 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 10652
sahilmgandhi 18:6a4db94011d3 10653 /* Register: QDEC_REPORTPER */
sahilmgandhi 18:6a4db94011d3 10654 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
sahilmgandhi 18:6a4db94011d3 10655
sahilmgandhi 18:6a4db94011d3 10656 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
sahilmgandhi 18:6a4db94011d3 10657 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
sahilmgandhi 18:6a4db94011d3 10658 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
sahilmgandhi 18:6a4db94011d3 10659 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
sahilmgandhi 18:6a4db94011d3 10660 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
sahilmgandhi 18:6a4db94011d3 10661 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
sahilmgandhi 18:6a4db94011d3 10662 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
sahilmgandhi 18:6a4db94011d3 10663 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
sahilmgandhi 18:6a4db94011d3 10664 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
sahilmgandhi 18:6a4db94011d3 10665 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
sahilmgandhi 18:6a4db94011d3 10666 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
sahilmgandhi 18:6a4db94011d3 10667 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
sahilmgandhi 18:6a4db94011d3 10668
sahilmgandhi 18:6a4db94011d3 10669 /* Register: QDEC_ACC */
sahilmgandhi 18:6a4db94011d3 10670 /* Description: Register accumulating the valid transitions */
sahilmgandhi 18:6a4db94011d3 10671
sahilmgandhi 18:6a4db94011d3 10672 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
sahilmgandhi 18:6a4db94011d3 10673 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
sahilmgandhi 18:6a4db94011d3 10674 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
sahilmgandhi 18:6a4db94011d3 10675
sahilmgandhi 18:6a4db94011d3 10676 /* Register: QDEC_ACCREAD */
sahilmgandhi 18:6a4db94011d3 10677 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
sahilmgandhi 18:6a4db94011d3 10678
sahilmgandhi 18:6a4db94011d3 10679 /* Bits 31..0 : Snapshot of the ACC register. */
sahilmgandhi 18:6a4db94011d3 10680 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
sahilmgandhi 18:6a4db94011d3 10681 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
sahilmgandhi 18:6a4db94011d3 10682
sahilmgandhi 18:6a4db94011d3 10683 /* Register: QDEC_PSEL_LED */
sahilmgandhi 18:6a4db94011d3 10684 /* Description: Pin select for LED signal */
sahilmgandhi 18:6a4db94011d3 10685
sahilmgandhi 18:6a4db94011d3 10686 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 10687 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10688 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10689 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 10690 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 10691
sahilmgandhi 18:6a4db94011d3 10692 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 10693 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 10694 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 10695
sahilmgandhi 18:6a4db94011d3 10696 /* Register: QDEC_PSEL_A */
sahilmgandhi 18:6a4db94011d3 10697 /* Description: Pin select for A signal */
sahilmgandhi 18:6a4db94011d3 10698
sahilmgandhi 18:6a4db94011d3 10699 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 10700 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10701 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10702 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 10703 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 10704
sahilmgandhi 18:6a4db94011d3 10705 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 10706 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 10707 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 10708
sahilmgandhi 18:6a4db94011d3 10709 /* Register: QDEC_PSEL_B */
sahilmgandhi 18:6a4db94011d3 10710 /* Description: Pin select for B signal */
sahilmgandhi 18:6a4db94011d3 10711
sahilmgandhi 18:6a4db94011d3 10712 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 10713 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10714 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 10715 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 10716 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 10717
sahilmgandhi 18:6a4db94011d3 10718 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 10719 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 10720 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 10721
sahilmgandhi 18:6a4db94011d3 10722 /* Register: QDEC_DBFEN */
sahilmgandhi 18:6a4db94011d3 10723 /* Description: Enable input debounce filters */
sahilmgandhi 18:6a4db94011d3 10724
sahilmgandhi 18:6a4db94011d3 10725 /* Bit 0 : Enable input debounce filters */
sahilmgandhi 18:6a4db94011d3 10726 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
sahilmgandhi 18:6a4db94011d3 10727 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
sahilmgandhi 18:6a4db94011d3 10728 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
sahilmgandhi 18:6a4db94011d3 10729 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
sahilmgandhi 18:6a4db94011d3 10730
sahilmgandhi 18:6a4db94011d3 10731 /* Register: QDEC_LEDPRE */
sahilmgandhi 18:6a4db94011d3 10732 /* Description: Time period the LED is switched ON prior to sampling */
sahilmgandhi 18:6a4db94011d3 10733
sahilmgandhi 18:6a4db94011d3 10734 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
sahilmgandhi 18:6a4db94011d3 10735 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
sahilmgandhi 18:6a4db94011d3 10736 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
sahilmgandhi 18:6a4db94011d3 10737
sahilmgandhi 18:6a4db94011d3 10738 /* Register: QDEC_ACCDBL */
sahilmgandhi 18:6a4db94011d3 10739 /* Description: Register accumulating the number of detected double transitions */
sahilmgandhi 18:6a4db94011d3 10740
sahilmgandhi 18:6a4db94011d3 10741 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
sahilmgandhi 18:6a4db94011d3 10742 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
sahilmgandhi 18:6a4db94011d3 10743 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
sahilmgandhi 18:6a4db94011d3 10744
sahilmgandhi 18:6a4db94011d3 10745 /* Register: QDEC_ACCDBLREAD */
sahilmgandhi 18:6a4db94011d3 10746 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
sahilmgandhi 18:6a4db94011d3 10747
sahilmgandhi 18:6a4db94011d3 10748 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
sahilmgandhi 18:6a4db94011d3 10749 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
sahilmgandhi 18:6a4db94011d3 10750 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
sahilmgandhi 18:6a4db94011d3 10751
sahilmgandhi 18:6a4db94011d3 10752
sahilmgandhi 18:6a4db94011d3 10753 /* Peripheral: RADIO */
sahilmgandhi 18:6a4db94011d3 10754 /* Description: 2.4 GHz Radio */
sahilmgandhi 18:6a4db94011d3 10755
sahilmgandhi 18:6a4db94011d3 10756 /* Register: RADIO_SHORTS */
sahilmgandhi 18:6a4db94011d3 10757 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 10758
sahilmgandhi 18:6a4db94011d3 10759 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
sahilmgandhi 18:6a4db94011d3 10760 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
sahilmgandhi 18:6a4db94011d3 10761 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
sahilmgandhi 18:6a4db94011d3 10762 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10763 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10764
sahilmgandhi 18:6a4db94011d3 10765 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
sahilmgandhi 18:6a4db94011d3 10766 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
sahilmgandhi 18:6a4db94011d3 10767 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
sahilmgandhi 18:6a4db94011d3 10768 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10769 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10770
sahilmgandhi 18:6a4db94011d3 10771 /* Bit 5 : Shortcut between END event and START task */
sahilmgandhi 18:6a4db94011d3 10772 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
sahilmgandhi 18:6a4db94011d3 10773 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
sahilmgandhi 18:6a4db94011d3 10774 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10775 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10776
sahilmgandhi 18:6a4db94011d3 10777 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
sahilmgandhi 18:6a4db94011d3 10778 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
sahilmgandhi 18:6a4db94011d3 10779 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
sahilmgandhi 18:6a4db94011d3 10780 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10781 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10782
sahilmgandhi 18:6a4db94011d3 10783 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
sahilmgandhi 18:6a4db94011d3 10784 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
sahilmgandhi 18:6a4db94011d3 10785 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
sahilmgandhi 18:6a4db94011d3 10786 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10787 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10788
sahilmgandhi 18:6a4db94011d3 10789 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
sahilmgandhi 18:6a4db94011d3 10790 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
sahilmgandhi 18:6a4db94011d3 10791 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
sahilmgandhi 18:6a4db94011d3 10792 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10793 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10794
sahilmgandhi 18:6a4db94011d3 10795 /* Bit 1 : Shortcut between END event and DISABLE task */
sahilmgandhi 18:6a4db94011d3 10796 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
sahilmgandhi 18:6a4db94011d3 10797 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
sahilmgandhi 18:6a4db94011d3 10798 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10799 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10800
sahilmgandhi 18:6a4db94011d3 10801 /* Bit 0 : Shortcut between READY event and START task */
sahilmgandhi 18:6a4db94011d3 10802 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
sahilmgandhi 18:6a4db94011d3 10803 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
sahilmgandhi 18:6a4db94011d3 10804 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 10805 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 10806
sahilmgandhi 18:6a4db94011d3 10807 /* Register: RADIO_INTENSET */
sahilmgandhi 18:6a4db94011d3 10808 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 10809
sahilmgandhi 18:6a4db94011d3 10810 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
sahilmgandhi 18:6a4db94011d3 10811 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
sahilmgandhi 18:6a4db94011d3 10812 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
sahilmgandhi 18:6a4db94011d3 10813 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10814 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10815 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10816
sahilmgandhi 18:6a4db94011d3 10817 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
sahilmgandhi 18:6a4db94011d3 10818 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
sahilmgandhi 18:6a4db94011d3 10819 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
sahilmgandhi 18:6a4db94011d3 10820 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10821 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10822 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10823
sahilmgandhi 18:6a4db94011d3 10824 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
sahilmgandhi 18:6a4db94011d3 10825 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 10826 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 10827 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10828 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10829 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10830
sahilmgandhi 18:6a4db94011d3 10831 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
sahilmgandhi 18:6a4db94011d3 10832 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 10833 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 10834 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10835 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10836 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10837
sahilmgandhi 18:6a4db94011d3 10838 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
sahilmgandhi 18:6a4db94011d3 10839 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 10840 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 10841 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10842 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10843 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10844
sahilmgandhi 18:6a4db94011d3 10845 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
sahilmgandhi 18:6a4db94011d3 10846 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 10847 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 10848 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10849 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10850 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10851
sahilmgandhi 18:6a4db94011d3 10852 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
sahilmgandhi 18:6a4db94011d3 10853 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 10854 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 10855 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10856 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10857 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10858
sahilmgandhi 18:6a4db94011d3 10859 /* Bit 3 : Write '1' to Enable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 10860 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 10861 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 10862 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10863 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10864 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10865
sahilmgandhi 18:6a4db94011d3 10866 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
sahilmgandhi 18:6a4db94011d3 10867 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 10868 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 10869 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10870 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10871 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10872
sahilmgandhi 18:6a4db94011d3 10873 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
sahilmgandhi 18:6a4db94011d3 10874 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 10875 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 10876 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10877 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10878 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10879
sahilmgandhi 18:6a4db94011d3 10880 /* Bit 0 : Write '1' to Enable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 10881 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 10882 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 10883 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10884 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10885 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 10886
sahilmgandhi 18:6a4db94011d3 10887 /* Register: RADIO_INTENCLR */
sahilmgandhi 18:6a4db94011d3 10888 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 10889
sahilmgandhi 18:6a4db94011d3 10890 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
sahilmgandhi 18:6a4db94011d3 10891 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
sahilmgandhi 18:6a4db94011d3 10892 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
sahilmgandhi 18:6a4db94011d3 10893 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10894 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10895 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10896
sahilmgandhi 18:6a4db94011d3 10897 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
sahilmgandhi 18:6a4db94011d3 10898 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
sahilmgandhi 18:6a4db94011d3 10899 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
sahilmgandhi 18:6a4db94011d3 10900 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10901 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10902 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10903
sahilmgandhi 18:6a4db94011d3 10904 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
sahilmgandhi 18:6a4db94011d3 10905 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 10906 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 10907 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10908 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10909 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10910
sahilmgandhi 18:6a4db94011d3 10911 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
sahilmgandhi 18:6a4db94011d3 10912 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 10913 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 10914 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10915 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10916 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10917
sahilmgandhi 18:6a4db94011d3 10918 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
sahilmgandhi 18:6a4db94011d3 10919 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 10920 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 10921 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10922 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10923 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10924
sahilmgandhi 18:6a4db94011d3 10925 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
sahilmgandhi 18:6a4db94011d3 10926 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 10927 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 10928 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10929 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10930 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10931
sahilmgandhi 18:6a4db94011d3 10932 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
sahilmgandhi 18:6a4db94011d3 10933 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 10934 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 10935 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10936 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10937 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10938
sahilmgandhi 18:6a4db94011d3 10939 /* Bit 3 : Write '1' to Disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 10940 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 10941 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 10942 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10943 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10944 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10945
sahilmgandhi 18:6a4db94011d3 10946 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
sahilmgandhi 18:6a4db94011d3 10947 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 10948 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 10949 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10950 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10951 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10952
sahilmgandhi 18:6a4db94011d3 10953 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
sahilmgandhi 18:6a4db94011d3 10954 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 10955 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 10956 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10957 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10958 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10959
sahilmgandhi 18:6a4db94011d3 10960 /* Bit 0 : Write '1' to Disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 10961 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 10962 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 10963 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 10964 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 10965 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 10966
sahilmgandhi 18:6a4db94011d3 10967 /* Register: RADIO_CRCSTATUS */
sahilmgandhi 18:6a4db94011d3 10968 /* Description: CRC status */
sahilmgandhi 18:6a4db94011d3 10969
sahilmgandhi 18:6a4db94011d3 10970 /* Bit 0 : CRC status of packet received */
sahilmgandhi 18:6a4db94011d3 10971 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
sahilmgandhi 18:6a4db94011d3 10972 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
sahilmgandhi 18:6a4db94011d3 10973 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
sahilmgandhi 18:6a4db94011d3 10974 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
sahilmgandhi 18:6a4db94011d3 10975
sahilmgandhi 18:6a4db94011d3 10976 /* Register: RADIO_RXMATCH */
sahilmgandhi 18:6a4db94011d3 10977 /* Description: Received address */
sahilmgandhi 18:6a4db94011d3 10978
sahilmgandhi 18:6a4db94011d3 10979 /* Bits 2..0 : Received address */
sahilmgandhi 18:6a4db94011d3 10980 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
sahilmgandhi 18:6a4db94011d3 10981 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
sahilmgandhi 18:6a4db94011d3 10982
sahilmgandhi 18:6a4db94011d3 10983 /* Register: RADIO_RXCRC */
sahilmgandhi 18:6a4db94011d3 10984 /* Description: CRC field of previously received packet */
sahilmgandhi 18:6a4db94011d3 10985
sahilmgandhi 18:6a4db94011d3 10986 /* Bits 23..0 : CRC field of previously received packet */
sahilmgandhi 18:6a4db94011d3 10987 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
sahilmgandhi 18:6a4db94011d3 10988 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
sahilmgandhi 18:6a4db94011d3 10989
sahilmgandhi 18:6a4db94011d3 10990 /* Register: RADIO_DAI */
sahilmgandhi 18:6a4db94011d3 10991 /* Description: Device address match index */
sahilmgandhi 18:6a4db94011d3 10992
sahilmgandhi 18:6a4db94011d3 10993 /* Bits 2..0 : Device address match index */
sahilmgandhi 18:6a4db94011d3 10994 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
sahilmgandhi 18:6a4db94011d3 10995 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
sahilmgandhi 18:6a4db94011d3 10996
sahilmgandhi 18:6a4db94011d3 10997 /* Register: RADIO_PACKETPTR */
sahilmgandhi 18:6a4db94011d3 10998 /* Description: Packet pointer */
sahilmgandhi 18:6a4db94011d3 10999
sahilmgandhi 18:6a4db94011d3 11000 /* Bits 31..0 : Packet pointer */
sahilmgandhi 18:6a4db94011d3 11001 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
sahilmgandhi 18:6a4db94011d3 11002 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
sahilmgandhi 18:6a4db94011d3 11003
sahilmgandhi 18:6a4db94011d3 11004 /* Register: RADIO_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 11005 /* Description: Frequency */
sahilmgandhi 18:6a4db94011d3 11006
sahilmgandhi 18:6a4db94011d3 11007 /* Bit 8 : Channel map selection. */
sahilmgandhi 18:6a4db94011d3 11008 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
sahilmgandhi 18:6a4db94011d3 11009 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
sahilmgandhi 18:6a4db94011d3 11010 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
sahilmgandhi 18:6a4db94011d3 11011 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
sahilmgandhi 18:6a4db94011d3 11012
sahilmgandhi 18:6a4db94011d3 11013 /* Bits 6..0 : Radio channel frequency */
sahilmgandhi 18:6a4db94011d3 11014 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 11015 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 11016
sahilmgandhi 18:6a4db94011d3 11017 /* Register: RADIO_TXPOWER */
sahilmgandhi 18:6a4db94011d3 11018 /* Description: Output power */
sahilmgandhi 18:6a4db94011d3 11019
sahilmgandhi 18:6a4db94011d3 11020 /* Bits 7..0 : RADIO output power. */
sahilmgandhi 18:6a4db94011d3 11021 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
sahilmgandhi 18:6a4db94011d3 11022 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
sahilmgandhi 18:6a4db94011d3 11023 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
sahilmgandhi 18:6a4db94011d3 11024 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
sahilmgandhi 18:6a4db94011d3 11025 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
sahilmgandhi 18:6a4db94011d3 11026 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */
sahilmgandhi 18:6a4db94011d3 11027 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
sahilmgandhi 18:6a4db94011d3 11028 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
sahilmgandhi 18:6a4db94011d3 11029 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
sahilmgandhi 18:6a4db94011d3 11030 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
sahilmgandhi 18:6a4db94011d3 11031 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
sahilmgandhi 18:6a4db94011d3 11032 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
sahilmgandhi 18:6a4db94011d3 11033
sahilmgandhi 18:6a4db94011d3 11034 /* Register: RADIO_MODE */
sahilmgandhi 18:6a4db94011d3 11035 /* Description: Data rate and modulation */
sahilmgandhi 18:6a4db94011d3 11036
sahilmgandhi 18:6a4db94011d3 11037 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
sahilmgandhi 18:6a4db94011d3 11038 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 11039 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 11040 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
sahilmgandhi 18:6a4db94011d3 11041 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
sahilmgandhi 18:6a4db94011d3 11042 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
sahilmgandhi 18:6a4db94011d3 11043 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
sahilmgandhi 18:6a4db94011d3 11044
sahilmgandhi 18:6a4db94011d3 11045 /* Register: RADIO_PCNF0 */
sahilmgandhi 18:6a4db94011d3 11046 /* Description: Packet configuration register 0 */
sahilmgandhi 18:6a4db94011d3 11047
sahilmgandhi 18:6a4db94011d3 11048 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
sahilmgandhi 18:6a4db94011d3 11049 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
sahilmgandhi 18:6a4db94011d3 11050 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
sahilmgandhi 18:6a4db94011d3 11051 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
sahilmgandhi 18:6a4db94011d3 11052 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
sahilmgandhi 18:6a4db94011d3 11053
sahilmgandhi 18:6a4db94011d3 11054 /* Bit 20 : Include or exclude S1 field in RAM */
sahilmgandhi 18:6a4db94011d3 11055 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
sahilmgandhi 18:6a4db94011d3 11056 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
sahilmgandhi 18:6a4db94011d3 11057 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
sahilmgandhi 18:6a4db94011d3 11058 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
sahilmgandhi 18:6a4db94011d3 11059
sahilmgandhi 18:6a4db94011d3 11060 /* Bits 19..16 : Length on air of S1 field in number of bits. */
sahilmgandhi 18:6a4db94011d3 11061 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
sahilmgandhi 18:6a4db94011d3 11062 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
sahilmgandhi 18:6a4db94011d3 11063
sahilmgandhi 18:6a4db94011d3 11064 /* Bit 8 : Length on air of S0 field in number of bytes. */
sahilmgandhi 18:6a4db94011d3 11065 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
sahilmgandhi 18:6a4db94011d3 11066 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
sahilmgandhi 18:6a4db94011d3 11067
sahilmgandhi 18:6a4db94011d3 11068 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
sahilmgandhi 18:6a4db94011d3 11069 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
sahilmgandhi 18:6a4db94011d3 11070 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
sahilmgandhi 18:6a4db94011d3 11071
sahilmgandhi 18:6a4db94011d3 11072 /* Register: RADIO_PCNF1 */
sahilmgandhi 18:6a4db94011d3 11073 /* Description: Packet configuration register 1 */
sahilmgandhi 18:6a4db94011d3 11074
sahilmgandhi 18:6a4db94011d3 11075 /* Bit 25 : Enable or disable packet whitening */
sahilmgandhi 18:6a4db94011d3 11076 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
sahilmgandhi 18:6a4db94011d3 11077 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
sahilmgandhi 18:6a4db94011d3 11078 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11079 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11080
sahilmgandhi 18:6a4db94011d3 11081 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
sahilmgandhi 18:6a4db94011d3 11082 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
sahilmgandhi 18:6a4db94011d3 11083 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
sahilmgandhi 18:6a4db94011d3 11084 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
sahilmgandhi 18:6a4db94011d3 11085 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
sahilmgandhi 18:6a4db94011d3 11086
sahilmgandhi 18:6a4db94011d3 11087 /* Bits 18..16 : Base address length in number of bytes */
sahilmgandhi 18:6a4db94011d3 11088 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
sahilmgandhi 18:6a4db94011d3 11089 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
sahilmgandhi 18:6a4db94011d3 11090
sahilmgandhi 18:6a4db94011d3 11091 /* Bits 15..8 : Static length in number of bytes */
sahilmgandhi 18:6a4db94011d3 11092 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
sahilmgandhi 18:6a4db94011d3 11093 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
sahilmgandhi 18:6a4db94011d3 11094
sahilmgandhi 18:6a4db94011d3 11095 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
sahilmgandhi 18:6a4db94011d3 11096 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
sahilmgandhi 18:6a4db94011d3 11097 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
sahilmgandhi 18:6a4db94011d3 11098
sahilmgandhi 18:6a4db94011d3 11099 /* Register: RADIO_BASE0 */
sahilmgandhi 18:6a4db94011d3 11100 /* Description: Base address 0 */
sahilmgandhi 18:6a4db94011d3 11101
sahilmgandhi 18:6a4db94011d3 11102 /* Bits 31..0 : Base address 0 */
sahilmgandhi 18:6a4db94011d3 11103 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
sahilmgandhi 18:6a4db94011d3 11104 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
sahilmgandhi 18:6a4db94011d3 11105
sahilmgandhi 18:6a4db94011d3 11106 /* Register: RADIO_BASE1 */
sahilmgandhi 18:6a4db94011d3 11107 /* Description: Base address 1 */
sahilmgandhi 18:6a4db94011d3 11108
sahilmgandhi 18:6a4db94011d3 11109 /* Bits 31..0 : Base address 1 */
sahilmgandhi 18:6a4db94011d3 11110 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
sahilmgandhi 18:6a4db94011d3 11111 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
sahilmgandhi 18:6a4db94011d3 11112
sahilmgandhi 18:6a4db94011d3 11113 /* Register: RADIO_PREFIX0 */
sahilmgandhi 18:6a4db94011d3 11114 /* Description: Prefixes bytes for logical addresses 0-3 */
sahilmgandhi 18:6a4db94011d3 11115
sahilmgandhi 18:6a4db94011d3 11116 /* Bits 31..24 : Address prefix 3. */
sahilmgandhi 18:6a4db94011d3 11117 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
sahilmgandhi 18:6a4db94011d3 11118 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
sahilmgandhi 18:6a4db94011d3 11119
sahilmgandhi 18:6a4db94011d3 11120 /* Bits 23..16 : Address prefix 2. */
sahilmgandhi 18:6a4db94011d3 11121 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
sahilmgandhi 18:6a4db94011d3 11122 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
sahilmgandhi 18:6a4db94011d3 11123
sahilmgandhi 18:6a4db94011d3 11124 /* Bits 15..8 : Address prefix 1. */
sahilmgandhi 18:6a4db94011d3 11125 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
sahilmgandhi 18:6a4db94011d3 11126 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
sahilmgandhi 18:6a4db94011d3 11127
sahilmgandhi 18:6a4db94011d3 11128 /* Bits 7..0 : Address prefix 0. */
sahilmgandhi 18:6a4db94011d3 11129 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
sahilmgandhi 18:6a4db94011d3 11130 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
sahilmgandhi 18:6a4db94011d3 11131
sahilmgandhi 18:6a4db94011d3 11132 /* Register: RADIO_PREFIX1 */
sahilmgandhi 18:6a4db94011d3 11133 /* Description: Prefixes bytes for logical addresses 4-7 */
sahilmgandhi 18:6a4db94011d3 11134
sahilmgandhi 18:6a4db94011d3 11135 /* Bits 31..24 : Address prefix 7. */
sahilmgandhi 18:6a4db94011d3 11136 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
sahilmgandhi 18:6a4db94011d3 11137 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
sahilmgandhi 18:6a4db94011d3 11138
sahilmgandhi 18:6a4db94011d3 11139 /* Bits 23..16 : Address prefix 6. */
sahilmgandhi 18:6a4db94011d3 11140 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
sahilmgandhi 18:6a4db94011d3 11141 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
sahilmgandhi 18:6a4db94011d3 11142
sahilmgandhi 18:6a4db94011d3 11143 /* Bits 15..8 : Address prefix 5. */
sahilmgandhi 18:6a4db94011d3 11144 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
sahilmgandhi 18:6a4db94011d3 11145 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
sahilmgandhi 18:6a4db94011d3 11146
sahilmgandhi 18:6a4db94011d3 11147 /* Bits 7..0 : Address prefix 4. */
sahilmgandhi 18:6a4db94011d3 11148 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
sahilmgandhi 18:6a4db94011d3 11149 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
sahilmgandhi 18:6a4db94011d3 11150
sahilmgandhi 18:6a4db94011d3 11151 /* Register: RADIO_TXADDRESS */
sahilmgandhi 18:6a4db94011d3 11152 /* Description: Transmit address select */
sahilmgandhi 18:6a4db94011d3 11153
sahilmgandhi 18:6a4db94011d3 11154 /* Bits 2..0 : Transmit address select */
sahilmgandhi 18:6a4db94011d3 11155 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
sahilmgandhi 18:6a4db94011d3 11156 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
sahilmgandhi 18:6a4db94011d3 11157
sahilmgandhi 18:6a4db94011d3 11158 /* Register: RADIO_RXADDRESSES */
sahilmgandhi 18:6a4db94011d3 11159 /* Description: Receive address select */
sahilmgandhi 18:6a4db94011d3 11160
sahilmgandhi 18:6a4db94011d3 11161 /* Bit 7 : Enable or disable reception on logical address 7. */
sahilmgandhi 18:6a4db94011d3 11162 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
sahilmgandhi 18:6a4db94011d3 11163 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
sahilmgandhi 18:6a4db94011d3 11164 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11165 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11166
sahilmgandhi 18:6a4db94011d3 11167 /* Bit 6 : Enable or disable reception on logical address 6. */
sahilmgandhi 18:6a4db94011d3 11168 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
sahilmgandhi 18:6a4db94011d3 11169 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
sahilmgandhi 18:6a4db94011d3 11170 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11171 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11172
sahilmgandhi 18:6a4db94011d3 11173 /* Bit 5 : Enable or disable reception on logical address 5. */
sahilmgandhi 18:6a4db94011d3 11174 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
sahilmgandhi 18:6a4db94011d3 11175 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
sahilmgandhi 18:6a4db94011d3 11176 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11177 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11178
sahilmgandhi 18:6a4db94011d3 11179 /* Bit 4 : Enable or disable reception on logical address 4. */
sahilmgandhi 18:6a4db94011d3 11180 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
sahilmgandhi 18:6a4db94011d3 11181 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
sahilmgandhi 18:6a4db94011d3 11182 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11183 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11184
sahilmgandhi 18:6a4db94011d3 11185 /* Bit 3 : Enable or disable reception on logical address 3. */
sahilmgandhi 18:6a4db94011d3 11186 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
sahilmgandhi 18:6a4db94011d3 11187 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
sahilmgandhi 18:6a4db94011d3 11188 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11189 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11190
sahilmgandhi 18:6a4db94011d3 11191 /* Bit 2 : Enable or disable reception on logical address 2. */
sahilmgandhi 18:6a4db94011d3 11192 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
sahilmgandhi 18:6a4db94011d3 11193 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
sahilmgandhi 18:6a4db94011d3 11194 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11195 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11196
sahilmgandhi 18:6a4db94011d3 11197 /* Bit 1 : Enable or disable reception on logical address 1. */
sahilmgandhi 18:6a4db94011d3 11198 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
sahilmgandhi 18:6a4db94011d3 11199 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
sahilmgandhi 18:6a4db94011d3 11200 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11201 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11202
sahilmgandhi 18:6a4db94011d3 11203 /* Bit 0 : Enable or disable reception on logical address 0. */
sahilmgandhi 18:6a4db94011d3 11204 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
sahilmgandhi 18:6a4db94011d3 11205 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
sahilmgandhi 18:6a4db94011d3 11206 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11207 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11208
sahilmgandhi 18:6a4db94011d3 11209 /* Register: RADIO_CRCCNF */
sahilmgandhi 18:6a4db94011d3 11210 /* Description: CRC configuration */
sahilmgandhi 18:6a4db94011d3 11211
sahilmgandhi 18:6a4db94011d3 11212 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
sahilmgandhi 18:6a4db94011d3 11213 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
sahilmgandhi 18:6a4db94011d3 11214 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
sahilmgandhi 18:6a4db94011d3 11215 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
sahilmgandhi 18:6a4db94011d3 11216 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
sahilmgandhi 18:6a4db94011d3 11217
sahilmgandhi 18:6a4db94011d3 11218 /* Bits 1..0 : CRC length in number of bytes. */
sahilmgandhi 18:6a4db94011d3 11219 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
sahilmgandhi 18:6a4db94011d3 11220 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
sahilmgandhi 18:6a4db94011d3 11221 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
sahilmgandhi 18:6a4db94011d3 11222 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
sahilmgandhi 18:6a4db94011d3 11223 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
sahilmgandhi 18:6a4db94011d3 11224 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
sahilmgandhi 18:6a4db94011d3 11225
sahilmgandhi 18:6a4db94011d3 11226 /* Register: RADIO_CRCPOLY */
sahilmgandhi 18:6a4db94011d3 11227 /* Description: CRC polynomial */
sahilmgandhi 18:6a4db94011d3 11228
sahilmgandhi 18:6a4db94011d3 11229 /* Bits 23..0 : CRC polynomial */
sahilmgandhi 18:6a4db94011d3 11230 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
sahilmgandhi 18:6a4db94011d3 11231 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
sahilmgandhi 18:6a4db94011d3 11232
sahilmgandhi 18:6a4db94011d3 11233 /* Register: RADIO_CRCINIT */
sahilmgandhi 18:6a4db94011d3 11234 /* Description: CRC initial value */
sahilmgandhi 18:6a4db94011d3 11235
sahilmgandhi 18:6a4db94011d3 11236 /* Bits 23..0 : CRC initial value */
sahilmgandhi 18:6a4db94011d3 11237 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
sahilmgandhi 18:6a4db94011d3 11238 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
sahilmgandhi 18:6a4db94011d3 11239
sahilmgandhi 18:6a4db94011d3 11240 /* Register: RADIO_TIFS */
sahilmgandhi 18:6a4db94011d3 11241 /* Description: Inter Frame Spacing in us */
sahilmgandhi 18:6a4db94011d3 11242
sahilmgandhi 18:6a4db94011d3 11243 /* Bits 7..0 : Inter Frame Spacing in us */
sahilmgandhi 18:6a4db94011d3 11244 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
sahilmgandhi 18:6a4db94011d3 11245 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
sahilmgandhi 18:6a4db94011d3 11246
sahilmgandhi 18:6a4db94011d3 11247 /* Register: RADIO_RSSISAMPLE */
sahilmgandhi 18:6a4db94011d3 11248 /* Description: RSSI sample */
sahilmgandhi 18:6a4db94011d3 11249
sahilmgandhi 18:6a4db94011d3 11250 /* Bits 6..0 : RSSI sample */
sahilmgandhi 18:6a4db94011d3 11251 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
sahilmgandhi 18:6a4db94011d3 11252 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
sahilmgandhi 18:6a4db94011d3 11253
sahilmgandhi 18:6a4db94011d3 11254 /* Register: RADIO_STATE */
sahilmgandhi 18:6a4db94011d3 11255 /* Description: Current radio state */
sahilmgandhi 18:6a4db94011d3 11256
sahilmgandhi 18:6a4db94011d3 11257 /* Bits 3..0 : Current radio state */
sahilmgandhi 18:6a4db94011d3 11258 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
sahilmgandhi 18:6a4db94011d3 11259 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
sahilmgandhi 18:6a4db94011d3 11260 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
sahilmgandhi 18:6a4db94011d3 11261 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
sahilmgandhi 18:6a4db94011d3 11262 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
sahilmgandhi 18:6a4db94011d3 11263 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
sahilmgandhi 18:6a4db94011d3 11264 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
sahilmgandhi 18:6a4db94011d3 11265 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
sahilmgandhi 18:6a4db94011d3 11266 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
sahilmgandhi 18:6a4db94011d3 11267 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
sahilmgandhi 18:6a4db94011d3 11268 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
sahilmgandhi 18:6a4db94011d3 11269
sahilmgandhi 18:6a4db94011d3 11270 /* Register: RADIO_DATAWHITEIV */
sahilmgandhi 18:6a4db94011d3 11271 /* Description: Data whitening initial value */
sahilmgandhi 18:6a4db94011d3 11272
sahilmgandhi 18:6a4db94011d3 11273 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
sahilmgandhi 18:6a4db94011d3 11274 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
sahilmgandhi 18:6a4db94011d3 11275 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
sahilmgandhi 18:6a4db94011d3 11276
sahilmgandhi 18:6a4db94011d3 11277 /* Register: RADIO_BCC */
sahilmgandhi 18:6a4db94011d3 11278 /* Description: Bit counter compare */
sahilmgandhi 18:6a4db94011d3 11279
sahilmgandhi 18:6a4db94011d3 11280 /* Bits 31..0 : Bit counter compare */
sahilmgandhi 18:6a4db94011d3 11281 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
sahilmgandhi 18:6a4db94011d3 11282 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
sahilmgandhi 18:6a4db94011d3 11283
sahilmgandhi 18:6a4db94011d3 11284 /* Register: RADIO_DAB */
sahilmgandhi 18:6a4db94011d3 11285 /* Description: Description collection[0]: Device address base segment 0 */
sahilmgandhi 18:6a4db94011d3 11286
sahilmgandhi 18:6a4db94011d3 11287 /* Bits 31..0 : Device address base segment 0 */
sahilmgandhi 18:6a4db94011d3 11288 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
sahilmgandhi 18:6a4db94011d3 11289 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
sahilmgandhi 18:6a4db94011d3 11290
sahilmgandhi 18:6a4db94011d3 11291 /* Register: RADIO_DAP */
sahilmgandhi 18:6a4db94011d3 11292 /* Description: Description collection[0]: Device address prefix 0 */
sahilmgandhi 18:6a4db94011d3 11293
sahilmgandhi 18:6a4db94011d3 11294 /* Bits 15..0 : Device address prefix 0 */
sahilmgandhi 18:6a4db94011d3 11295 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
sahilmgandhi 18:6a4db94011d3 11296 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
sahilmgandhi 18:6a4db94011d3 11297
sahilmgandhi 18:6a4db94011d3 11298 /* Register: RADIO_DACNF */
sahilmgandhi 18:6a4db94011d3 11299 /* Description: Device address match configuration */
sahilmgandhi 18:6a4db94011d3 11300
sahilmgandhi 18:6a4db94011d3 11301 /* Bit 15 : TxAdd for device address 7 */
sahilmgandhi 18:6a4db94011d3 11302 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
sahilmgandhi 18:6a4db94011d3 11303 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
sahilmgandhi 18:6a4db94011d3 11304
sahilmgandhi 18:6a4db94011d3 11305 /* Bit 14 : TxAdd for device address 6 */
sahilmgandhi 18:6a4db94011d3 11306 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
sahilmgandhi 18:6a4db94011d3 11307 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
sahilmgandhi 18:6a4db94011d3 11308
sahilmgandhi 18:6a4db94011d3 11309 /* Bit 13 : TxAdd for device address 5 */
sahilmgandhi 18:6a4db94011d3 11310 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
sahilmgandhi 18:6a4db94011d3 11311 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
sahilmgandhi 18:6a4db94011d3 11312
sahilmgandhi 18:6a4db94011d3 11313 /* Bit 12 : TxAdd for device address 4 */
sahilmgandhi 18:6a4db94011d3 11314 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
sahilmgandhi 18:6a4db94011d3 11315 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
sahilmgandhi 18:6a4db94011d3 11316
sahilmgandhi 18:6a4db94011d3 11317 /* Bit 11 : TxAdd for device address 3 */
sahilmgandhi 18:6a4db94011d3 11318 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
sahilmgandhi 18:6a4db94011d3 11319 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
sahilmgandhi 18:6a4db94011d3 11320
sahilmgandhi 18:6a4db94011d3 11321 /* Bit 10 : TxAdd for device address 2 */
sahilmgandhi 18:6a4db94011d3 11322 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
sahilmgandhi 18:6a4db94011d3 11323 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
sahilmgandhi 18:6a4db94011d3 11324
sahilmgandhi 18:6a4db94011d3 11325 /* Bit 9 : TxAdd for device address 1 */
sahilmgandhi 18:6a4db94011d3 11326 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
sahilmgandhi 18:6a4db94011d3 11327 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
sahilmgandhi 18:6a4db94011d3 11328
sahilmgandhi 18:6a4db94011d3 11329 /* Bit 8 : TxAdd for device address 0 */
sahilmgandhi 18:6a4db94011d3 11330 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
sahilmgandhi 18:6a4db94011d3 11331 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
sahilmgandhi 18:6a4db94011d3 11332
sahilmgandhi 18:6a4db94011d3 11333 /* Bit 7 : Enable or disable device address matching using device address 7 */
sahilmgandhi 18:6a4db94011d3 11334 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
sahilmgandhi 18:6a4db94011d3 11335 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
sahilmgandhi 18:6a4db94011d3 11336 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11337 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11338
sahilmgandhi 18:6a4db94011d3 11339 /* Bit 6 : Enable or disable device address matching using device address 6 */
sahilmgandhi 18:6a4db94011d3 11340 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
sahilmgandhi 18:6a4db94011d3 11341 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
sahilmgandhi 18:6a4db94011d3 11342 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11343 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11344
sahilmgandhi 18:6a4db94011d3 11345 /* Bit 5 : Enable or disable device address matching using device address 5 */
sahilmgandhi 18:6a4db94011d3 11346 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
sahilmgandhi 18:6a4db94011d3 11347 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
sahilmgandhi 18:6a4db94011d3 11348 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11349 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11350
sahilmgandhi 18:6a4db94011d3 11351 /* Bit 4 : Enable or disable device address matching using device address 4 */
sahilmgandhi 18:6a4db94011d3 11352 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
sahilmgandhi 18:6a4db94011d3 11353 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
sahilmgandhi 18:6a4db94011d3 11354 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11355 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11356
sahilmgandhi 18:6a4db94011d3 11357 /* Bit 3 : Enable or disable device address matching using device address 3 */
sahilmgandhi 18:6a4db94011d3 11358 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
sahilmgandhi 18:6a4db94011d3 11359 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
sahilmgandhi 18:6a4db94011d3 11360 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11361 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11362
sahilmgandhi 18:6a4db94011d3 11363 /* Bit 2 : Enable or disable device address matching using device address 2 */
sahilmgandhi 18:6a4db94011d3 11364 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
sahilmgandhi 18:6a4db94011d3 11365 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
sahilmgandhi 18:6a4db94011d3 11366 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11367 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11368
sahilmgandhi 18:6a4db94011d3 11369 /* Bit 1 : Enable or disable device address matching using device address 1 */
sahilmgandhi 18:6a4db94011d3 11370 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
sahilmgandhi 18:6a4db94011d3 11371 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
sahilmgandhi 18:6a4db94011d3 11372 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11373 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11374
sahilmgandhi 18:6a4db94011d3 11375 /* Bit 0 : Enable or disable device address matching using device address 0 */
sahilmgandhi 18:6a4db94011d3 11376 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
sahilmgandhi 18:6a4db94011d3 11377 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
sahilmgandhi 18:6a4db94011d3 11378 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11379 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11380
sahilmgandhi 18:6a4db94011d3 11381 /* Register: RADIO_MODECNF0 */
sahilmgandhi 18:6a4db94011d3 11382 /* Description: Radio mode configuration register 0 */
sahilmgandhi 18:6a4db94011d3 11383
sahilmgandhi 18:6a4db94011d3 11384 /* Bits 9..8 : Default TX value */
sahilmgandhi 18:6a4db94011d3 11385 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
sahilmgandhi 18:6a4db94011d3 11386 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
sahilmgandhi 18:6a4db94011d3 11387 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
sahilmgandhi 18:6a4db94011d3 11388 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
sahilmgandhi 18:6a4db94011d3 11389 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
sahilmgandhi 18:6a4db94011d3 11390
sahilmgandhi 18:6a4db94011d3 11391 /* Bit 0 : Radio ramp-up time */
sahilmgandhi 18:6a4db94011d3 11392 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
sahilmgandhi 18:6a4db94011d3 11393 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
sahilmgandhi 18:6a4db94011d3 11394 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
sahilmgandhi 18:6a4db94011d3 11395 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
sahilmgandhi 18:6a4db94011d3 11396
sahilmgandhi 18:6a4db94011d3 11397 /* Register: RADIO_POWER */
sahilmgandhi 18:6a4db94011d3 11398 /* Description: Peripheral power control */
sahilmgandhi 18:6a4db94011d3 11399
sahilmgandhi 18:6a4db94011d3 11400 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
sahilmgandhi 18:6a4db94011d3 11401 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 11402 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 11403 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
sahilmgandhi 18:6a4db94011d3 11404 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
sahilmgandhi 18:6a4db94011d3 11405
sahilmgandhi 18:6a4db94011d3 11406
sahilmgandhi 18:6a4db94011d3 11407 /* Peripheral: RNG */
sahilmgandhi 18:6a4db94011d3 11408 /* Description: Random Number Generator */
sahilmgandhi 18:6a4db94011d3 11409
sahilmgandhi 18:6a4db94011d3 11410 /* Register: RNG_SHORTS */
sahilmgandhi 18:6a4db94011d3 11411 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 11412
sahilmgandhi 18:6a4db94011d3 11413 /* Bit 0 : Shortcut between VALRDY event and STOP task */
sahilmgandhi 18:6a4db94011d3 11414 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 11415 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 11416 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 11417 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 11418
sahilmgandhi 18:6a4db94011d3 11419 /* Register: RNG_INTENSET */
sahilmgandhi 18:6a4db94011d3 11420 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 11421
sahilmgandhi 18:6a4db94011d3 11422 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
sahilmgandhi 18:6a4db94011d3 11423 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 11424 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 11425 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11426 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11427 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11428
sahilmgandhi 18:6a4db94011d3 11429 /* Register: RNG_INTENCLR */
sahilmgandhi 18:6a4db94011d3 11430 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 11431
sahilmgandhi 18:6a4db94011d3 11432 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
sahilmgandhi 18:6a4db94011d3 11433 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 11434 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 11435 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11436 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11437 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11438
sahilmgandhi 18:6a4db94011d3 11439 /* Register: RNG_CONFIG */
sahilmgandhi 18:6a4db94011d3 11440 /* Description: Configuration register */
sahilmgandhi 18:6a4db94011d3 11441
sahilmgandhi 18:6a4db94011d3 11442 /* Bit 0 : Bias correction */
sahilmgandhi 18:6a4db94011d3 11443 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
sahilmgandhi 18:6a4db94011d3 11444 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
sahilmgandhi 18:6a4db94011d3 11445 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 11446 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 11447
sahilmgandhi 18:6a4db94011d3 11448 /* Register: RNG_VALUE */
sahilmgandhi 18:6a4db94011d3 11449 /* Description: Output random number */
sahilmgandhi 18:6a4db94011d3 11450
sahilmgandhi 18:6a4db94011d3 11451 /* Bits 7..0 : Generated random number */
sahilmgandhi 18:6a4db94011d3 11452 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
sahilmgandhi 18:6a4db94011d3 11453 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
sahilmgandhi 18:6a4db94011d3 11454
sahilmgandhi 18:6a4db94011d3 11455
sahilmgandhi 18:6a4db94011d3 11456 /* Peripheral: RTC */
sahilmgandhi 18:6a4db94011d3 11457 /* Description: Real time counter 0 */
sahilmgandhi 18:6a4db94011d3 11458
sahilmgandhi 18:6a4db94011d3 11459 /* Register: RTC_INTENSET */
sahilmgandhi 18:6a4db94011d3 11460 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 11461
sahilmgandhi 18:6a4db94011d3 11462 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 11463 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11464 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11465 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11466 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11467 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11468
sahilmgandhi 18:6a4db94011d3 11469 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 11470 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11471 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11472 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11473 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11474 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11475
sahilmgandhi 18:6a4db94011d3 11476 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 11477 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11478 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11479 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11480 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11481 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11482
sahilmgandhi 18:6a4db94011d3 11483 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 11484 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11485 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11486 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11487 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11488 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11489
sahilmgandhi 18:6a4db94011d3 11490 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
sahilmgandhi 18:6a4db94011d3 11491 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11492 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11493 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11494 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11495 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11496
sahilmgandhi 18:6a4db94011d3 11497 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
sahilmgandhi 18:6a4db94011d3 11498 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 11499 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 11500 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11501 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11502 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11503
sahilmgandhi 18:6a4db94011d3 11504 /* Register: RTC_INTENCLR */
sahilmgandhi 18:6a4db94011d3 11505 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 11506
sahilmgandhi 18:6a4db94011d3 11507 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 11508 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11509 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11510 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11511 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11512 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11513
sahilmgandhi 18:6a4db94011d3 11514 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 11515 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11516 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11517 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11518 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11519 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11520
sahilmgandhi 18:6a4db94011d3 11521 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 11522 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11523 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11524 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11525 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11526 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11527
sahilmgandhi 18:6a4db94011d3 11528 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 11529 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11530 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11531 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11532 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11533 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11534
sahilmgandhi 18:6a4db94011d3 11535 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
sahilmgandhi 18:6a4db94011d3 11536 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11537 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11538 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11539 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11540 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11541
sahilmgandhi 18:6a4db94011d3 11542 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
sahilmgandhi 18:6a4db94011d3 11543 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 11544 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 11545 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11546 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11547 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11548
sahilmgandhi 18:6a4db94011d3 11549 /* Register: RTC_EVTEN */
sahilmgandhi 18:6a4db94011d3 11550 /* Description: Enable or disable event routing */
sahilmgandhi 18:6a4db94011d3 11551
sahilmgandhi 18:6a4db94011d3 11552 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 11553 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11554 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11555 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11556 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11557
sahilmgandhi 18:6a4db94011d3 11558 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 11559 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11560 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11561 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11562 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11563
sahilmgandhi 18:6a4db94011d3 11564 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 11565 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11566 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11567 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11568 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11569
sahilmgandhi 18:6a4db94011d3 11570 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 11571 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11572 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11573 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11574 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11575
sahilmgandhi 18:6a4db94011d3 11576 /* Bit 1 : Enable or disable event routing for OVRFLW event */
sahilmgandhi 18:6a4db94011d3 11577 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11578 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11579 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11580 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11581
sahilmgandhi 18:6a4db94011d3 11582 /* Bit 0 : Enable or disable event routing for TICK event */
sahilmgandhi 18:6a4db94011d3 11583 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 11584 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 11585 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11586 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11587
sahilmgandhi 18:6a4db94011d3 11588 /* Register: RTC_EVTENSET */
sahilmgandhi 18:6a4db94011d3 11589 /* Description: Enable event routing */
sahilmgandhi 18:6a4db94011d3 11590
sahilmgandhi 18:6a4db94011d3 11591 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 11592 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11593 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11594 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11595 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11596 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11597
sahilmgandhi 18:6a4db94011d3 11598 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 11599 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11600 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11601 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11602 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11603 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11604
sahilmgandhi 18:6a4db94011d3 11605 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 11606 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11607 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11608 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11609 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11610 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11611
sahilmgandhi 18:6a4db94011d3 11612 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 11613 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11614 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11615 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11616 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11617 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11618
sahilmgandhi 18:6a4db94011d3 11619 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
sahilmgandhi 18:6a4db94011d3 11620 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11621 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11622 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11623 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11624 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11625
sahilmgandhi 18:6a4db94011d3 11626 /* Bit 0 : Write '1' to Enable event routing for TICK event */
sahilmgandhi 18:6a4db94011d3 11627 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 11628 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 11629 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11630 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11631 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11632
sahilmgandhi 18:6a4db94011d3 11633 /* Register: RTC_EVTENCLR */
sahilmgandhi 18:6a4db94011d3 11634 /* Description: Disable event routing */
sahilmgandhi 18:6a4db94011d3 11635
sahilmgandhi 18:6a4db94011d3 11636 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 11637 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11638 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 11639 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11640 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11641 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11642
sahilmgandhi 18:6a4db94011d3 11643 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 11644 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11645 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 11646 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11647 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11648 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11649
sahilmgandhi 18:6a4db94011d3 11650 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 11651 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11652 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 11653 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11654 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11655 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11656
sahilmgandhi 18:6a4db94011d3 11657 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 11658 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11659 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 11660 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11661 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11662 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11663
sahilmgandhi 18:6a4db94011d3 11664 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
sahilmgandhi 18:6a4db94011d3 11665 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11666 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 11667 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11668 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11669 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11670
sahilmgandhi 18:6a4db94011d3 11671 /* Bit 0 : Write '1' to Disable event routing for TICK event */
sahilmgandhi 18:6a4db94011d3 11672 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 11673 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 11674 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11675 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11676 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11677
sahilmgandhi 18:6a4db94011d3 11678 /* Register: RTC_COUNTER */
sahilmgandhi 18:6a4db94011d3 11679 /* Description: Current COUNTER value */
sahilmgandhi 18:6a4db94011d3 11680
sahilmgandhi 18:6a4db94011d3 11681 /* Bits 23..0 : Counter value */
sahilmgandhi 18:6a4db94011d3 11682 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
sahilmgandhi 18:6a4db94011d3 11683 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
sahilmgandhi 18:6a4db94011d3 11684
sahilmgandhi 18:6a4db94011d3 11685 /* Register: RTC_PRESCALER */
sahilmgandhi 18:6a4db94011d3 11686 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
sahilmgandhi 18:6a4db94011d3 11687
sahilmgandhi 18:6a4db94011d3 11688 /* Bits 11..0 : Prescaler value */
sahilmgandhi 18:6a4db94011d3 11689 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 11690 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 11691
sahilmgandhi 18:6a4db94011d3 11692 /* Register: RTC_CC */
sahilmgandhi 18:6a4db94011d3 11693 /* Description: Description collection[0]: Compare register 0 */
sahilmgandhi 18:6a4db94011d3 11694
sahilmgandhi 18:6a4db94011d3 11695 /* Bits 23..0 : Compare value */
sahilmgandhi 18:6a4db94011d3 11696 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
sahilmgandhi 18:6a4db94011d3 11697 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
sahilmgandhi 18:6a4db94011d3 11698
sahilmgandhi 18:6a4db94011d3 11699
sahilmgandhi 18:6a4db94011d3 11700 /* Peripheral: SAADC */
sahilmgandhi 18:6a4db94011d3 11701 /* Description: Analog to Digital Converter */
sahilmgandhi 18:6a4db94011d3 11702
sahilmgandhi 18:6a4db94011d3 11703 /* Register: SAADC_INTEN */
sahilmgandhi 18:6a4db94011d3 11704 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 11705
sahilmgandhi 18:6a4db94011d3 11706 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11707 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11708 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11709 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11710 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11711
sahilmgandhi 18:6a4db94011d3 11712 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11713 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11714 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11715 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11716 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11717
sahilmgandhi 18:6a4db94011d3 11718 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11719 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11720 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11721 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11722 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11723
sahilmgandhi 18:6a4db94011d3 11724 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11725 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11726 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11727 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11728 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11729
sahilmgandhi 18:6a4db94011d3 11730 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11731 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11732 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11733 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11734 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11735
sahilmgandhi 18:6a4db94011d3 11736 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11737 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11738 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11739 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11740 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11741
sahilmgandhi 18:6a4db94011d3 11742 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11743 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11744 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11745 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11746 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11747
sahilmgandhi 18:6a4db94011d3 11748 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11749 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11750 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11751 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11752 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11753
sahilmgandhi 18:6a4db94011d3 11754 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11755 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11756 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11757 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11758 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11759
sahilmgandhi 18:6a4db94011d3 11760 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11761 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11762 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11763 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11764 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11765
sahilmgandhi 18:6a4db94011d3 11766 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11767 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11768 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11769 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11770 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11771
sahilmgandhi 18:6a4db94011d3 11772 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11773 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11774 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11775 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11776 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11777
sahilmgandhi 18:6a4db94011d3 11778 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11779 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11780 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11781 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11782 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11783
sahilmgandhi 18:6a4db94011d3 11784 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11785 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11786 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11787 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11788 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11789
sahilmgandhi 18:6a4db94011d3 11790 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11791 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11792 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11793 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11794 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11795
sahilmgandhi 18:6a4db94011d3 11796 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11797 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11798 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11799 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11800 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11801
sahilmgandhi 18:6a4db94011d3 11802 /* Bit 5 : Enable or disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 11803 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 11804 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 11805 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11806 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11807
sahilmgandhi 18:6a4db94011d3 11808 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
sahilmgandhi 18:6a4db94011d3 11809 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
sahilmgandhi 18:6a4db94011d3 11810 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
sahilmgandhi 18:6a4db94011d3 11811 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11812 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11813
sahilmgandhi 18:6a4db94011d3 11814 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
sahilmgandhi 18:6a4db94011d3 11815 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
sahilmgandhi 18:6a4db94011d3 11816 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
sahilmgandhi 18:6a4db94011d3 11817 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11818 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11819
sahilmgandhi 18:6a4db94011d3 11820 /* Bit 2 : Enable or disable interrupt for DONE event */
sahilmgandhi 18:6a4db94011d3 11821 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 11822 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 11823 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11824 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11825
sahilmgandhi 18:6a4db94011d3 11826 /* Bit 1 : Enable or disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 11827 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 11828 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 11829 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11830 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11831
sahilmgandhi 18:6a4db94011d3 11832 /* Bit 0 : Enable or disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 11833 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 11834 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 11835 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 11836 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11837
sahilmgandhi 18:6a4db94011d3 11838 /* Register: SAADC_INTENSET */
sahilmgandhi 18:6a4db94011d3 11839 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 11840
sahilmgandhi 18:6a4db94011d3 11841 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11842 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11843 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11844 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11845 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11846 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11847
sahilmgandhi 18:6a4db94011d3 11848 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11849 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11850 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11851 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11852 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11853 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11854
sahilmgandhi 18:6a4db94011d3 11855 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11856 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11857 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11858 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11859 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11860 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11861
sahilmgandhi 18:6a4db94011d3 11862 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11863 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11864 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11865 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11866 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11867 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11868
sahilmgandhi 18:6a4db94011d3 11869 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11870 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11871 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11872 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11873 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11874 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11875
sahilmgandhi 18:6a4db94011d3 11876 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11877 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11878 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11879 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11880 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11881 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11882
sahilmgandhi 18:6a4db94011d3 11883 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11884 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11885 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11886 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11887 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11888 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11889
sahilmgandhi 18:6a4db94011d3 11890 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11891 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11892 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11893 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11894 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11895 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11896
sahilmgandhi 18:6a4db94011d3 11897 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11898 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11899 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11900 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11901 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11902 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11903
sahilmgandhi 18:6a4db94011d3 11904 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11905 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11906 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11907 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11908 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11909 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11910
sahilmgandhi 18:6a4db94011d3 11911 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11912 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11913 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11914 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11915 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11916 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11917
sahilmgandhi 18:6a4db94011d3 11918 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11919 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11920 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11921 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11922 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11923 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11924
sahilmgandhi 18:6a4db94011d3 11925 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11926 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11927 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11928 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11929 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11930 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11931
sahilmgandhi 18:6a4db94011d3 11932 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11933 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11934 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11935 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11936 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11937 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11938
sahilmgandhi 18:6a4db94011d3 11939 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11940 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11941 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
sahilmgandhi 18:6a4db94011d3 11942 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11943 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11944 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11945
sahilmgandhi 18:6a4db94011d3 11946 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
sahilmgandhi 18:6a4db94011d3 11947 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11948 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
sahilmgandhi 18:6a4db94011d3 11949 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11950 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11951 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11952
sahilmgandhi 18:6a4db94011d3 11953 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 11954 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 11955 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 11956 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11957 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11958 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11959
sahilmgandhi 18:6a4db94011d3 11960 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
sahilmgandhi 18:6a4db94011d3 11961 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
sahilmgandhi 18:6a4db94011d3 11962 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
sahilmgandhi 18:6a4db94011d3 11963 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11964 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11965 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11966
sahilmgandhi 18:6a4db94011d3 11967 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
sahilmgandhi 18:6a4db94011d3 11968 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
sahilmgandhi 18:6a4db94011d3 11969 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
sahilmgandhi 18:6a4db94011d3 11970 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11971 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11972 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11973
sahilmgandhi 18:6a4db94011d3 11974 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
sahilmgandhi 18:6a4db94011d3 11975 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 11976 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 11977 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11978 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11979 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11980
sahilmgandhi 18:6a4db94011d3 11981 /* Bit 1 : Write '1' to Enable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 11982 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 11983 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 11984 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11985 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11986 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11987
sahilmgandhi 18:6a4db94011d3 11988 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 11989 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 11990 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 11991 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 11992 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 11993 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 11994
sahilmgandhi 18:6a4db94011d3 11995 /* Register: SAADC_INTENCLR */
sahilmgandhi 18:6a4db94011d3 11996 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 11997
sahilmgandhi 18:6a4db94011d3 11998 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
sahilmgandhi 18:6a4db94011d3 11999 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12000 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12001 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12002 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12003 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12004
sahilmgandhi 18:6a4db94011d3 12005 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12006 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12007 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12008 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12009 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12010 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12011
sahilmgandhi 18:6a4db94011d3 12012 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12013 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12014 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12015 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12016 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12017 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12018
sahilmgandhi 18:6a4db94011d3 12019 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12020 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12021 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12022 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12023 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12024 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12025
sahilmgandhi 18:6a4db94011d3 12026 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12027 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12028 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12029 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12030 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12031 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12032
sahilmgandhi 18:6a4db94011d3 12033 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12034 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12035 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12036 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12037 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12038 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12039
sahilmgandhi 18:6a4db94011d3 12040 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12041 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12042 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12043 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12044 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12045 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12046
sahilmgandhi 18:6a4db94011d3 12047 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12048 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12049 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12050 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12051 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12052 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12053
sahilmgandhi 18:6a4db94011d3 12054 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12055 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12056 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12057 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12058 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12059 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12060
sahilmgandhi 18:6a4db94011d3 12061 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12062 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12063 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12064 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12065 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12066 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12067
sahilmgandhi 18:6a4db94011d3 12068 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12069 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12070 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12071 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12072 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12073 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12074
sahilmgandhi 18:6a4db94011d3 12075 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12076 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12077 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12078 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12079 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12080 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12081
sahilmgandhi 18:6a4db94011d3 12082 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12083 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12084 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12085 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12086 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12087 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12088
sahilmgandhi 18:6a4db94011d3 12089 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12090 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12091 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12092 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12093 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12094 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12095
sahilmgandhi 18:6a4db94011d3 12096 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
sahilmgandhi 18:6a4db94011d3 12097 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12098 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
sahilmgandhi 18:6a4db94011d3 12099 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12100 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12101 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12102
sahilmgandhi 18:6a4db94011d3 12103 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
sahilmgandhi 18:6a4db94011d3 12104 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12105 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
sahilmgandhi 18:6a4db94011d3 12106 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12107 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12108 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12109
sahilmgandhi 18:6a4db94011d3 12110 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 12111 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 12112 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 12113 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12114 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12115 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12116
sahilmgandhi 18:6a4db94011d3 12117 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
sahilmgandhi 18:6a4db94011d3 12118 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
sahilmgandhi 18:6a4db94011d3 12119 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
sahilmgandhi 18:6a4db94011d3 12120 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12121 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12122 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12123
sahilmgandhi 18:6a4db94011d3 12124 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
sahilmgandhi 18:6a4db94011d3 12125 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
sahilmgandhi 18:6a4db94011d3 12126 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
sahilmgandhi 18:6a4db94011d3 12127 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12128 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12129 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12130
sahilmgandhi 18:6a4db94011d3 12131 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
sahilmgandhi 18:6a4db94011d3 12132 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 12133 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 12134 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12135 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12136 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12137
sahilmgandhi 18:6a4db94011d3 12138 /* Bit 1 : Write '1' to Disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 12139 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 12140 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 12141 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12142 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12143 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12144
sahilmgandhi 18:6a4db94011d3 12145 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 12146 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 12147 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 12148 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12149 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12150 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12151
sahilmgandhi 18:6a4db94011d3 12152 /* Register: SAADC_STATUS */
sahilmgandhi 18:6a4db94011d3 12153 /* Description: Status */
sahilmgandhi 18:6a4db94011d3 12154
sahilmgandhi 18:6a4db94011d3 12155 /* Bit 0 : Status */
sahilmgandhi 18:6a4db94011d3 12156 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 12157 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 12158 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
sahilmgandhi 18:6a4db94011d3 12159 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
sahilmgandhi 18:6a4db94011d3 12160
sahilmgandhi 18:6a4db94011d3 12161 /* Register: SAADC_ENABLE */
sahilmgandhi 18:6a4db94011d3 12162 /* Description: Enable or disable ADC */
sahilmgandhi 18:6a4db94011d3 12163
sahilmgandhi 18:6a4db94011d3 12164 /* Bit 0 : Enable or disable ADC */
sahilmgandhi 18:6a4db94011d3 12165 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12166 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12167 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
sahilmgandhi 18:6a4db94011d3 12168 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
sahilmgandhi 18:6a4db94011d3 12169
sahilmgandhi 18:6a4db94011d3 12170 /* Register: SAADC_CH_PSELP */
sahilmgandhi 18:6a4db94011d3 12171 /* Description: Description cluster[0]: Input positive pin selection for CH[0] */
sahilmgandhi 18:6a4db94011d3 12172
sahilmgandhi 18:6a4db94011d3 12173 /* Bits 4..0 : Analog positive input channel */
sahilmgandhi 18:6a4db94011d3 12174 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
sahilmgandhi 18:6a4db94011d3 12175 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
sahilmgandhi 18:6a4db94011d3 12176 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
sahilmgandhi 18:6a4db94011d3 12177 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
sahilmgandhi 18:6a4db94011d3 12178 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
sahilmgandhi 18:6a4db94011d3 12179 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
sahilmgandhi 18:6a4db94011d3 12180 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
sahilmgandhi 18:6a4db94011d3 12181 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
sahilmgandhi 18:6a4db94011d3 12182 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
sahilmgandhi 18:6a4db94011d3 12183 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
sahilmgandhi 18:6a4db94011d3 12184 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
sahilmgandhi 18:6a4db94011d3 12185 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
sahilmgandhi 18:6a4db94011d3 12186
sahilmgandhi 18:6a4db94011d3 12187 /* Register: SAADC_CH_PSELN */
sahilmgandhi 18:6a4db94011d3 12188 /* Description: Description cluster[0]: Input negative pin selection for CH[0] */
sahilmgandhi 18:6a4db94011d3 12189
sahilmgandhi 18:6a4db94011d3 12190 /* Bits 4..0 : Analog negative input, enables differential channel */
sahilmgandhi 18:6a4db94011d3 12191 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
sahilmgandhi 18:6a4db94011d3 12192 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
sahilmgandhi 18:6a4db94011d3 12193 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
sahilmgandhi 18:6a4db94011d3 12194 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
sahilmgandhi 18:6a4db94011d3 12195 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
sahilmgandhi 18:6a4db94011d3 12196 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
sahilmgandhi 18:6a4db94011d3 12197 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
sahilmgandhi 18:6a4db94011d3 12198 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
sahilmgandhi 18:6a4db94011d3 12199 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
sahilmgandhi 18:6a4db94011d3 12200 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
sahilmgandhi 18:6a4db94011d3 12201 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
sahilmgandhi 18:6a4db94011d3 12202 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
sahilmgandhi 18:6a4db94011d3 12203
sahilmgandhi 18:6a4db94011d3 12204 /* Register: SAADC_CH_CONFIG */
sahilmgandhi 18:6a4db94011d3 12205 /* Description: Description cluster[0]: Input configuration for CH[0] */
sahilmgandhi 18:6a4db94011d3 12206
sahilmgandhi 18:6a4db94011d3 12207 /* Bit 24 : Enable burst mode */
sahilmgandhi 18:6a4db94011d3 12208 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
sahilmgandhi 18:6a4db94011d3 12209 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
sahilmgandhi 18:6a4db94011d3 12210 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
sahilmgandhi 18:6a4db94011d3 12211 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
sahilmgandhi 18:6a4db94011d3 12212
sahilmgandhi 18:6a4db94011d3 12213 /* Bit 20 : Enable differential mode */
sahilmgandhi 18:6a4db94011d3 12214 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 12215 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 12216 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
sahilmgandhi 18:6a4db94011d3 12217 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
sahilmgandhi 18:6a4db94011d3 12218
sahilmgandhi 18:6a4db94011d3 12219 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
sahilmgandhi 18:6a4db94011d3 12220 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
sahilmgandhi 18:6a4db94011d3 12221 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
sahilmgandhi 18:6a4db94011d3 12222 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
sahilmgandhi 18:6a4db94011d3 12223 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
sahilmgandhi 18:6a4db94011d3 12224 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
sahilmgandhi 18:6a4db94011d3 12225 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
sahilmgandhi 18:6a4db94011d3 12226 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
sahilmgandhi 18:6a4db94011d3 12227 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
sahilmgandhi 18:6a4db94011d3 12228
sahilmgandhi 18:6a4db94011d3 12229 /* Bit 12 : Reference control */
sahilmgandhi 18:6a4db94011d3 12230 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 12231 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 12232 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
sahilmgandhi 18:6a4db94011d3 12233 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
sahilmgandhi 18:6a4db94011d3 12234
sahilmgandhi 18:6a4db94011d3 12235 /* Bits 10..8 : Gain control */
sahilmgandhi 18:6a4db94011d3 12236 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
sahilmgandhi 18:6a4db94011d3 12237 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
sahilmgandhi 18:6a4db94011d3 12238 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
sahilmgandhi 18:6a4db94011d3 12239 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
sahilmgandhi 18:6a4db94011d3 12240 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
sahilmgandhi 18:6a4db94011d3 12241 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
sahilmgandhi 18:6a4db94011d3 12242 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
sahilmgandhi 18:6a4db94011d3 12243 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
sahilmgandhi 18:6a4db94011d3 12244 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
sahilmgandhi 18:6a4db94011d3 12245 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
sahilmgandhi 18:6a4db94011d3 12246
sahilmgandhi 18:6a4db94011d3 12247 /* Bits 5..4 : Negative channel resistor control */
sahilmgandhi 18:6a4db94011d3 12248 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
sahilmgandhi 18:6a4db94011d3 12249 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
sahilmgandhi 18:6a4db94011d3 12250 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
sahilmgandhi 18:6a4db94011d3 12251 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
sahilmgandhi 18:6a4db94011d3 12252 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
sahilmgandhi 18:6a4db94011d3 12253 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
sahilmgandhi 18:6a4db94011d3 12254
sahilmgandhi 18:6a4db94011d3 12255 /* Bits 1..0 : Positive channel resistor control */
sahilmgandhi 18:6a4db94011d3 12256 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
sahilmgandhi 18:6a4db94011d3 12257 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
sahilmgandhi 18:6a4db94011d3 12258 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
sahilmgandhi 18:6a4db94011d3 12259 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
sahilmgandhi 18:6a4db94011d3 12260 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
sahilmgandhi 18:6a4db94011d3 12261 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
sahilmgandhi 18:6a4db94011d3 12262
sahilmgandhi 18:6a4db94011d3 12263 /* Register: SAADC_CH_LIMIT */
sahilmgandhi 18:6a4db94011d3 12264 /* Description: Description cluster[0]: High/low limits for event monitoring a channel */
sahilmgandhi 18:6a4db94011d3 12265
sahilmgandhi 18:6a4db94011d3 12266 /* Bits 31..16 : High level limit */
sahilmgandhi 18:6a4db94011d3 12267 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
sahilmgandhi 18:6a4db94011d3 12268 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
sahilmgandhi 18:6a4db94011d3 12269
sahilmgandhi 18:6a4db94011d3 12270 /* Bits 15..0 : Low level limit */
sahilmgandhi 18:6a4db94011d3 12271 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
sahilmgandhi 18:6a4db94011d3 12272 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
sahilmgandhi 18:6a4db94011d3 12273
sahilmgandhi 18:6a4db94011d3 12274 /* Register: SAADC_RESOLUTION */
sahilmgandhi 18:6a4db94011d3 12275 /* Description: Resolution configuration */
sahilmgandhi 18:6a4db94011d3 12276
sahilmgandhi 18:6a4db94011d3 12277 /* Bits 2..0 : Set the resolution */
sahilmgandhi 18:6a4db94011d3 12278 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
sahilmgandhi 18:6a4db94011d3 12279 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
sahilmgandhi 18:6a4db94011d3 12280 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
sahilmgandhi 18:6a4db94011d3 12281 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
sahilmgandhi 18:6a4db94011d3 12282 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
sahilmgandhi 18:6a4db94011d3 12283 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
sahilmgandhi 18:6a4db94011d3 12284
sahilmgandhi 18:6a4db94011d3 12285 /* Register: SAADC_OVERSAMPLE */
sahilmgandhi 18:6a4db94011d3 12286 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
sahilmgandhi 18:6a4db94011d3 12287
sahilmgandhi 18:6a4db94011d3 12288 /* Bits 3..0 : Oversample control */
sahilmgandhi 18:6a4db94011d3 12289 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
sahilmgandhi 18:6a4db94011d3 12290 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
sahilmgandhi 18:6a4db94011d3 12291 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
sahilmgandhi 18:6a4db94011d3 12292 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
sahilmgandhi 18:6a4db94011d3 12293 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
sahilmgandhi 18:6a4db94011d3 12294 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
sahilmgandhi 18:6a4db94011d3 12295 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
sahilmgandhi 18:6a4db94011d3 12296 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
sahilmgandhi 18:6a4db94011d3 12297 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
sahilmgandhi 18:6a4db94011d3 12298 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
sahilmgandhi 18:6a4db94011d3 12299 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
sahilmgandhi 18:6a4db94011d3 12300
sahilmgandhi 18:6a4db94011d3 12301 /* Register: SAADC_SAMPLERATE */
sahilmgandhi 18:6a4db94011d3 12302 /* Description: Controls normal or continuous sample rate */
sahilmgandhi 18:6a4db94011d3 12303
sahilmgandhi 18:6a4db94011d3 12304 /* Bit 12 : Select mode for sample rate control */
sahilmgandhi 18:6a4db94011d3 12305 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 12306 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 12307 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
sahilmgandhi 18:6a4db94011d3 12308 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
sahilmgandhi 18:6a4db94011d3 12309
sahilmgandhi 18:6a4db94011d3 12310 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
sahilmgandhi 18:6a4db94011d3 12311 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
sahilmgandhi 18:6a4db94011d3 12312 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
sahilmgandhi 18:6a4db94011d3 12313
sahilmgandhi 18:6a4db94011d3 12314 /* Register: SAADC_RESULT_PTR */
sahilmgandhi 18:6a4db94011d3 12315 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 12316
sahilmgandhi 18:6a4db94011d3 12317 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 12318 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 12319 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 12320
sahilmgandhi 18:6a4db94011d3 12321 /* Register: SAADC_RESULT_MAXCNT */
sahilmgandhi 18:6a4db94011d3 12322 /* Description: Maximum number of buffer words to transfer */
sahilmgandhi 18:6a4db94011d3 12323
sahilmgandhi 18:6a4db94011d3 12324 /* Bits 14..0 : Maximum number of buffer words to transfer */
sahilmgandhi 18:6a4db94011d3 12325 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12326 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12327
sahilmgandhi 18:6a4db94011d3 12328 /* Register: SAADC_RESULT_AMOUNT */
sahilmgandhi 18:6a4db94011d3 12329 /* Description: Number of buffer words transferred since last START */
sahilmgandhi 18:6a4db94011d3 12330
sahilmgandhi 18:6a4db94011d3 12331 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
sahilmgandhi 18:6a4db94011d3 12332 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12333 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12334
sahilmgandhi 18:6a4db94011d3 12335
sahilmgandhi 18:6a4db94011d3 12336 /* Peripheral: SPI */
sahilmgandhi 18:6a4db94011d3 12337 /* Description: Serial Peripheral Interface 0 */
sahilmgandhi 18:6a4db94011d3 12338
sahilmgandhi 18:6a4db94011d3 12339 /* Register: SPI_INTENSET */
sahilmgandhi 18:6a4db94011d3 12340 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 12341
sahilmgandhi 18:6a4db94011d3 12342 /* Bit 2 : Write '1' to Enable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 12343 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 12344 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 12345 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12346 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12347 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12348
sahilmgandhi 18:6a4db94011d3 12349 /* Register: SPI_INTENCLR */
sahilmgandhi 18:6a4db94011d3 12350 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 12351
sahilmgandhi 18:6a4db94011d3 12352 /* Bit 2 : Write '1' to Disable interrupt for READY event */
sahilmgandhi 18:6a4db94011d3 12353 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 12354 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 12355 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12356 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12357 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12358
sahilmgandhi 18:6a4db94011d3 12359 /* Register: SPI_ENABLE */
sahilmgandhi 18:6a4db94011d3 12360 /* Description: Enable SPI */
sahilmgandhi 18:6a4db94011d3 12361
sahilmgandhi 18:6a4db94011d3 12362 /* Bits 3..0 : Enable or disable SPI */
sahilmgandhi 18:6a4db94011d3 12363 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12364 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12365 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
sahilmgandhi 18:6a4db94011d3 12366 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
sahilmgandhi 18:6a4db94011d3 12367
sahilmgandhi 18:6a4db94011d3 12368 /* Register: SPI_PSEL_SCK */
sahilmgandhi 18:6a4db94011d3 12369 /* Description: Pin select for SCK */
sahilmgandhi 18:6a4db94011d3 12370
sahilmgandhi 18:6a4db94011d3 12371 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
sahilmgandhi 18:6a4db94011d3 12372 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
sahilmgandhi 18:6a4db94011d3 12373 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
sahilmgandhi 18:6a4db94011d3 12374 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12375
sahilmgandhi 18:6a4db94011d3 12376 /* Register: SPI_PSEL_MOSI */
sahilmgandhi 18:6a4db94011d3 12377 /* Description: Pin select for MOSI */
sahilmgandhi 18:6a4db94011d3 12378
sahilmgandhi 18:6a4db94011d3 12379 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
sahilmgandhi 18:6a4db94011d3 12380 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
sahilmgandhi 18:6a4db94011d3 12381 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
sahilmgandhi 18:6a4db94011d3 12382 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12383
sahilmgandhi 18:6a4db94011d3 12384 /* Register: SPI_PSEL_MISO */
sahilmgandhi 18:6a4db94011d3 12385 /* Description: Pin select for MISO */
sahilmgandhi 18:6a4db94011d3 12386
sahilmgandhi 18:6a4db94011d3 12387 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
sahilmgandhi 18:6a4db94011d3 12388 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
sahilmgandhi 18:6a4db94011d3 12389 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
sahilmgandhi 18:6a4db94011d3 12390 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12391
sahilmgandhi 18:6a4db94011d3 12392 /* Register: SPI_RXD */
sahilmgandhi 18:6a4db94011d3 12393 /* Description: RXD register */
sahilmgandhi 18:6a4db94011d3 12394
sahilmgandhi 18:6a4db94011d3 12395 /* Bits 7..0 : RX data received. Double buffered */
sahilmgandhi 18:6a4db94011d3 12396 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
sahilmgandhi 18:6a4db94011d3 12397 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
sahilmgandhi 18:6a4db94011d3 12398
sahilmgandhi 18:6a4db94011d3 12399 /* Register: SPI_TXD */
sahilmgandhi 18:6a4db94011d3 12400 /* Description: TXD register */
sahilmgandhi 18:6a4db94011d3 12401
sahilmgandhi 18:6a4db94011d3 12402 /* Bits 7..0 : TX data to send. Double buffered */
sahilmgandhi 18:6a4db94011d3 12403 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
sahilmgandhi 18:6a4db94011d3 12404 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
sahilmgandhi 18:6a4db94011d3 12405
sahilmgandhi 18:6a4db94011d3 12406 /* Register: SPI_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 12407 /* Description: SPI frequency */
sahilmgandhi 18:6a4db94011d3 12408
sahilmgandhi 18:6a4db94011d3 12409 /* Bits 31..0 : SPI master data rate */
sahilmgandhi 18:6a4db94011d3 12410 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 12411 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 12412 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
sahilmgandhi 18:6a4db94011d3 12413 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
sahilmgandhi 18:6a4db94011d3 12414 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
sahilmgandhi 18:6a4db94011d3 12415 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
sahilmgandhi 18:6a4db94011d3 12416 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
sahilmgandhi 18:6a4db94011d3 12417 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
sahilmgandhi 18:6a4db94011d3 12418 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
sahilmgandhi 18:6a4db94011d3 12419
sahilmgandhi 18:6a4db94011d3 12420 /* Register: SPI_CONFIG */
sahilmgandhi 18:6a4db94011d3 12421 /* Description: Configuration register */
sahilmgandhi 18:6a4db94011d3 12422
sahilmgandhi 18:6a4db94011d3 12423 /* Bit 2 : Serial clock (SCK) polarity */
sahilmgandhi 18:6a4db94011d3 12424 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
sahilmgandhi 18:6a4db94011d3 12425 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
sahilmgandhi 18:6a4db94011d3 12426 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
sahilmgandhi 18:6a4db94011d3 12427 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
sahilmgandhi 18:6a4db94011d3 12428
sahilmgandhi 18:6a4db94011d3 12429 /* Bit 1 : Serial clock (SCK) phase */
sahilmgandhi 18:6a4db94011d3 12430 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
sahilmgandhi 18:6a4db94011d3 12431 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
sahilmgandhi 18:6a4db94011d3 12432 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
sahilmgandhi 18:6a4db94011d3 12433 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
sahilmgandhi 18:6a4db94011d3 12434
sahilmgandhi 18:6a4db94011d3 12435 /* Bit 0 : Bit order */
sahilmgandhi 18:6a4db94011d3 12436 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
sahilmgandhi 18:6a4db94011d3 12437 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
sahilmgandhi 18:6a4db94011d3 12438 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
sahilmgandhi 18:6a4db94011d3 12439 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
sahilmgandhi 18:6a4db94011d3 12440
sahilmgandhi 18:6a4db94011d3 12441
sahilmgandhi 18:6a4db94011d3 12442 /* Peripheral: SPIM */
sahilmgandhi 18:6a4db94011d3 12443 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
sahilmgandhi 18:6a4db94011d3 12444
sahilmgandhi 18:6a4db94011d3 12445 /* Register: SPIM_SHORTS */
sahilmgandhi 18:6a4db94011d3 12446 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 12447
sahilmgandhi 18:6a4db94011d3 12448 /* Bit 17 : Shortcut between END event and START task */
sahilmgandhi 18:6a4db94011d3 12449 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
sahilmgandhi 18:6a4db94011d3 12450 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
sahilmgandhi 18:6a4db94011d3 12451 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 12452 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 12453
sahilmgandhi 18:6a4db94011d3 12454 /* Register: SPIM_INTENSET */
sahilmgandhi 18:6a4db94011d3 12455 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 12456
sahilmgandhi 18:6a4db94011d3 12457 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 12458 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 12459 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 12460 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12461 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12462 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12463
sahilmgandhi 18:6a4db94011d3 12464 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 12465 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 12466 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 12467 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12468 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12469 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12470
sahilmgandhi 18:6a4db94011d3 12471 /* Bit 6 : Write '1' to Enable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 12472 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 12473 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 12474 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12475 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12476 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12477
sahilmgandhi 18:6a4db94011d3 12478 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 12479 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12480 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12481 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12482 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12483 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12484
sahilmgandhi 18:6a4db94011d3 12485 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 12486 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 12487 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 12488 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12489 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12490 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12491
sahilmgandhi 18:6a4db94011d3 12492 /* Register: SPIM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 12493 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 12494
sahilmgandhi 18:6a4db94011d3 12495 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
sahilmgandhi 18:6a4db94011d3 12496 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 12497 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 12498 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12499 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12500 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12501
sahilmgandhi 18:6a4db94011d3 12502 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 12503 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 12504 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 12505 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12506 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12507 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12508
sahilmgandhi 18:6a4db94011d3 12509 /* Bit 6 : Write '1' to Disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 12510 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 12511 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 12512 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12513 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12514 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12515
sahilmgandhi 18:6a4db94011d3 12516 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 12517 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12518 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12519 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12520 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12521 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12522
sahilmgandhi 18:6a4db94011d3 12523 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 12524 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 12525 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 12526 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12527 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12528 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12529
sahilmgandhi 18:6a4db94011d3 12530 /* Register: SPIM_ENABLE */
sahilmgandhi 18:6a4db94011d3 12531 /* Description: Enable SPIM */
sahilmgandhi 18:6a4db94011d3 12532
sahilmgandhi 18:6a4db94011d3 12533 /* Bits 3..0 : Enable or disable SPIM */
sahilmgandhi 18:6a4db94011d3 12534 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12535 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12536 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
sahilmgandhi 18:6a4db94011d3 12537 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
sahilmgandhi 18:6a4db94011d3 12538
sahilmgandhi 18:6a4db94011d3 12539 /* Register: SPIM_PSEL_SCK */
sahilmgandhi 18:6a4db94011d3 12540 /* Description: Pin select for SCK */
sahilmgandhi 18:6a4db94011d3 12541
sahilmgandhi 18:6a4db94011d3 12542 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12543 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12544 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12545 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12546 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12547
sahilmgandhi 18:6a4db94011d3 12548 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12549 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12550 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12551
sahilmgandhi 18:6a4db94011d3 12552 /* Register: SPIM_PSEL_MOSI */
sahilmgandhi 18:6a4db94011d3 12553 /* Description: Pin select for MOSI signal */
sahilmgandhi 18:6a4db94011d3 12554
sahilmgandhi 18:6a4db94011d3 12555 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12556 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12557 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12558 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12559 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12560
sahilmgandhi 18:6a4db94011d3 12561 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12562 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12563 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12564
sahilmgandhi 18:6a4db94011d3 12565 /* Register: SPIM_PSEL_MISO */
sahilmgandhi 18:6a4db94011d3 12566 /* Description: Pin select for MISO signal */
sahilmgandhi 18:6a4db94011d3 12567
sahilmgandhi 18:6a4db94011d3 12568 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12569 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12570 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12571 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12572 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12573
sahilmgandhi 18:6a4db94011d3 12574 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12575 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12576 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12577
sahilmgandhi 18:6a4db94011d3 12578 /* Register: SPIM_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 12579 /* Description: SPI frequency */
sahilmgandhi 18:6a4db94011d3 12580
sahilmgandhi 18:6a4db94011d3 12581 /* Bits 31..0 : SPI master data rate */
sahilmgandhi 18:6a4db94011d3 12582 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 12583 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 12584 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
sahilmgandhi 18:6a4db94011d3 12585 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
sahilmgandhi 18:6a4db94011d3 12586 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
sahilmgandhi 18:6a4db94011d3 12587 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
sahilmgandhi 18:6a4db94011d3 12588 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
sahilmgandhi 18:6a4db94011d3 12589 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
sahilmgandhi 18:6a4db94011d3 12590 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
sahilmgandhi 18:6a4db94011d3 12591
sahilmgandhi 18:6a4db94011d3 12592 /* Register: SPIM_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 12593 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 12594
sahilmgandhi 18:6a4db94011d3 12595 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 12596 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 12597 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 12598
sahilmgandhi 18:6a4db94011d3 12599 /* Register: SPIM_RXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 12600 /* Description: Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 12601
sahilmgandhi 18:6a4db94011d3 12602 /* Bits 7..0 : Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 12603 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12604 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12605
sahilmgandhi 18:6a4db94011d3 12606 /* Register: SPIM_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 12607 /* Description: Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 12608
sahilmgandhi 18:6a4db94011d3 12609 /* Bits 7..0 : Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 12610 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12611 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12612
sahilmgandhi 18:6a4db94011d3 12613 /* Register: SPIM_RXD_LIST */
sahilmgandhi 18:6a4db94011d3 12614 /* Description: EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 12615
sahilmgandhi 18:6a4db94011d3 12616 /* Bits 2..0 : List type */
sahilmgandhi 18:6a4db94011d3 12617 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
sahilmgandhi 18:6a4db94011d3 12618 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
sahilmgandhi 18:6a4db94011d3 12619 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
sahilmgandhi 18:6a4db94011d3 12620 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
sahilmgandhi 18:6a4db94011d3 12621
sahilmgandhi 18:6a4db94011d3 12622 /* Register: SPIM_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 12623 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 12624
sahilmgandhi 18:6a4db94011d3 12625 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 12626 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 12627 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 12628
sahilmgandhi 18:6a4db94011d3 12629 /* Register: SPIM_TXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 12630 /* Description: Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 12631
sahilmgandhi 18:6a4db94011d3 12632 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 12633 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12634 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12635
sahilmgandhi 18:6a4db94011d3 12636 /* Register: SPIM_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 12637 /* Description: Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 12638
sahilmgandhi 18:6a4db94011d3 12639 /* Bits 7..0 : Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 12640 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12641 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12642
sahilmgandhi 18:6a4db94011d3 12643 /* Register: SPIM_TXD_LIST */
sahilmgandhi 18:6a4db94011d3 12644 /* Description: EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 12645
sahilmgandhi 18:6a4db94011d3 12646 /* Bits 2..0 : List type */
sahilmgandhi 18:6a4db94011d3 12647 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
sahilmgandhi 18:6a4db94011d3 12648 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
sahilmgandhi 18:6a4db94011d3 12649 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
sahilmgandhi 18:6a4db94011d3 12650 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
sahilmgandhi 18:6a4db94011d3 12651
sahilmgandhi 18:6a4db94011d3 12652 /* Register: SPIM_CONFIG */
sahilmgandhi 18:6a4db94011d3 12653 /* Description: Configuration register */
sahilmgandhi 18:6a4db94011d3 12654
sahilmgandhi 18:6a4db94011d3 12655 /* Bit 2 : Serial clock (SCK) polarity */
sahilmgandhi 18:6a4db94011d3 12656 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
sahilmgandhi 18:6a4db94011d3 12657 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
sahilmgandhi 18:6a4db94011d3 12658 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
sahilmgandhi 18:6a4db94011d3 12659 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
sahilmgandhi 18:6a4db94011d3 12660
sahilmgandhi 18:6a4db94011d3 12661 /* Bit 1 : Serial clock (SCK) phase */
sahilmgandhi 18:6a4db94011d3 12662 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
sahilmgandhi 18:6a4db94011d3 12663 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
sahilmgandhi 18:6a4db94011d3 12664 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
sahilmgandhi 18:6a4db94011d3 12665 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
sahilmgandhi 18:6a4db94011d3 12666
sahilmgandhi 18:6a4db94011d3 12667 /* Bit 0 : Bit order */
sahilmgandhi 18:6a4db94011d3 12668 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
sahilmgandhi 18:6a4db94011d3 12669 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
sahilmgandhi 18:6a4db94011d3 12670 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
sahilmgandhi 18:6a4db94011d3 12671 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
sahilmgandhi 18:6a4db94011d3 12672
sahilmgandhi 18:6a4db94011d3 12673 /* Register: SPIM_ORC */
sahilmgandhi 18:6a4db94011d3 12674 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
sahilmgandhi 18:6a4db94011d3 12675
sahilmgandhi 18:6a4db94011d3 12676 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
sahilmgandhi 18:6a4db94011d3 12677 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
sahilmgandhi 18:6a4db94011d3 12678 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
sahilmgandhi 18:6a4db94011d3 12679
sahilmgandhi 18:6a4db94011d3 12680
sahilmgandhi 18:6a4db94011d3 12681 /* Peripheral: SPIS */
sahilmgandhi 18:6a4db94011d3 12682 /* Description: SPI Slave 0 */
sahilmgandhi 18:6a4db94011d3 12683
sahilmgandhi 18:6a4db94011d3 12684 /* Register: SPIS_SHORTS */
sahilmgandhi 18:6a4db94011d3 12685 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 12686
sahilmgandhi 18:6a4db94011d3 12687 /* Bit 2 : Shortcut between END event and ACQUIRE task */
sahilmgandhi 18:6a4db94011d3 12688 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
sahilmgandhi 18:6a4db94011d3 12689 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
sahilmgandhi 18:6a4db94011d3 12690 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 12691 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 12692
sahilmgandhi 18:6a4db94011d3 12693 /* Register: SPIS_INTENSET */
sahilmgandhi 18:6a4db94011d3 12694 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 12695
sahilmgandhi 18:6a4db94011d3 12696 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
sahilmgandhi 18:6a4db94011d3 12697 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 12698 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 12699 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12700 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12701 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12702
sahilmgandhi 18:6a4db94011d3 12703 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 12704 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12705 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12706 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12707 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12708 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12709
sahilmgandhi 18:6a4db94011d3 12710 /* Bit 1 : Write '1' to Enable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 12711 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 12712 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 12713 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12714 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12715 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12716
sahilmgandhi 18:6a4db94011d3 12717 /* Register: SPIS_INTENCLR */
sahilmgandhi 18:6a4db94011d3 12718 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 12719
sahilmgandhi 18:6a4db94011d3 12720 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
sahilmgandhi 18:6a4db94011d3 12721 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 12722 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 12723 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12724 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12725 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12726
sahilmgandhi 18:6a4db94011d3 12727 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 12728 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12729 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 12730 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12731 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12732 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12733
sahilmgandhi 18:6a4db94011d3 12734 /* Bit 1 : Write '1' to Disable interrupt for END event */
sahilmgandhi 18:6a4db94011d3 12735 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 12736 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 12737 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12738 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12739 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12740
sahilmgandhi 18:6a4db94011d3 12741 /* Register: SPIS_SEMSTAT */
sahilmgandhi 18:6a4db94011d3 12742 /* Description: Semaphore status register */
sahilmgandhi 18:6a4db94011d3 12743
sahilmgandhi 18:6a4db94011d3 12744 /* Bits 1..0 : Semaphore status */
sahilmgandhi 18:6a4db94011d3 12745 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
sahilmgandhi 18:6a4db94011d3 12746 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
sahilmgandhi 18:6a4db94011d3 12747 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
sahilmgandhi 18:6a4db94011d3 12748 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
sahilmgandhi 18:6a4db94011d3 12749 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
sahilmgandhi 18:6a4db94011d3 12750 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
sahilmgandhi 18:6a4db94011d3 12751
sahilmgandhi 18:6a4db94011d3 12752 /* Register: SPIS_STATUS */
sahilmgandhi 18:6a4db94011d3 12753 /* Description: Status from last transaction */
sahilmgandhi 18:6a4db94011d3 12754
sahilmgandhi 18:6a4db94011d3 12755 /* Bit 1 : RX buffer overflow detected, and prevented */
sahilmgandhi 18:6a4db94011d3 12756 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
sahilmgandhi 18:6a4db94011d3 12757 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
sahilmgandhi 18:6a4db94011d3 12758 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 12759 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 12760 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
sahilmgandhi 18:6a4db94011d3 12761
sahilmgandhi 18:6a4db94011d3 12762 /* Bit 0 : TX buffer over-read detected, and prevented */
sahilmgandhi 18:6a4db94011d3 12763 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
sahilmgandhi 18:6a4db94011d3 12764 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
sahilmgandhi 18:6a4db94011d3 12765 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 12766 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 12767 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
sahilmgandhi 18:6a4db94011d3 12768
sahilmgandhi 18:6a4db94011d3 12769 /* Register: SPIS_ENABLE */
sahilmgandhi 18:6a4db94011d3 12770 /* Description: Enable SPI slave */
sahilmgandhi 18:6a4db94011d3 12771
sahilmgandhi 18:6a4db94011d3 12772 /* Bits 3..0 : Enable or disable SPI slave */
sahilmgandhi 18:6a4db94011d3 12773 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12774 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 12775 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
sahilmgandhi 18:6a4db94011d3 12776 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
sahilmgandhi 18:6a4db94011d3 12777
sahilmgandhi 18:6a4db94011d3 12778 /* Register: SPIS_PSEL_SCK */
sahilmgandhi 18:6a4db94011d3 12779 /* Description: Pin select for SCK */
sahilmgandhi 18:6a4db94011d3 12780
sahilmgandhi 18:6a4db94011d3 12781 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12782 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12783 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12784 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12785 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12786
sahilmgandhi 18:6a4db94011d3 12787 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12788 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12789 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12790
sahilmgandhi 18:6a4db94011d3 12791 /* Register: SPIS_PSEL_MISO */
sahilmgandhi 18:6a4db94011d3 12792 /* Description: Pin select for MISO signal */
sahilmgandhi 18:6a4db94011d3 12793
sahilmgandhi 18:6a4db94011d3 12794 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12795 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12796 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12797 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12798 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12799
sahilmgandhi 18:6a4db94011d3 12800 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12801 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12802 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12803
sahilmgandhi 18:6a4db94011d3 12804 /* Register: SPIS_PSEL_MOSI */
sahilmgandhi 18:6a4db94011d3 12805 /* Description: Pin select for MOSI signal */
sahilmgandhi 18:6a4db94011d3 12806
sahilmgandhi 18:6a4db94011d3 12807 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12808 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12809 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12810 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12811 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12812
sahilmgandhi 18:6a4db94011d3 12813 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12814 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12815 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12816
sahilmgandhi 18:6a4db94011d3 12817 /* Register: SPIS_PSEL_CSN */
sahilmgandhi 18:6a4db94011d3 12818 /* Description: Pin select for CSN signal */
sahilmgandhi 18:6a4db94011d3 12819
sahilmgandhi 18:6a4db94011d3 12820 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 12821 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12822 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 12823 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 12824 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 12825
sahilmgandhi 18:6a4db94011d3 12826 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 12827 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 12828 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 12829
sahilmgandhi 18:6a4db94011d3 12830 /* Register: SPIS_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 12831 /* Description: RXD data pointer */
sahilmgandhi 18:6a4db94011d3 12832
sahilmgandhi 18:6a4db94011d3 12833 /* Bits 31..0 : RXD data pointer */
sahilmgandhi 18:6a4db94011d3 12834 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 12835 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 12836
sahilmgandhi 18:6a4db94011d3 12837 /* Register: SPIS_RXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 12838 /* Description: Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 12839
sahilmgandhi 18:6a4db94011d3 12840 /* Bits 7..0 : Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 12841 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12842 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12843
sahilmgandhi 18:6a4db94011d3 12844 /* Register: SPIS_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 12845 /* Description: Number of bytes received in last granted transaction */
sahilmgandhi 18:6a4db94011d3 12846
sahilmgandhi 18:6a4db94011d3 12847 /* Bits 7..0 : Number of bytes received in the last granted transaction */
sahilmgandhi 18:6a4db94011d3 12848 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12849 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12850
sahilmgandhi 18:6a4db94011d3 12851 /* Register: SPIS_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 12852 /* Description: TXD data pointer */
sahilmgandhi 18:6a4db94011d3 12853
sahilmgandhi 18:6a4db94011d3 12854 /* Bits 31..0 : TXD data pointer */
sahilmgandhi 18:6a4db94011d3 12855 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 12856 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 12857
sahilmgandhi 18:6a4db94011d3 12858 /* Register: SPIS_TXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 12859 /* Description: Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 12860
sahilmgandhi 18:6a4db94011d3 12861 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 12862 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12863 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 12864
sahilmgandhi 18:6a4db94011d3 12865 /* Register: SPIS_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 12866 /* Description: Number of bytes transmitted in last granted transaction */
sahilmgandhi 18:6a4db94011d3 12867
sahilmgandhi 18:6a4db94011d3 12868 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
sahilmgandhi 18:6a4db94011d3 12869 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12870 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 12871
sahilmgandhi 18:6a4db94011d3 12872 /* Register: SPIS_CONFIG */
sahilmgandhi 18:6a4db94011d3 12873 /* Description: Configuration register */
sahilmgandhi 18:6a4db94011d3 12874
sahilmgandhi 18:6a4db94011d3 12875 /* Bit 2 : Serial clock (SCK) polarity */
sahilmgandhi 18:6a4db94011d3 12876 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
sahilmgandhi 18:6a4db94011d3 12877 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
sahilmgandhi 18:6a4db94011d3 12878 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
sahilmgandhi 18:6a4db94011d3 12879 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
sahilmgandhi 18:6a4db94011d3 12880
sahilmgandhi 18:6a4db94011d3 12881 /* Bit 1 : Serial clock (SCK) phase */
sahilmgandhi 18:6a4db94011d3 12882 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
sahilmgandhi 18:6a4db94011d3 12883 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
sahilmgandhi 18:6a4db94011d3 12884 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
sahilmgandhi 18:6a4db94011d3 12885 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
sahilmgandhi 18:6a4db94011d3 12886
sahilmgandhi 18:6a4db94011d3 12887 /* Bit 0 : Bit order */
sahilmgandhi 18:6a4db94011d3 12888 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
sahilmgandhi 18:6a4db94011d3 12889 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
sahilmgandhi 18:6a4db94011d3 12890 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
sahilmgandhi 18:6a4db94011d3 12891 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
sahilmgandhi 18:6a4db94011d3 12892
sahilmgandhi 18:6a4db94011d3 12893 /* Register: SPIS_DEF */
sahilmgandhi 18:6a4db94011d3 12894 /* Description: Default character. Character clocked out in case of an ignored transaction. */
sahilmgandhi 18:6a4db94011d3 12895
sahilmgandhi 18:6a4db94011d3 12896 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
sahilmgandhi 18:6a4db94011d3 12897 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
sahilmgandhi 18:6a4db94011d3 12898 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
sahilmgandhi 18:6a4db94011d3 12899
sahilmgandhi 18:6a4db94011d3 12900 /* Register: SPIS_ORC */
sahilmgandhi 18:6a4db94011d3 12901 /* Description: Over-read character */
sahilmgandhi 18:6a4db94011d3 12902
sahilmgandhi 18:6a4db94011d3 12903 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 12904 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
sahilmgandhi 18:6a4db94011d3 12905 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
sahilmgandhi 18:6a4db94011d3 12906
sahilmgandhi 18:6a4db94011d3 12907
sahilmgandhi 18:6a4db94011d3 12908 /* Peripheral: TEMP */
sahilmgandhi 18:6a4db94011d3 12909 /* Description: Temperature Sensor */
sahilmgandhi 18:6a4db94011d3 12910
sahilmgandhi 18:6a4db94011d3 12911 /* Register: TEMP_INTENSET */
sahilmgandhi 18:6a4db94011d3 12912 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 12913
sahilmgandhi 18:6a4db94011d3 12914 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
sahilmgandhi 18:6a4db94011d3 12915 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 12916 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 12917 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12918 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12919 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 12920
sahilmgandhi 18:6a4db94011d3 12921 /* Register: TEMP_INTENCLR */
sahilmgandhi 18:6a4db94011d3 12922 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 12923
sahilmgandhi 18:6a4db94011d3 12924 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
sahilmgandhi 18:6a4db94011d3 12925 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 12926 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 12927 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 12928 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 12929 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 12930
sahilmgandhi 18:6a4db94011d3 12931 /* Register: TEMP_TEMP */
sahilmgandhi 18:6a4db94011d3 12932 /* Description: Temperature in degC (0.25deg steps) */
sahilmgandhi 18:6a4db94011d3 12933
sahilmgandhi 18:6a4db94011d3 12934 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
sahilmgandhi 18:6a4db94011d3 12935 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
sahilmgandhi 18:6a4db94011d3 12936 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
sahilmgandhi 18:6a4db94011d3 12937
sahilmgandhi 18:6a4db94011d3 12938 /* Register: TEMP_A0 */
sahilmgandhi 18:6a4db94011d3 12939 /* Description: Slope of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12940
sahilmgandhi 18:6a4db94011d3 12941 /* Bits 11..0 : Slope of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12942 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
sahilmgandhi 18:6a4db94011d3 12943 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
sahilmgandhi 18:6a4db94011d3 12944
sahilmgandhi 18:6a4db94011d3 12945 /* Register: TEMP_A1 */
sahilmgandhi 18:6a4db94011d3 12946 /* Description: Slope of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12947
sahilmgandhi 18:6a4db94011d3 12948 /* Bits 11..0 : Slope of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12949 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
sahilmgandhi 18:6a4db94011d3 12950 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
sahilmgandhi 18:6a4db94011d3 12951
sahilmgandhi 18:6a4db94011d3 12952 /* Register: TEMP_A2 */
sahilmgandhi 18:6a4db94011d3 12953 /* Description: Slope of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12954
sahilmgandhi 18:6a4db94011d3 12955 /* Bits 11..0 : Slope of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12956 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
sahilmgandhi 18:6a4db94011d3 12957 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
sahilmgandhi 18:6a4db94011d3 12958
sahilmgandhi 18:6a4db94011d3 12959 /* Register: TEMP_A3 */
sahilmgandhi 18:6a4db94011d3 12960 /* Description: Slope of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12961
sahilmgandhi 18:6a4db94011d3 12962 /* Bits 11..0 : Slope of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12963 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
sahilmgandhi 18:6a4db94011d3 12964 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
sahilmgandhi 18:6a4db94011d3 12965
sahilmgandhi 18:6a4db94011d3 12966 /* Register: TEMP_A4 */
sahilmgandhi 18:6a4db94011d3 12967 /* Description: Slope of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12968
sahilmgandhi 18:6a4db94011d3 12969 /* Bits 11..0 : Slope of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12970 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
sahilmgandhi 18:6a4db94011d3 12971 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
sahilmgandhi 18:6a4db94011d3 12972
sahilmgandhi 18:6a4db94011d3 12973 /* Register: TEMP_A5 */
sahilmgandhi 18:6a4db94011d3 12974 /* Description: Slope of 6th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12975
sahilmgandhi 18:6a4db94011d3 12976 /* Bits 11..0 : Slope of 6th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12977 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
sahilmgandhi 18:6a4db94011d3 12978 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
sahilmgandhi 18:6a4db94011d3 12979
sahilmgandhi 18:6a4db94011d3 12980 /* Register: TEMP_B0 */
sahilmgandhi 18:6a4db94011d3 12981 /* Description: y-intercept of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12982
sahilmgandhi 18:6a4db94011d3 12983 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12984 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
sahilmgandhi 18:6a4db94011d3 12985 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
sahilmgandhi 18:6a4db94011d3 12986
sahilmgandhi 18:6a4db94011d3 12987 /* Register: TEMP_B1 */
sahilmgandhi 18:6a4db94011d3 12988 /* Description: y-intercept of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12989
sahilmgandhi 18:6a4db94011d3 12990 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12991 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
sahilmgandhi 18:6a4db94011d3 12992 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
sahilmgandhi 18:6a4db94011d3 12993
sahilmgandhi 18:6a4db94011d3 12994 /* Register: TEMP_B2 */
sahilmgandhi 18:6a4db94011d3 12995 /* Description: y-intercept of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12996
sahilmgandhi 18:6a4db94011d3 12997 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 12998 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
sahilmgandhi 18:6a4db94011d3 12999 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
sahilmgandhi 18:6a4db94011d3 13000
sahilmgandhi 18:6a4db94011d3 13001 /* Register: TEMP_B3 */
sahilmgandhi 18:6a4db94011d3 13002 /* Description: y-intercept of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13003
sahilmgandhi 18:6a4db94011d3 13004 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13005 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
sahilmgandhi 18:6a4db94011d3 13006 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
sahilmgandhi 18:6a4db94011d3 13007
sahilmgandhi 18:6a4db94011d3 13008 /* Register: TEMP_B4 */
sahilmgandhi 18:6a4db94011d3 13009 /* Description: y-intercept of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13010
sahilmgandhi 18:6a4db94011d3 13011 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13012 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
sahilmgandhi 18:6a4db94011d3 13013 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
sahilmgandhi 18:6a4db94011d3 13014
sahilmgandhi 18:6a4db94011d3 13015 /* Register: TEMP_B5 */
sahilmgandhi 18:6a4db94011d3 13016 /* Description: y-intercept of 6th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13017
sahilmgandhi 18:6a4db94011d3 13018 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13019 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
sahilmgandhi 18:6a4db94011d3 13020 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
sahilmgandhi 18:6a4db94011d3 13021
sahilmgandhi 18:6a4db94011d3 13022 /* Register: TEMP_T0 */
sahilmgandhi 18:6a4db94011d3 13023 /* Description: End point of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13024
sahilmgandhi 18:6a4db94011d3 13025 /* Bits 7..0 : End point of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13026 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
sahilmgandhi 18:6a4db94011d3 13027 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
sahilmgandhi 18:6a4db94011d3 13028
sahilmgandhi 18:6a4db94011d3 13029 /* Register: TEMP_T1 */
sahilmgandhi 18:6a4db94011d3 13030 /* Description: End point of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13031
sahilmgandhi 18:6a4db94011d3 13032 /* Bits 7..0 : End point of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13033 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
sahilmgandhi 18:6a4db94011d3 13034 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
sahilmgandhi 18:6a4db94011d3 13035
sahilmgandhi 18:6a4db94011d3 13036 /* Register: TEMP_T2 */
sahilmgandhi 18:6a4db94011d3 13037 /* Description: End point of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13038
sahilmgandhi 18:6a4db94011d3 13039 /* Bits 7..0 : End point of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13040 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
sahilmgandhi 18:6a4db94011d3 13041 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
sahilmgandhi 18:6a4db94011d3 13042
sahilmgandhi 18:6a4db94011d3 13043 /* Register: TEMP_T3 */
sahilmgandhi 18:6a4db94011d3 13044 /* Description: End point of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13045
sahilmgandhi 18:6a4db94011d3 13046 /* Bits 7..0 : End point of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13047 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
sahilmgandhi 18:6a4db94011d3 13048 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
sahilmgandhi 18:6a4db94011d3 13049
sahilmgandhi 18:6a4db94011d3 13050 /* Register: TEMP_T4 */
sahilmgandhi 18:6a4db94011d3 13051 /* Description: End point of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13052
sahilmgandhi 18:6a4db94011d3 13053 /* Bits 7..0 : End point of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 13054 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
sahilmgandhi 18:6a4db94011d3 13055 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
sahilmgandhi 18:6a4db94011d3 13056
sahilmgandhi 18:6a4db94011d3 13057
sahilmgandhi 18:6a4db94011d3 13058 /* Peripheral: TIMER */
sahilmgandhi 18:6a4db94011d3 13059 /* Description: Timer/Counter 0 */
sahilmgandhi 18:6a4db94011d3 13060
sahilmgandhi 18:6a4db94011d3 13061 /* Register: TIMER_SHORTS */
sahilmgandhi 18:6a4db94011d3 13062 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 13063
sahilmgandhi 18:6a4db94011d3 13064 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
sahilmgandhi 18:6a4db94011d3 13065 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
sahilmgandhi 18:6a4db94011d3 13066 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
sahilmgandhi 18:6a4db94011d3 13067 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13068 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13069
sahilmgandhi 18:6a4db94011d3 13070 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
sahilmgandhi 18:6a4db94011d3 13071 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
sahilmgandhi 18:6a4db94011d3 13072 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
sahilmgandhi 18:6a4db94011d3 13073 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13074 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13075
sahilmgandhi 18:6a4db94011d3 13076 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
sahilmgandhi 18:6a4db94011d3 13077 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
sahilmgandhi 18:6a4db94011d3 13078 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
sahilmgandhi 18:6a4db94011d3 13079 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13080 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13081
sahilmgandhi 18:6a4db94011d3 13082 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
sahilmgandhi 18:6a4db94011d3 13083 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
sahilmgandhi 18:6a4db94011d3 13084 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
sahilmgandhi 18:6a4db94011d3 13085 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13086 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13087
sahilmgandhi 18:6a4db94011d3 13088 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
sahilmgandhi 18:6a4db94011d3 13089 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
sahilmgandhi 18:6a4db94011d3 13090 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
sahilmgandhi 18:6a4db94011d3 13091 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13092 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13093
sahilmgandhi 18:6a4db94011d3 13094 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
sahilmgandhi 18:6a4db94011d3 13095 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
sahilmgandhi 18:6a4db94011d3 13096 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
sahilmgandhi 18:6a4db94011d3 13097 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13098 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13099
sahilmgandhi 18:6a4db94011d3 13100 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
sahilmgandhi 18:6a4db94011d3 13101 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13102 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13103 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13104 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13105
sahilmgandhi 18:6a4db94011d3 13106 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
sahilmgandhi 18:6a4db94011d3 13107 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13108 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13109 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13110 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13111
sahilmgandhi 18:6a4db94011d3 13112 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
sahilmgandhi 18:6a4db94011d3 13113 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13114 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13115 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13116 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13117
sahilmgandhi 18:6a4db94011d3 13118 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
sahilmgandhi 18:6a4db94011d3 13119 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13120 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13121 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13122 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13123
sahilmgandhi 18:6a4db94011d3 13124 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
sahilmgandhi 18:6a4db94011d3 13125 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13126 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13127 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13128 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13129
sahilmgandhi 18:6a4db94011d3 13130 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
sahilmgandhi 18:6a4db94011d3 13131 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13132 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 13133 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13134 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13135
sahilmgandhi 18:6a4db94011d3 13136 /* Register: TIMER_INTENSET */
sahilmgandhi 18:6a4db94011d3 13137 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 13138
sahilmgandhi 18:6a4db94011d3 13139 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
sahilmgandhi 18:6a4db94011d3 13140 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
sahilmgandhi 18:6a4db94011d3 13141 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
sahilmgandhi 18:6a4db94011d3 13142 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13143 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13144 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13145
sahilmgandhi 18:6a4db94011d3 13146 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
sahilmgandhi 18:6a4db94011d3 13147 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
sahilmgandhi 18:6a4db94011d3 13148 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
sahilmgandhi 18:6a4db94011d3 13149 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13150 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13151 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13152
sahilmgandhi 18:6a4db94011d3 13153 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 13154 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 13155 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 13156 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13157 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13158 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13159
sahilmgandhi 18:6a4db94011d3 13160 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 13161 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 13162 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 13163 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13164 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13165 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13166
sahilmgandhi 18:6a4db94011d3 13167 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 13168 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 13169 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 13170 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13171 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13172 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13173
sahilmgandhi 18:6a4db94011d3 13174 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 13175 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 13176 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 13177 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13178 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13179 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13180
sahilmgandhi 18:6a4db94011d3 13181 /* Register: TIMER_INTENCLR */
sahilmgandhi 18:6a4db94011d3 13182 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 13183
sahilmgandhi 18:6a4db94011d3 13184 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
sahilmgandhi 18:6a4db94011d3 13185 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
sahilmgandhi 18:6a4db94011d3 13186 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
sahilmgandhi 18:6a4db94011d3 13187 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13188 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13189 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13190
sahilmgandhi 18:6a4db94011d3 13191 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
sahilmgandhi 18:6a4db94011d3 13192 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
sahilmgandhi 18:6a4db94011d3 13193 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
sahilmgandhi 18:6a4db94011d3 13194 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13195 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13196 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13197
sahilmgandhi 18:6a4db94011d3 13198 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
sahilmgandhi 18:6a4db94011d3 13199 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 13200 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 13201 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13202 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13203 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13204
sahilmgandhi 18:6a4db94011d3 13205 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
sahilmgandhi 18:6a4db94011d3 13206 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 13207 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 13208 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13209 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13210 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13211
sahilmgandhi 18:6a4db94011d3 13212 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
sahilmgandhi 18:6a4db94011d3 13213 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 13214 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 13215 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13216 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13217 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13218
sahilmgandhi 18:6a4db94011d3 13219 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
sahilmgandhi 18:6a4db94011d3 13220 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 13221 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 13222 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13223 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13224 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13225
sahilmgandhi 18:6a4db94011d3 13226 /* Register: TIMER_MODE */
sahilmgandhi 18:6a4db94011d3 13227 /* Description: Timer mode selection */
sahilmgandhi 18:6a4db94011d3 13228
sahilmgandhi 18:6a4db94011d3 13229 /* Bits 1..0 : Timer mode */
sahilmgandhi 18:6a4db94011d3 13230 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 13231 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 13232 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
sahilmgandhi 18:6a4db94011d3 13233 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
sahilmgandhi 18:6a4db94011d3 13234 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
sahilmgandhi 18:6a4db94011d3 13235
sahilmgandhi 18:6a4db94011d3 13236 /* Register: TIMER_BITMODE */
sahilmgandhi 18:6a4db94011d3 13237 /* Description: Configure the number of bits used by the TIMER */
sahilmgandhi 18:6a4db94011d3 13238
sahilmgandhi 18:6a4db94011d3 13239 /* Bits 1..0 : Timer bit width */
sahilmgandhi 18:6a4db94011d3 13240 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
sahilmgandhi 18:6a4db94011d3 13241 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
sahilmgandhi 18:6a4db94011d3 13242 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
sahilmgandhi 18:6a4db94011d3 13243 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
sahilmgandhi 18:6a4db94011d3 13244 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
sahilmgandhi 18:6a4db94011d3 13245 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
sahilmgandhi 18:6a4db94011d3 13246
sahilmgandhi 18:6a4db94011d3 13247 /* Register: TIMER_PRESCALER */
sahilmgandhi 18:6a4db94011d3 13248 /* Description: Timer prescaler register */
sahilmgandhi 18:6a4db94011d3 13249
sahilmgandhi 18:6a4db94011d3 13250 /* Bits 3..0 : Prescaler value */
sahilmgandhi 18:6a4db94011d3 13251 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 13252 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 13253
sahilmgandhi 18:6a4db94011d3 13254 /* Register: TIMER_CC */
sahilmgandhi 18:6a4db94011d3 13255 /* Description: Description collection[0]: Capture/Compare register 0 */
sahilmgandhi 18:6a4db94011d3 13256
sahilmgandhi 18:6a4db94011d3 13257 /* Bits 31..0 : Capture/Compare value */
sahilmgandhi 18:6a4db94011d3 13258 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
sahilmgandhi 18:6a4db94011d3 13259 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
sahilmgandhi 18:6a4db94011d3 13260
sahilmgandhi 18:6a4db94011d3 13261
sahilmgandhi 18:6a4db94011d3 13262 /* Peripheral: TWI */
sahilmgandhi 18:6a4db94011d3 13263 /* Description: I2C compatible Two-Wire Interface 0 */
sahilmgandhi 18:6a4db94011d3 13264
sahilmgandhi 18:6a4db94011d3 13265 /* Register: TWI_SHORTS */
sahilmgandhi 18:6a4db94011d3 13266 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 13267
sahilmgandhi 18:6a4db94011d3 13268 /* Bit 1 : Shortcut between BB event and STOP task */
sahilmgandhi 18:6a4db94011d3 13269 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
sahilmgandhi 18:6a4db94011d3 13270 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
sahilmgandhi 18:6a4db94011d3 13271 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13272 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13273
sahilmgandhi 18:6a4db94011d3 13274 /* Bit 0 : Shortcut between BB event and SUSPEND task */
sahilmgandhi 18:6a4db94011d3 13275 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13276 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13277 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13278 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13279
sahilmgandhi 18:6a4db94011d3 13280 /* Register: TWI_INTENSET */
sahilmgandhi 18:6a4db94011d3 13281 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 13282
sahilmgandhi 18:6a4db94011d3 13283 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
sahilmgandhi 18:6a4db94011d3 13284 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13285 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13286 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13287 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13288 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13289
sahilmgandhi 18:6a4db94011d3 13290 /* Bit 14 : Write '1' to Enable interrupt for BB event */
sahilmgandhi 18:6a4db94011d3 13291 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
sahilmgandhi 18:6a4db94011d3 13292 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
sahilmgandhi 18:6a4db94011d3 13293 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13294 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13295 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13296
sahilmgandhi 18:6a4db94011d3 13297 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13298 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13299 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13300 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13301 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13302 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13303
sahilmgandhi 18:6a4db94011d3 13304 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
sahilmgandhi 18:6a4db94011d3 13305 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 13306 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 13307 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13308 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13309 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13310
sahilmgandhi 18:6a4db94011d3 13311 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
sahilmgandhi 18:6a4db94011d3 13312 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 13313 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 13314 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13315 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13316 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13317
sahilmgandhi 18:6a4db94011d3 13318 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13319 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13320 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13321 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13322 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13323 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13324
sahilmgandhi 18:6a4db94011d3 13325 /* Register: TWI_INTENCLR */
sahilmgandhi 18:6a4db94011d3 13326 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 13327
sahilmgandhi 18:6a4db94011d3 13328 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
sahilmgandhi 18:6a4db94011d3 13329 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13330 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13331 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13332 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13333 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13334
sahilmgandhi 18:6a4db94011d3 13335 /* Bit 14 : Write '1' to Disable interrupt for BB event */
sahilmgandhi 18:6a4db94011d3 13336 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
sahilmgandhi 18:6a4db94011d3 13337 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
sahilmgandhi 18:6a4db94011d3 13338 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13339 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13340 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13341
sahilmgandhi 18:6a4db94011d3 13342 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13343 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13344 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13345 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13346 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13347 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13348
sahilmgandhi 18:6a4db94011d3 13349 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
sahilmgandhi 18:6a4db94011d3 13350 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 13351 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 13352 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13353 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13354 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13355
sahilmgandhi 18:6a4db94011d3 13356 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
sahilmgandhi 18:6a4db94011d3 13357 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 13358 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 13359 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13360 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13361 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13362
sahilmgandhi 18:6a4db94011d3 13363 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13364 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13365 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13366 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13367 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13368 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13369
sahilmgandhi 18:6a4db94011d3 13370 /* Register: TWI_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 13371 /* Description: Error source */
sahilmgandhi 18:6a4db94011d3 13372
sahilmgandhi 18:6a4db94011d3 13373 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 13374 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
sahilmgandhi 18:6a4db94011d3 13375 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
sahilmgandhi 18:6a4db94011d3 13376 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 13377 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 13378
sahilmgandhi 18:6a4db94011d3 13379 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 13380 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
sahilmgandhi 18:6a4db94011d3 13381 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
sahilmgandhi 18:6a4db94011d3 13382 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 13383 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 13384
sahilmgandhi 18:6a4db94011d3 13385 /* Bit 0 : Overrun error */
sahilmgandhi 18:6a4db94011d3 13386 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 13387 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 13388 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
sahilmgandhi 18:6a4db94011d3 13389 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
sahilmgandhi 18:6a4db94011d3 13390
sahilmgandhi 18:6a4db94011d3 13391 /* Register: TWI_ENABLE */
sahilmgandhi 18:6a4db94011d3 13392 /* Description: Enable TWI */
sahilmgandhi 18:6a4db94011d3 13393
sahilmgandhi 18:6a4db94011d3 13394 /* Bits 3..0 : Enable or disable TWI */
sahilmgandhi 18:6a4db94011d3 13395 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 13396 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 13397 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
sahilmgandhi 18:6a4db94011d3 13398 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
sahilmgandhi 18:6a4db94011d3 13399
sahilmgandhi 18:6a4db94011d3 13400 /* Register: TWI_PSELSCL */
sahilmgandhi 18:6a4db94011d3 13401 /* Description: Pin select for SCL */
sahilmgandhi 18:6a4db94011d3 13402
sahilmgandhi 18:6a4db94011d3 13403 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
sahilmgandhi 18:6a4db94011d3 13404 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
sahilmgandhi 18:6a4db94011d3 13405 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
sahilmgandhi 18:6a4db94011d3 13406 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 13407
sahilmgandhi 18:6a4db94011d3 13408 /* Register: TWI_PSELSDA */
sahilmgandhi 18:6a4db94011d3 13409 /* Description: Pin select for SDA */
sahilmgandhi 18:6a4db94011d3 13410
sahilmgandhi 18:6a4db94011d3 13411 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
sahilmgandhi 18:6a4db94011d3 13412 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
sahilmgandhi 18:6a4db94011d3 13413 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
sahilmgandhi 18:6a4db94011d3 13414 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 13415
sahilmgandhi 18:6a4db94011d3 13416 /* Register: TWI_RXD */
sahilmgandhi 18:6a4db94011d3 13417 /* Description: RXD register */
sahilmgandhi 18:6a4db94011d3 13418
sahilmgandhi 18:6a4db94011d3 13419 /* Bits 7..0 : RXD register */
sahilmgandhi 18:6a4db94011d3 13420 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
sahilmgandhi 18:6a4db94011d3 13421 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
sahilmgandhi 18:6a4db94011d3 13422
sahilmgandhi 18:6a4db94011d3 13423 /* Register: TWI_TXD */
sahilmgandhi 18:6a4db94011d3 13424 /* Description: TXD register */
sahilmgandhi 18:6a4db94011d3 13425
sahilmgandhi 18:6a4db94011d3 13426 /* Bits 7..0 : TXD register */
sahilmgandhi 18:6a4db94011d3 13427 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
sahilmgandhi 18:6a4db94011d3 13428 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
sahilmgandhi 18:6a4db94011d3 13429
sahilmgandhi 18:6a4db94011d3 13430 /* Register: TWI_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 13431 /* Description: TWI frequency */
sahilmgandhi 18:6a4db94011d3 13432
sahilmgandhi 18:6a4db94011d3 13433 /* Bits 31..0 : TWI master clock frequency */
sahilmgandhi 18:6a4db94011d3 13434 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 13435 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 13436 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
sahilmgandhi 18:6a4db94011d3 13437 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
sahilmgandhi 18:6a4db94011d3 13438 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
sahilmgandhi 18:6a4db94011d3 13439
sahilmgandhi 18:6a4db94011d3 13440 /* Register: TWI_ADDRESS */
sahilmgandhi 18:6a4db94011d3 13441 /* Description: Address used in the TWI transfer */
sahilmgandhi 18:6a4db94011d3 13442
sahilmgandhi 18:6a4db94011d3 13443 /* Bits 6..0 : Address used in the TWI transfer */
sahilmgandhi 18:6a4db94011d3 13444 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 13445 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 13446
sahilmgandhi 18:6a4db94011d3 13447
sahilmgandhi 18:6a4db94011d3 13448 /* Peripheral: TWIM */
sahilmgandhi 18:6a4db94011d3 13449 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
sahilmgandhi 18:6a4db94011d3 13450
sahilmgandhi 18:6a4db94011d3 13451 /* Register: TWIM_SHORTS */
sahilmgandhi 18:6a4db94011d3 13452 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 13453
sahilmgandhi 18:6a4db94011d3 13454 /* Bit 12 : Shortcut between LASTRX event and STOP task */
sahilmgandhi 18:6a4db94011d3 13455 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
sahilmgandhi 18:6a4db94011d3 13456 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
sahilmgandhi 18:6a4db94011d3 13457 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13458 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13459
sahilmgandhi 18:6a4db94011d3 13460 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */
sahilmgandhi 18:6a4db94011d3 13461 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
sahilmgandhi 18:6a4db94011d3 13462 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
sahilmgandhi 18:6a4db94011d3 13463 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13464 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13465
sahilmgandhi 18:6a4db94011d3 13466 /* Bit 9 : Shortcut between LASTTX event and STOP task */
sahilmgandhi 18:6a4db94011d3 13467 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
sahilmgandhi 18:6a4db94011d3 13468 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
sahilmgandhi 18:6a4db94011d3 13469 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13470 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13471
sahilmgandhi 18:6a4db94011d3 13472 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
sahilmgandhi 18:6a4db94011d3 13473 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13474 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13475 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13476 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13477
sahilmgandhi 18:6a4db94011d3 13478 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */
sahilmgandhi 18:6a4db94011d3 13479 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 13480 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 13481 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13482 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13483
sahilmgandhi 18:6a4db94011d3 13484 /* Register: TWIM_INTEN */
sahilmgandhi 18:6a4db94011d3 13485 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 13486
sahilmgandhi 18:6a4db94011d3 13487 /* Bit 24 : Enable or disable interrupt for LASTTX event */
sahilmgandhi 18:6a4db94011d3 13488 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
sahilmgandhi 18:6a4db94011d3 13489 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
sahilmgandhi 18:6a4db94011d3 13490 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13491 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13492
sahilmgandhi 18:6a4db94011d3 13493 /* Bit 23 : Enable or disable interrupt for LASTRX event */
sahilmgandhi 18:6a4db94011d3 13494 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
sahilmgandhi 18:6a4db94011d3 13495 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
sahilmgandhi 18:6a4db94011d3 13496 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13497 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13498
sahilmgandhi 18:6a4db94011d3 13499 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13500 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13501 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13502 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13503 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13504
sahilmgandhi 18:6a4db94011d3 13505 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13506 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13507 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13508 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13509 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13510
sahilmgandhi 18:6a4db94011d3 13511 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
sahilmgandhi 18:6a4db94011d3 13512 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13513 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13514 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13515 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13516
sahilmgandhi 18:6a4db94011d3 13517 /* Bit 9 : Enable or disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13518 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13519 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13520 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13521 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13522
sahilmgandhi 18:6a4db94011d3 13523 /* Bit 1 : Enable or disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13524 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13525 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13526 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13527 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13528
sahilmgandhi 18:6a4db94011d3 13529 /* Register: TWIM_INTENSET */
sahilmgandhi 18:6a4db94011d3 13530 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 13531
sahilmgandhi 18:6a4db94011d3 13532 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
sahilmgandhi 18:6a4db94011d3 13533 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
sahilmgandhi 18:6a4db94011d3 13534 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
sahilmgandhi 18:6a4db94011d3 13535 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13536 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13537 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13538
sahilmgandhi 18:6a4db94011d3 13539 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
sahilmgandhi 18:6a4db94011d3 13540 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
sahilmgandhi 18:6a4db94011d3 13541 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
sahilmgandhi 18:6a4db94011d3 13542 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13543 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13544 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13545
sahilmgandhi 18:6a4db94011d3 13546 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13547 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13548 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13549 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13550 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13551 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13552
sahilmgandhi 18:6a4db94011d3 13553 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13554 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13555 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13556 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13557 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13558 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13559
sahilmgandhi 18:6a4db94011d3 13560 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
sahilmgandhi 18:6a4db94011d3 13561 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13562 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13563 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13564 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13565 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13566
sahilmgandhi 18:6a4db94011d3 13567 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13568 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13569 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13570 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13571 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13572 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13573
sahilmgandhi 18:6a4db94011d3 13574 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13575 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13576 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13577 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13578 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13579 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13580
sahilmgandhi 18:6a4db94011d3 13581 /* Register: TWIM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 13582 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 13583
sahilmgandhi 18:6a4db94011d3 13584 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
sahilmgandhi 18:6a4db94011d3 13585 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
sahilmgandhi 18:6a4db94011d3 13586 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
sahilmgandhi 18:6a4db94011d3 13587 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13588 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13589 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13590
sahilmgandhi 18:6a4db94011d3 13591 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
sahilmgandhi 18:6a4db94011d3 13592 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
sahilmgandhi 18:6a4db94011d3 13593 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
sahilmgandhi 18:6a4db94011d3 13594 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13595 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13596 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13597
sahilmgandhi 18:6a4db94011d3 13598 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13599 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13600 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13601 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13602 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13603 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13604
sahilmgandhi 18:6a4db94011d3 13605 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13606 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13607 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13608 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13609 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13610 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13611
sahilmgandhi 18:6a4db94011d3 13612 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
sahilmgandhi 18:6a4db94011d3 13613 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13614 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 13615 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13616 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13617 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13618
sahilmgandhi 18:6a4db94011d3 13619 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13620 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13621 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13622 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13623 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13624 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13625
sahilmgandhi 18:6a4db94011d3 13626 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13627 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13628 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13629 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13630 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13631 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13632
sahilmgandhi 18:6a4db94011d3 13633 /* Register: TWIM_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 13634 /* Description: Error source */
sahilmgandhi 18:6a4db94011d3 13635
sahilmgandhi 18:6a4db94011d3 13636 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 13637 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
sahilmgandhi 18:6a4db94011d3 13638 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
sahilmgandhi 18:6a4db94011d3 13639 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
sahilmgandhi 18:6a4db94011d3 13640 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
sahilmgandhi 18:6a4db94011d3 13641
sahilmgandhi 18:6a4db94011d3 13642 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
sahilmgandhi 18:6a4db94011d3 13643 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
sahilmgandhi 18:6a4db94011d3 13644 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
sahilmgandhi 18:6a4db94011d3 13645 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
sahilmgandhi 18:6a4db94011d3 13646 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
sahilmgandhi 18:6a4db94011d3 13647
sahilmgandhi 18:6a4db94011d3 13648 /* Register: TWIM_ENABLE */
sahilmgandhi 18:6a4db94011d3 13649 /* Description: Enable TWIM */
sahilmgandhi 18:6a4db94011d3 13650
sahilmgandhi 18:6a4db94011d3 13651 /* Bits 3..0 : Enable or disable TWIM */
sahilmgandhi 18:6a4db94011d3 13652 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 13653 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 13654 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
sahilmgandhi 18:6a4db94011d3 13655 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
sahilmgandhi 18:6a4db94011d3 13656
sahilmgandhi 18:6a4db94011d3 13657 /* Register: TWIM_PSEL_SCL */
sahilmgandhi 18:6a4db94011d3 13658 /* Description: Pin select for SCL signal */
sahilmgandhi 18:6a4db94011d3 13659
sahilmgandhi 18:6a4db94011d3 13660 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 13661 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13662 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13663 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 13664 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 13665
sahilmgandhi 18:6a4db94011d3 13666 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 13667 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 13668 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 13669
sahilmgandhi 18:6a4db94011d3 13670 /* Register: TWIM_PSEL_SDA */
sahilmgandhi 18:6a4db94011d3 13671 /* Description: Pin select for SDA signal */
sahilmgandhi 18:6a4db94011d3 13672
sahilmgandhi 18:6a4db94011d3 13673 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 13674 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13675 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13676 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 13677 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 13678
sahilmgandhi 18:6a4db94011d3 13679 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 13680 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 13681 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 13682
sahilmgandhi 18:6a4db94011d3 13683 /* Register: TWIM_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 13684 /* Description: TWI frequency */
sahilmgandhi 18:6a4db94011d3 13685
sahilmgandhi 18:6a4db94011d3 13686 /* Bits 31..0 : TWI master clock frequency */
sahilmgandhi 18:6a4db94011d3 13687 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 13688 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 13689 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
sahilmgandhi 18:6a4db94011d3 13690 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
sahilmgandhi 18:6a4db94011d3 13691 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
sahilmgandhi 18:6a4db94011d3 13692
sahilmgandhi 18:6a4db94011d3 13693 /* Register: TWIM_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 13694 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 13695
sahilmgandhi 18:6a4db94011d3 13696 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 13697 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 13698 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 13699
sahilmgandhi 18:6a4db94011d3 13700 /* Register: TWIM_RXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 13701 /* Description: Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 13702
sahilmgandhi 18:6a4db94011d3 13703 /* Bits 7..0 : Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 13704 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 13705 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 13706
sahilmgandhi 18:6a4db94011d3 13707 /* Register: TWIM_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 13708 /* Description: Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 13709
sahilmgandhi 18:6a4db94011d3 13710 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
sahilmgandhi 18:6a4db94011d3 13711 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 13712 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 13713
sahilmgandhi 18:6a4db94011d3 13714 /* Register: TWIM_RXD_LIST */
sahilmgandhi 18:6a4db94011d3 13715 /* Description: EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 13716
sahilmgandhi 18:6a4db94011d3 13717 /* Bits 2..0 : List type */
sahilmgandhi 18:6a4db94011d3 13718 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
sahilmgandhi 18:6a4db94011d3 13719 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
sahilmgandhi 18:6a4db94011d3 13720 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
sahilmgandhi 18:6a4db94011d3 13721 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
sahilmgandhi 18:6a4db94011d3 13722
sahilmgandhi 18:6a4db94011d3 13723 /* Register: TWIM_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 13724 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 13725
sahilmgandhi 18:6a4db94011d3 13726 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 13727 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 13728 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 13729
sahilmgandhi 18:6a4db94011d3 13730 /* Register: TWIM_TXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 13731 /* Description: Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 13732
sahilmgandhi 18:6a4db94011d3 13733 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 13734 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 13735 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 13736
sahilmgandhi 18:6a4db94011d3 13737 /* Register: TWIM_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 13738 /* Description: Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 13739
sahilmgandhi 18:6a4db94011d3 13740 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
sahilmgandhi 18:6a4db94011d3 13741 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 13742 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 13743
sahilmgandhi 18:6a4db94011d3 13744 /* Register: TWIM_TXD_LIST */
sahilmgandhi 18:6a4db94011d3 13745 /* Description: EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 13746
sahilmgandhi 18:6a4db94011d3 13747 /* Bits 2..0 : List type */
sahilmgandhi 18:6a4db94011d3 13748 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
sahilmgandhi 18:6a4db94011d3 13749 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
sahilmgandhi 18:6a4db94011d3 13750 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
sahilmgandhi 18:6a4db94011d3 13751 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
sahilmgandhi 18:6a4db94011d3 13752
sahilmgandhi 18:6a4db94011d3 13753 /* Register: TWIM_ADDRESS */
sahilmgandhi 18:6a4db94011d3 13754 /* Description: Address used in the TWI transfer */
sahilmgandhi 18:6a4db94011d3 13755
sahilmgandhi 18:6a4db94011d3 13756 /* Bits 6..0 : Address used in the TWI transfer */
sahilmgandhi 18:6a4db94011d3 13757 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 13758 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 13759
sahilmgandhi 18:6a4db94011d3 13760
sahilmgandhi 18:6a4db94011d3 13761 /* Peripheral: TWIS */
sahilmgandhi 18:6a4db94011d3 13762 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
sahilmgandhi 18:6a4db94011d3 13763
sahilmgandhi 18:6a4db94011d3 13764 /* Register: TWIS_SHORTS */
sahilmgandhi 18:6a4db94011d3 13765 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 13766
sahilmgandhi 18:6a4db94011d3 13767 /* Bit 14 : Shortcut between READ event and SUSPEND task */
sahilmgandhi 18:6a4db94011d3 13768 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13769 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13770 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13771 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13772
sahilmgandhi 18:6a4db94011d3 13773 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
sahilmgandhi 18:6a4db94011d3 13774 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13775 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 13776 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 13777 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 13778
sahilmgandhi 18:6a4db94011d3 13779 /* Register: TWIS_INTEN */
sahilmgandhi 18:6a4db94011d3 13780 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 13781
sahilmgandhi 18:6a4db94011d3 13782 /* Bit 26 : Enable or disable interrupt for READ event */
sahilmgandhi 18:6a4db94011d3 13783 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
sahilmgandhi 18:6a4db94011d3 13784 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
sahilmgandhi 18:6a4db94011d3 13785 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13786 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13787
sahilmgandhi 18:6a4db94011d3 13788 /* Bit 25 : Enable or disable interrupt for WRITE event */
sahilmgandhi 18:6a4db94011d3 13789 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
sahilmgandhi 18:6a4db94011d3 13790 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
sahilmgandhi 18:6a4db94011d3 13791 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13792 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13793
sahilmgandhi 18:6a4db94011d3 13794 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13795 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13796 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13797 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13798 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13799
sahilmgandhi 18:6a4db94011d3 13800 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13801 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13802 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13803 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13804 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13805
sahilmgandhi 18:6a4db94011d3 13806 /* Bit 9 : Enable or disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13807 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13808 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13809 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13810 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13811
sahilmgandhi 18:6a4db94011d3 13812 /* Bit 1 : Enable or disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13813 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13814 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13815 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13816 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13817
sahilmgandhi 18:6a4db94011d3 13818 /* Register: TWIS_INTENSET */
sahilmgandhi 18:6a4db94011d3 13819 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 13820
sahilmgandhi 18:6a4db94011d3 13821 /* Bit 26 : Write '1' to Enable interrupt for READ event */
sahilmgandhi 18:6a4db94011d3 13822 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
sahilmgandhi 18:6a4db94011d3 13823 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
sahilmgandhi 18:6a4db94011d3 13824 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13825 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13826 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13827
sahilmgandhi 18:6a4db94011d3 13828 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
sahilmgandhi 18:6a4db94011d3 13829 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
sahilmgandhi 18:6a4db94011d3 13830 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
sahilmgandhi 18:6a4db94011d3 13831 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13832 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13833 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13834
sahilmgandhi 18:6a4db94011d3 13835 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13836 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13837 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13838 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13839 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13840 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13841
sahilmgandhi 18:6a4db94011d3 13842 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13843 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13844 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13845 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13846 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13847 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13848
sahilmgandhi 18:6a4db94011d3 13849 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13850 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13851 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13852 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13853 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13854 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13855
sahilmgandhi 18:6a4db94011d3 13856 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13857 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13858 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13859 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13860 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13861 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 13862
sahilmgandhi 18:6a4db94011d3 13863 /* Register: TWIS_INTENCLR */
sahilmgandhi 18:6a4db94011d3 13864 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 13865
sahilmgandhi 18:6a4db94011d3 13866 /* Bit 26 : Write '1' to Disable interrupt for READ event */
sahilmgandhi 18:6a4db94011d3 13867 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
sahilmgandhi 18:6a4db94011d3 13868 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
sahilmgandhi 18:6a4db94011d3 13869 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13870 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13871 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13872
sahilmgandhi 18:6a4db94011d3 13873 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
sahilmgandhi 18:6a4db94011d3 13874 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
sahilmgandhi 18:6a4db94011d3 13875 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
sahilmgandhi 18:6a4db94011d3 13876 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13877 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13878 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13879
sahilmgandhi 18:6a4db94011d3 13880 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13881 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13882 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13883 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13884 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13885 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13886
sahilmgandhi 18:6a4db94011d3 13887 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 13888 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13889 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 13890 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13891 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13892 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13893
sahilmgandhi 18:6a4db94011d3 13894 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 13895 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13896 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 13897 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13898 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13899 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13900
sahilmgandhi 18:6a4db94011d3 13901 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
sahilmgandhi 18:6a4db94011d3 13902 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13903 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 13904 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 13905 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 13906 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 13907
sahilmgandhi 18:6a4db94011d3 13908 /* Register: TWIS_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 13909 /* Description: Error source */
sahilmgandhi 18:6a4db94011d3 13910
sahilmgandhi 18:6a4db94011d3 13911 /* Bit 3 : TX buffer over-read detected, and prevented */
sahilmgandhi 18:6a4db94011d3 13912 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
sahilmgandhi 18:6a4db94011d3 13913 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
sahilmgandhi 18:6a4db94011d3 13914 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
sahilmgandhi 18:6a4db94011d3 13915 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
sahilmgandhi 18:6a4db94011d3 13916
sahilmgandhi 18:6a4db94011d3 13917 /* Bit 2 : NACK sent after receiving a data byte */
sahilmgandhi 18:6a4db94011d3 13918 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
sahilmgandhi 18:6a4db94011d3 13919 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
sahilmgandhi 18:6a4db94011d3 13920 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
sahilmgandhi 18:6a4db94011d3 13921 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
sahilmgandhi 18:6a4db94011d3 13922
sahilmgandhi 18:6a4db94011d3 13923 /* Bit 0 : RX buffer overflow detected, and prevented */
sahilmgandhi 18:6a4db94011d3 13924 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
sahilmgandhi 18:6a4db94011d3 13925 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
sahilmgandhi 18:6a4db94011d3 13926 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
sahilmgandhi 18:6a4db94011d3 13927 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
sahilmgandhi 18:6a4db94011d3 13928
sahilmgandhi 18:6a4db94011d3 13929 /* Register: TWIS_MATCH */
sahilmgandhi 18:6a4db94011d3 13930 /* Description: Status register indicating which address had a match */
sahilmgandhi 18:6a4db94011d3 13931
sahilmgandhi 18:6a4db94011d3 13932 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
sahilmgandhi 18:6a4db94011d3 13933 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
sahilmgandhi 18:6a4db94011d3 13934 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
sahilmgandhi 18:6a4db94011d3 13935
sahilmgandhi 18:6a4db94011d3 13936 /* Register: TWIS_ENABLE */
sahilmgandhi 18:6a4db94011d3 13937 /* Description: Enable TWIS */
sahilmgandhi 18:6a4db94011d3 13938
sahilmgandhi 18:6a4db94011d3 13939 /* Bits 3..0 : Enable or disable TWIS */
sahilmgandhi 18:6a4db94011d3 13940 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 13941 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 13942 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
sahilmgandhi 18:6a4db94011d3 13943 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
sahilmgandhi 18:6a4db94011d3 13944
sahilmgandhi 18:6a4db94011d3 13945 /* Register: TWIS_PSEL_SCL */
sahilmgandhi 18:6a4db94011d3 13946 /* Description: Pin select for SCL signal */
sahilmgandhi 18:6a4db94011d3 13947
sahilmgandhi 18:6a4db94011d3 13948 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 13949 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13950 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13951 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 13952 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 13953
sahilmgandhi 18:6a4db94011d3 13954 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 13955 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 13956 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 13957
sahilmgandhi 18:6a4db94011d3 13958 /* Register: TWIS_PSEL_SDA */
sahilmgandhi 18:6a4db94011d3 13959 /* Description: Pin select for SDA signal */
sahilmgandhi 18:6a4db94011d3 13960
sahilmgandhi 18:6a4db94011d3 13961 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 13962 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13963 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 13964 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 13965 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 13966
sahilmgandhi 18:6a4db94011d3 13967 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 13968 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 13969 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 13970
sahilmgandhi 18:6a4db94011d3 13971 /* Register: TWIS_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 13972 /* Description: RXD Data pointer */
sahilmgandhi 18:6a4db94011d3 13973
sahilmgandhi 18:6a4db94011d3 13974 /* Bits 31..0 : RXD Data pointer */
sahilmgandhi 18:6a4db94011d3 13975 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 13976 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 13977
sahilmgandhi 18:6a4db94011d3 13978 /* Register: TWIS_RXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 13979 /* Description: Maximum number of bytes in RXD buffer */
sahilmgandhi 18:6a4db94011d3 13980
sahilmgandhi 18:6a4db94011d3 13981 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
sahilmgandhi 18:6a4db94011d3 13982 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 13983 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 13984
sahilmgandhi 18:6a4db94011d3 13985 /* Register: TWIS_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 13986 /* Description: Number of bytes transferred in the last RXD transaction */
sahilmgandhi 18:6a4db94011d3 13987
sahilmgandhi 18:6a4db94011d3 13988 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
sahilmgandhi 18:6a4db94011d3 13989 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 13990 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 13991
sahilmgandhi 18:6a4db94011d3 13992 /* Register: TWIS_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 13993 /* Description: TXD Data pointer */
sahilmgandhi 18:6a4db94011d3 13994
sahilmgandhi 18:6a4db94011d3 13995 /* Bits 31..0 : TXD Data pointer */
sahilmgandhi 18:6a4db94011d3 13996 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 13997 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 13998
sahilmgandhi 18:6a4db94011d3 13999 /* Register: TWIS_TXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 14000 /* Description: Maximum number of bytes in TXD buffer */
sahilmgandhi 18:6a4db94011d3 14001
sahilmgandhi 18:6a4db94011d3 14002 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
sahilmgandhi 18:6a4db94011d3 14003 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 14004 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 14005
sahilmgandhi 18:6a4db94011d3 14006 /* Register: TWIS_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 14007 /* Description: Number of bytes transferred in the last TXD transaction */
sahilmgandhi 18:6a4db94011d3 14008
sahilmgandhi 18:6a4db94011d3 14009 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
sahilmgandhi 18:6a4db94011d3 14010 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 14011 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 14012
sahilmgandhi 18:6a4db94011d3 14013 /* Register: TWIS_ADDRESS */
sahilmgandhi 18:6a4db94011d3 14014 /* Description: Description collection[0]: TWI slave address 0 */
sahilmgandhi 18:6a4db94011d3 14015
sahilmgandhi 18:6a4db94011d3 14016 /* Bits 6..0 : TWI slave address */
sahilmgandhi 18:6a4db94011d3 14017 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 14018 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 14019
sahilmgandhi 18:6a4db94011d3 14020 /* Register: TWIS_CONFIG */
sahilmgandhi 18:6a4db94011d3 14021 /* Description: Configuration register for the address match mechanism */
sahilmgandhi 18:6a4db94011d3 14022
sahilmgandhi 18:6a4db94011d3 14023 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
sahilmgandhi 18:6a4db94011d3 14024 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
sahilmgandhi 18:6a4db94011d3 14025 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
sahilmgandhi 18:6a4db94011d3 14026 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 14027 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 14028
sahilmgandhi 18:6a4db94011d3 14029 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
sahilmgandhi 18:6a4db94011d3 14030 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
sahilmgandhi 18:6a4db94011d3 14031 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
sahilmgandhi 18:6a4db94011d3 14032 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 14033 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 14034
sahilmgandhi 18:6a4db94011d3 14035 /* Register: TWIS_ORC */
sahilmgandhi 18:6a4db94011d3 14036 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 14037
sahilmgandhi 18:6a4db94011d3 14038 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 14039 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
sahilmgandhi 18:6a4db94011d3 14040 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
sahilmgandhi 18:6a4db94011d3 14041
sahilmgandhi 18:6a4db94011d3 14042
sahilmgandhi 18:6a4db94011d3 14043 /* Peripheral: UART */
sahilmgandhi 18:6a4db94011d3 14044 /* Description: Universal Asynchronous Receiver/Transmitter */
sahilmgandhi 18:6a4db94011d3 14045
sahilmgandhi 18:6a4db94011d3 14046 /* Register: UART_SHORTS */
sahilmgandhi 18:6a4db94011d3 14047 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 14048
sahilmgandhi 18:6a4db94011d3 14049 /* Bit 4 : Shortcut between NCTS event and STOPRX task */
sahilmgandhi 18:6a4db94011d3 14050 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
sahilmgandhi 18:6a4db94011d3 14051 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
sahilmgandhi 18:6a4db94011d3 14052 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 14053 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 14054
sahilmgandhi 18:6a4db94011d3 14055 /* Bit 3 : Shortcut between CTS event and STARTRX task */
sahilmgandhi 18:6a4db94011d3 14056 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 14057 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 14058 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 14059 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 14060
sahilmgandhi 18:6a4db94011d3 14061 /* Register: UART_INTENSET */
sahilmgandhi 18:6a4db94011d3 14062 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 14063
sahilmgandhi 18:6a4db94011d3 14064 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
sahilmgandhi 18:6a4db94011d3 14065 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14066 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14067 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14068 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14069 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14070
sahilmgandhi 18:6a4db94011d3 14071 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 14072 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14073 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14074 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14075 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14076 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14077
sahilmgandhi 18:6a4db94011d3 14078 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
sahilmgandhi 18:6a4db94011d3 14079 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14080 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14081 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14082 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14083 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14084
sahilmgandhi 18:6a4db94011d3 14085 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
sahilmgandhi 18:6a4db94011d3 14086 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14087 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14088 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14089 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14090 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14091
sahilmgandhi 18:6a4db94011d3 14092 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
sahilmgandhi 18:6a4db94011d3 14093 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14094 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14095 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14096 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14097 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14098
sahilmgandhi 18:6a4db94011d3 14099 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
sahilmgandhi 18:6a4db94011d3 14100 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 14101 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 14102 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14103 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14104 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14105
sahilmgandhi 18:6a4db94011d3 14106 /* Register: UART_INTENCLR */
sahilmgandhi 18:6a4db94011d3 14107 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 14108
sahilmgandhi 18:6a4db94011d3 14109 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
sahilmgandhi 18:6a4db94011d3 14110 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14111 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14112 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14113 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14114 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14115
sahilmgandhi 18:6a4db94011d3 14116 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 14117 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14118 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14119 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14120 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14121 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14122
sahilmgandhi 18:6a4db94011d3 14123 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
sahilmgandhi 18:6a4db94011d3 14124 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14125 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14126 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14127 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14128 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14129
sahilmgandhi 18:6a4db94011d3 14130 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
sahilmgandhi 18:6a4db94011d3 14131 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14132 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 14133 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14134 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14135 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14136
sahilmgandhi 18:6a4db94011d3 14137 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
sahilmgandhi 18:6a4db94011d3 14138 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14139 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14140 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14141 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14142 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14143
sahilmgandhi 18:6a4db94011d3 14144 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
sahilmgandhi 18:6a4db94011d3 14145 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 14146 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 14147 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14148 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14149 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14150
sahilmgandhi 18:6a4db94011d3 14151 /* Register: UART_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 14152 /* Description: Error source */
sahilmgandhi 18:6a4db94011d3 14153
sahilmgandhi 18:6a4db94011d3 14154 /* Bit 3 : Break condition */
sahilmgandhi 18:6a4db94011d3 14155 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
sahilmgandhi 18:6a4db94011d3 14156 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
sahilmgandhi 18:6a4db94011d3 14157 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14158 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14159
sahilmgandhi 18:6a4db94011d3 14160 /* Bit 2 : Framing error occurred */
sahilmgandhi 18:6a4db94011d3 14161 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
sahilmgandhi 18:6a4db94011d3 14162 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
sahilmgandhi 18:6a4db94011d3 14163 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14164 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14165
sahilmgandhi 18:6a4db94011d3 14166 /* Bit 1 : Parity error */
sahilmgandhi 18:6a4db94011d3 14167 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14168 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14169 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14170 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14171
sahilmgandhi 18:6a4db94011d3 14172 /* Bit 0 : Overrun error */
sahilmgandhi 18:6a4db94011d3 14173 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 14174 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 14175 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14176 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14177
sahilmgandhi 18:6a4db94011d3 14178 /* Register: UART_ENABLE */
sahilmgandhi 18:6a4db94011d3 14179 /* Description: Enable UART */
sahilmgandhi 18:6a4db94011d3 14180
sahilmgandhi 18:6a4db94011d3 14181 /* Bits 3..0 : Enable or disable UART */
sahilmgandhi 18:6a4db94011d3 14182 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 14183 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 14184 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
sahilmgandhi 18:6a4db94011d3 14185 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
sahilmgandhi 18:6a4db94011d3 14186
sahilmgandhi 18:6a4db94011d3 14187 /* Register: UART_PSELRTS */
sahilmgandhi 18:6a4db94011d3 14188 /* Description: Pin select for RTS */
sahilmgandhi 18:6a4db94011d3 14189
sahilmgandhi 18:6a4db94011d3 14190 /* Bits 31..0 : Pin number configuration for UART RTS signal */
sahilmgandhi 18:6a4db94011d3 14191 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
sahilmgandhi 18:6a4db94011d3 14192 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
sahilmgandhi 18:6a4db94011d3 14193 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14194
sahilmgandhi 18:6a4db94011d3 14195 /* Register: UART_PSELTXD */
sahilmgandhi 18:6a4db94011d3 14196 /* Description: Pin select for TXD */
sahilmgandhi 18:6a4db94011d3 14197
sahilmgandhi 18:6a4db94011d3 14198 /* Bits 31..0 : Pin number configuration for UART TXD signal */
sahilmgandhi 18:6a4db94011d3 14199 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
sahilmgandhi 18:6a4db94011d3 14200 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
sahilmgandhi 18:6a4db94011d3 14201 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14202
sahilmgandhi 18:6a4db94011d3 14203 /* Register: UART_PSELCTS */
sahilmgandhi 18:6a4db94011d3 14204 /* Description: Pin select for CTS */
sahilmgandhi 18:6a4db94011d3 14205
sahilmgandhi 18:6a4db94011d3 14206 /* Bits 31..0 : Pin number configuration for UART CTS signal */
sahilmgandhi 18:6a4db94011d3 14207 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
sahilmgandhi 18:6a4db94011d3 14208 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
sahilmgandhi 18:6a4db94011d3 14209 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14210
sahilmgandhi 18:6a4db94011d3 14211 /* Register: UART_PSELRXD */
sahilmgandhi 18:6a4db94011d3 14212 /* Description: Pin select for RXD */
sahilmgandhi 18:6a4db94011d3 14213
sahilmgandhi 18:6a4db94011d3 14214 /* Bits 31..0 : Pin number configuration for UART RXD signal */
sahilmgandhi 18:6a4db94011d3 14215 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
sahilmgandhi 18:6a4db94011d3 14216 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
sahilmgandhi 18:6a4db94011d3 14217 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14218
sahilmgandhi 18:6a4db94011d3 14219 /* Register: UART_RXD */
sahilmgandhi 18:6a4db94011d3 14220 /* Description: RXD register */
sahilmgandhi 18:6a4db94011d3 14221
sahilmgandhi 18:6a4db94011d3 14222 /* Bits 7..0 : RX data received in previous transfers, double buffered */
sahilmgandhi 18:6a4db94011d3 14223 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
sahilmgandhi 18:6a4db94011d3 14224 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
sahilmgandhi 18:6a4db94011d3 14225
sahilmgandhi 18:6a4db94011d3 14226 /* Register: UART_TXD */
sahilmgandhi 18:6a4db94011d3 14227 /* Description: TXD register */
sahilmgandhi 18:6a4db94011d3 14228
sahilmgandhi 18:6a4db94011d3 14229 /* Bits 7..0 : TX data to be transferred */
sahilmgandhi 18:6a4db94011d3 14230 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
sahilmgandhi 18:6a4db94011d3 14231 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
sahilmgandhi 18:6a4db94011d3 14232
sahilmgandhi 18:6a4db94011d3 14233 /* Register: UART_BAUDRATE */
sahilmgandhi 18:6a4db94011d3 14234 /* Description: Baud rate */
sahilmgandhi 18:6a4db94011d3 14235
sahilmgandhi 18:6a4db94011d3 14236 /* Bits 31..0 : Baud-rate */
sahilmgandhi 18:6a4db94011d3 14237 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
sahilmgandhi 18:6a4db94011d3 14238 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
sahilmgandhi 18:6a4db94011d3 14239 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
sahilmgandhi 18:6a4db94011d3 14240 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
sahilmgandhi 18:6a4db94011d3 14241 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
sahilmgandhi 18:6a4db94011d3 14242 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
sahilmgandhi 18:6a4db94011d3 14243 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
sahilmgandhi 18:6a4db94011d3 14244 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
sahilmgandhi 18:6a4db94011d3 14245 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
sahilmgandhi 18:6a4db94011d3 14246 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
sahilmgandhi 18:6a4db94011d3 14247 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
sahilmgandhi 18:6a4db94011d3 14248 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
sahilmgandhi 18:6a4db94011d3 14249 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
sahilmgandhi 18:6a4db94011d3 14250 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
sahilmgandhi 18:6a4db94011d3 14251 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
sahilmgandhi 18:6a4db94011d3 14252 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
sahilmgandhi 18:6a4db94011d3 14253 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
sahilmgandhi 18:6a4db94011d3 14254 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
sahilmgandhi 18:6a4db94011d3 14255
sahilmgandhi 18:6a4db94011d3 14256 /* Register: UART_CONFIG */
sahilmgandhi 18:6a4db94011d3 14257 /* Description: Configuration of parity and hardware flow control */
sahilmgandhi 18:6a4db94011d3 14258
sahilmgandhi 18:6a4db94011d3 14259 /* Bits 3..1 : Parity */
sahilmgandhi 18:6a4db94011d3 14260 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14261 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14262 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
sahilmgandhi 18:6a4db94011d3 14263 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
sahilmgandhi 18:6a4db94011d3 14264
sahilmgandhi 18:6a4db94011d3 14265 /* Bit 0 : Hardware flow control */
sahilmgandhi 18:6a4db94011d3 14266 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
sahilmgandhi 18:6a4db94011d3 14267 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
sahilmgandhi 18:6a4db94011d3 14268 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 14269 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 14270
sahilmgandhi 18:6a4db94011d3 14271
sahilmgandhi 18:6a4db94011d3 14272 /* Peripheral: UARTE */
sahilmgandhi 18:6a4db94011d3 14273 /* Description: UART with EasyDMA */
sahilmgandhi 18:6a4db94011d3 14274
sahilmgandhi 18:6a4db94011d3 14275 /* Register: UARTE_SHORTS */
sahilmgandhi 18:6a4db94011d3 14276 /* Description: Shortcut register */
sahilmgandhi 18:6a4db94011d3 14277
sahilmgandhi 18:6a4db94011d3 14278 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */
sahilmgandhi 18:6a4db94011d3 14279 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
sahilmgandhi 18:6a4db94011d3 14280 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
sahilmgandhi 18:6a4db94011d3 14281 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 14282 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 14283
sahilmgandhi 18:6a4db94011d3 14284 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */
sahilmgandhi 18:6a4db94011d3 14285 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 14286 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 14287 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
sahilmgandhi 18:6a4db94011d3 14288 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
sahilmgandhi 18:6a4db94011d3 14289
sahilmgandhi 18:6a4db94011d3 14290 /* Register: UARTE_INTEN */
sahilmgandhi 18:6a4db94011d3 14291 /* Description: Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 14292
sahilmgandhi 18:6a4db94011d3 14293 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
sahilmgandhi 18:6a4db94011d3 14294 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
sahilmgandhi 18:6a4db94011d3 14295 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
sahilmgandhi 18:6a4db94011d3 14296 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14297 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14298
sahilmgandhi 18:6a4db94011d3 14299 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 14300 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14301 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14302 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14303 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14304
sahilmgandhi 18:6a4db94011d3 14305 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 14306 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14307 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14308 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14309 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14310
sahilmgandhi 18:6a4db94011d3 14311 /* Bit 17 : Enable or disable interrupt for RXTO event */
sahilmgandhi 18:6a4db94011d3 14312 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14313 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14314 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14315 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14316
sahilmgandhi 18:6a4db94011d3 14317 /* Bit 9 : Enable or disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 14318 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14319 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14320 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14321 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14322
sahilmgandhi 18:6a4db94011d3 14323 /* Bit 8 : Enable or disable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 14324 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 14325 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 14326 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14327 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14328
sahilmgandhi 18:6a4db94011d3 14329 /* Bit 4 : Enable or disable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 14330 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 14331 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 14332 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14333 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14334
sahilmgandhi 18:6a4db94011d3 14335 /* Bit 1 : Enable or disable interrupt for NCTS event */
sahilmgandhi 18:6a4db94011d3 14336 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14337 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14338 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14339 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14340
sahilmgandhi 18:6a4db94011d3 14341 /* Bit 0 : Enable or disable interrupt for CTS event */
sahilmgandhi 18:6a4db94011d3 14342 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 14343 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 14344 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14345 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14346
sahilmgandhi 18:6a4db94011d3 14347 /* Register: UARTE_INTENSET */
sahilmgandhi 18:6a4db94011d3 14348 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 14349
sahilmgandhi 18:6a4db94011d3 14350 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
sahilmgandhi 18:6a4db94011d3 14351 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
sahilmgandhi 18:6a4db94011d3 14352 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
sahilmgandhi 18:6a4db94011d3 14353 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14354 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14355 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14356
sahilmgandhi 18:6a4db94011d3 14357 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 14358 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14359 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14360 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14361 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14362 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14363
sahilmgandhi 18:6a4db94011d3 14364 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 14365 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14366 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14367 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14368 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14369 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14370
sahilmgandhi 18:6a4db94011d3 14371 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
sahilmgandhi 18:6a4db94011d3 14372 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14373 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14374 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14375 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14376 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14377
sahilmgandhi 18:6a4db94011d3 14378 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 14379 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14380 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14381 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14382 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14383 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14384
sahilmgandhi 18:6a4db94011d3 14385 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 14386 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 14387 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 14388 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14389 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14390 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14391
sahilmgandhi 18:6a4db94011d3 14392 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 14393 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 14394 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 14395 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14396 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14397 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14398
sahilmgandhi 18:6a4db94011d3 14399 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
sahilmgandhi 18:6a4db94011d3 14400 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14401 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14402 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14403 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14404 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14405
sahilmgandhi 18:6a4db94011d3 14406 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
sahilmgandhi 18:6a4db94011d3 14407 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 14408 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 14409 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14410 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14411 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14412
sahilmgandhi 18:6a4db94011d3 14413 /* Register: UARTE_INTENCLR */
sahilmgandhi 18:6a4db94011d3 14414 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 14415
sahilmgandhi 18:6a4db94011d3 14416 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
sahilmgandhi 18:6a4db94011d3 14417 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
sahilmgandhi 18:6a4db94011d3 14418 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
sahilmgandhi 18:6a4db94011d3 14419 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14420 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14421 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14422
sahilmgandhi 18:6a4db94011d3 14423 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
sahilmgandhi 18:6a4db94011d3 14424 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14425 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14426 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14427 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14428 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14429
sahilmgandhi 18:6a4db94011d3 14430 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
sahilmgandhi 18:6a4db94011d3 14431 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14432 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
sahilmgandhi 18:6a4db94011d3 14433 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14434 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14435 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14436
sahilmgandhi 18:6a4db94011d3 14437 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
sahilmgandhi 18:6a4db94011d3 14438 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14439 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 14440 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14441 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14442 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14443
sahilmgandhi 18:6a4db94011d3 14444 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
sahilmgandhi 18:6a4db94011d3 14445 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14446 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 14447 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14448 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14449 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14450
sahilmgandhi 18:6a4db94011d3 14451 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
sahilmgandhi 18:6a4db94011d3 14452 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 14453 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 14454 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14455 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14456 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14457
sahilmgandhi 18:6a4db94011d3 14458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
sahilmgandhi 18:6a4db94011d3 14459 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 14460 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 14461 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14462 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14463 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14464
sahilmgandhi 18:6a4db94011d3 14465 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
sahilmgandhi 18:6a4db94011d3 14466 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14467 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 14468 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14469 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14470 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14471
sahilmgandhi 18:6a4db94011d3 14472 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
sahilmgandhi 18:6a4db94011d3 14473 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 14474 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 14475 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14476 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14477 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14478
sahilmgandhi 18:6a4db94011d3 14479 /* Register: UARTE_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 14480 /* Description: Error source */
sahilmgandhi 18:6a4db94011d3 14481
sahilmgandhi 18:6a4db94011d3 14482 /* Bit 3 : Break condition */
sahilmgandhi 18:6a4db94011d3 14483 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
sahilmgandhi 18:6a4db94011d3 14484 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
sahilmgandhi 18:6a4db94011d3 14485 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14486 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14487
sahilmgandhi 18:6a4db94011d3 14488 /* Bit 2 : Framing error occurred */
sahilmgandhi 18:6a4db94011d3 14489 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
sahilmgandhi 18:6a4db94011d3 14490 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
sahilmgandhi 18:6a4db94011d3 14491 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14492 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14493
sahilmgandhi 18:6a4db94011d3 14494 /* Bit 1 : Parity error */
sahilmgandhi 18:6a4db94011d3 14495 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14496 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14497 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14498 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14499
sahilmgandhi 18:6a4db94011d3 14500 /* Bit 0 : Overrun error */
sahilmgandhi 18:6a4db94011d3 14501 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 14502 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 14503 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
sahilmgandhi 18:6a4db94011d3 14504 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
sahilmgandhi 18:6a4db94011d3 14505
sahilmgandhi 18:6a4db94011d3 14506 /* Register: UARTE_ENABLE */
sahilmgandhi 18:6a4db94011d3 14507 /* Description: Enable UART */
sahilmgandhi 18:6a4db94011d3 14508
sahilmgandhi 18:6a4db94011d3 14509 /* Bits 3..0 : Enable or disable UARTE */
sahilmgandhi 18:6a4db94011d3 14510 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 14511 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 14512 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
sahilmgandhi 18:6a4db94011d3 14513 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
sahilmgandhi 18:6a4db94011d3 14514
sahilmgandhi 18:6a4db94011d3 14515 /* Register: UARTE_PSEL_RTS */
sahilmgandhi 18:6a4db94011d3 14516 /* Description: Pin select for RTS signal */
sahilmgandhi 18:6a4db94011d3 14517
sahilmgandhi 18:6a4db94011d3 14518 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 14519 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14520 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14521 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 14522 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14523
sahilmgandhi 18:6a4db94011d3 14524 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 14525 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 14526 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 14527
sahilmgandhi 18:6a4db94011d3 14528 /* Register: UARTE_PSEL_TXD */
sahilmgandhi 18:6a4db94011d3 14529 /* Description: Pin select for TXD signal */
sahilmgandhi 18:6a4db94011d3 14530
sahilmgandhi 18:6a4db94011d3 14531 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 14532 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14533 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14534 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 14535 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14536
sahilmgandhi 18:6a4db94011d3 14537 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 14538 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 14539 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 14540
sahilmgandhi 18:6a4db94011d3 14541 /* Register: UARTE_PSEL_CTS */
sahilmgandhi 18:6a4db94011d3 14542 /* Description: Pin select for CTS signal */
sahilmgandhi 18:6a4db94011d3 14543
sahilmgandhi 18:6a4db94011d3 14544 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 14545 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14546 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14547 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 14548 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14549
sahilmgandhi 18:6a4db94011d3 14550 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 14551 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 14552 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 14553
sahilmgandhi 18:6a4db94011d3 14554 /* Register: UARTE_PSEL_RXD */
sahilmgandhi 18:6a4db94011d3 14555 /* Description: Pin select for RXD signal */
sahilmgandhi 18:6a4db94011d3 14556
sahilmgandhi 18:6a4db94011d3 14557 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 14558 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14559 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14560 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 14561 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14562
sahilmgandhi 18:6a4db94011d3 14563 /* Bits 4..0 : Pin number */
sahilmgandhi 18:6a4db94011d3 14564 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 14565 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 14566
sahilmgandhi 18:6a4db94011d3 14567 /* Register: UARTE_BAUDRATE */
sahilmgandhi 18:6a4db94011d3 14568 /* Description: Baud rate */
sahilmgandhi 18:6a4db94011d3 14569
sahilmgandhi 18:6a4db94011d3 14570 /* Bits 31..0 : Baud-rate */
sahilmgandhi 18:6a4db94011d3 14571 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
sahilmgandhi 18:6a4db94011d3 14572 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
sahilmgandhi 18:6a4db94011d3 14573 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
sahilmgandhi 18:6a4db94011d3 14574 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
sahilmgandhi 18:6a4db94011d3 14575 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
sahilmgandhi 18:6a4db94011d3 14576 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
sahilmgandhi 18:6a4db94011d3 14577 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
sahilmgandhi 18:6a4db94011d3 14578 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
sahilmgandhi 18:6a4db94011d3 14579 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
sahilmgandhi 18:6a4db94011d3 14580 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
sahilmgandhi 18:6a4db94011d3 14581 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
sahilmgandhi 18:6a4db94011d3 14582 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
sahilmgandhi 18:6a4db94011d3 14583 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
sahilmgandhi 18:6a4db94011d3 14584 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
sahilmgandhi 18:6a4db94011d3 14585 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
sahilmgandhi 18:6a4db94011d3 14586 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
sahilmgandhi 18:6a4db94011d3 14587 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
sahilmgandhi 18:6a4db94011d3 14588 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
sahilmgandhi 18:6a4db94011d3 14589
sahilmgandhi 18:6a4db94011d3 14590 /* Register: UARTE_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 14591 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 14592
sahilmgandhi 18:6a4db94011d3 14593 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 14594 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 14595 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 14596
sahilmgandhi 18:6a4db94011d3 14597 /* Register: UARTE_RXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 14598 /* Description: Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 14599
sahilmgandhi 18:6a4db94011d3 14600 /* Bits 7..0 : Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 14601 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 14602 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 14603
sahilmgandhi 18:6a4db94011d3 14604 /* Register: UARTE_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 14605 /* Description: Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 14606
sahilmgandhi 18:6a4db94011d3 14607 /* Bits 7..0 : Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 14608 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 14609 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 14610
sahilmgandhi 18:6a4db94011d3 14611 /* Register: UARTE_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 14612 /* Description: Data pointer */
sahilmgandhi 18:6a4db94011d3 14613
sahilmgandhi 18:6a4db94011d3 14614 /* Bits 31..0 : Data pointer */
sahilmgandhi 18:6a4db94011d3 14615 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 14616 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 14617
sahilmgandhi 18:6a4db94011d3 14618 /* Register: UARTE_TXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 14619 /* Description: Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 14620
sahilmgandhi 18:6a4db94011d3 14621 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 14622 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 14623 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 14624
sahilmgandhi 18:6a4db94011d3 14625 /* Register: UARTE_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 14626 /* Description: Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 14627
sahilmgandhi 18:6a4db94011d3 14628 /* Bits 7..0 : Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 14629 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 14630 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 14631
sahilmgandhi 18:6a4db94011d3 14632 /* Register: UARTE_CONFIG */
sahilmgandhi 18:6a4db94011d3 14633 /* Description: Configuration of parity and hardware flow control */
sahilmgandhi 18:6a4db94011d3 14634
sahilmgandhi 18:6a4db94011d3 14635 /* Bits 3..1 : Parity */
sahilmgandhi 18:6a4db94011d3 14636 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14637 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 14638 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
sahilmgandhi 18:6a4db94011d3 14639 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
sahilmgandhi 18:6a4db94011d3 14640
sahilmgandhi 18:6a4db94011d3 14641 /* Bit 0 : Hardware flow control */
sahilmgandhi 18:6a4db94011d3 14642 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
sahilmgandhi 18:6a4db94011d3 14643 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
sahilmgandhi 18:6a4db94011d3 14644 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
sahilmgandhi 18:6a4db94011d3 14645 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
sahilmgandhi 18:6a4db94011d3 14646
sahilmgandhi 18:6a4db94011d3 14647
sahilmgandhi 18:6a4db94011d3 14648 /* Peripheral: UICR */
sahilmgandhi 18:6a4db94011d3 14649 /* Description: User Information Configuration Registers */
sahilmgandhi 18:6a4db94011d3 14650
sahilmgandhi 18:6a4db94011d3 14651 /* Register: UICR_NRFFW */
sahilmgandhi 18:6a4db94011d3 14652 /* Description: Description collection[0]: Reserved for Nordic firmware design */
sahilmgandhi 18:6a4db94011d3 14653
sahilmgandhi 18:6a4db94011d3 14654 /* Bits 31..0 : Reserved for Nordic firmware design */
sahilmgandhi 18:6a4db94011d3 14655 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
sahilmgandhi 18:6a4db94011d3 14656 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
sahilmgandhi 18:6a4db94011d3 14657
sahilmgandhi 18:6a4db94011d3 14658 /* Register: UICR_NRFHW */
sahilmgandhi 18:6a4db94011d3 14659 /* Description: Description collection[0]: Reserved for Nordic hardware design */
sahilmgandhi 18:6a4db94011d3 14660
sahilmgandhi 18:6a4db94011d3 14661 /* Bits 31..0 : Reserved for Nordic hardware design */
sahilmgandhi 18:6a4db94011d3 14662 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
sahilmgandhi 18:6a4db94011d3 14663 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
sahilmgandhi 18:6a4db94011d3 14664
sahilmgandhi 18:6a4db94011d3 14665 /* Register: UICR_CUSTOMER */
sahilmgandhi 18:6a4db94011d3 14666 /* Description: Description collection[0]: Reserved for customer */
sahilmgandhi 18:6a4db94011d3 14667
sahilmgandhi 18:6a4db94011d3 14668 /* Bits 31..0 : Reserved for customer */
sahilmgandhi 18:6a4db94011d3 14669 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
sahilmgandhi 18:6a4db94011d3 14670 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
sahilmgandhi 18:6a4db94011d3 14671
sahilmgandhi 18:6a4db94011d3 14672 /* Register: UICR_PSELRESET */
sahilmgandhi 18:6a4db94011d3 14673 /* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
sahilmgandhi 18:6a4db94011d3 14674
sahilmgandhi 18:6a4db94011d3 14675 /* Bit 31 : Connection */
sahilmgandhi 18:6a4db94011d3 14676 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14677 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
sahilmgandhi 18:6a4db94011d3 14678 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
sahilmgandhi 18:6a4db94011d3 14679 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
sahilmgandhi 18:6a4db94011d3 14680
sahilmgandhi 18:6a4db94011d3 14681 /* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
sahilmgandhi 18:6a4db94011d3 14682 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
sahilmgandhi 18:6a4db94011d3 14683 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
sahilmgandhi 18:6a4db94011d3 14684
sahilmgandhi 18:6a4db94011d3 14685 /* Register: UICR_APPROTECT */
sahilmgandhi 18:6a4db94011d3 14686 /* Description: Access Port protection */
sahilmgandhi 18:6a4db94011d3 14687
sahilmgandhi 18:6a4db94011d3 14688 /* Bits 7..0 : Enable or disable Access Port protection. */
sahilmgandhi 18:6a4db94011d3 14689 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
sahilmgandhi 18:6a4db94011d3 14690 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
sahilmgandhi 18:6a4db94011d3 14691 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14692 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14693
sahilmgandhi 18:6a4db94011d3 14694 /* Register: UICR_NFCPINS */
sahilmgandhi 18:6a4db94011d3 14695 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
sahilmgandhi 18:6a4db94011d3 14696
sahilmgandhi 18:6a4db94011d3 14697 /* Bit 0 : Setting of pins dedicated to NFC functionality */
sahilmgandhi 18:6a4db94011d3 14698 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
sahilmgandhi 18:6a4db94011d3 14699 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
sahilmgandhi 18:6a4db94011d3 14700 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
sahilmgandhi 18:6a4db94011d3 14701 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
sahilmgandhi 18:6a4db94011d3 14702
sahilmgandhi 18:6a4db94011d3 14703
sahilmgandhi 18:6a4db94011d3 14704 /* Peripheral: WDT */
sahilmgandhi 18:6a4db94011d3 14705 /* Description: Watchdog Timer */
sahilmgandhi 18:6a4db94011d3 14706
sahilmgandhi 18:6a4db94011d3 14707 /* Register: WDT_INTENSET */
sahilmgandhi 18:6a4db94011d3 14708 /* Description: Enable interrupt */
sahilmgandhi 18:6a4db94011d3 14709
sahilmgandhi 18:6a4db94011d3 14710 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
sahilmgandhi 18:6a4db94011d3 14711 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 14712 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 14713 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14714 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14715 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
sahilmgandhi 18:6a4db94011d3 14716
sahilmgandhi 18:6a4db94011d3 14717 /* Register: WDT_INTENCLR */
sahilmgandhi 18:6a4db94011d3 14718 /* Description: Disable interrupt */
sahilmgandhi 18:6a4db94011d3 14719
sahilmgandhi 18:6a4db94011d3 14720 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
sahilmgandhi 18:6a4db94011d3 14721 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 14722 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 14723 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
sahilmgandhi 18:6a4db94011d3 14724 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
sahilmgandhi 18:6a4db94011d3 14725 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
sahilmgandhi 18:6a4db94011d3 14726
sahilmgandhi 18:6a4db94011d3 14727 /* Register: WDT_RUNSTATUS */
sahilmgandhi 18:6a4db94011d3 14728 /* Description: Run status */
sahilmgandhi 18:6a4db94011d3 14729
sahilmgandhi 18:6a4db94011d3 14730 /* Bit 0 : Indicates whether or not the watchdog is running */
sahilmgandhi 18:6a4db94011d3 14731 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
sahilmgandhi 18:6a4db94011d3 14732 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
sahilmgandhi 18:6a4db94011d3 14733 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
sahilmgandhi 18:6a4db94011d3 14734 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
sahilmgandhi 18:6a4db94011d3 14735
sahilmgandhi 18:6a4db94011d3 14736 /* Register: WDT_REQSTATUS */
sahilmgandhi 18:6a4db94011d3 14737 /* Description: Request status */
sahilmgandhi 18:6a4db94011d3 14738
sahilmgandhi 18:6a4db94011d3 14739 /* Bit 7 : Request status for RR[7] register */
sahilmgandhi 18:6a4db94011d3 14740 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
sahilmgandhi 18:6a4db94011d3 14741 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
sahilmgandhi 18:6a4db94011d3 14742 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14743 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14744
sahilmgandhi 18:6a4db94011d3 14745 /* Bit 6 : Request status for RR[6] register */
sahilmgandhi 18:6a4db94011d3 14746 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
sahilmgandhi 18:6a4db94011d3 14747 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
sahilmgandhi 18:6a4db94011d3 14748 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14749 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14750
sahilmgandhi 18:6a4db94011d3 14751 /* Bit 5 : Request status for RR[5] register */
sahilmgandhi 18:6a4db94011d3 14752 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
sahilmgandhi 18:6a4db94011d3 14753 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
sahilmgandhi 18:6a4db94011d3 14754 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14755 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14756
sahilmgandhi 18:6a4db94011d3 14757 /* Bit 4 : Request status for RR[4] register */
sahilmgandhi 18:6a4db94011d3 14758 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
sahilmgandhi 18:6a4db94011d3 14759 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
sahilmgandhi 18:6a4db94011d3 14760 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14761 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14762
sahilmgandhi 18:6a4db94011d3 14763 /* Bit 3 : Request status for RR[3] register */
sahilmgandhi 18:6a4db94011d3 14764 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
sahilmgandhi 18:6a4db94011d3 14765 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
sahilmgandhi 18:6a4db94011d3 14766 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14767 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14768
sahilmgandhi 18:6a4db94011d3 14769 /* Bit 2 : Request status for RR[2] register */
sahilmgandhi 18:6a4db94011d3 14770 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
sahilmgandhi 18:6a4db94011d3 14771 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
sahilmgandhi 18:6a4db94011d3 14772 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14773 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14774
sahilmgandhi 18:6a4db94011d3 14775 /* Bit 1 : Request status for RR[1] register */
sahilmgandhi 18:6a4db94011d3 14776 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
sahilmgandhi 18:6a4db94011d3 14777 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
sahilmgandhi 18:6a4db94011d3 14778 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14779 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14780
sahilmgandhi 18:6a4db94011d3 14781 /* Bit 0 : Request status for RR[0] register */
sahilmgandhi 18:6a4db94011d3 14782 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
sahilmgandhi 18:6a4db94011d3 14783 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
sahilmgandhi 18:6a4db94011d3 14784 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
sahilmgandhi 18:6a4db94011d3 14785 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
sahilmgandhi 18:6a4db94011d3 14786
sahilmgandhi 18:6a4db94011d3 14787 /* Register: WDT_CRV */
sahilmgandhi 18:6a4db94011d3 14788 /* Description: Counter reload value */
sahilmgandhi 18:6a4db94011d3 14789
sahilmgandhi 18:6a4db94011d3 14790 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
sahilmgandhi 18:6a4db94011d3 14791 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
sahilmgandhi 18:6a4db94011d3 14792 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
sahilmgandhi 18:6a4db94011d3 14793
sahilmgandhi 18:6a4db94011d3 14794 /* Register: WDT_RREN */
sahilmgandhi 18:6a4db94011d3 14795 /* Description: Enable register for reload request registers */
sahilmgandhi 18:6a4db94011d3 14796
sahilmgandhi 18:6a4db94011d3 14797 /* Bit 7 : Enable or disable RR[7] register */
sahilmgandhi 18:6a4db94011d3 14798 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
sahilmgandhi 18:6a4db94011d3 14799 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
sahilmgandhi 18:6a4db94011d3 14800 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
sahilmgandhi 18:6a4db94011d3 14801 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
sahilmgandhi 18:6a4db94011d3 14802
sahilmgandhi 18:6a4db94011d3 14803 /* Bit 6 : Enable or disable RR[6] register */
sahilmgandhi 18:6a4db94011d3 14804 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
sahilmgandhi 18:6a4db94011d3 14805 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
sahilmgandhi 18:6a4db94011d3 14806 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
sahilmgandhi 18:6a4db94011d3 14807 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
sahilmgandhi 18:6a4db94011d3 14808
sahilmgandhi 18:6a4db94011d3 14809 /* Bit 5 : Enable or disable RR[5] register */
sahilmgandhi 18:6a4db94011d3 14810 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
sahilmgandhi 18:6a4db94011d3 14811 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
sahilmgandhi 18:6a4db94011d3 14812 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
sahilmgandhi 18:6a4db94011d3 14813 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
sahilmgandhi 18:6a4db94011d3 14814
sahilmgandhi 18:6a4db94011d3 14815 /* Bit 4 : Enable or disable RR[4] register */
sahilmgandhi 18:6a4db94011d3 14816 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
sahilmgandhi 18:6a4db94011d3 14817 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
sahilmgandhi 18:6a4db94011d3 14818 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
sahilmgandhi 18:6a4db94011d3 14819 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
sahilmgandhi 18:6a4db94011d3 14820
sahilmgandhi 18:6a4db94011d3 14821 /* Bit 3 : Enable or disable RR[3] register */
sahilmgandhi 18:6a4db94011d3 14822 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
sahilmgandhi 18:6a4db94011d3 14823 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
sahilmgandhi 18:6a4db94011d3 14824 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
sahilmgandhi 18:6a4db94011d3 14825 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
sahilmgandhi 18:6a4db94011d3 14826
sahilmgandhi 18:6a4db94011d3 14827 /* Bit 2 : Enable or disable RR[2] register */
sahilmgandhi 18:6a4db94011d3 14828 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
sahilmgandhi 18:6a4db94011d3 14829 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
sahilmgandhi 18:6a4db94011d3 14830 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
sahilmgandhi 18:6a4db94011d3 14831 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
sahilmgandhi 18:6a4db94011d3 14832
sahilmgandhi 18:6a4db94011d3 14833 /* Bit 1 : Enable or disable RR[1] register */
sahilmgandhi 18:6a4db94011d3 14834 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
sahilmgandhi 18:6a4db94011d3 14835 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
sahilmgandhi 18:6a4db94011d3 14836 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
sahilmgandhi 18:6a4db94011d3 14837 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
sahilmgandhi 18:6a4db94011d3 14838
sahilmgandhi 18:6a4db94011d3 14839 /* Bit 0 : Enable or disable RR[0] register */
sahilmgandhi 18:6a4db94011d3 14840 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
sahilmgandhi 18:6a4db94011d3 14841 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
sahilmgandhi 18:6a4db94011d3 14842 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
sahilmgandhi 18:6a4db94011d3 14843 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
sahilmgandhi 18:6a4db94011d3 14844
sahilmgandhi 18:6a4db94011d3 14845 /* Register: WDT_CONFIG */
sahilmgandhi 18:6a4db94011d3 14846 /* Description: Configuration register */
sahilmgandhi 18:6a4db94011d3 14847
sahilmgandhi 18:6a4db94011d3 14848 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
sahilmgandhi 18:6a4db94011d3 14849 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
sahilmgandhi 18:6a4db94011d3 14850 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
sahilmgandhi 18:6a4db94011d3 14851 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
sahilmgandhi 18:6a4db94011d3 14852 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
sahilmgandhi 18:6a4db94011d3 14853
sahilmgandhi 18:6a4db94011d3 14854 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
sahilmgandhi 18:6a4db94011d3 14855 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
sahilmgandhi 18:6a4db94011d3 14856 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
sahilmgandhi 18:6a4db94011d3 14857 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
sahilmgandhi 18:6a4db94011d3 14858 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
sahilmgandhi 18:6a4db94011d3 14859
sahilmgandhi 18:6a4db94011d3 14860 /* Register: WDT_RR */
sahilmgandhi 18:6a4db94011d3 14861 /* Description: Description collection[0]: Reload request 0 */
sahilmgandhi 18:6a4db94011d3 14862
sahilmgandhi 18:6a4db94011d3 14863 /* Bits 31..0 : Reload request register */
sahilmgandhi 18:6a4db94011d3 14864 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
sahilmgandhi 18:6a4db94011d3 14865 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
sahilmgandhi 18:6a4db94011d3 14866 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
sahilmgandhi 18:6a4db94011d3 14867
sahilmgandhi 18:6a4db94011d3 14868
sahilmgandhi 18:6a4db94011d3 14869 /*lint --flb "Leave library region" */
sahilmgandhi 18:6a4db94011d3 14870 #endif