MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 3 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 6 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * 1. Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 9 * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 12 * integrated circuit in a product or a software update for such product, must reproduce
sahilmgandhi 18:6a4db94011d3 13 * the above copyright notice, this list of conditions and the following disclaimer in
sahilmgandhi 18:6a4db94011d3 14 * the documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
sahilmgandhi 18:6a4db94011d3 17 * used to endorse or promote products derived from this software without specific prior
sahilmgandhi 18:6a4db94011d3 18 * written permission.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * 4. This software, with or without modification, must only be used with a
sahilmgandhi 18:6a4db94011d3 21 * Nordic Semiconductor ASA integrated circuit.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * 5. Any software provided in binary or object form under this license must not be reverse
sahilmgandhi 18:6a4db94011d3 24 * engineered, decompiled, modified and/or disassembled.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 36 *
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 #ifndef __NRF51_BITS_H
sahilmgandhi 18:6a4db94011d3 40 #define __NRF51_BITS_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /*lint ++flb "Enter library region" */
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /* Peripheral: AAR */
sahilmgandhi 18:6a4db94011d3 45 /* Description: Accelerated Address Resolver. */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /* Register: AAR_INTENSET */
sahilmgandhi 18:6a4db94011d3 48 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
sahilmgandhi 18:6a4db94011d3 51 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 52 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 53 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 54 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 55 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Bit 1 : Enable interrupt on RESOLVED event. */
sahilmgandhi 18:6a4db94011d3 58 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 59 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 60 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 61 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 62 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /* Bit 0 : Enable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 65 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 66 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 67 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 68 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 69 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /* Register: AAR_INTENCLR */
sahilmgandhi 18:6a4db94011d3 72 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
sahilmgandhi 18:6a4db94011d3 75 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 76 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
sahilmgandhi 18:6a4db94011d3 77 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 78 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 79 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /* Bit 1 : Disable interrupt on RESOLVED event. */
sahilmgandhi 18:6a4db94011d3 82 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 83 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
sahilmgandhi 18:6a4db94011d3 84 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 85 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 86 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
sahilmgandhi 18:6a4db94011d3 89 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 90 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 91 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 92 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 93 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /* Register: AAR_STATUS */
sahilmgandhi 18:6a4db94011d3 96 /* Description: Resolution status. */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /* Bits 3..0 : The IRK used last time an address was resolved. */
sahilmgandhi 18:6a4db94011d3 99 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 100 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /* Register: AAR_ENABLE */
sahilmgandhi 18:6a4db94011d3 103 /* Description: Enable AAR. */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /* Bits 1..0 : Enable AAR. */
sahilmgandhi 18:6a4db94011d3 106 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 107 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 108 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
sahilmgandhi 18:6a4db94011d3 109 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /* Register: AAR_NIRK */
sahilmgandhi 18:6a4db94011d3 112 /* Description: Number of Identity root Keys in the IRK data structure. */
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
sahilmgandhi 18:6a4db94011d3 115 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
sahilmgandhi 18:6a4db94011d3 116 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* Register: AAR_POWER */
sahilmgandhi 18:6a4db94011d3 119 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 122 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 123 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 124 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 125 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* Peripheral: ADC */
sahilmgandhi 18:6a4db94011d3 129 /* Description: Analog to digital converter. */
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /* Register: ADC_INTENSET */
sahilmgandhi 18:6a4db94011d3 132 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 /* Bit 0 : Enable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 135 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 136 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 137 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 138 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 139 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /* Register: ADC_INTENCLR */
sahilmgandhi 18:6a4db94011d3 142 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /* Bit 0 : Disable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 145 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 146 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 147 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 148 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 149 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* Register: ADC_BUSY */
sahilmgandhi 18:6a4db94011d3 152 /* Description: ADC busy register. */
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /* Bit 0 : ADC busy register. */
sahilmgandhi 18:6a4db94011d3 155 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
sahilmgandhi 18:6a4db94011d3 156 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
sahilmgandhi 18:6a4db94011d3 157 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
sahilmgandhi 18:6a4db94011d3 158 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /* Register: ADC_ENABLE */
sahilmgandhi 18:6a4db94011d3 161 /* Description: ADC enable. */
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /* Bits 1..0 : ADC enable. */
sahilmgandhi 18:6a4db94011d3 164 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 165 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 166 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
sahilmgandhi 18:6a4db94011d3 167 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 /* Register: ADC_CONFIG */
sahilmgandhi 18:6a4db94011d3 170 /* Description: ADC configuration register. */
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /* Bits 17..16 : ADC external reference pin selection. */
sahilmgandhi 18:6a4db94011d3 173 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 174 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 175 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
sahilmgandhi 18:6a4db94011d3 176 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
sahilmgandhi 18:6a4db94011d3 177 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /* Bits 15..8 : ADC analog pin selection. */
sahilmgandhi 18:6a4db94011d3 180 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
sahilmgandhi 18:6a4db94011d3 181 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
sahilmgandhi 18:6a4db94011d3 182 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
sahilmgandhi 18:6a4db94011d3 183 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
sahilmgandhi 18:6a4db94011d3 184 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
sahilmgandhi 18:6a4db94011d3 185 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
sahilmgandhi 18:6a4db94011d3 186 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
sahilmgandhi 18:6a4db94011d3 187 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
sahilmgandhi 18:6a4db94011d3 188 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
sahilmgandhi 18:6a4db94011d3 189 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
sahilmgandhi 18:6a4db94011d3 190 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /* Bits 6..5 : ADC reference selection. */
sahilmgandhi 18:6a4db94011d3 193 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 194 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 195 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
sahilmgandhi 18:6a4db94011d3 196 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
sahilmgandhi 18:6a4db94011d3 197 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
sahilmgandhi 18:6a4db94011d3 198 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /* Bits 4..2 : ADC input selection. */
sahilmgandhi 18:6a4db94011d3 201 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
sahilmgandhi 18:6a4db94011d3 202 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
sahilmgandhi 18:6a4db94011d3 203 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
sahilmgandhi 18:6a4db94011d3 204 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
sahilmgandhi 18:6a4db94011d3 205 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
sahilmgandhi 18:6a4db94011d3 206 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
sahilmgandhi 18:6a4db94011d3 207 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* Bits 1..0 : ADC resolution. */
sahilmgandhi 18:6a4db94011d3 210 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
sahilmgandhi 18:6a4db94011d3 211 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
sahilmgandhi 18:6a4db94011d3 212 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
sahilmgandhi 18:6a4db94011d3 213 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
sahilmgandhi 18:6a4db94011d3 214 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /* Register: ADC_RESULT */
sahilmgandhi 18:6a4db94011d3 217 /* Description: Result of ADC conversion. */
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /* Bits 9..0 : Result of ADC conversion. */
sahilmgandhi 18:6a4db94011d3 220 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
sahilmgandhi 18:6a4db94011d3 221 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /* Register: ADC_POWER */
sahilmgandhi 18:6a4db94011d3 224 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 227 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 228 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 229 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 230 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /* Peripheral: AMLI */
sahilmgandhi 18:6a4db94011d3 234 /* Description: AHB Multi-Layer Interface. */
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /* Register: AMLI_RAMPRI_CPU0 */
sahilmgandhi 18:6a4db94011d3 237 /* Description: Configurable priority configuration register for CPU0. */
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 /* Bits 31..28 : Configuration field for RAM block 7. */
sahilmgandhi 18:6a4db94011d3 240 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 241 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 242 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 243 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 244 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 245 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 246 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 247 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 248 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 249 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Bits 27..24 : Configuration field for RAM block 6. */
sahilmgandhi 18:6a4db94011d3 252 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 253 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 254 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 255 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 256 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 257 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 258 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 259 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 260 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 261 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /* Bits 23..20 : Configuration field for RAM block 5. */
sahilmgandhi 18:6a4db94011d3 264 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 265 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 266 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 267 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 268 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 269 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 270 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 271 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 272 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 273 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /* Bits 19..16 : Configuration field for RAM block 4. */
sahilmgandhi 18:6a4db94011d3 276 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 277 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 278 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 279 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 280 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 281 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 282 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 283 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 284 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 285 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /* Bits 15..12 : Configuration field for RAM block 3. */
sahilmgandhi 18:6a4db94011d3 288 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 289 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 290 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 291 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 292 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 293 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 294 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 295 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 296 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 297 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 /* Bits 11..8 : Configuration field for RAM block 2. */
sahilmgandhi 18:6a4db94011d3 300 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 301 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 302 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 303 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 304 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 305 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 306 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 307 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 308 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 309 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /* Bits 7..4 : Configuration field for RAM block 1. */
sahilmgandhi 18:6a4db94011d3 312 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 313 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 314 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 315 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 316 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 317 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 318 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 319 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 320 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 321 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /* Bits 3..0 : Configuration field for RAM block 0. */
sahilmgandhi 18:6a4db94011d3 324 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 325 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 326 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 327 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 328 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 329 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 330 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 331 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 332 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 333 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /* Register: AMLI_RAMPRI_SPIS1 */
sahilmgandhi 18:6a4db94011d3 336 /* Description: Configurable priority configuration register for SPIS1. */
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /* Bits 31..28 : Configuration field for RAM block 7. */
sahilmgandhi 18:6a4db94011d3 339 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 340 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 342 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 343 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 344 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 345 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 346 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 347 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 348 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /* Bits 27..24 : Configuration field for RAM block 6. */
sahilmgandhi 18:6a4db94011d3 351 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 352 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 354 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 355 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 356 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 357 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 358 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 359 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 360 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 /* Bits 23..20 : Configuration field for RAM block 5. */
sahilmgandhi 18:6a4db94011d3 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 364 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 368 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 369 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 370 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 371 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 372 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 /* Bits 19..16 : Configuration field for RAM block 4. */
sahilmgandhi 18:6a4db94011d3 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 376 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 380 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 381 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 382 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 383 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 384 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /* Bits 15..12 : Configuration field for RAM block 3. */
sahilmgandhi 18:6a4db94011d3 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 388 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 391 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /* Bits 11..8 : Configuration field for RAM block 2. */
sahilmgandhi 18:6a4db94011d3 399 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 400 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 402 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 403 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 404 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 405 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 406 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 407 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 408 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /* Bits 7..4 : Configuration field for RAM block 1. */
sahilmgandhi 18:6a4db94011d3 411 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 412 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 414 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 415 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 416 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 417 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 418 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 419 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 420 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 /* Bits 3..0 : Configuration field for RAM block 0. */
sahilmgandhi 18:6a4db94011d3 423 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 424 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 426 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 427 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 428 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 429 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 430 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 431 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 432 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /* Register: AMLI_RAMPRI_RADIO */
sahilmgandhi 18:6a4db94011d3 435 /* Description: Configurable priority configuration register for RADIO. */
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /* Bits 31..28 : Configuration field for RAM block 7. */
sahilmgandhi 18:6a4db94011d3 438 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 439 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 440 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 441 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 442 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 443 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 444 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 445 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 446 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 447 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /* Bits 27..24 : Configuration field for RAM block 6. */
sahilmgandhi 18:6a4db94011d3 450 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 451 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 452 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 453 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 454 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 455 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 456 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 457 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 458 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 459 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* Bits 23..20 : Configuration field for RAM block 5. */
sahilmgandhi 18:6a4db94011d3 462 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 463 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 464 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 465 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 466 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 467 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 468 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 469 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 470 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 471 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 /* Bits 19..16 : Configuration field for RAM block 4. */
sahilmgandhi 18:6a4db94011d3 474 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 475 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 476 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 477 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 478 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 479 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 480 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 481 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 482 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 483 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 /* Bits 15..12 : Configuration field for RAM block 3. */
sahilmgandhi 18:6a4db94011d3 486 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 487 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 488 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 489 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 490 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 491 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 492 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 493 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 494 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 495 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /* Bits 11..8 : Configuration field for RAM block 2. */
sahilmgandhi 18:6a4db94011d3 498 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 499 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 500 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 501 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 502 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 503 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 504 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 505 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 506 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 507 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 /* Bits 7..4 : Configuration field for RAM block 1. */
sahilmgandhi 18:6a4db94011d3 510 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 511 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 512 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 513 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 514 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 515 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 516 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 517 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 518 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 519 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 /* Bits 3..0 : Configuration field for RAM block 0. */
sahilmgandhi 18:6a4db94011d3 522 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 523 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 524 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 525 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 526 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 527 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 528 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 529 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 530 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 531 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 /* Register: AMLI_RAMPRI_ECB */
sahilmgandhi 18:6a4db94011d3 534 /* Description: Configurable priority configuration register for ECB. */
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 /* Bits 31..28 : Configuration field for RAM block 7. */
sahilmgandhi 18:6a4db94011d3 537 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 538 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 539 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 540 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 541 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 542 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 543 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 544 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 545 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 546 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 /* Bits 27..24 : Configuration field for RAM block 6. */
sahilmgandhi 18:6a4db94011d3 549 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 550 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 551 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 552 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 553 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 554 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 555 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 556 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 557 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 558 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /* Bits 23..20 : Configuration field for RAM block 5. */
sahilmgandhi 18:6a4db94011d3 561 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 562 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 563 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 564 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 565 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 566 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 567 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 568 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 569 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 570 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /* Bits 19..16 : Configuration field for RAM block 4. */
sahilmgandhi 18:6a4db94011d3 573 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 574 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 575 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 576 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 577 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 578 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 579 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 580 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 581 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 582 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 /* Bits 15..12 : Configuration field for RAM block 3. */
sahilmgandhi 18:6a4db94011d3 585 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 586 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 587 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 588 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 589 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 590 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 591 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 592 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 593 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 594 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 /* Bits 11..8 : Configuration field for RAM block 2. */
sahilmgandhi 18:6a4db94011d3 597 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 598 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 599 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 600 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 601 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 602 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 603 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 604 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 605 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 606 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Bits 7..4 : Configuration field for RAM block 1. */
sahilmgandhi 18:6a4db94011d3 609 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 610 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 611 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 612 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 613 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 614 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 615 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 616 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 617 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 618 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /* Bits 3..0 : Configuration field for RAM block 0. */
sahilmgandhi 18:6a4db94011d3 621 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 622 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 623 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 624 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 625 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 626 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 627 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 628 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 629 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 630 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632 /* Register: AMLI_RAMPRI_CCM */
sahilmgandhi 18:6a4db94011d3 633 /* Description: Configurable priority configuration register for CCM. */
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /* Bits 31..28 : Configuration field for RAM block 7. */
sahilmgandhi 18:6a4db94011d3 636 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 637 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 638 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 639 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 640 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 641 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 642 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 643 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 644 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 645 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 /* Bits 27..24 : Configuration field for RAM block 6. */
sahilmgandhi 18:6a4db94011d3 648 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 649 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 650 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 651 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 652 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 653 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 654 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 655 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 656 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 657 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 /* Bits 23..20 : Configuration field for RAM block 5. */
sahilmgandhi 18:6a4db94011d3 660 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 661 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 662 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 663 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 664 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 665 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 666 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 667 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 668 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 669 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 /* Bits 19..16 : Configuration field for RAM block 4. */
sahilmgandhi 18:6a4db94011d3 672 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 673 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 674 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 675 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 676 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 677 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 678 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 679 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 680 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 681 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 /* Bits 15..12 : Configuration field for RAM block 3. */
sahilmgandhi 18:6a4db94011d3 684 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 685 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 686 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 687 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 688 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 689 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 690 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 691 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 692 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 693 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 /* Bits 11..8 : Configuration field for RAM block 2. */
sahilmgandhi 18:6a4db94011d3 696 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 697 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 698 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 699 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 700 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 701 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 702 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 703 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 704 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 705 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 /* Bits 7..4 : Configuration field for RAM block 1. */
sahilmgandhi 18:6a4db94011d3 708 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 709 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 710 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 711 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 712 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 713 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 714 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 715 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 716 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 717 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 718
sahilmgandhi 18:6a4db94011d3 719 /* Bits 3..0 : Configuration field for RAM block 0. */
sahilmgandhi 18:6a4db94011d3 720 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 721 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 722 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 723 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 724 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 725 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 726 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 727 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 728 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 729 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 /* Register: AMLI_RAMPRI_AAR */
sahilmgandhi 18:6a4db94011d3 732 /* Description: Configurable priority configuration register for AAR. */
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734 /* Bits 31..28 : Configuration field for RAM block 7. */
sahilmgandhi 18:6a4db94011d3 735 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 736 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
sahilmgandhi 18:6a4db94011d3 737 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 738 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 739 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 740 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 741 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 742 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 743 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 744 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 /* Bits 27..24 : Configuration field for RAM block 6. */
sahilmgandhi 18:6a4db94011d3 747 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 748 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
sahilmgandhi 18:6a4db94011d3 749 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 750 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 751 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 752 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 753 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 754 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 755 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 756 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 /* Bits 23..20 : Configuration field for RAM block 5. */
sahilmgandhi 18:6a4db94011d3 759 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 760 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
sahilmgandhi 18:6a4db94011d3 761 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 762 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 763 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 764 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 765 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 766 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 767 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 768 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /* Bits 19..16 : Configuration field for RAM block 4. */
sahilmgandhi 18:6a4db94011d3 771 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 772 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
sahilmgandhi 18:6a4db94011d3 773 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 774 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 775 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 776 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 777 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 778 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 779 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 780 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782 /* Bits 15..12 : Configuration field for RAM block 3. */
sahilmgandhi 18:6a4db94011d3 783 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 784 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
sahilmgandhi 18:6a4db94011d3 785 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 786 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 787 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 788 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 789 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 790 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 791 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 792 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 /* Bits 11..8 : Configuration field for RAM block 2. */
sahilmgandhi 18:6a4db94011d3 795 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 796 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
sahilmgandhi 18:6a4db94011d3 797 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 798 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 799 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 800 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 801 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 802 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 803 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 804 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 /* Bits 7..4 : Configuration field for RAM block 1. */
sahilmgandhi 18:6a4db94011d3 807 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 808 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
sahilmgandhi 18:6a4db94011d3 809 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 810 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 811 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 812 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 813 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 814 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 815 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 816 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /* Bits 3..0 : Configuration field for RAM block 0. */
sahilmgandhi 18:6a4db94011d3 819 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 820 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
sahilmgandhi 18:6a4db94011d3 821 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
sahilmgandhi 18:6a4db94011d3 822 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
sahilmgandhi 18:6a4db94011d3 823 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
sahilmgandhi 18:6a4db94011d3 824 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
sahilmgandhi 18:6a4db94011d3 825 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
sahilmgandhi 18:6a4db94011d3 826 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
sahilmgandhi 18:6a4db94011d3 827 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
sahilmgandhi 18:6a4db94011d3 828 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
sahilmgandhi 18:6a4db94011d3 829
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 /* Peripheral: CCM */
sahilmgandhi 18:6a4db94011d3 832 /* Description: AES CCM Mode Encryption. */
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 /* Register: CCM_SHORTS */
sahilmgandhi 18:6a4db94011d3 835 /* Description: Shortcuts for the CCM. */
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
sahilmgandhi 18:6a4db94011d3 838 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
sahilmgandhi 18:6a4db94011d3 839 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
sahilmgandhi 18:6a4db94011d3 840 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 841 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 /* Register: CCM_INTENSET */
sahilmgandhi 18:6a4db94011d3 844 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 /* Bit 2 : Enable interrupt on ERROR event. */
sahilmgandhi 18:6a4db94011d3 847 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 848 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 849 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 850 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 851 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
sahilmgandhi 18:6a4db94011d3 854 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 855 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 856 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 857 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 858 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
sahilmgandhi 18:6a4db94011d3 861 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 862 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 863 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 864 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 865 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 866
sahilmgandhi 18:6a4db94011d3 867 /* Register: CCM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 868 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 /* Bit 2 : Disable interrupt on ERROR event. */
sahilmgandhi 18:6a4db94011d3 871 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 872 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 873 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 874 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 875 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 876
sahilmgandhi 18:6a4db94011d3 877 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
sahilmgandhi 18:6a4db94011d3 878 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 879 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
sahilmgandhi 18:6a4db94011d3 880 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 881 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 882 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
sahilmgandhi 18:6a4db94011d3 885 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 886 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
sahilmgandhi 18:6a4db94011d3 887 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 888 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 889 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 890
sahilmgandhi 18:6a4db94011d3 891 /* Register: CCM_MICSTATUS */
sahilmgandhi 18:6a4db94011d3 892 /* Description: CCM RX MIC check result. */
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
sahilmgandhi 18:6a4db94011d3 895 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
sahilmgandhi 18:6a4db94011d3 896 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
sahilmgandhi 18:6a4db94011d3 897 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
sahilmgandhi 18:6a4db94011d3 898 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
sahilmgandhi 18:6a4db94011d3 899
sahilmgandhi 18:6a4db94011d3 900 /* Register: CCM_ENABLE */
sahilmgandhi 18:6a4db94011d3 901 /* Description: CCM enable. */
sahilmgandhi 18:6a4db94011d3 902
sahilmgandhi 18:6a4db94011d3 903 /* Bits 1..0 : CCM enable. */
sahilmgandhi 18:6a4db94011d3 904 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 905 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 906 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
sahilmgandhi 18:6a4db94011d3 907 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
sahilmgandhi 18:6a4db94011d3 908
sahilmgandhi 18:6a4db94011d3 909 /* Register: CCM_MODE */
sahilmgandhi 18:6a4db94011d3 910 /* Description: Operation mode. */
sahilmgandhi 18:6a4db94011d3 911
sahilmgandhi 18:6a4db94011d3 912 /* Bit 0 : CCM mode operation. */
sahilmgandhi 18:6a4db94011d3 913 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 914 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 915 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
sahilmgandhi 18:6a4db94011d3 916 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918 /* Register: CCM_POWER */
sahilmgandhi 18:6a4db94011d3 919 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 920
sahilmgandhi 18:6a4db94011d3 921 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 922 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 923 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 924 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 925 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927
sahilmgandhi 18:6a4db94011d3 928 /* Peripheral: CLOCK */
sahilmgandhi 18:6a4db94011d3 929 /* Description: Clock control. */
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 /* Register: CLOCK_INTENSET */
sahilmgandhi 18:6a4db94011d3 932 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 /* Bit 4 : Enable interrupt on CTTO event. */
sahilmgandhi 18:6a4db94011d3 935 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
sahilmgandhi 18:6a4db94011d3 936 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
sahilmgandhi 18:6a4db94011d3 937 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 938 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 939 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 940
sahilmgandhi 18:6a4db94011d3 941 /* Bit 3 : Enable interrupt on DONE event. */
sahilmgandhi 18:6a4db94011d3 942 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 943 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 944 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 945 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 946 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 947
sahilmgandhi 18:6a4db94011d3 948 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
sahilmgandhi 18:6a4db94011d3 949 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 950 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 951 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 952 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 953 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
sahilmgandhi 18:6a4db94011d3 956 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 957 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 958 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 959 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 960 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 961
sahilmgandhi 18:6a4db94011d3 962 /* Register: CLOCK_INTENCLR */
sahilmgandhi 18:6a4db94011d3 963 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 964
sahilmgandhi 18:6a4db94011d3 965 /* Bit 4 : Disable interrupt on CTTO event. */
sahilmgandhi 18:6a4db94011d3 966 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
sahilmgandhi 18:6a4db94011d3 967 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
sahilmgandhi 18:6a4db94011d3 968 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 969 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 970 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 971
sahilmgandhi 18:6a4db94011d3 972 /* Bit 3 : Disable interrupt on DONE event. */
sahilmgandhi 18:6a4db94011d3 973 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
sahilmgandhi 18:6a4db94011d3 974 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
sahilmgandhi 18:6a4db94011d3 975 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 976 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 977 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 978
sahilmgandhi 18:6a4db94011d3 979 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
sahilmgandhi 18:6a4db94011d3 980 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 981 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 982 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 983 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 984 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
sahilmgandhi 18:6a4db94011d3 987 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 988 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
sahilmgandhi 18:6a4db94011d3 989 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 990 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 991 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 /* Register: CLOCK_HFCLKRUN */
sahilmgandhi 18:6a4db94011d3 994 /* Description: Task HFCLKSTART trigger status. */
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 /* Bit 0 : Task HFCLKSTART trigger status. */
sahilmgandhi 18:6a4db94011d3 997 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 998 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 999 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
sahilmgandhi 18:6a4db94011d3 1000 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 /* Register: CLOCK_HFCLKSTAT */
sahilmgandhi 18:6a4db94011d3 1003 /* Description: High frequency clock status. */
sahilmgandhi 18:6a4db94011d3 1004
sahilmgandhi 18:6a4db94011d3 1005 /* Bit 16 : State for the HFCLK. */
sahilmgandhi 18:6a4db94011d3 1006 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
sahilmgandhi 18:6a4db94011d3 1007 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
sahilmgandhi 18:6a4db94011d3 1008 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
sahilmgandhi 18:6a4db94011d3 1009 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
sahilmgandhi 18:6a4db94011d3 1010
sahilmgandhi 18:6a4db94011d3 1011 /* Bit 0 : Active clock source for the HF clock. */
sahilmgandhi 18:6a4db94011d3 1012 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 1013 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 1014 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
sahilmgandhi 18:6a4db94011d3 1015 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 /* Register: CLOCK_LFCLKRUN */
sahilmgandhi 18:6a4db94011d3 1018 /* Description: Task LFCLKSTART triggered status. */
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 /* Bit 0 : Task LFCLKSTART triggered status. */
sahilmgandhi 18:6a4db94011d3 1021 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
sahilmgandhi 18:6a4db94011d3 1022 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
sahilmgandhi 18:6a4db94011d3 1023 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
sahilmgandhi 18:6a4db94011d3 1024 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
sahilmgandhi 18:6a4db94011d3 1025
sahilmgandhi 18:6a4db94011d3 1026 /* Register: CLOCK_LFCLKSTAT */
sahilmgandhi 18:6a4db94011d3 1027 /* Description: Low frequency clock status. */
sahilmgandhi 18:6a4db94011d3 1028
sahilmgandhi 18:6a4db94011d3 1029 /* Bit 16 : State for the LF clock. */
sahilmgandhi 18:6a4db94011d3 1030 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
sahilmgandhi 18:6a4db94011d3 1031 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
sahilmgandhi 18:6a4db94011d3 1032 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
sahilmgandhi 18:6a4db94011d3 1033 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 /* Bits 1..0 : Active clock source for the LF clock. */
sahilmgandhi 18:6a4db94011d3 1036 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 1037 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 1038 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
sahilmgandhi 18:6a4db94011d3 1039 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
sahilmgandhi 18:6a4db94011d3 1040 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 /* Register: CLOCK_LFCLKSRCCOPY */
sahilmgandhi 18:6a4db94011d3 1043 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
sahilmgandhi 18:6a4db94011d3 1046 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 1047 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 1048 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
sahilmgandhi 18:6a4db94011d3 1049 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
sahilmgandhi 18:6a4db94011d3 1050 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 /* Register: CLOCK_LFCLKSRC */
sahilmgandhi 18:6a4db94011d3 1053 /* Description: Clock source for the LFCLK clock. */
sahilmgandhi 18:6a4db94011d3 1054
sahilmgandhi 18:6a4db94011d3 1055 /* Bits 1..0 : Clock source. */
sahilmgandhi 18:6a4db94011d3 1056 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
sahilmgandhi 18:6a4db94011d3 1057 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
sahilmgandhi 18:6a4db94011d3 1058 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
sahilmgandhi 18:6a4db94011d3 1059 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
sahilmgandhi 18:6a4db94011d3 1060 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /* Register: CLOCK_CTIV */
sahilmgandhi 18:6a4db94011d3 1063 /* Description: Calibration timer interval. */
sahilmgandhi 18:6a4db94011d3 1064
sahilmgandhi 18:6a4db94011d3 1065 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
sahilmgandhi 18:6a4db94011d3 1066 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
sahilmgandhi 18:6a4db94011d3 1067 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /* Register: CLOCK_XTALFREQ */
sahilmgandhi 18:6a4db94011d3 1070 /* Description: Crystal frequency. */
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /* Bits 7..0 : External Xtal frequency selection. */
sahilmgandhi 18:6a4db94011d3 1073 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
sahilmgandhi 18:6a4db94011d3 1074 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
sahilmgandhi 18:6a4db94011d3 1075 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
sahilmgandhi 18:6a4db94011d3 1076 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078
sahilmgandhi 18:6a4db94011d3 1079 /* Peripheral: ECB */
sahilmgandhi 18:6a4db94011d3 1080 /* Description: AES ECB Mode Encryption. */
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082 /* Register: ECB_INTENSET */
sahilmgandhi 18:6a4db94011d3 1083 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 1084
sahilmgandhi 18:6a4db94011d3 1085 /* Bit 1 : Enable interrupt on ERRORECB event. */
sahilmgandhi 18:6a4db94011d3 1086 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 1087 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 1088 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 1089 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 1090 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 1091
sahilmgandhi 18:6a4db94011d3 1092 /* Bit 0 : Enable interrupt on ENDECB event. */
sahilmgandhi 18:6a4db94011d3 1093 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 1094 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 1095 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 1096 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 1097 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 1098
sahilmgandhi 18:6a4db94011d3 1099 /* Register: ECB_INTENCLR */
sahilmgandhi 18:6a4db94011d3 1100 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 1101
sahilmgandhi 18:6a4db94011d3 1102 /* Bit 1 : Disable interrupt on ERRORECB event. */
sahilmgandhi 18:6a4db94011d3 1103 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 1104 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
sahilmgandhi 18:6a4db94011d3 1105 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 1106 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 1107 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 1108
sahilmgandhi 18:6a4db94011d3 1109 /* Bit 0 : Disable interrupt on ENDECB event. */
sahilmgandhi 18:6a4db94011d3 1110 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 1111 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
sahilmgandhi 18:6a4db94011d3 1112 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 1113 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 1114 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 1115
sahilmgandhi 18:6a4db94011d3 1116 /* Register: ECB_POWER */
sahilmgandhi 18:6a4db94011d3 1117 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 1118
sahilmgandhi 18:6a4db94011d3 1119 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 1120 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 1121 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 1122 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 1123 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125
sahilmgandhi 18:6a4db94011d3 1126 /* Peripheral: FICR */
sahilmgandhi 18:6a4db94011d3 1127 /* Description: Factory Information Configuration. */
sahilmgandhi 18:6a4db94011d3 1128
sahilmgandhi 18:6a4db94011d3 1129 /* Register: FICR_PPFC */
sahilmgandhi 18:6a4db94011d3 1130 /* Description: Pre-programmed factory code present. */
sahilmgandhi 18:6a4db94011d3 1131
sahilmgandhi 18:6a4db94011d3 1132 /* Bits 7..0 : Pre-programmed factory code present. */
sahilmgandhi 18:6a4db94011d3 1133 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
sahilmgandhi 18:6a4db94011d3 1134 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
sahilmgandhi 18:6a4db94011d3 1135 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
sahilmgandhi 18:6a4db94011d3 1136 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
sahilmgandhi 18:6a4db94011d3 1137
sahilmgandhi 18:6a4db94011d3 1138 /* Register: FICR_CONFIGID */
sahilmgandhi 18:6a4db94011d3 1139 /* Description: Configuration identifier. */
sahilmgandhi 18:6a4db94011d3 1140
sahilmgandhi 18:6a4db94011d3 1141 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
sahilmgandhi 18:6a4db94011d3 1142 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
sahilmgandhi 18:6a4db94011d3 1143 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
sahilmgandhi 18:6a4db94011d3 1144
sahilmgandhi 18:6a4db94011d3 1145 /* Bits 15..0 : Hardware Identification Number. */
sahilmgandhi 18:6a4db94011d3 1146 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
sahilmgandhi 18:6a4db94011d3 1147 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
sahilmgandhi 18:6a4db94011d3 1148
sahilmgandhi 18:6a4db94011d3 1149 /* Register: FICR_DEVICEADDRTYPE */
sahilmgandhi 18:6a4db94011d3 1150 /* Description: Device address type. */
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 /* Bit 0 : Device address type. */
sahilmgandhi 18:6a4db94011d3 1153 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
sahilmgandhi 18:6a4db94011d3 1154 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
sahilmgandhi 18:6a4db94011d3 1155 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
sahilmgandhi 18:6a4db94011d3 1156 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 /* Register: FICR_OVERRIDEEN */
sahilmgandhi 18:6a4db94011d3 1159 /* Description: Radio calibration override enable. */
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 /* Bit 3 : Override default values for BLE_1Mbit mode. */
sahilmgandhi 18:6a4db94011d3 1162 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
sahilmgandhi 18:6a4db94011d3 1163 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
sahilmgandhi 18:6a4db94011d3 1164 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
sahilmgandhi 18:6a4db94011d3 1165 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
sahilmgandhi 18:6a4db94011d3 1166
sahilmgandhi 18:6a4db94011d3 1167 /* Bit 0 : Override default values for NRF_1Mbit mode. */
sahilmgandhi 18:6a4db94011d3 1168 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
sahilmgandhi 18:6a4db94011d3 1169 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
sahilmgandhi 18:6a4db94011d3 1170 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
sahilmgandhi 18:6a4db94011d3 1171 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
sahilmgandhi 18:6a4db94011d3 1172
sahilmgandhi 18:6a4db94011d3 1173
sahilmgandhi 18:6a4db94011d3 1174 /* Peripheral: GPIO */
sahilmgandhi 18:6a4db94011d3 1175 /* Description: General purpose input and output. */
sahilmgandhi 18:6a4db94011d3 1176
sahilmgandhi 18:6a4db94011d3 1177 /* Register: GPIO_OUT */
sahilmgandhi 18:6a4db94011d3 1178 /* Description: Write GPIO port. */
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 /* Bit 31 : Pin 31. */
sahilmgandhi 18:6a4db94011d3 1181 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1182 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1183 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1184 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1185
sahilmgandhi 18:6a4db94011d3 1186 /* Bit 30 : Pin 30. */
sahilmgandhi 18:6a4db94011d3 1187 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1188 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1189 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1190 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1191
sahilmgandhi 18:6a4db94011d3 1192 /* Bit 29 : Pin 29. */
sahilmgandhi 18:6a4db94011d3 1193 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1194 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1195 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1196 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198 /* Bit 28 : Pin 28. */
sahilmgandhi 18:6a4db94011d3 1199 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1200 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1201 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1202 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 /* Bit 27 : Pin 27. */
sahilmgandhi 18:6a4db94011d3 1205 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1206 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1207 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1208 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1209
sahilmgandhi 18:6a4db94011d3 1210 /* Bit 26 : Pin 26. */
sahilmgandhi 18:6a4db94011d3 1211 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1212 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1213 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1214 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1215
sahilmgandhi 18:6a4db94011d3 1216 /* Bit 25 : Pin 25. */
sahilmgandhi 18:6a4db94011d3 1217 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1218 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1219 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1220 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 /* Bit 24 : Pin 24. */
sahilmgandhi 18:6a4db94011d3 1223 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1224 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1225 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1226 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1227
sahilmgandhi 18:6a4db94011d3 1228 /* Bit 23 : Pin 23. */
sahilmgandhi 18:6a4db94011d3 1229 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1230 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1231 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1232 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1233
sahilmgandhi 18:6a4db94011d3 1234 /* Bit 22 : Pin 22. */
sahilmgandhi 18:6a4db94011d3 1235 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1236 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1237 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1238 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1239
sahilmgandhi 18:6a4db94011d3 1240 /* Bit 21 : Pin 21. */
sahilmgandhi 18:6a4db94011d3 1241 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1242 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1243 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1244 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1245
sahilmgandhi 18:6a4db94011d3 1246 /* Bit 20 : Pin 20. */
sahilmgandhi 18:6a4db94011d3 1247 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1248 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1249 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1250 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 /* Bit 19 : Pin 19. */
sahilmgandhi 18:6a4db94011d3 1253 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1254 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1255 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1256 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1257
sahilmgandhi 18:6a4db94011d3 1258 /* Bit 18 : Pin 18. */
sahilmgandhi 18:6a4db94011d3 1259 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1260 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1261 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1262 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1263
sahilmgandhi 18:6a4db94011d3 1264 /* Bit 17 : Pin 17. */
sahilmgandhi 18:6a4db94011d3 1265 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1266 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1267 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1268 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1269
sahilmgandhi 18:6a4db94011d3 1270 /* Bit 16 : Pin 16. */
sahilmgandhi 18:6a4db94011d3 1271 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1272 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1273 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1274 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1275
sahilmgandhi 18:6a4db94011d3 1276 /* Bit 15 : Pin 15. */
sahilmgandhi 18:6a4db94011d3 1277 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1278 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1279 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1280 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1281
sahilmgandhi 18:6a4db94011d3 1282 /* Bit 14 : Pin 14. */
sahilmgandhi 18:6a4db94011d3 1283 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1284 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1285 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1286 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1287
sahilmgandhi 18:6a4db94011d3 1288 /* Bit 13 : Pin 13. */
sahilmgandhi 18:6a4db94011d3 1289 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1290 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1291 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1292 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1293
sahilmgandhi 18:6a4db94011d3 1294 /* Bit 12 : Pin 12. */
sahilmgandhi 18:6a4db94011d3 1295 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1296 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1297 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1298 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1299
sahilmgandhi 18:6a4db94011d3 1300 /* Bit 11 : Pin 11. */
sahilmgandhi 18:6a4db94011d3 1301 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1302 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1303 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1304 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1305
sahilmgandhi 18:6a4db94011d3 1306 /* Bit 10 : Pin 10. */
sahilmgandhi 18:6a4db94011d3 1307 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1308 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1309 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1310 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1311
sahilmgandhi 18:6a4db94011d3 1312 /* Bit 9 : Pin 9. */
sahilmgandhi 18:6a4db94011d3 1313 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1314 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1315 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1316 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1317
sahilmgandhi 18:6a4db94011d3 1318 /* Bit 8 : Pin 8. */
sahilmgandhi 18:6a4db94011d3 1319 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1320 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1321 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1322 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1323
sahilmgandhi 18:6a4db94011d3 1324 /* Bit 7 : Pin 7. */
sahilmgandhi 18:6a4db94011d3 1325 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1326 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1327 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1328 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1329
sahilmgandhi 18:6a4db94011d3 1330 /* Bit 6 : Pin 6. */
sahilmgandhi 18:6a4db94011d3 1331 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1332 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1333 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1334 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1335
sahilmgandhi 18:6a4db94011d3 1336 /* Bit 5 : Pin 5. */
sahilmgandhi 18:6a4db94011d3 1337 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1338 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1339 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1340 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1341
sahilmgandhi 18:6a4db94011d3 1342 /* Bit 4 : Pin 4. */
sahilmgandhi 18:6a4db94011d3 1343 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1344 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1345 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1346 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1347
sahilmgandhi 18:6a4db94011d3 1348 /* Bit 3 : Pin 3. */
sahilmgandhi 18:6a4db94011d3 1349 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1350 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1351 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1352 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1353
sahilmgandhi 18:6a4db94011d3 1354 /* Bit 2 : Pin 2. */
sahilmgandhi 18:6a4db94011d3 1355 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 1356 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 1357 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1358 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1359
sahilmgandhi 18:6a4db94011d3 1360 /* Bit 1 : Pin 1. */
sahilmgandhi 18:6a4db94011d3 1361 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 1362 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 1363 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1364 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1365
sahilmgandhi 18:6a4db94011d3 1366 /* Bit 0 : Pin 0. */
sahilmgandhi 18:6a4db94011d3 1367 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 1368 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 1369 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1370 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1371
sahilmgandhi 18:6a4db94011d3 1372 /* Register: GPIO_OUTSET */
sahilmgandhi 18:6a4db94011d3 1373 /* Description: Set individual bits in GPIO port. */
sahilmgandhi 18:6a4db94011d3 1374
sahilmgandhi 18:6a4db94011d3 1375 /* Bit 31 : Pin 31. */
sahilmgandhi 18:6a4db94011d3 1376 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1377 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1378 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1379 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1380 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1381
sahilmgandhi 18:6a4db94011d3 1382 /* Bit 30 : Pin 30. */
sahilmgandhi 18:6a4db94011d3 1383 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1384 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1385 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1386 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1387 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1388
sahilmgandhi 18:6a4db94011d3 1389 /* Bit 29 : Pin 29. */
sahilmgandhi 18:6a4db94011d3 1390 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1391 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1392 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1393 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1394 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1395
sahilmgandhi 18:6a4db94011d3 1396 /* Bit 28 : Pin 28. */
sahilmgandhi 18:6a4db94011d3 1397 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1398 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1399 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1400 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1401 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1402
sahilmgandhi 18:6a4db94011d3 1403 /* Bit 27 : Pin 27. */
sahilmgandhi 18:6a4db94011d3 1404 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1405 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1406 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1407 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1408 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1409
sahilmgandhi 18:6a4db94011d3 1410 /* Bit 26 : Pin 26. */
sahilmgandhi 18:6a4db94011d3 1411 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1412 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1413 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1414 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1415 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1416
sahilmgandhi 18:6a4db94011d3 1417 /* Bit 25 : Pin 25. */
sahilmgandhi 18:6a4db94011d3 1418 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1419 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1420 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1421 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1422 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1423
sahilmgandhi 18:6a4db94011d3 1424 /* Bit 24 : Pin 24. */
sahilmgandhi 18:6a4db94011d3 1425 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1426 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1427 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1428 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1429 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1430
sahilmgandhi 18:6a4db94011d3 1431 /* Bit 23 : Pin 23. */
sahilmgandhi 18:6a4db94011d3 1432 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1433 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1434 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1435 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1436 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1437
sahilmgandhi 18:6a4db94011d3 1438 /* Bit 22 : Pin 22. */
sahilmgandhi 18:6a4db94011d3 1439 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1440 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1441 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1442 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1443 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1444
sahilmgandhi 18:6a4db94011d3 1445 /* Bit 21 : Pin 21. */
sahilmgandhi 18:6a4db94011d3 1446 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1447 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1448 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1449 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1450 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1451
sahilmgandhi 18:6a4db94011d3 1452 /* Bit 20 : Pin 20. */
sahilmgandhi 18:6a4db94011d3 1453 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1454 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1455 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1456 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1457 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1458
sahilmgandhi 18:6a4db94011d3 1459 /* Bit 19 : Pin 19. */
sahilmgandhi 18:6a4db94011d3 1460 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1461 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1462 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1463 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1464 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1465
sahilmgandhi 18:6a4db94011d3 1466 /* Bit 18 : Pin 18. */
sahilmgandhi 18:6a4db94011d3 1467 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1468 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1469 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1470 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1471 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1472
sahilmgandhi 18:6a4db94011d3 1473 /* Bit 17 : Pin 17. */
sahilmgandhi 18:6a4db94011d3 1474 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1475 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1476 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1477 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1478 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1479
sahilmgandhi 18:6a4db94011d3 1480 /* Bit 16 : Pin 16. */
sahilmgandhi 18:6a4db94011d3 1481 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1482 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1483 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1484 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1485 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1486
sahilmgandhi 18:6a4db94011d3 1487 /* Bit 15 : Pin 15. */
sahilmgandhi 18:6a4db94011d3 1488 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1489 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1490 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1491 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1492 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1493
sahilmgandhi 18:6a4db94011d3 1494 /* Bit 14 : Pin 14. */
sahilmgandhi 18:6a4db94011d3 1495 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1496 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1497 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1498 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1499 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1500
sahilmgandhi 18:6a4db94011d3 1501 /* Bit 13 : Pin 13. */
sahilmgandhi 18:6a4db94011d3 1502 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1503 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1504 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1505 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1506 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1507
sahilmgandhi 18:6a4db94011d3 1508 /* Bit 12 : Pin 12. */
sahilmgandhi 18:6a4db94011d3 1509 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1510 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1511 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1512 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1513 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1514
sahilmgandhi 18:6a4db94011d3 1515 /* Bit 11 : Pin 11. */
sahilmgandhi 18:6a4db94011d3 1516 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1517 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1518 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1519 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1520 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1521
sahilmgandhi 18:6a4db94011d3 1522 /* Bit 10 : Pin 10. */
sahilmgandhi 18:6a4db94011d3 1523 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1524 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1525 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1526 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1527 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1528
sahilmgandhi 18:6a4db94011d3 1529 /* Bit 9 : Pin 9. */
sahilmgandhi 18:6a4db94011d3 1530 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1531 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1532 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1533 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1534 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1535
sahilmgandhi 18:6a4db94011d3 1536 /* Bit 8 : Pin 8. */
sahilmgandhi 18:6a4db94011d3 1537 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1538 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1539 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1540 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1541 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1542
sahilmgandhi 18:6a4db94011d3 1543 /* Bit 7 : Pin 7. */
sahilmgandhi 18:6a4db94011d3 1544 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1545 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1546 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1547 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1548 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1549
sahilmgandhi 18:6a4db94011d3 1550 /* Bit 6 : Pin 6. */
sahilmgandhi 18:6a4db94011d3 1551 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1552 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1553 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1554 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1555 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1556
sahilmgandhi 18:6a4db94011d3 1557 /* Bit 5 : Pin 5. */
sahilmgandhi 18:6a4db94011d3 1558 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1559 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1560 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1561 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1562 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1563
sahilmgandhi 18:6a4db94011d3 1564 /* Bit 4 : Pin 4. */
sahilmgandhi 18:6a4db94011d3 1565 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1566 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1567 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1568 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1569 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1570
sahilmgandhi 18:6a4db94011d3 1571 /* Bit 3 : Pin 3. */
sahilmgandhi 18:6a4db94011d3 1572 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1573 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1574 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1575 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1576 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1577
sahilmgandhi 18:6a4db94011d3 1578 /* Bit 2 : Pin 2. */
sahilmgandhi 18:6a4db94011d3 1579 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 1580 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 1581 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1582 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1583 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1584
sahilmgandhi 18:6a4db94011d3 1585 /* Bit 1 : Pin 1. */
sahilmgandhi 18:6a4db94011d3 1586 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 1587 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 1588 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1589 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1590 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1591
sahilmgandhi 18:6a4db94011d3 1592 /* Bit 0 : Pin 0. */
sahilmgandhi 18:6a4db94011d3 1593 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 1594 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 1595 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1596 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1597 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
sahilmgandhi 18:6a4db94011d3 1598
sahilmgandhi 18:6a4db94011d3 1599 /* Register: GPIO_OUTCLR */
sahilmgandhi 18:6a4db94011d3 1600 /* Description: Clear individual bits in GPIO port. */
sahilmgandhi 18:6a4db94011d3 1601
sahilmgandhi 18:6a4db94011d3 1602 /* Bit 31 : Pin 31. */
sahilmgandhi 18:6a4db94011d3 1603 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1604 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1605 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1606 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1607 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1608
sahilmgandhi 18:6a4db94011d3 1609 /* Bit 30 : Pin 30. */
sahilmgandhi 18:6a4db94011d3 1610 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1611 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1612 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1613 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1614 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1615
sahilmgandhi 18:6a4db94011d3 1616 /* Bit 29 : Pin 29. */
sahilmgandhi 18:6a4db94011d3 1617 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1618 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1619 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1620 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1621 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1622
sahilmgandhi 18:6a4db94011d3 1623 /* Bit 28 : Pin 28. */
sahilmgandhi 18:6a4db94011d3 1624 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1625 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1626 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1627 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1628 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1629
sahilmgandhi 18:6a4db94011d3 1630 /* Bit 27 : Pin 27. */
sahilmgandhi 18:6a4db94011d3 1631 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1632 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1633 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1634 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1635 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1636
sahilmgandhi 18:6a4db94011d3 1637 /* Bit 26 : Pin 26. */
sahilmgandhi 18:6a4db94011d3 1638 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1639 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1640 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1641 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1642 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1643
sahilmgandhi 18:6a4db94011d3 1644 /* Bit 25 : Pin 25. */
sahilmgandhi 18:6a4db94011d3 1645 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1646 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1647 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1648 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1649 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1650
sahilmgandhi 18:6a4db94011d3 1651 /* Bit 24 : Pin 24. */
sahilmgandhi 18:6a4db94011d3 1652 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1653 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1654 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1655 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1656 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1657
sahilmgandhi 18:6a4db94011d3 1658 /* Bit 23 : Pin 23. */
sahilmgandhi 18:6a4db94011d3 1659 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1660 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1661 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1662 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1663 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1664
sahilmgandhi 18:6a4db94011d3 1665 /* Bit 22 : Pin 22. */
sahilmgandhi 18:6a4db94011d3 1666 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1667 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1668 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1669 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1670 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1671
sahilmgandhi 18:6a4db94011d3 1672 /* Bit 21 : Pin 21. */
sahilmgandhi 18:6a4db94011d3 1673 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1674 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1675 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1676 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1677 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1678
sahilmgandhi 18:6a4db94011d3 1679 /* Bit 20 : Pin 20. */
sahilmgandhi 18:6a4db94011d3 1680 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1681 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1682 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1683 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1684 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1685
sahilmgandhi 18:6a4db94011d3 1686 /* Bit 19 : Pin 19. */
sahilmgandhi 18:6a4db94011d3 1687 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1688 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1689 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1690 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1691 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1692
sahilmgandhi 18:6a4db94011d3 1693 /* Bit 18 : Pin 18. */
sahilmgandhi 18:6a4db94011d3 1694 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1695 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1696 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1697 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1698 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1699
sahilmgandhi 18:6a4db94011d3 1700 /* Bit 17 : Pin 17. */
sahilmgandhi 18:6a4db94011d3 1701 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1702 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1703 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1704 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1705 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1706
sahilmgandhi 18:6a4db94011d3 1707 /* Bit 16 : Pin 16. */
sahilmgandhi 18:6a4db94011d3 1708 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1709 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1710 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1711 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1712 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1713
sahilmgandhi 18:6a4db94011d3 1714 /* Bit 15 : Pin 15. */
sahilmgandhi 18:6a4db94011d3 1715 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1716 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1717 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1718 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1719 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1720
sahilmgandhi 18:6a4db94011d3 1721 /* Bit 14 : Pin 14. */
sahilmgandhi 18:6a4db94011d3 1722 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1723 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1724 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1725 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1726 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1727
sahilmgandhi 18:6a4db94011d3 1728 /* Bit 13 : Pin 13. */
sahilmgandhi 18:6a4db94011d3 1729 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1730 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1731 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1732 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1733 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1734
sahilmgandhi 18:6a4db94011d3 1735 /* Bit 12 : Pin 12. */
sahilmgandhi 18:6a4db94011d3 1736 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1737 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1738 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1739 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1740 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1741
sahilmgandhi 18:6a4db94011d3 1742 /* Bit 11 : Pin 11. */
sahilmgandhi 18:6a4db94011d3 1743 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1744 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1745 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1746 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1747 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1748
sahilmgandhi 18:6a4db94011d3 1749 /* Bit 10 : Pin 10. */
sahilmgandhi 18:6a4db94011d3 1750 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1751 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1752 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1753 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1754 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1755
sahilmgandhi 18:6a4db94011d3 1756 /* Bit 9 : Pin 9. */
sahilmgandhi 18:6a4db94011d3 1757 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1758 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1759 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1760 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1761 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1762
sahilmgandhi 18:6a4db94011d3 1763 /* Bit 8 : Pin 8. */
sahilmgandhi 18:6a4db94011d3 1764 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1765 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1766 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1767 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1768 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1769
sahilmgandhi 18:6a4db94011d3 1770 /* Bit 7 : Pin 7. */
sahilmgandhi 18:6a4db94011d3 1771 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1772 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1773 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1774 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1775 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1776
sahilmgandhi 18:6a4db94011d3 1777 /* Bit 6 : Pin 6. */
sahilmgandhi 18:6a4db94011d3 1778 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1779 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1780 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1781 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1782 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1783
sahilmgandhi 18:6a4db94011d3 1784 /* Bit 5 : Pin 5. */
sahilmgandhi 18:6a4db94011d3 1785 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1786 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1787 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1788 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1789 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1790
sahilmgandhi 18:6a4db94011d3 1791 /* Bit 4 : Pin 4. */
sahilmgandhi 18:6a4db94011d3 1792 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1793 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1794 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1795 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1796 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1797
sahilmgandhi 18:6a4db94011d3 1798 /* Bit 3 : Pin 3. */
sahilmgandhi 18:6a4db94011d3 1799 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1800 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1801 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1802 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1803 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1804
sahilmgandhi 18:6a4db94011d3 1805 /* Bit 2 : Pin 2. */
sahilmgandhi 18:6a4db94011d3 1806 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 1807 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 1808 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1809 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1810 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1811
sahilmgandhi 18:6a4db94011d3 1812 /* Bit 1 : Pin 1. */
sahilmgandhi 18:6a4db94011d3 1813 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 1814 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 1815 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1816 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1817 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1818
sahilmgandhi 18:6a4db94011d3 1819 /* Bit 0 : Pin 0. */
sahilmgandhi 18:6a4db94011d3 1820 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 1821 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 1822 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
sahilmgandhi 18:6a4db94011d3 1823 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
sahilmgandhi 18:6a4db94011d3 1824 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
sahilmgandhi 18:6a4db94011d3 1825
sahilmgandhi 18:6a4db94011d3 1826 /* Register: GPIO_IN */
sahilmgandhi 18:6a4db94011d3 1827 /* Description: Read GPIO port. */
sahilmgandhi 18:6a4db94011d3 1828
sahilmgandhi 18:6a4db94011d3 1829 /* Bit 31 : Pin 31. */
sahilmgandhi 18:6a4db94011d3 1830 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1831 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 1832 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1833 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1834
sahilmgandhi 18:6a4db94011d3 1835 /* Bit 30 : Pin 30. */
sahilmgandhi 18:6a4db94011d3 1836 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1837 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 1838 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1839 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1840
sahilmgandhi 18:6a4db94011d3 1841 /* Bit 29 : Pin 29. */
sahilmgandhi 18:6a4db94011d3 1842 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1843 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 1844 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1845 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1846
sahilmgandhi 18:6a4db94011d3 1847 /* Bit 28 : Pin 28. */
sahilmgandhi 18:6a4db94011d3 1848 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1849 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 1850 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1851 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1852
sahilmgandhi 18:6a4db94011d3 1853 /* Bit 27 : Pin 27. */
sahilmgandhi 18:6a4db94011d3 1854 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1855 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 1856 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1857 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1858
sahilmgandhi 18:6a4db94011d3 1859 /* Bit 26 : Pin 26. */
sahilmgandhi 18:6a4db94011d3 1860 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1861 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 1862 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1863 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1864
sahilmgandhi 18:6a4db94011d3 1865 /* Bit 25 : Pin 25. */
sahilmgandhi 18:6a4db94011d3 1866 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1867 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 1868 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1869 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1870
sahilmgandhi 18:6a4db94011d3 1871 /* Bit 24 : Pin 24. */
sahilmgandhi 18:6a4db94011d3 1872 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1873 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 1874 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1875 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1876
sahilmgandhi 18:6a4db94011d3 1877 /* Bit 23 : Pin 23. */
sahilmgandhi 18:6a4db94011d3 1878 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1879 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 1880 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1881 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1882
sahilmgandhi 18:6a4db94011d3 1883 /* Bit 22 : Pin 22. */
sahilmgandhi 18:6a4db94011d3 1884 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1885 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 1886 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1887 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1888
sahilmgandhi 18:6a4db94011d3 1889 /* Bit 21 : Pin 21. */
sahilmgandhi 18:6a4db94011d3 1890 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1891 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 1892 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1893 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1894
sahilmgandhi 18:6a4db94011d3 1895 /* Bit 20 : Pin 20. */
sahilmgandhi 18:6a4db94011d3 1896 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1897 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 1898 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1899 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1900
sahilmgandhi 18:6a4db94011d3 1901 /* Bit 19 : Pin 19. */
sahilmgandhi 18:6a4db94011d3 1902 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1903 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 1904 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1905 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1906
sahilmgandhi 18:6a4db94011d3 1907 /* Bit 18 : Pin 18. */
sahilmgandhi 18:6a4db94011d3 1908 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1909 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 1910 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1911 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1912
sahilmgandhi 18:6a4db94011d3 1913 /* Bit 17 : Pin 17. */
sahilmgandhi 18:6a4db94011d3 1914 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1915 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 1916 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1917 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1918
sahilmgandhi 18:6a4db94011d3 1919 /* Bit 16 : Pin 16. */
sahilmgandhi 18:6a4db94011d3 1920 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1921 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 1922 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1923 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1924
sahilmgandhi 18:6a4db94011d3 1925 /* Bit 15 : Pin 15. */
sahilmgandhi 18:6a4db94011d3 1926 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1927 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 1928 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1929 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1930
sahilmgandhi 18:6a4db94011d3 1931 /* Bit 14 : Pin 14. */
sahilmgandhi 18:6a4db94011d3 1932 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1933 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 1934 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1935 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1936
sahilmgandhi 18:6a4db94011d3 1937 /* Bit 13 : Pin 13. */
sahilmgandhi 18:6a4db94011d3 1938 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1939 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 1940 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1941 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1942
sahilmgandhi 18:6a4db94011d3 1943 /* Bit 12 : Pin 12. */
sahilmgandhi 18:6a4db94011d3 1944 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1945 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 1946 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1947 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1948
sahilmgandhi 18:6a4db94011d3 1949 /* Bit 11 : Pin 11. */
sahilmgandhi 18:6a4db94011d3 1950 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1951 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 1952 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1953 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1954
sahilmgandhi 18:6a4db94011d3 1955 /* Bit 10 : Pin 10. */
sahilmgandhi 18:6a4db94011d3 1956 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1957 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 1958 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1959 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1960
sahilmgandhi 18:6a4db94011d3 1961 /* Bit 9 : Pin 9. */
sahilmgandhi 18:6a4db94011d3 1962 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1963 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 1964 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1965 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1966
sahilmgandhi 18:6a4db94011d3 1967 /* Bit 8 : Pin 8. */
sahilmgandhi 18:6a4db94011d3 1968 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1969 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 1970 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1971 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1972
sahilmgandhi 18:6a4db94011d3 1973 /* Bit 7 : Pin 7. */
sahilmgandhi 18:6a4db94011d3 1974 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1975 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 1976 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1977 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1978
sahilmgandhi 18:6a4db94011d3 1979 /* Bit 6 : Pin 6. */
sahilmgandhi 18:6a4db94011d3 1980 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1981 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 1982 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1983 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1984
sahilmgandhi 18:6a4db94011d3 1985 /* Bit 5 : Pin 5. */
sahilmgandhi 18:6a4db94011d3 1986 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1987 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 1988 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1989 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1990
sahilmgandhi 18:6a4db94011d3 1991 /* Bit 4 : Pin 4. */
sahilmgandhi 18:6a4db94011d3 1992 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1993 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 1994 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 1995 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 1996
sahilmgandhi 18:6a4db94011d3 1997 /* Bit 3 : Pin 3. */
sahilmgandhi 18:6a4db94011d3 1998 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 1999 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2000 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 2001 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 2002
sahilmgandhi 18:6a4db94011d3 2003 /* Bit 2 : Pin 2. */
sahilmgandhi 18:6a4db94011d3 2004 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2005 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2006 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 2007 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 2008
sahilmgandhi 18:6a4db94011d3 2009 /* Bit 1 : Pin 1. */
sahilmgandhi 18:6a4db94011d3 2010 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2011 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2012 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 2013 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 2014
sahilmgandhi 18:6a4db94011d3 2015 /* Bit 0 : Pin 0. */
sahilmgandhi 18:6a4db94011d3 2016 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2017 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2018 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
sahilmgandhi 18:6a4db94011d3 2019 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
sahilmgandhi 18:6a4db94011d3 2020
sahilmgandhi 18:6a4db94011d3 2021 /* Register: GPIO_DIR */
sahilmgandhi 18:6a4db94011d3 2022 /* Description: Direction of GPIO pins. */
sahilmgandhi 18:6a4db94011d3 2023
sahilmgandhi 18:6a4db94011d3 2024 /* Bit 31 : Pin 31. */
sahilmgandhi 18:6a4db94011d3 2025 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 2026 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 2027 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2028 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2029
sahilmgandhi 18:6a4db94011d3 2030 /* Bit 30 : Pin 30. */
sahilmgandhi 18:6a4db94011d3 2031 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 2032 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 2033 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2034 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2035
sahilmgandhi 18:6a4db94011d3 2036 /* Bit 29 : Pin 29. */
sahilmgandhi 18:6a4db94011d3 2037 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 2038 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 2039 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2040 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2041
sahilmgandhi 18:6a4db94011d3 2042 /* Bit 28 : Pin 28. */
sahilmgandhi 18:6a4db94011d3 2043 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 2044 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 2045 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2046 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2047
sahilmgandhi 18:6a4db94011d3 2048 /* Bit 27 : Pin 27. */
sahilmgandhi 18:6a4db94011d3 2049 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 2050 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 2051 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2052 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2053
sahilmgandhi 18:6a4db94011d3 2054 /* Bit 26 : Pin 26. */
sahilmgandhi 18:6a4db94011d3 2055 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 2056 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 2057 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2058 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2059
sahilmgandhi 18:6a4db94011d3 2060 /* Bit 25 : Pin 25. */
sahilmgandhi 18:6a4db94011d3 2061 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 2062 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 2063 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2064 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2065
sahilmgandhi 18:6a4db94011d3 2066 /* Bit 24 : Pin 24. */
sahilmgandhi 18:6a4db94011d3 2067 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 2068 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 2069 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2070 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2071
sahilmgandhi 18:6a4db94011d3 2072 /* Bit 23 : Pin 23. */
sahilmgandhi 18:6a4db94011d3 2073 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 2074 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 2075 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2076 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2077
sahilmgandhi 18:6a4db94011d3 2078 /* Bit 22 : Pin 22. */
sahilmgandhi 18:6a4db94011d3 2079 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 2080 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 2081 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2082 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2083
sahilmgandhi 18:6a4db94011d3 2084 /* Bit 21 : Pin 21. */
sahilmgandhi 18:6a4db94011d3 2085 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 2086 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 2087 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2088 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2089
sahilmgandhi 18:6a4db94011d3 2090 /* Bit 20 : Pin 20. */
sahilmgandhi 18:6a4db94011d3 2091 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 2092 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 2093 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2094 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2095
sahilmgandhi 18:6a4db94011d3 2096 /* Bit 19 : Pin 19. */
sahilmgandhi 18:6a4db94011d3 2097 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 2098 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 2099 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2100 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2101
sahilmgandhi 18:6a4db94011d3 2102 /* Bit 18 : Pin 18. */
sahilmgandhi 18:6a4db94011d3 2103 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 2104 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 2105 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2106 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2107
sahilmgandhi 18:6a4db94011d3 2108 /* Bit 17 : Pin 17. */
sahilmgandhi 18:6a4db94011d3 2109 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 2110 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 2111 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2112 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2113
sahilmgandhi 18:6a4db94011d3 2114 /* Bit 16 : Pin 16. */
sahilmgandhi 18:6a4db94011d3 2115 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 2116 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 2117 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2118 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2119
sahilmgandhi 18:6a4db94011d3 2120 /* Bit 15 : Pin 15. */
sahilmgandhi 18:6a4db94011d3 2121 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 2122 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 2123 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2124 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2125
sahilmgandhi 18:6a4db94011d3 2126 /* Bit 14 : Pin 14. */
sahilmgandhi 18:6a4db94011d3 2127 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 2128 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 2129 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2130 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2131
sahilmgandhi 18:6a4db94011d3 2132 /* Bit 13 : Pin 13. */
sahilmgandhi 18:6a4db94011d3 2133 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 2134 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 2135 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2136 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2137
sahilmgandhi 18:6a4db94011d3 2138 /* Bit 12 : Pin 12. */
sahilmgandhi 18:6a4db94011d3 2139 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 2140 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 2141 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2142 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2143
sahilmgandhi 18:6a4db94011d3 2144 /* Bit 11 : Pin 11. */
sahilmgandhi 18:6a4db94011d3 2145 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 2146 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 2147 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2148 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2149
sahilmgandhi 18:6a4db94011d3 2150 /* Bit 10 : Pin 10. */
sahilmgandhi 18:6a4db94011d3 2151 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 2152 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 2153 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2154 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2155
sahilmgandhi 18:6a4db94011d3 2156 /* Bit 9 : Pin 9. */
sahilmgandhi 18:6a4db94011d3 2157 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 2158 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 2159 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2160 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2161
sahilmgandhi 18:6a4db94011d3 2162 /* Bit 8 : Pin 8. */
sahilmgandhi 18:6a4db94011d3 2163 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 2164 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 2165 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2166 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2167
sahilmgandhi 18:6a4db94011d3 2168 /* Bit 7 : Pin 7. */
sahilmgandhi 18:6a4db94011d3 2169 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 2170 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 2171 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2172 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2173
sahilmgandhi 18:6a4db94011d3 2174 /* Bit 6 : Pin 6. */
sahilmgandhi 18:6a4db94011d3 2175 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 2176 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 2177 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2178 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2179
sahilmgandhi 18:6a4db94011d3 2180 /* Bit 5 : Pin 5. */
sahilmgandhi 18:6a4db94011d3 2181 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 2182 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 2183 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2184 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2185
sahilmgandhi 18:6a4db94011d3 2186 /* Bit 4 : Pin 4. */
sahilmgandhi 18:6a4db94011d3 2187 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 2188 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 2189 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2190 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2191
sahilmgandhi 18:6a4db94011d3 2192 /* Bit 3 : Pin 3. */
sahilmgandhi 18:6a4db94011d3 2193 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2194 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2195 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2196 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2197
sahilmgandhi 18:6a4db94011d3 2198 /* Bit 2 : Pin 2. */
sahilmgandhi 18:6a4db94011d3 2199 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2200 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2201 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2202 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2203
sahilmgandhi 18:6a4db94011d3 2204 /* Bit 1 : Pin 1. */
sahilmgandhi 18:6a4db94011d3 2205 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2206 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2207 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2208 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2209
sahilmgandhi 18:6a4db94011d3 2210 /* Bit 0 : Pin 0. */
sahilmgandhi 18:6a4db94011d3 2211 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2212 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2213 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2214 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2215
sahilmgandhi 18:6a4db94011d3 2216 /* Register: GPIO_DIRSET */
sahilmgandhi 18:6a4db94011d3 2217 /* Description: DIR set register. */
sahilmgandhi 18:6a4db94011d3 2218
sahilmgandhi 18:6a4db94011d3 2219 /* Bit 31 : Set as output pin 31. */
sahilmgandhi 18:6a4db94011d3 2220 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 2221 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 2222 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2223 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2224 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2225
sahilmgandhi 18:6a4db94011d3 2226 /* Bit 30 : Set as output pin 30. */
sahilmgandhi 18:6a4db94011d3 2227 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 2228 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 2229 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2230 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2231 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2232
sahilmgandhi 18:6a4db94011d3 2233 /* Bit 29 : Set as output pin 29. */
sahilmgandhi 18:6a4db94011d3 2234 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 2235 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 2236 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2237 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2238 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2239
sahilmgandhi 18:6a4db94011d3 2240 /* Bit 28 : Set as output pin 28. */
sahilmgandhi 18:6a4db94011d3 2241 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 2242 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 2243 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2244 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2245 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2246
sahilmgandhi 18:6a4db94011d3 2247 /* Bit 27 : Set as output pin 27. */
sahilmgandhi 18:6a4db94011d3 2248 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 2249 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 2250 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2251 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2252 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2253
sahilmgandhi 18:6a4db94011d3 2254 /* Bit 26 : Set as output pin 26. */
sahilmgandhi 18:6a4db94011d3 2255 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 2256 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 2257 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2258 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2259 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2260
sahilmgandhi 18:6a4db94011d3 2261 /* Bit 25 : Set as output pin 25. */
sahilmgandhi 18:6a4db94011d3 2262 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 2263 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 2264 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2265 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2266 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2267
sahilmgandhi 18:6a4db94011d3 2268 /* Bit 24 : Set as output pin 24. */
sahilmgandhi 18:6a4db94011d3 2269 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 2270 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 2271 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2272 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2273 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2274
sahilmgandhi 18:6a4db94011d3 2275 /* Bit 23 : Set as output pin 23. */
sahilmgandhi 18:6a4db94011d3 2276 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 2277 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 2278 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2279 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2280 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2281
sahilmgandhi 18:6a4db94011d3 2282 /* Bit 22 : Set as output pin 22. */
sahilmgandhi 18:6a4db94011d3 2283 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 2284 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 2285 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2286 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2287 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2288
sahilmgandhi 18:6a4db94011d3 2289 /* Bit 21 : Set as output pin 21. */
sahilmgandhi 18:6a4db94011d3 2290 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 2291 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 2292 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2293 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2294 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2295
sahilmgandhi 18:6a4db94011d3 2296 /* Bit 20 : Set as output pin 20. */
sahilmgandhi 18:6a4db94011d3 2297 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 2298 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 2299 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2300 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2301 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2302
sahilmgandhi 18:6a4db94011d3 2303 /* Bit 19 : Set as output pin 19. */
sahilmgandhi 18:6a4db94011d3 2304 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 2305 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 2306 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2307 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2308 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2309
sahilmgandhi 18:6a4db94011d3 2310 /* Bit 18 : Set as output pin 18. */
sahilmgandhi 18:6a4db94011d3 2311 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 2312 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 2313 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2314 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2315 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2316
sahilmgandhi 18:6a4db94011d3 2317 /* Bit 17 : Set as output pin 17. */
sahilmgandhi 18:6a4db94011d3 2318 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 2319 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 2320 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2321 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2322 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2323
sahilmgandhi 18:6a4db94011d3 2324 /* Bit 16 : Set as output pin 16. */
sahilmgandhi 18:6a4db94011d3 2325 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 2326 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 2327 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2328 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2329 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2330
sahilmgandhi 18:6a4db94011d3 2331 /* Bit 15 : Set as output pin 15. */
sahilmgandhi 18:6a4db94011d3 2332 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 2333 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 2334 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2335 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2336 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2337
sahilmgandhi 18:6a4db94011d3 2338 /* Bit 14 : Set as output pin 14. */
sahilmgandhi 18:6a4db94011d3 2339 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 2340 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 2341 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2342 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2343 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2344
sahilmgandhi 18:6a4db94011d3 2345 /* Bit 13 : Set as output pin 13. */
sahilmgandhi 18:6a4db94011d3 2346 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 2347 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 2348 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2349 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2350 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2351
sahilmgandhi 18:6a4db94011d3 2352 /* Bit 12 : Set as output pin 12. */
sahilmgandhi 18:6a4db94011d3 2353 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 2354 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 2355 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2356 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2357 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2358
sahilmgandhi 18:6a4db94011d3 2359 /* Bit 11 : Set as output pin 11. */
sahilmgandhi 18:6a4db94011d3 2360 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 2361 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 2362 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2363 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2364 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2365
sahilmgandhi 18:6a4db94011d3 2366 /* Bit 10 : Set as output pin 10. */
sahilmgandhi 18:6a4db94011d3 2367 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 2368 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 2369 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2370 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2371 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2372
sahilmgandhi 18:6a4db94011d3 2373 /* Bit 9 : Set as output pin 9. */
sahilmgandhi 18:6a4db94011d3 2374 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 2375 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 2376 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2377 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2378 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2379
sahilmgandhi 18:6a4db94011d3 2380 /* Bit 8 : Set as output pin 8. */
sahilmgandhi 18:6a4db94011d3 2381 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 2382 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 2383 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2384 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2385 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2386
sahilmgandhi 18:6a4db94011d3 2387 /* Bit 7 : Set as output pin 7. */
sahilmgandhi 18:6a4db94011d3 2388 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 2389 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 2390 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2391 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2392 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2393
sahilmgandhi 18:6a4db94011d3 2394 /* Bit 6 : Set as output pin 6. */
sahilmgandhi 18:6a4db94011d3 2395 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 2396 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 2397 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2398 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2399 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2400
sahilmgandhi 18:6a4db94011d3 2401 /* Bit 5 : Set as output pin 5. */
sahilmgandhi 18:6a4db94011d3 2402 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 2403 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 2404 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2405 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2406 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2407
sahilmgandhi 18:6a4db94011d3 2408 /* Bit 4 : Set as output pin 4. */
sahilmgandhi 18:6a4db94011d3 2409 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 2410 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 2411 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2412 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2413 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2414
sahilmgandhi 18:6a4db94011d3 2415 /* Bit 3 : Set as output pin 3. */
sahilmgandhi 18:6a4db94011d3 2416 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2417 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2418 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2419 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2420 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2421
sahilmgandhi 18:6a4db94011d3 2422 /* Bit 2 : Set as output pin 2. */
sahilmgandhi 18:6a4db94011d3 2423 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2424 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2425 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2426 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2427 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2428
sahilmgandhi 18:6a4db94011d3 2429 /* Bit 1 : Set as output pin 1. */
sahilmgandhi 18:6a4db94011d3 2430 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2431 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2432 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2433 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2434 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2435
sahilmgandhi 18:6a4db94011d3 2436 /* Bit 0 : Set as output pin 0. */
sahilmgandhi 18:6a4db94011d3 2437 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2438 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2439 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2440 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2441 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
sahilmgandhi 18:6a4db94011d3 2442
sahilmgandhi 18:6a4db94011d3 2443 /* Register: GPIO_DIRCLR */
sahilmgandhi 18:6a4db94011d3 2444 /* Description: DIR clear register. */
sahilmgandhi 18:6a4db94011d3 2445
sahilmgandhi 18:6a4db94011d3 2446 /* Bit 31 : Set as input pin 31. */
sahilmgandhi 18:6a4db94011d3 2447 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 2448 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
sahilmgandhi 18:6a4db94011d3 2449 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2450 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2451 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2452
sahilmgandhi 18:6a4db94011d3 2453 /* Bit 30 : Set as input pin 30. */
sahilmgandhi 18:6a4db94011d3 2454 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 2455 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
sahilmgandhi 18:6a4db94011d3 2456 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2457 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2458 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2459
sahilmgandhi 18:6a4db94011d3 2460 /* Bit 29 : Set as input pin 29. */
sahilmgandhi 18:6a4db94011d3 2461 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 2462 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
sahilmgandhi 18:6a4db94011d3 2463 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2464 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2465 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2466
sahilmgandhi 18:6a4db94011d3 2467 /* Bit 28 : Set as input pin 28. */
sahilmgandhi 18:6a4db94011d3 2468 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 2469 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
sahilmgandhi 18:6a4db94011d3 2470 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2471 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2472 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2473
sahilmgandhi 18:6a4db94011d3 2474 /* Bit 27 : Set as input pin 27. */
sahilmgandhi 18:6a4db94011d3 2475 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 2476 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
sahilmgandhi 18:6a4db94011d3 2477 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2478 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2479 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2480
sahilmgandhi 18:6a4db94011d3 2481 /* Bit 26 : Set as input pin 26. */
sahilmgandhi 18:6a4db94011d3 2482 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 2483 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
sahilmgandhi 18:6a4db94011d3 2484 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2485 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2486 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2487
sahilmgandhi 18:6a4db94011d3 2488 /* Bit 25 : Set as input pin 25. */
sahilmgandhi 18:6a4db94011d3 2489 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 2490 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
sahilmgandhi 18:6a4db94011d3 2491 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2492 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2493 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2494
sahilmgandhi 18:6a4db94011d3 2495 /* Bit 24 : Set as input pin 24. */
sahilmgandhi 18:6a4db94011d3 2496 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 2497 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
sahilmgandhi 18:6a4db94011d3 2498 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2499 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2500 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2501
sahilmgandhi 18:6a4db94011d3 2502 /* Bit 23 : Set as input pin 23. */
sahilmgandhi 18:6a4db94011d3 2503 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 2504 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
sahilmgandhi 18:6a4db94011d3 2505 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2506 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2507 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2508
sahilmgandhi 18:6a4db94011d3 2509 /* Bit 22 : Set as input pin 22. */
sahilmgandhi 18:6a4db94011d3 2510 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 2511 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
sahilmgandhi 18:6a4db94011d3 2512 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2513 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2514 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2515
sahilmgandhi 18:6a4db94011d3 2516 /* Bit 21 : Set as input pin 21. */
sahilmgandhi 18:6a4db94011d3 2517 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 2518 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
sahilmgandhi 18:6a4db94011d3 2519 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2520 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2521 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2522
sahilmgandhi 18:6a4db94011d3 2523 /* Bit 20 : Set as input pin 20. */
sahilmgandhi 18:6a4db94011d3 2524 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 2525 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
sahilmgandhi 18:6a4db94011d3 2526 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2527 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2528 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2529
sahilmgandhi 18:6a4db94011d3 2530 /* Bit 19 : Set as input pin 19. */
sahilmgandhi 18:6a4db94011d3 2531 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 2532 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
sahilmgandhi 18:6a4db94011d3 2533 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2534 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2535 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2536
sahilmgandhi 18:6a4db94011d3 2537 /* Bit 18 : Set as input pin 18. */
sahilmgandhi 18:6a4db94011d3 2538 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 2539 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
sahilmgandhi 18:6a4db94011d3 2540 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2541 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2542 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2543
sahilmgandhi 18:6a4db94011d3 2544 /* Bit 17 : Set as input pin 17. */
sahilmgandhi 18:6a4db94011d3 2545 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 2546 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
sahilmgandhi 18:6a4db94011d3 2547 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2548 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2549 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2550
sahilmgandhi 18:6a4db94011d3 2551 /* Bit 16 : Set as input pin 16. */
sahilmgandhi 18:6a4db94011d3 2552 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 2553 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
sahilmgandhi 18:6a4db94011d3 2554 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2555 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2556 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2557
sahilmgandhi 18:6a4db94011d3 2558 /* Bit 15 : Set as input pin 15. */
sahilmgandhi 18:6a4db94011d3 2559 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 2560 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
sahilmgandhi 18:6a4db94011d3 2561 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2562 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2563 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2564
sahilmgandhi 18:6a4db94011d3 2565 /* Bit 14 : Set as input pin 14. */
sahilmgandhi 18:6a4db94011d3 2566 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 2567 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
sahilmgandhi 18:6a4db94011d3 2568 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2569 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2570 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2571
sahilmgandhi 18:6a4db94011d3 2572 /* Bit 13 : Set as input pin 13. */
sahilmgandhi 18:6a4db94011d3 2573 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 2574 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
sahilmgandhi 18:6a4db94011d3 2575 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2576 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2577 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2578
sahilmgandhi 18:6a4db94011d3 2579 /* Bit 12 : Set as input pin 12. */
sahilmgandhi 18:6a4db94011d3 2580 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 2581 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
sahilmgandhi 18:6a4db94011d3 2582 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2583 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2584 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2585
sahilmgandhi 18:6a4db94011d3 2586 /* Bit 11 : Set as input pin 11. */
sahilmgandhi 18:6a4db94011d3 2587 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 2588 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
sahilmgandhi 18:6a4db94011d3 2589 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2590 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2591 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2592
sahilmgandhi 18:6a4db94011d3 2593 /* Bit 10 : Set as input pin 10. */
sahilmgandhi 18:6a4db94011d3 2594 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 2595 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
sahilmgandhi 18:6a4db94011d3 2596 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2597 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2598 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2599
sahilmgandhi 18:6a4db94011d3 2600 /* Bit 9 : Set as input pin 9. */
sahilmgandhi 18:6a4db94011d3 2601 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 2602 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
sahilmgandhi 18:6a4db94011d3 2603 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2604 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2605 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2606
sahilmgandhi 18:6a4db94011d3 2607 /* Bit 8 : Set as input pin 8. */
sahilmgandhi 18:6a4db94011d3 2608 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 2609 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
sahilmgandhi 18:6a4db94011d3 2610 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2611 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2612 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2613
sahilmgandhi 18:6a4db94011d3 2614 /* Bit 7 : Set as input pin 7. */
sahilmgandhi 18:6a4db94011d3 2615 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 2616 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
sahilmgandhi 18:6a4db94011d3 2617 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2618 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2619 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2620
sahilmgandhi 18:6a4db94011d3 2621 /* Bit 6 : Set as input pin 6. */
sahilmgandhi 18:6a4db94011d3 2622 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 2623 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
sahilmgandhi 18:6a4db94011d3 2624 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2625 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2626 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2627
sahilmgandhi 18:6a4db94011d3 2628 /* Bit 5 : Set as input pin 5. */
sahilmgandhi 18:6a4db94011d3 2629 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 2630 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
sahilmgandhi 18:6a4db94011d3 2631 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2632 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2633 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2634
sahilmgandhi 18:6a4db94011d3 2635 /* Bit 4 : Set as input pin 4. */
sahilmgandhi 18:6a4db94011d3 2636 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 2637 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
sahilmgandhi 18:6a4db94011d3 2638 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2639 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2640 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2641
sahilmgandhi 18:6a4db94011d3 2642 /* Bit 3 : Set as input pin 3. */
sahilmgandhi 18:6a4db94011d3 2643 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2644 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
sahilmgandhi 18:6a4db94011d3 2645 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2646 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2647 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2648
sahilmgandhi 18:6a4db94011d3 2649 /* Bit 2 : Set as input pin 2. */
sahilmgandhi 18:6a4db94011d3 2650 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2651 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
sahilmgandhi 18:6a4db94011d3 2652 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2653 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2654 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2655
sahilmgandhi 18:6a4db94011d3 2656 /* Bit 1 : Set as input pin 1. */
sahilmgandhi 18:6a4db94011d3 2657 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2658 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
sahilmgandhi 18:6a4db94011d3 2659 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2660 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2661 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2662
sahilmgandhi 18:6a4db94011d3 2663 /* Bit 0 : Set as input pin 0. */
sahilmgandhi 18:6a4db94011d3 2664 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2665 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
sahilmgandhi 18:6a4db94011d3 2666 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
sahilmgandhi 18:6a4db94011d3 2667 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
sahilmgandhi 18:6a4db94011d3 2668 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
sahilmgandhi 18:6a4db94011d3 2669
sahilmgandhi 18:6a4db94011d3 2670 /* Register: GPIO_PIN_CNF */
sahilmgandhi 18:6a4db94011d3 2671 /* Description: Configuration of GPIO pins. */
sahilmgandhi 18:6a4db94011d3 2672
sahilmgandhi 18:6a4db94011d3 2673 /* Bits 17..16 : Pin sensing mechanism. */
sahilmgandhi 18:6a4db94011d3 2674 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
sahilmgandhi 18:6a4db94011d3 2675 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
sahilmgandhi 18:6a4db94011d3 2676 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 2677 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
sahilmgandhi 18:6a4db94011d3 2678 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
sahilmgandhi 18:6a4db94011d3 2679
sahilmgandhi 18:6a4db94011d3 2680 /* Bits 10..8 : Drive configuration. */
sahilmgandhi 18:6a4db94011d3 2681 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
sahilmgandhi 18:6a4db94011d3 2682 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
sahilmgandhi 18:6a4db94011d3 2683 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
sahilmgandhi 18:6a4db94011d3 2684 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
sahilmgandhi 18:6a4db94011d3 2685 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
sahilmgandhi 18:6a4db94011d3 2686 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
sahilmgandhi 18:6a4db94011d3 2687 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
sahilmgandhi 18:6a4db94011d3 2688 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
sahilmgandhi 18:6a4db94011d3 2689 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
sahilmgandhi 18:6a4db94011d3 2690 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
sahilmgandhi 18:6a4db94011d3 2691
sahilmgandhi 18:6a4db94011d3 2692 /* Bits 3..2 : Pull-up or -down configuration. */
sahilmgandhi 18:6a4db94011d3 2693 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
sahilmgandhi 18:6a4db94011d3 2694 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
sahilmgandhi 18:6a4db94011d3 2695 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
sahilmgandhi 18:6a4db94011d3 2696 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
sahilmgandhi 18:6a4db94011d3 2697 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
sahilmgandhi 18:6a4db94011d3 2698
sahilmgandhi 18:6a4db94011d3 2699 /* Bit 1 : Connect or disconnect input path. */
sahilmgandhi 18:6a4db94011d3 2700 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
sahilmgandhi 18:6a4db94011d3 2701 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
sahilmgandhi 18:6a4db94011d3 2702 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
sahilmgandhi 18:6a4db94011d3 2703 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
sahilmgandhi 18:6a4db94011d3 2704
sahilmgandhi 18:6a4db94011d3 2705 /* Bit 0 : Pin direction. */
sahilmgandhi 18:6a4db94011d3 2706 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
sahilmgandhi 18:6a4db94011d3 2707 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
sahilmgandhi 18:6a4db94011d3 2708 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
sahilmgandhi 18:6a4db94011d3 2709 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
sahilmgandhi 18:6a4db94011d3 2710
sahilmgandhi 18:6a4db94011d3 2711
sahilmgandhi 18:6a4db94011d3 2712 /* Peripheral: GPIOTE */
sahilmgandhi 18:6a4db94011d3 2713 /* Description: GPIO tasks and events. */
sahilmgandhi 18:6a4db94011d3 2714
sahilmgandhi 18:6a4db94011d3 2715 /* Register: GPIOTE_INTENSET */
sahilmgandhi 18:6a4db94011d3 2716 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 2717
sahilmgandhi 18:6a4db94011d3 2718 /* Bit 31 : Enable interrupt on PORT event. */
sahilmgandhi 18:6a4db94011d3 2719 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
sahilmgandhi 18:6a4db94011d3 2720 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
sahilmgandhi 18:6a4db94011d3 2721 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2722 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2723 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2724
sahilmgandhi 18:6a4db94011d3 2725 /* Bit 3 : Enable interrupt on IN[3] event. */
sahilmgandhi 18:6a4db94011d3 2726 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
sahilmgandhi 18:6a4db94011d3 2727 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
sahilmgandhi 18:6a4db94011d3 2728 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2729 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2730 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2731
sahilmgandhi 18:6a4db94011d3 2732 /* Bit 2 : Enable interrupt on IN[2] event. */
sahilmgandhi 18:6a4db94011d3 2733 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
sahilmgandhi 18:6a4db94011d3 2734 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
sahilmgandhi 18:6a4db94011d3 2735 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2736 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2737 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2738
sahilmgandhi 18:6a4db94011d3 2739 /* Bit 1 : Enable interrupt on IN[1] event. */
sahilmgandhi 18:6a4db94011d3 2740 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
sahilmgandhi 18:6a4db94011d3 2741 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
sahilmgandhi 18:6a4db94011d3 2742 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2743 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2744 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2745
sahilmgandhi 18:6a4db94011d3 2746 /* Bit 0 : Enable interrupt on IN[0] event. */
sahilmgandhi 18:6a4db94011d3 2747 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
sahilmgandhi 18:6a4db94011d3 2748 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
sahilmgandhi 18:6a4db94011d3 2749 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2750 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2751 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2752
sahilmgandhi 18:6a4db94011d3 2753 /* Register: GPIOTE_INTENCLR */
sahilmgandhi 18:6a4db94011d3 2754 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 2755
sahilmgandhi 18:6a4db94011d3 2756 /* Bit 31 : Disable interrupt on PORT event. */
sahilmgandhi 18:6a4db94011d3 2757 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
sahilmgandhi 18:6a4db94011d3 2758 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
sahilmgandhi 18:6a4db94011d3 2759 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2760 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2761 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2762
sahilmgandhi 18:6a4db94011d3 2763 /* Bit 3 : Disable interrupt on IN[3] event. */
sahilmgandhi 18:6a4db94011d3 2764 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
sahilmgandhi 18:6a4db94011d3 2765 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
sahilmgandhi 18:6a4db94011d3 2766 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2767 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2768 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2769
sahilmgandhi 18:6a4db94011d3 2770 /* Bit 2 : Disable interrupt on IN[2] event. */
sahilmgandhi 18:6a4db94011d3 2771 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
sahilmgandhi 18:6a4db94011d3 2772 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
sahilmgandhi 18:6a4db94011d3 2773 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2774 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2775 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2776
sahilmgandhi 18:6a4db94011d3 2777 /* Bit 1 : Disable interrupt on IN[1] event. */
sahilmgandhi 18:6a4db94011d3 2778 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
sahilmgandhi 18:6a4db94011d3 2779 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
sahilmgandhi 18:6a4db94011d3 2780 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2781 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2782 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2783
sahilmgandhi 18:6a4db94011d3 2784 /* Bit 0 : Disable interrupt on IN[0] event. */
sahilmgandhi 18:6a4db94011d3 2785 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
sahilmgandhi 18:6a4db94011d3 2786 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
sahilmgandhi 18:6a4db94011d3 2787 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2788 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2789 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2790
sahilmgandhi 18:6a4db94011d3 2791 /* Register: GPIOTE_CONFIG */
sahilmgandhi 18:6a4db94011d3 2792 /* Description: Channel configuration registers. */
sahilmgandhi 18:6a4db94011d3 2793
sahilmgandhi 18:6a4db94011d3 2794 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
sahilmgandhi 18:6a4db94011d3 2795 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
sahilmgandhi 18:6a4db94011d3 2796 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
sahilmgandhi 18:6a4db94011d3 2797 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
sahilmgandhi 18:6a4db94011d3 2798 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
sahilmgandhi 18:6a4db94011d3 2799
sahilmgandhi 18:6a4db94011d3 2800 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
sahilmgandhi 18:6a4db94011d3 2801 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
sahilmgandhi 18:6a4db94011d3 2802 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
sahilmgandhi 18:6a4db94011d3 2803 #define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
sahilmgandhi 18:6a4db94011d3 2804 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
sahilmgandhi 18:6a4db94011d3 2805 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
sahilmgandhi 18:6a4db94011d3 2806 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
sahilmgandhi 18:6a4db94011d3 2807
sahilmgandhi 18:6a4db94011d3 2808 /* Bits 12..8 : Pin select. */
sahilmgandhi 18:6a4db94011d3 2809 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
sahilmgandhi 18:6a4db94011d3 2810 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
sahilmgandhi 18:6a4db94011d3 2811
sahilmgandhi 18:6a4db94011d3 2812 /* Bits 1..0 : Mode */
sahilmgandhi 18:6a4db94011d3 2813 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 2814 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 2815 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 2816 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
sahilmgandhi 18:6a4db94011d3 2817 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
sahilmgandhi 18:6a4db94011d3 2818
sahilmgandhi 18:6a4db94011d3 2819 /* Register: GPIOTE_POWER */
sahilmgandhi 18:6a4db94011d3 2820 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 2821
sahilmgandhi 18:6a4db94011d3 2822 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 2823 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 2824 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 2825 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 2826 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 2827
sahilmgandhi 18:6a4db94011d3 2828
sahilmgandhi 18:6a4db94011d3 2829 /* Peripheral: LPCOMP */
sahilmgandhi 18:6a4db94011d3 2830 /* Description: Low power comparator. */
sahilmgandhi 18:6a4db94011d3 2831
sahilmgandhi 18:6a4db94011d3 2832 /* Register: LPCOMP_SHORTS */
sahilmgandhi 18:6a4db94011d3 2833 /* Description: Shortcuts for the LPCOMP. */
sahilmgandhi 18:6a4db94011d3 2834
sahilmgandhi 18:6a4db94011d3 2835 /* Bit 4 : Shortcut between CROSS event and STOP task. */
sahilmgandhi 18:6a4db94011d3 2836 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
sahilmgandhi 18:6a4db94011d3 2837 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
sahilmgandhi 18:6a4db94011d3 2838 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 2839 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 2840
sahilmgandhi 18:6a4db94011d3 2841 /* Bit 3 : Shortcut between UP event and STOP task. */
sahilmgandhi 18:6a4db94011d3 2842 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
sahilmgandhi 18:6a4db94011d3 2843 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
sahilmgandhi 18:6a4db94011d3 2844 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 2845 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 2846
sahilmgandhi 18:6a4db94011d3 2847 /* Bit 2 : Shortcut between DOWN event and STOP task. */
sahilmgandhi 18:6a4db94011d3 2848 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
sahilmgandhi 18:6a4db94011d3 2849 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
sahilmgandhi 18:6a4db94011d3 2850 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 2851 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 2852
sahilmgandhi 18:6a4db94011d3 2853 /* Bit 1 : Shortcut between RADY event and STOP task. */
sahilmgandhi 18:6a4db94011d3 2854 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
sahilmgandhi 18:6a4db94011d3 2855 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
sahilmgandhi 18:6a4db94011d3 2856 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 2857 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 2858
sahilmgandhi 18:6a4db94011d3 2859 /* Bit 0 : Shortcut between READY event and SAMPLE task. */
sahilmgandhi 18:6a4db94011d3 2860 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 2861 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 2862 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 2863 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 2864
sahilmgandhi 18:6a4db94011d3 2865 /* Register: LPCOMP_INTENSET */
sahilmgandhi 18:6a4db94011d3 2866 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 2867
sahilmgandhi 18:6a4db94011d3 2868 /* Bit 3 : Enable interrupt on CROSS event. */
sahilmgandhi 18:6a4db94011d3 2869 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 2870 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 2871 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2872 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2873 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2874
sahilmgandhi 18:6a4db94011d3 2875 /* Bit 2 : Enable interrupt on UP event. */
sahilmgandhi 18:6a4db94011d3 2876 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 2877 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 2878 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2879 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2880 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2881
sahilmgandhi 18:6a4db94011d3 2882 /* Bit 1 : Enable interrupt on DOWN event. */
sahilmgandhi 18:6a4db94011d3 2883 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 2884 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 2885 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2886 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2887 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2888
sahilmgandhi 18:6a4db94011d3 2889 /* Bit 0 : Enable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 2890 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 2891 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 2892 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2893 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2894 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2895
sahilmgandhi 18:6a4db94011d3 2896 /* Register: LPCOMP_INTENCLR */
sahilmgandhi 18:6a4db94011d3 2897 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 2898
sahilmgandhi 18:6a4db94011d3 2899 /* Bit 3 : Disable interrupt on CROSS event. */
sahilmgandhi 18:6a4db94011d3 2900 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
sahilmgandhi 18:6a4db94011d3 2901 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
sahilmgandhi 18:6a4db94011d3 2902 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2903 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2904 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2905
sahilmgandhi 18:6a4db94011d3 2906 /* Bit 2 : Disable interrupt on UP event. */
sahilmgandhi 18:6a4db94011d3 2907 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
sahilmgandhi 18:6a4db94011d3 2908 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
sahilmgandhi 18:6a4db94011d3 2909 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2910 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2911 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2912
sahilmgandhi 18:6a4db94011d3 2913 /* Bit 1 : Disable interrupt on DOWN event. */
sahilmgandhi 18:6a4db94011d3 2914 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
sahilmgandhi 18:6a4db94011d3 2915 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
sahilmgandhi 18:6a4db94011d3 2916 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2917 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2918 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2919
sahilmgandhi 18:6a4db94011d3 2920 /* Bit 0 : Disable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 2921 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 2922 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 2923 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 2924 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 2925 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 2926
sahilmgandhi 18:6a4db94011d3 2927 /* Register: LPCOMP_RESULT */
sahilmgandhi 18:6a4db94011d3 2928 /* Description: Result of last compare. */
sahilmgandhi 18:6a4db94011d3 2929
sahilmgandhi 18:6a4db94011d3 2930 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
sahilmgandhi 18:6a4db94011d3 2931 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
sahilmgandhi 18:6a4db94011d3 2932 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
sahilmgandhi 18:6a4db94011d3 2933 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
sahilmgandhi 18:6a4db94011d3 2934 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
sahilmgandhi 18:6a4db94011d3 2935
sahilmgandhi 18:6a4db94011d3 2936 /* Register: LPCOMP_ENABLE */
sahilmgandhi 18:6a4db94011d3 2937 /* Description: Enable the LPCOMP. */
sahilmgandhi 18:6a4db94011d3 2938
sahilmgandhi 18:6a4db94011d3 2939 /* Bits 1..0 : Enable or disable LPCOMP. */
sahilmgandhi 18:6a4db94011d3 2940 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 2941 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 2942 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
sahilmgandhi 18:6a4db94011d3 2943 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
sahilmgandhi 18:6a4db94011d3 2944
sahilmgandhi 18:6a4db94011d3 2945 /* Register: LPCOMP_PSEL */
sahilmgandhi 18:6a4db94011d3 2946 /* Description: Input pin select. */
sahilmgandhi 18:6a4db94011d3 2947
sahilmgandhi 18:6a4db94011d3 2948 /* Bits 2..0 : Analog input pin select. */
sahilmgandhi 18:6a4db94011d3 2949 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
sahilmgandhi 18:6a4db94011d3 2950 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
sahilmgandhi 18:6a4db94011d3 2951 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
sahilmgandhi 18:6a4db94011d3 2952 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
sahilmgandhi 18:6a4db94011d3 2953 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
sahilmgandhi 18:6a4db94011d3 2954 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
sahilmgandhi 18:6a4db94011d3 2955 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
sahilmgandhi 18:6a4db94011d3 2956 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
sahilmgandhi 18:6a4db94011d3 2957 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
sahilmgandhi 18:6a4db94011d3 2958 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
sahilmgandhi 18:6a4db94011d3 2959
sahilmgandhi 18:6a4db94011d3 2960 /* Register: LPCOMP_REFSEL */
sahilmgandhi 18:6a4db94011d3 2961 /* Description: Reference select. */
sahilmgandhi 18:6a4db94011d3 2962
sahilmgandhi 18:6a4db94011d3 2963 /* Bits 2..0 : Reference select. */
sahilmgandhi 18:6a4db94011d3 2964 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 2965 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
sahilmgandhi 18:6a4db94011d3 2966 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2967 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2968 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2969 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2970 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2971 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2972 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
sahilmgandhi 18:6a4db94011d3 2973 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
sahilmgandhi 18:6a4db94011d3 2974
sahilmgandhi 18:6a4db94011d3 2975 /* Register: LPCOMP_EXTREFSEL */
sahilmgandhi 18:6a4db94011d3 2976 /* Description: External reference select. */
sahilmgandhi 18:6a4db94011d3 2977
sahilmgandhi 18:6a4db94011d3 2978 /* Bit 0 : External analog reference pin selection. */
sahilmgandhi 18:6a4db94011d3 2979 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 2980 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
sahilmgandhi 18:6a4db94011d3 2981 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
sahilmgandhi 18:6a4db94011d3 2982 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
sahilmgandhi 18:6a4db94011d3 2983
sahilmgandhi 18:6a4db94011d3 2984 /* Register: LPCOMP_ANADETECT */
sahilmgandhi 18:6a4db94011d3 2985 /* Description: Analog detect configuration. */
sahilmgandhi 18:6a4db94011d3 2986
sahilmgandhi 18:6a4db94011d3 2987 /* Bits 1..0 : Analog detect configuration. */
sahilmgandhi 18:6a4db94011d3 2988 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
sahilmgandhi 18:6a4db94011d3 2989 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
sahilmgandhi 18:6a4db94011d3 2990 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
sahilmgandhi 18:6a4db94011d3 2991 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
sahilmgandhi 18:6a4db94011d3 2992 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
sahilmgandhi 18:6a4db94011d3 2993
sahilmgandhi 18:6a4db94011d3 2994 /* Register: LPCOMP_POWER */
sahilmgandhi 18:6a4db94011d3 2995 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 2996
sahilmgandhi 18:6a4db94011d3 2997 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 2998 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 2999 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 3000 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 3001 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 3002
sahilmgandhi 18:6a4db94011d3 3003
sahilmgandhi 18:6a4db94011d3 3004 /* Peripheral: MPU */
sahilmgandhi 18:6a4db94011d3 3005 /* Description: Memory Protection Unit. */
sahilmgandhi 18:6a4db94011d3 3006
sahilmgandhi 18:6a4db94011d3 3007 /* Register: MPU_PERR0 */
sahilmgandhi 18:6a4db94011d3 3008 /* Description: Configuration of peripherals in mpu regions. */
sahilmgandhi 18:6a4db94011d3 3009
sahilmgandhi 18:6a4db94011d3 3010 /* Bit 31 : PPI region configuration. */
sahilmgandhi 18:6a4db94011d3 3011 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
sahilmgandhi 18:6a4db94011d3 3012 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
sahilmgandhi 18:6a4db94011d3 3013 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3014 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3015
sahilmgandhi 18:6a4db94011d3 3016 /* Bit 30 : NVMC region configuration. */
sahilmgandhi 18:6a4db94011d3 3017 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
sahilmgandhi 18:6a4db94011d3 3018 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
sahilmgandhi 18:6a4db94011d3 3019 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3020 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3021
sahilmgandhi 18:6a4db94011d3 3022 /* Bit 19 : LPCOMP region configuration. */
sahilmgandhi 18:6a4db94011d3 3023 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
sahilmgandhi 18:6a4db94011d3 3024 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
sahilmgandhi 18:6a4db94011d3 3025 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3026 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3027
sahilmgandhi 18:6a4db94011d3 3028 /* Bit 18 : QDEC region configuration. */
sahilmgandhi 18:6a4db94011d3 3029 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
sahilmgandhi 18:6a4db94011d3 3030 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
sahilmgandhi 18:6a4db94011d3 3031 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3032 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3033
sahilmgandhi 18:6a4db94011d3 3034 /* Bit 17 : RTC1 region configuration. */
sahilmgandhi 18:6a4db94011d3 3035 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
sahilmgandhi 18:6a4db94011d3 3036 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
sahilmgandhi 18:6a4db94011d3 3037 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3038 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3039
sahilmgandhi 18:6a4db94011d3 3040 /* Bit 16 : WDT region configuration. */
sahilmgandhi 18:6a4db94011d3 3041 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
sahilmgandhi 18:6a4db94011d3 3042 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
sahilmgandhi 18:6a4db94011d3 3043 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3044 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3045
sahilmgandhi 18:6a4db94011d3 3046 /* Bit 15 : CCM and AAR region configuration. */
sahilmgandhi 18:6a4db94011d3 3047 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
sahilmgandhi 18:6a4db94011d3 3048 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
sahilmgandhi 18:6a4db94011d3 3049 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3050 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3051
sahilmgandhi 18:6a4db94011d3 3052 /* Bit 14 : ECB region configuration. */
sahilmgandhi 18:6a4db94011d3 3053 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
sahilmgandhi 18:6a4db94011d3 3054 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
sahilmgandhi 18:6a4db94011d3 3055 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3056 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3057
sahilmgandhi 18:6a4db94011d3 3058 /* Bit 13 : RNG region configuration. */
sahilmgandhi 18:6a4db94011d3 3059 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
sahilmgandhi 18:6a4db94011d3 3060 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
sahilmgandhi 18:6a4db94011d3 3061 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3062 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3063
sahilmgandhi 18:6a4db94011d3 3064 /* Bit 12 : TEMP region configuration. */
sahilmgandhi 18:6a4db94011d3 3065 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
sahilmgandhi 18:6a4db94011d3 3066 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
sahilmgandhi 18:6a4db94011d3 3067 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3068 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3069
sahilmgandhi 18:6a4db94011d3 3070 /* Bit 11 : RTC0 region configuration. */
sahilmgandhi 18:6a4db94011d3 3071 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
sahilmgandhi 18:6a4db94011d3 3072 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
sahilmgandhi 18:6a4db94011d3 3073 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3074 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3075
sahilmgandhi 18:6a4db94011d3 3076 /* Bit 10 : TIMER2 region configuration. */
sahilmgandhi 18:6a4db94011d3 3077 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
sahilmgandhi 18:6a4db94011d3 3078 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
sahilmgandhi 18:6a4db94011d3 3079 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3080 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3081
sahilmgandhi 18:6a4db94011d3 3082 /* Bit 9 : TIMER1 region configuration. */
sahilmgandhi 18:6a4db94011d3 3083 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
sahilmgandhi 18:6a4db94011d3 3084 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
sahilmgandhi 18:6a4db94011d3 3085 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3086 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3087
sahilmgandhi 18:6a4db94011d3 3088 /* Bit 8 : TIMER0 region configuration. */
sahilmgandhi 18:6a4db94011d3 3089 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
sahilmgandhi 18:6a4db94011d3 3090 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
sahilmgandhi 18:6a4db94011d3 3091 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3092 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3093
sahilmgandhi 18:6a4db94011d3 3094 /* Bit 7 : ADC region configuration. */
sahilmgandhi 18:6a4db94011d3 3095 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
sahilmgandhi 18:6a4db94011d3 3096 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
sahilmgandhi 18:6a4db94011d3 3097 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3098 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3099
sahilmgandhi 18:6a4db94011d3 3100 /* Bit 6 : GPIOTE region configuration. */
sahilmgandhi 18:6a4db94011d3 3101 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
sahilmgandhi 18:6a4db94011d3 3102 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
sahilmgandhi 18:6a4db94011d3 3103 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3104 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3105
sahilmgandhi 18:6a4db94011d3 3106 /* Bit 4 : SPI1 and TWI1 region configuration. */
sahilmgandhi 18:6a4db94011d3 3107 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
sahilmgandhi 18:6a4db94011d3 3108 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
sahilmgandhi 18:6a4db94011d3 3109 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3110 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3111
sahilmgandhi 18:6a4db94011d3 3112 /* Bit 3 : SPI0 and TWI0 region configuration. */
sahilmgandhi 18:6a4db94011d3 3113 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
sahilmgandhi 18:6a4db94011d3 3114 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
sahilmgandhi 18:6a4db94011d3 3115 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3116 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3117
sahilmgandhi 18:6a4db94011d3 3118 /* Bit 2 : UART0 region configuration. */
sahilmgandhi 18:6a4db94011d3 3119 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
sahilmgandhi 18:6a4db94011d3 3120 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
sahilmgandhi 18:6a4db94011d3 3121 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3122 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3123
sahilmgandhi 18:6a4db94011d3 3124 /* Bit 1 : RADIO region configuration. */
sahilmgandhi 18:6a4db94011d3 3125 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
sahilmgandhi 18:6a4db94011d3 3126 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
sahilmgandhi 18:6a4db94011d3 3127 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3128 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3129
sahilmgandhi 18:6a4db94011d3 3130 /* Bit 0 : POWER_CLOCK region configuration. */
sahilmgandhi 18:6a4db94011d3 3131 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
sahilmgandhi 18:6a4db94011d3 3132 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
sahilmgandhi 18:6a4db94011d3 3133 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
sahilmgandhi 18:6a4db94011d3 3134 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
sahilmgandhi 18:6a4db94011d3 3135
sahilmgandhi 18:6a4db94011d3 3136 /* Register: MPU_PROTENSET0 */
sahilmgandhi 18:6a4db94011d3 3137 /* Description: Erase and write protection bit enable set register. */
sahilmgandhi 18:6a4db94011d3 3138
sahilmgandhi 18:6a4db94011d3 3139 /* Bit 31 : Protection enable for region 31. */
sahilmgandhi 18:6a4db94011d3 3140 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
sahilmgandhi 18:6a4db94011d3 3141 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
sahilmgandhi 18:6a4db94011d3 3142 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3143 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3144 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3145
sahilmgandhi 18:6a4db94011d3 3146 /* Bit 30 : Protection enable for region 30. */
sahilmgandhi 18:6a4db94011d3 3147 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
sahilmgandhi 18:6a4db94011d3 3148 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
sahilmgandhi 18:6a4db94011d3 3149 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3150 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3151 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3152
sahilmgandhi 18:6a4db94011d3 3153 /* Bit 29 : Protection enable for region 29. */
sahilmgandhi 18:6a4db94011d3 3154 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
sahilmgandhi 18:6a4db94011d3 3155 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
sahilmgandhi 18:6a4db94011d3 3156 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3157 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3158 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3159
sahilmgandhi 18:6a4db94011d3 3160 /* Bit 28 : Protection enable for region 28. */
sahilmgandhi 18:6a4db94011d3 3161 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
sahilmgandhi 18:6a4db94011d3 3162 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
sahilmgandhi 18:6a4db94011d3 3163 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3164 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3165 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3166
sahilmgandhi 18:6a4db94011d3 3167 /* Bit 27 : Protection enable for region 27. */
sahilmgandhi 18:6a4db94011d3 3168 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
sahilmgandhi 18:6a4db94011d3 3169 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
sahilmgandhi 18:6a4db94011d3 3170 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3171 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3172 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3173
sahilmgandhi 18:6a4db94011d3 3174 /* Bit 26 : Protection enable for region 26. */
sahilmgandhi 18:6a4db94011d3 3175 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
sahilmgandhi 18:6a4db94011d3 3176 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
sahilmgandhi 18:6a4db94011d3 3177 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3178 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3179 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3180
sahilmgandhi 18:6a4db94011d3 3181 /* Bit 25 : Protection enable for region 25. */
sahilmgandhi 18:6a4db94011d3 3182 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
sahilmgandhi 18:6a4db94011d3 3183 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
sahilmgandhi 18:6a4db94011d3 3184 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3185 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3186 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3187
sahilmgandhi 18:6a4db94011d3 3188 /* Bit 24 : Protection enable for region 24. */
sahilmgandhi 18:6a4db94011d3 3189 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
sahilmgandhi 18:6a4db94011d3 3190 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
sahilmgandhi 18:6a4db94011d3 3191 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3192 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3193 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3194
sahilmgandhi 18:6a4db94011d3 3195 /* Bit 23 : Protection enable for region 23. */
sahilmgandhi 18:6a4db94011d3 3196 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
sahilmgandhi 18:6a4db94011d3 3197 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
sahilmgandhi 18:6a4db94011d3 3198 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3199 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3200 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3201
sahilmgandhi 18:6a4db94011d3 3202 /* Bit 22 : Protection enable for region 22. */
sahilmgandhi 18:6a4db94011d3 3203 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
sahilmgandhi 18:6a4db94011d3 3204 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
sahilmgandhi 18:6a4db94011d3 3205 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3206 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3207 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3208
sahilmgandhi 18:6a4db94011d3 3209 /* Bit 21 : Protection enable for region 21. */
sahilmgandhi 18:6a4db94011d3 3210 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
sahilmgandhi 18:6a4db94011d3 3211 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
sahilmgandhi 18:6a4db94011d3 3212 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3213 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3214 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3215
sahilmgandhi 18:6a4db94011d3 3216 /* Bit 20 : Protection enable for region 20. */
sahilmgandhi 18:6a4db94011d3 3217 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
sahilmgandhi 18:6a4db94011d3 3218 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
sahilmgandhi 18:6a4db94011d3 3219 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3220 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3221 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3222
sahilmgandhi 18:6a4db94011d3 3223 /* Bit 19 : Protection enable for region 19. */
sahilmgandhi 18:6a4db94011d3 3224 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
sahilmgandhi 18:6a4db94011d3 3225 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
sahilmgandhi 18:6a4db94011d3 3226 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3227 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3228 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3229
sahilmgandhi 18:6a4db94011d3 3230 /* Bit 18 : Protection enable for region 18. */
sahilmgandhi 18:6a4db94011d3 3231 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
sahilmgandhi 18:6a4db94011d3 3232 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
sahilmgandhi 18:6a4db94011d3 3233 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3234 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3235 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3236
sahilmgandhi 18:6a4db94011d3 3237 /* Bit 17 : Protection enable for region 17. */
sahilmgandhi 18:6a4db94011d3 3238 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
sahilmgandhi 18:6a4db94011d3 3239 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
sahilmgandhi 18:6a4db94011d3 3240 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3241 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3242 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3243
sahilmgandhi 18:6a4db94011d3 3244 /* Bit 16 : Protection enable for region 16. */
sahilmgandhi 18:6a4db94011d3 3245 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
sahilmgandhi 18:6a4db94011d3 3246 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
sahilmgandhi 18:6a4db94011d3 3247 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3248 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3249 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3250
sahilmgandhi 18:6a4db94011d3 3251 /* Bit 15 : Protection enable for region 15. */
sahilmgandhi 18:6a4db94011d3 3252 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
sahilmgandhi 18:6a4db94011d3 3253 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
sahilmgandhi 18:6a4db94011d3 3254 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3255 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3256 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3257
sahilmgandhi 18:6a4db94011d3 3258 /* Bit 14 : Protection enable for region 14. */
sahilmgandhi 18:6a4db94011d3 3259 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
sahilmgandhi 18:6a4db94011d3 3260 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
sahilmgandhi 18:6a4db94011d3 3261 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3262 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3263 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3264
sahilmgandhi 18:6a4db94011d3 3265 /* Bit 13 : Protection enable for region 13. */
sahilmgandhi 18:6a4db94011d3 3266 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
sahilmgandhi 18:6a4db94011d3 3267 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
sahilmgandhi 18:6a4db94011d3 3268 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3269 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3270 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3271
sahilmgandhi 18:6a4db94011d3 3272 /* Bit 12 : Protection enable for region 12. */
sahilmgandhi 18:6a4db94011d3 3273 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
sahilmgandhi 18:6a4db94011d3 3274 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
sahilmgandhi 18:6a4db94011d3 3275 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3276 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3277 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3278
sahilmgandhi 18:6a4db94011d3 3279 /* Bit 11 : Protection enable for region 11. */
sahilmgandhi 18:6a4db94011d3 3280 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
sahilmgandhi 18:6a4db94011d3 3281 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
sahilmgandhi 18:6a4db94011d3 3282 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3283 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3284 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3285
sahilmgandhi 18:6a4db94011d3 3286 /* Bit 10 : Protection enable for region 10. */
sahilmgandhi 18:6a4db94011d3 3287 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
sahilmgandhi 18:6a4db94011d3 3288 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
sahilmgandhi 18:6a4db94011d3 3289 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3290 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3291 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3292
sahilmgandhi 18:6a4db94011d3 3293 /* Bit 9 : Protection enable for region 9. */
sahilmgandhi 18:6a4db94011d3 3294 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
sahilmgandhi 18:6a4db94011d3 3295 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
sahilmgandhi 18:6a4db94011d3 3296 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3297 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3298 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3299
sahilmgandhi 18:6a4db94011d3 3300 /* Bit 8 : Protection enable for region 8. */
sahilmgandhi 18:6a4db94011d3 3301 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
sahilmgandhi 18:6a4db94011d3 3302 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
sahilmgandhi 18:6a4db94011d3 3303 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3304 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3305 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3306
sahilmgandhi 18:6a4db94011d3 3307 /* Bit 7 : Protection enable for region 7. */
sahilmgandhi 18:6a4db94011d3 3308 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
sahilmgandhi 18:6a4db94011d3 3309 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
sahilmgandhi 18:6a4db94011d3 3310 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3311 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3312 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3313
sahilmgandhi 18:6a4db94011d3 3314 /* Bit 6 : Protection enable for region 6. */
sahilmgandhi 18:6a4db94011d3 3315 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
sahilmgandhi 18:6a4db94011d3 3316 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
sahilmgandhi 18:6a4db94011d3 3317 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3318 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3319 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3320
sahilmgandhi 18:6a4db94011d3 3321 /* Bit 5 : Protection enable for region 5. */
sahilmgandhi 18:6a4db94011d3 3322 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
sahilmgandhi 18:6a4db94011d3 3323 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
sahilmgandhi 18:6a4db94011d3 3324 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3325 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3326 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3327
sahilmgandhi 18:6a4db94011d3 3328 /* Bit 4 : Protection enable for region 4. */
sahilmgandhi 18:6a4db94011d3 3329 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
sahilmgandhi 18:6a4db94011d3 3330 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
sahilmgandhi 18:6a4db94011d3 3331 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3332 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3333 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3334
sahilmgandhi 18:6a4db94011d3 3335 /* Bit 3 : Protection enable for region 3. */
sahilmgandhi 18:6a4db94011d3 3336 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
sahilmgandhi 18:6a4db94011d3 3337 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
sahilmgandhi 18:6a4db94011d3 3338 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3339 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3340 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3341
sahilmgandhi 18:6a4db94011d3 3342 /* Bit 2 : Protection enable for region 2. */
sahilmgandhi 18:6a4db94011d3 3343 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
sahilmgandhi 18:6a4db94011d3 3344 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
sahilmgandhi 18:6a4db94011d3 3345 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3346 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3347 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3348
sahilmgandhi 18:6a4db94011d3 3349 /* Bit 1 : Protection enable for region 1. */
sahilmgandhi 18:6a4db94011d3 3350 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
sahilmgandhi 18:6a4db94011d3 3351 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
sahilmgandhi 18:6a4db94011d3 3352 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3353 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3354 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3355
sahilmgandhi 18:6a4db94011d3 3356 /* Bit 0 : Protection enable for region 0. */
sahilmgandhi 18:6a4db94011d3 3357 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
sahilmgandhi 18:6a4db94011d3 3358 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
sahilmgandhi 18:6a4db94011d3 3359 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3360 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3361 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3362
sahilmgandhi 18:6a4db94011d3 3363 /* Register: MPU_PROTENSET1 */
sahilmgandhi 18:6a4db94011d3 3364 /* Description: Erase and write protection bit enable set register. */
sahilmgandhi 18:6a4db94011d3 3365
sahilmgandhi 18:6a4db94011d3 3366 /* Bit 31 : Protection enable for region 63. */
sahilmgandhi 18:6a4db94011d3 3367 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
sahilmgandhi 18:6a4db94011d3 3368 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
sahilmgandhi 18:6a4db94011d3 3369 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3370 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3371 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3372
sahilmgandhi 18:6a4db94011d3 3373 /* Bit 30 : Protection enable for region 62. */
sahilmgandhi 18:6a4db94011d3 3374 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
sahilmgandhi 18:6a4db94011d3 3375 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
sahilmgandhi 18:6a4db94011d3 3376 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3377 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3378 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3379
sahilmgandhi 18:6a4db94011d3 3380 /* Bit 29 : Protection enable for region 61. */
sahilmgandhi 18:6a4db94011d3 3381 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
sahilmgandhi 18:6a4db94011d3 3382 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
sahilmgandhi 18:6a4db94011d3 3383 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3384 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3385 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3386
sahilmgandhi 18:6a4db94011d3 3387 /* Bit 28 : Protection enable for region 60. */
sahilmgandhi 18:6a4db94011d3 3388 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
sahilmgandhi 18:6a4db94011d3 3389 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
sahilmgandhi 18:6a4db94011d3 3390 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3391 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3392 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3393
sahilmgandhi 18:6a4db94011d3 3394 /* Bit 27 : Protection enable for region 59. */
sahilmgandhi 18:6a4db94011d3 3395 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
sahilmgandhi 18:6a4db94011d3 3396 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
sahilmgandhi 18:6a4db94011d3 3397 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3398 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3399 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3400
sahilmgandhi 18:6a4db94011d3 3401 /* Bit 26 : Protection enable for region 58. */
sahilmgandhi 18:6a4db94011d3 3402 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
sahilmgandhi 18:6a4db94011d3 3403 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
sahilmgandhi 18:6a4db94011d3 3404 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3405 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3406 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3407
sahilmgandhi 18:6a4db94011d3 3408 /* Bit 25 : Protection enable for region 57. */
sahilmgandhi 18:6a4db94011d3 3409 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
sahilmgandhi 18:6a4db94011d3 3410 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
sahilmgandhi 18:6a4db94011d3 3411 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3412 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3413 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3414
sahilmgandhi 18:6a4db94011d3 3415 /* Bit 24 : Protection enable for region 56. */
sahilmgandhi 18:6a4db94011d3 3416 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
sahilmgandhi 18:6a4db94011d3 3417 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
sahilmgandhi 18:6a4db94011d3 3418 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3419 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3420 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3421
sahilmgandhi 18:6a4db94011d3 3422 /* Bit 23 : Protection enable for region 55. */
sahilmgandhi 18:6a4db94011d3 3423 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
sahilmgandhi 18:6a4db94011d3 3424 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
sahilmgandhi 18:6a4db94011d3 3425 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3426 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3427 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3428
sahilmgandhi 18:6a4db94011d3 3429 /* Bit 22 : Protection enable for region 54. */
sahilmgandhi 18:6a4db94011d3 3430 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
sahilmgandhi 18:6a4db94011d3 3431 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
sahilmgandhi 18:6a4db94011d3 3432 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3433 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3434 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3435
sahilmgandhi 18:6a4db94011d3 3436 /* Bit 21 : Protection enable for region 53. */
sahilmgandhi 18:6a4db94011d3 3437 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
sahilmgandhi 18:6a4db94011d3 3438 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
sahilmgandhi 18:6a4db94011d3 3439 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3440 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3441 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3442
sahilmgandhi 18:6a4db94011d3 3443 /* Bit 20 : Protection enable for region 52. */
sahilmgandhi 18:6a4db94011d3 3444 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
sahilmgandhi 18:6a4db94011d3 3445 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
sahilmgandhi 18:6a4db94011d3 3446 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3447 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3448 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3449
sahilmgandhi 18:6a4db94011d3 3450 /* Bit 19 : Protection enable for region 51. */
sahilmgandhi 18:6a4db94011d3 3451 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
sahilmgandhi 18:6a4db94011d3 3452 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
sahilmgandhi 18:6a4db94011d3 3453 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3454 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3455 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3456
sahilmgandhi 18:6a4db94011d3 3457 /* Bit 18 : Protection enable for region 50. */
sahilmgandhi 18:6a4db94011d3 3458 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
sahilmgandhi 18:6a4db94011d3 3459 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
sahilmgandhi 18:6a4db94011d3 3460 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3461 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3462 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3463
sahilmgandhi 18:6a4db94011d3 3464 /* Bit 17 : Protection enable for region 49. */
sahilmgandhi 18:6a4db94011d3 3465 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
sahilmgandhi 18:6a4db94011d3 3466 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
sahilmgandhi 18:6a4db94011d3 3467 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3468 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3469 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3470
sahilmgandhi 18:6a4db94011d3 3471 /* Bit 16 : Protection enable for region 48. */
sahilmgandhi 18:6a4db94011d3 3472 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
sahilmgandhi 18:6a4db94011d3 3473 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
sahilmgandhi 18:6a4db94011d3 3474 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3475 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3476 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3477
sahilmgandhi 18:6a4db94011d3 3478 /* Bit 15 : Protection enable for region 47. */
sahilmgandhi 18:6a4db94011d3 3479 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
sahilmgandhi 18:6a4db94011d3 3480 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
sahilmgandhi 18:6a4db94011d3 3481 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3482 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3483 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3484
sahilmgandhi 18:6a4db94011d3 3485 /* Bit 14 : Protection enable for region 46. */
sahilmgandhi 18:6a4db94011d3 3486 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
sahilmgandhi 18:6a4db94011d3 3487 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
sahilmgandhi 18:6a4db94011d3 3488 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3489 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3490 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3491
sahilmgandhi 18:6a4db94011d3 3492 /* Bit 13 : Protection enable for region 45. */
sahilmgandhi 18:6a4db94011d3 3493 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
sahilmgandhi 18:6a4db94011d3 3494 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
sahilmgandhi 18:6a4db94011d3 3495 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3496 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3497 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3498
sahilmgandhi 18:6a4db94011d3 3499 /* Bit 12 : Protection enable for region 44. */
sahilmgandhi 18:6a4db94011d3 3500 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
sahilmgandhi 18:6a4db94011d3 3501 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
sahilmgandhi 18:6a4db94011d3 3502 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3503 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3504 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3505
sahilmgandhi 18:6a4db94011d3 3506 /* Bit 11 : Protection enable for region 43. */
sahilmgandhi 18:6a4db94011d3 3507 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
sahilmgandhi 18:6a4db94011d3 3508 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
sahilmgandhi 18:6a4db94011d3 3509 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3510 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3511 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3512
sahilmgandhi 18:6a4db94011d3 3513 /* Bit 10 : Protection enable for region 42. */
sahilmgandhi 18:6a4db94011d3 3514 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
sahilmgandhi 18:6a4db94011d3 3515 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
sahilmgandhi 18:6a4db94011d3 3516 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3517 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3518 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3519
sahilmgandhi 18:6a4db94011d3 3520 /* Bit 9 : Protection enable for region 41. */
sahilmgandhi 18:6a4db94011d3 3521 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
sahilmgandhi 18:6a4db94011d3 3522 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
sahilmgandhi 18:6a4db94011d3 3523 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3524 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3525 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3526
sahilmgandhi 18:6a4db94011d3 3527 /* Bit 8 : Protection enable for region 40. */
sahilmgandhi 18:6a4db94011d3 3528 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
sahilmgandhi 18:6a4db94011d3 3529 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
sahilmgandhi 18:6a4db94011d3 3530 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3531 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3532 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3533
sahilmgandhi 18:6a4db94011d3 3534 /* Bit 7 : Protection enable for region 39. */
sahilmgandhi 18:6a4db94011d3 3535 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
sahilmgandhi 18:6a4db94011d3 3536 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
sahilmgandhi 18:6a4db94011d3 3537 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3538 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3539 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3540
sahilmgandhi 18:6a4db94011d3 3541 /* Bit 6 : Protection enable for region 38. */
sahilmgandhi 18:6a4db94011d3 3542 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
sahilmgandhi 18:6a4db94011d3 3543 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
sahilmgandhi 18:6a4db94011d3 3544 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3545 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3546 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3547
sahilmgandhi 18:6a4db94011d3 3548 /* Bit 5 : Protection enable for region 37. */
sahilmgandhi 18:6a4db94011d3 3549 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
sahilmgandhi 18:6a4db94011d3 3550 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
sahilmgandhi 18:6a4db94011d3 3551 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3552 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3553 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3554
sahilmgandhi 18:6a4db94011d3 3555 /* Bit 4 : Protection enable for region 36. */
sahilmgandhi 18:6a4db94011d3 3556 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
sahilmgandhi 18:6a4db94011d3 3557 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
sahilmgandhi 18:6a4db94011d3 3558 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3559 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3560 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3561
sahilmgandhi 18:6a4db94011d3 3562 /* Bit 3 : Protection enable for region 35. */
sahilmgandhi 18:6a4db94011d3 3563 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
sahilmgandhi 18:6a4db94011d3 3564 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
sahilmgandhi 18:6a4db94011d3 3565 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3566 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3567 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3568
sahilmgandhi 18:6a4db94011d3 3569 /* Bit 2 : Protection enable for region 34. */
sahilmgandhi 18:6a4db94011d3 3570 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
sahilmgandhi 18:6a4db94011d3 3571 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
sahilmgandhi 18:6a4db94011d3 3572 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3573 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3574 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3575
sahilmgandhi 18:6a4db94011d3 3576 /* Bit 1 : Protection enable for region 33. */
sahilmgandhi 18:6a4db94011d3 3577 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
sahilmgandhi 18:6a4db94011d3 3578 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
sahilmgandhi 18:6a4db94011d3 3579 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3580 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3581 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3582
sahilmgandhi 18:6a4db94011d3 3583 /* Bit 0 : Protection enable for region 32. */
sahilmgandhi 18:6a4db94011d3 3584 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
sahilmgandhi 18:6a4db94011d3 3585 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
sahilmgandhi 18:6a4db94011d3 3586 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3587 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3588 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
sahilmgandhi 18:6a4db94011d3 3589
sahilmgandhi 18:6a4db94011d3 3590 /* Register: MPU_DISABLEINDEBUG */
sahilmgandhi 18:6a4db94011d3 3591 /* Description: Disable erase and write protection mechanism in debug mode. */
sahilmgandhi 18:6a4db94011d3 3592
sahilmgandhi 18:6a4db94011d3 3593 /* Bit 0 : Disable protection mechanism in debug mode. */
sahilmgandhi 18:6a4db94011d3 3594 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
sahilmgandhi 18:6a4db94011d3 3595 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
sahilmgandhi 18:6a4db94011d3 3596 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
sahilmgandhi 18:6a4db94011d3 3597 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
sahilmgandhi 18:6a4db94011d3 3598
sahilmgandhi 18:6a4db94011d3 3599 /* Register: MPU_PROTBLOCKSIZE */
sahilmgandhi 18:6a4db94011d3 3600 /* Description: Erase and write protection block size. */
sahilmgandhi 18:6a4db94011d3 3601
sahilmgandhi 18:6a4db94011d3 3602 /* Bits 1..0 : Erase and write protection block size. */
sahilmgandhi 18:6a4db94011d3 3603 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
sahilmgandhi 18:6a4db94011d3 3604 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
sahilmgandhi 18:6a4db94011d3 3605 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
sahilmgandhi 18:6a4db94011d3 3606
sahilmgandhi 18:6a4db94011d3 3607
sahilmgandhi 18:6a4db94011d3 3608 /* Peripheral: NVMC */
sahilmgandhi 18:6a4db94011d3 3609 /* Description: Non Volatile Memory Controller. */
sahilmgandhi 18:6a4db94011d3 3610
sahilmgandhi 18:6a4db94011d3 3611 /* Register: NVMC_READY */
sahilmgandhi 18:6a4db94011d3 3612 /* Description: Ready flag. */
sahilmgandhi 18:6a4db94011d3 3613
sahilmgandhi 18:6a4db94011d3 3614 /* Bit 0 : NVMC ready. */
sahilmgandhi 18:6a4db94011d3 3615 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 3616 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 3617 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
sahilmgandhi 18:6a4db94011d3 3618 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
sahilmgandhi 18:6a4db94011d3 3619
sahilmgandhi 18:6a4db94011d3 3620 /* Register: NVMC_CONFIG */
sahilmgandhi 18:6a4db94011d3 3621 /* Description: Configuration register. */
sahilmgandhi 18:6a4db94011d3 3622
sahilmgandhi 18:6a4db94011d3 3623 /* Bits 1..0 : Program write enable. */
sahilmgandhi 18:6a4db94011d3 3624 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
sahilmgandhi 18:6a4db94011d3 3625 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
sahilmgandhi 18:6a4db94011d3 3626 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
sahilmgandhi 18:6a4db94011d3 3627 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
sahilmgandhi 18:6a4db94011d3 3628 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
sahilmgandhi 18:6a4db94011d3 3629
sahilmgandhi 18:6a4db94011d3 3630 /* Register: NVMC_ERASEALL */
sahilmgandhi 18:6a4db94011d3 3631 /* Description: Register for erasing all non-volatile user memory. */
sahilmgandhi 18:6a4db94011d3 3632
sahilmgandhi 18:6a4db94011d3 3633 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
sahilmgandhi 18:6a4db94011d3 3634 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
sahilmgandhi 18:6a4db94011d3 3635 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
sahilmgandhi 18:6a4db94011d3 3636 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
sahilmgandhi 18:6a4db94011d3 3637 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
sahilmgandhi 18:6a4db94011d3 3638
sahilmgandhi 18:6a4db94011d3 3639 /* Register: NVMC_ERASEUICR */
sahilmgandhi 18:6a4db94011d3 3640 /* Description: Register for start erasing User Information Congfiguration Registers. */
sahilmgandhi 18:6a4db94011d3 3641
sahilmgandhi 18:6a4db94011d3 3642 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
sahilmgandhi 18:6a4db94011d3 3643 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
sahilmgandhi 18:6a4db94011d3 3644 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
sahilmgandhi 18:6a4db94011d3 3645 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
sahilmgandhi 18:6a4db94011d3 3646 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
sahilmgandhi 18:6a4db94011d3 3647
sahilmgandhi 18:6a4db94011d3 3648
sahilmgandhi 18:6a4db94011d3 3649 /* Peripheral: POWER */
sahilmgandhi 18:6a4db94011d3 3650 /* Description: Power Control. */
sahilmgandhi 18:6a4db94011d3 3651
sahilmgandhi 18:6a4db94011d3 3652 /* Register: POWER_INTENSET */
sahilmgandhi 18:6a4db94011d3 3653 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 3654
sahilmgandhi 18:6a4db94011d3 3655 /* Bit 2 : Enable interrupt on POFWARN event. */
sahilmgandhi 18:6a4db94011d3 3656 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 3657 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 3658 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 3659 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 3660 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 3661
sahilmgandhi 18:6a4db94011d3 3662 /* Register: POWER_INTENCLR */
sahilmgandhi 18:6a4db94011d3 3663 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 3664
sahilmgandhi 18:6a4db94011d3 3665 /* Bit 2 : Disable interrupt on POFWARN event. */
sahilmgandhi 18:6a4db94011d3 3666 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 3667 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
sahilmgandhi 18:6a4db94011d3 3668 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 3669 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 3670 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 3671
sahilmgandhi 18:6a4db94011d3 3672 /* Register: POWER_RESETREAS */
sahilmgandhi 18:6a4db94011d3 3673 /* Description: Reset reason. */
sahilmgandhi 18:6a4db94011d3 3674
sahilmgandhi 18:6a4db94011d3 3675 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
sahilmgandhi 18:6a4db94011d3 3676 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
sahilmgandhi 18:6a4db94011d3 3677 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
sahilmgandhi 18:6a4db94011d3 3678 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3679 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3680
sahilmgandhi 18:6a4db94011d3 3681 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
sahilmgandhi 18:6a4db94011d3 3682 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
sahilmgandhi 18:6a4db94011d3 3683 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
sahilmgandhi 18:6a4db94011d3 3684 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3685 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3686
sahilmgandhi 18:6a4db94011d3 3687 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
sahilmgandhi 18:6a4db94011d3 3688 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
sahilmgandhi 18:6a4db94011d3 3689 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
sahilmgandhi 18:6a4db94011d3 3690 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3691 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3692
sahilmgandhi 18:6a4db94011d3 3693 /* Bit 3 : Reset from CPU lock-up detected. */
sahilmgandhi 18:6a4db94011d3 3694 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
sahilmgandhi 18:6a4db94011d3 3695 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
sahilmgandhi 18:6a4db94011d3 3696 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3697 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3698
sahilmgandhi 18:6a4db94011d3 3699 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
sahilmgandhi 18:6a4db94011d3 3700 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
sahilmgandhi 18:6a4db94011d3 3701 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
sahilmgandhi 18:6a4db94011d3 3702 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3703 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3704
sahilmgandhi 18:6a4db94011d3 3705 /* Bit 1 : Reset from watchdog detected. */
sahilmgandhi 18:6a4db94011d3 3706 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
sahilmgandhi 18:6a4db94011d3 3707 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
sahilmgandhi 18:6a4db94011d3 3708 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3709 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3710
sahilmgandhi 18:6a4db94011d3 3711 /* Bit 0 : Reset from pin-reset detected. */
sahilmgandhi 18:6a4db94011d3 3712 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
sahilmgandhi 18:6a4db94011d3 3713 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
sahilmgandhi 18:6a4db94011d3 3714 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
sahilmgandhi 18:6a4db94011d3 3715 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
sahilmgandhi 18:6a4db94011d3 3716
sahilmgandhi 18:6a4db94011d3 3717 /* Register: POWER_RAMSTATUS */
sahilmgandhi 18:6a4db94011d3 3718 /* Description: Ram status register. */
sahilmgandhi 18:6a4db94011d3 3719
sahilmgandhi 18:6a4db94011d3 3720 /* Bit 3 : RAM block 3 status. */
sahilmgandhi 18:6a4db94011d3 3721 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
sahilmgandhi 18:6a4db94011d3 3722 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
sahilmgandhi 18:6a4db94011d3 3723 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
sahilmgandhi 18:6a4db94011d3 3724 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
sahilmgandhi 18:6a4db94011d3 3725
sahilmgandhi 18:6a4db94011d3 3726 /* Bit 2 : RAM block 2 status. */
sahilmgandhi 18:6a4db94011d3 3727 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
sahilmgandhi 18:6a4db94011d3 3728 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
sahilmgandhi 18:6a4db94011d3 3729 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
sahilmgandhi 18:6a4db94011d3 3730 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
sahilmgandhi 18:6a4db94011d3 3731
sahilmgandhi 18:6a4db94011d3 3732 /* Bit 1 : RAM block 1 status. */
sahilmgandhi 18:6a4db94011d3 3733 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
sahilmgandhi 18:6a4db94011d3 3734 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
sahilmgandhi 18:6a4db94011d3 3735 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
sahilmgandhi 18:6a4db94011d3 3736 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
sahilmgandhi 18:6a4db94011d3 3737
sahilmgandhi 18:6a4db94011d3 3738 /* Bit 0 : RAM block 0 status. */
sahilmgandhi 18:6a4db94011d3 3739 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
sahilmgandhi 18:6a4db94011d3 3740 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
sahilmgandhi 18:6a4db94011d3 3741 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
sahilmgandhi 18:6a4db94011d3 3742 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
sahilmgandhi 18:6a4db94011d3 3743
sahilmgandhi 18:6a4db94011d3 3744 /* Register: POWER_SYSTEMOFF */
sahilmgandhi 18:6a4db94011d3 3745 /* Description: System off register. */
sahilmgandhi 18:6a4db94011d3 3746
sahilmgandhi 18:6a4db94011d3 3747 /* Bit 0 : Enter system off mode. */
sahilmgandhi 18:6a4db94011d3 3748 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
sahilmgandhi 18:6a4db94011d3 3749 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
sahilmgandhi 18:6a4db94011d3 3750 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
sahilmgandhi 18:6a4db94011d3 3751
sahilmgandhi 18:6a4db94011d3 3752 /* Register: POWER_POFCON */
sahilmgandhi 18:6a4db94011d3 3753 /* Description: Power failure configuration. */
sahilmgandhi 18:6a4db94011d3 3754
sahilmgandhi 18:6a4db94011d3 3755 /* Bits 2..1 : Set threshold level. */
sahilmgandhi 18:6a4db94011d3 3756 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
sahilmgandhi 18:6a4db94011d3 3757 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
sahilmgandhi 18:6a4db94011d3 3758 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
sahilmgandhi 18:6a4db94011d3 3759 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
sahilmgandhi 18:6a4db94011d3 3760 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
sahilmgandhi 18:6a4db94011d3 3761 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
sahilmgandhi 18:6a4db94011d3 3762
sahilmgandhi 18:6a4db94011d3 3763 /* Bit 0 : Power failure comparator enable. */
sahilmgandhi 18:6a4db94011d3 3764 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
sahilmgandhi 18:6a4db94011d3 3765 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
sahilmgandhi 18:6a4db94011d3 3766 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 3767 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 3768
sahilmgandhi 18:6a4db94011d3 3769 /* Register: POWER_GPREGRET */
sahilmgandhi 18:6a4db94011d3 3770 /* Description: General purpose retention register. This register is a retained register. */
sahilmgandhi 18:6a4db94011d3 3771
sahilmgandhi 18:6a4db94011d3 3772 /* Bits 7..0 : General purpose retention register. */
sahilmgandhi 18:6a4db94011d3 3773 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
sahilmgandhi 18:6a4db94011d3 3774 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
sahilmgandhi 18:6a4db94011d3 3775
sahilmgandhi 18:6a4db94011d3 3776 /* Register: POWER_RAMON */
sahilmgandhi 18:6a4db94011d3 3777 /* Description: Ram on/off. */
sahilmgandhi 18:6a4db94011d3 3778
sahilmgandhi 18:6a4db94011d3 3779 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3780 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
sahilmgandhi 18:6a4db94011d3 3781 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
sahilmgandhi 18:6a4db94011d3 3782 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3783 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3784
sahilmgandhi 18:6a4db94011d3 3785 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3786 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
sahilmgandhi 18:6a4db94011d3 3787 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
sahilmgandhi 18:6a4db94011d3 3788 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3789 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3790
sahilmgandhi 18:6a4db94011d3 3791 /* Bit 1 : RAM block 1 behaviour in ON mode. */
sahilmgandhi 18:6a4db94011d3 3792 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
sahilmgandhi 18:6a4db94011d3 3793 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
sahilmgandhi 18:6a4db94011d3 3794 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
sahilmgandhi 18:6a4db94011d3 3795 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
sahilmgandhi 18:6a4db94011d3 3796
sahilmgandhi 18:6a4db94011d3 3797 /* Bit 0 : RAM block 0 behaviour in ON mode. */
sahilmgandhi 18:6a4db94011d3 3798 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
sahilmgandhi 18:6a4db94011d3 3799 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
sahilmgandhi 18:6a4db94011d3 3800 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
sahilmgandhi 18:6a4db94011d3 3801 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
sahilmgandhi 18:6a4db94011d3 3802
sahilmgandhi 18:6a4db94011d3 3803 /* Register: POWER_RESET */
sahilmgandhi 18:6a4db94011d3 3804 /* Description: Pin reset functionality configuration register. This register is a retained register. */
sahilmgandhi 18:6a4db94011d3 3805
sahilmgandhi 18:6a4db94011d3 3806 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
sahilmgandhi 18:6a4db94011d3 3807 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
sahilmgandhi 18:6a4db94011d3 3808 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
sahilmgandhi 18:6a4db94011d3 3809 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
sahilmgandhi 18:6a4db94011d3 3810 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
sahilmgandhi 18:6a4db94011d3 3811
sahilmgandhi 18:6a4db94011d3 3812 /* Register: POWER_RAMONB */
sahilmgandhi 18:6a4db94011d3 3813 /* Description: Ram on/off. */
sahilmgandhi 18:6a4db94011d3 3814
sahilmgandhi 18:6a4db94011d3 3815 /* Bit 17 : RAM block 3 behaviour in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3816 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
sahilmgandhi 18:6a4db94011d3 3817 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
sahilmgandhi 18:6a4db94011d3 3818 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3819 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3820
sahilmgandhi 18:6a4db94011d3 3821 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3822 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
sahilmgandhi 18:6a4db94011d3 3823 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
sahilmgandhi 18:6a4db94011d3 3824 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3825 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
sahilmgandhi 18:6a4db94011d3 3826
sahilmgandhi 18:6a4db94011d3 3827 /* Bit 1 : RAM block 3 behaviour in ON mode. */
sahilmgandhi 18:6a4db94011d3 3828 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
sahilmgandhi 18:6a4db94011d3 3829 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
sahilmgandhi 18:6a4db94011d3 3830 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
sahilmgandhi 18:6a4db94011d3 3831 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
sahilmgandhi 18:6a4db94011d3 3832
sahilmgandhi 18:6a4db94011d3 3833 /* Bit 0 : RAM block 2 behaviour in ON mode. */
sahilmgandhi 18:6a4db94011d3 3834 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
sahilmgandhi 18:6a4db94011d3 3835 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
sahilmgandhi 18:6a4db94011d3 3836 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
sahilmgandhi 18:6a4db94011d3 3837 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
sahilmgandhi 18:6a4db94011d3 3838
sahilmgandhi 18:6a4db94011d3 3839 /* Register: POWER_DCDCEN */
sahilmgandhi 18:6a4db94011d3 3840 /* Description: DCDC converter enable configuration register. */
sahilmgandhi 18:6a4db94011d3 3841
sahilmgandhi 18:6a4db94011d3 3842 /* Bit 0 : Enable DCDC converter. */
sahilmgandhi 18:6a4db94011d3 3843 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
sahilmgandhi 18:6a4db94011d3 3844 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
sahilmgandhi 18:6a4db94011d3 3845 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
sahilmgandhi 18:6a4db94011d3 3846 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
sahilmgandhi 18:6a4db94011d3 3847
sahilmgandhi 18:6a4db94011d3 3848 /* Register: POWER_DCDCFORCE */
sahilmgandhi 18:6a4db94011d3 3849 /* Description: DCDC power-up force register. */
sahilmgandhi 18:6a4db94011d3 3850
sahilmgandhi 18:6a4db94011d3 3851 /* Bit 1 : DCDC power-up force on. */
sahilmgandhi 18:6a4db94011d3 3852 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
sahilmgandhi 18:6a4db94011d3 3853 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
sahilmgandhi 18:6a4db94011d3 3854 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
sahilmgandhi 18:6a4db94011d3 3855 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
sahilmgandhi 18:6a4db94011d3 3856
sahilmgandhi 18:6a4db94011d3 3857 /* Bit 0 : DCDC power-up force off. */
sahilmgandhi 18:6a4db94011d3 3858 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
sahilmgandhi 18:6a4db94011d3 3859 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
sahilmgandhi 18:6a4db94011d3 3860 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
sahilmgandhi 18:6a4db94011d3 3861 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
sahilmgandhi 18:6a4db94011d3 3862
sahilmgandhi 18:6a4db94011d3 3863
sahilmgandhi 18:6a4db94011d3 3864 /* Peripheral: PPI */
sahilmgandhi 18:6a4db94011d3 3865 /* Description: PPI controller. */
sahilmgandhi 18:6a4db94011d3 3866
sahilmgandhi 18:6a4db94011d3 3867 /* Register: PPI_CHEN */
sahilmgandhi 18:6a4db94011d3 3868 /* Description: Channel enable. */
sahilmgandhi 18:6a4db94011d3 3869
sahilmgandhi 18:6a4db94011d3 3870 /* Bit 31 : Enable PPI channel 31. */
sahilmgandhi 18:6a4db94011d3 3871 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 3872 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 3873 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3874 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3875
sahilmgandhi 18:6a4db94011d3 3876 /* Bit 30 : Enable PPI channel 30. */
sahilmgandhi 18:6a4db94011d3 3877 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 3878 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 3879 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3880 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3881
sahilmgandhi 18:6a4db94011d3 3882 /* Bit 29 : Enable PPI channel 29. */
sahilmgandhi 18:6a4db94011d3 3883 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 3884 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 3885 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3886 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3887
sahilmgandhi 18:6a4db94011d3 3888 /* Bit 28 : Enable PPI channel 28. */
sahilmgandhi 18:6a4db94011d3 3889 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 3890 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 3891 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3892 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3893
sahilmgandhi 18:6a4db94011d3 3894 /* Bit 27 : Enable PPI channel 27. */
sahilmgandhi 18:6a4db94011d3 3895 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 3896 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 3897 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3898 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3899
sahilmgandhi 18:6a4db94011d3 3900 /* Bit 26 : Enable PPI channel 26. */
sahilmgandhi 18:6a4db94011d3 3901 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 3902 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 3903 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3904 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3905
sahilmgandhi 18:6a4db94011d3 3906 /* Bit 25 : Enable PPI channel 25. */
sahilmgandhi 18:6a4db94011d3 3907 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 3908 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 3909 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3910 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3911
sahilmgandhi 18:6a4db94011d3 3912 /* Bit 24 : Enable PPI channel 24. */
sahilmgandhi 18:6a4db94011d3 3913 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 3914 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 3915 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3916 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3917
sahilmgandhi 18:6a4db94011d3 3918 /* Bit 23 : Enable PPI channel 23. */
sahilmgandhi 18:6a4db94011d3 3919 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 3920 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 3921 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3922 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3923
sahilmgandhi 18:6a4db94011d3 3924 /* Bit 22 : Enable PPI channel 22. */
sahilmgandhi 18:6a4db94011d3 3925 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 3926 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 3927 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3928 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3929
sahilmgandhi 18:6a4db94011d3 3930 /* Bit 21 : Enable PPI channel 21. */
sahilmgandhi 18:6a4db94011d3 3931 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 3932 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 3933 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3934 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3935
sahilmgandhi 18:6a4db94011d3 3936 /* Bit 20 : Enable PPI channel 20. */
sahilmgandhi 18:6a4db94011d3 3937 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 3938 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 3939 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3940 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3941
sahilmgandhi 18:6a4db94011d3 3942 /* Bit 15 : Enable PPI channel 15. */
sahilmgandhi 18:6a4db94011d3 3943 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 3944 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 3945 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3946 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3947
sahilmgandhi 18:6a4db94011d3 3948 /* Bit 14 : Enable PPI channel 14. */
sahilmgandhi 18:6a4db94011d3 3949 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 3950 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 3951 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3952 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3953
sahilmgandhi 18:6a4db94011d3 3954 /* Bit 13 : Enable PPI channel 13. */
sahilmgandhi 18:6a4db94011d3 3955 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 3956 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 3957 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3958 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3959
sahilmgandhi 18:6a4db94011d3 3960 /* Bit 12 : Enable PPI channel 12. */
sahilmgandhi 18:6a4db94011d3 3961 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 3962 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 3963 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3964 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3965
sahilmgandhi 18:6a4db94011d3 3966 /* Bit 11 : Enable PPI channel 11. */
sahilmgandhi 18:6a4db94011d3 3967 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 3968 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 3969 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3970 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3971
sahilmgandhi 18:6a4db94011d3 3972 /* Bit 10 : Enable PPI channel 10. */
sahilmgandhi 18:6a4db94011d3 3973 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 3974 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 3975 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3976 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3977
sahilmgandhi 18:6a4db94011d3 3978 /* Bit 9 : Enable PPI channel 9. */
sahilmgandhi 18:6a4db94011d3 3979 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 3980 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 3981 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3982 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3983
sahilmgandhi 18:6a4db94011d3 3984 /* Bit 8 : Enable PPI channel 8. */
sahilmgandhi 18:6a4db94011d3 3985 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 3986 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 3987 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3988 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3989
sahilmgandhi 18:6a4db94011d3 3990 /* Bit 7 : Enable PPI channel 7. */
sahilmgandhi 18:6a4db94011d3 3991 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 3992 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 3993 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 3994 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 3995
sahilmgandhi 18:6a4db94011d3 3996 /* Bit 6 : Enable PPI channel 6. */
sahilmgandhi 18:6a4db94011d3 3997 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 3998 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 3999 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4000 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4001
sahilmgandhi 18:6a4db94011d3 4002 /* Bit 5 : Enable PPI channel 5. */
sahilmgandhi 18:6a4db94011d3 4003 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4004 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4005 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4006 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4007
sahilmgandhi 18:6a4db94011d3 4008 /* Bit 4 : Enable PPI channel 4. */
sahilmgandhi 18:6a4db94011d3 4009 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4010 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4011 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4012 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4013
sahilmgandhi 18:6a4db94011d3 4014 /* Bit 3 : Enable PPI channel 3. */
sahilmgandhi 18:6a4db94011d3 4015 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4016 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4017 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
sahilmgandhi 18:6a4db94011d3 4018 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
sahilmgandhi 18:6a4db94011d3 4019
sahilmgandhi 18:6a4db94011d3 4020 /* Bit 2 : Enable PPI channel 2. */
sahilmgandhi 18:6a4db94011d3 4021 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4022 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4023 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4024 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4025
sahilmgandhi 18:6a4db94011d3 4026 /* Bit 1 : Enable PPI channel 1. */
sahilmgandhi 18:6a4db94011d3 4027 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4028 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4029 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4030 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4031
sahilmgandhi 18:6a4db94011d3 4032 /* Bit 0 : Enable PPI channel 0. */
sahilmgandhi 18:6a4db94011d3 4033 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4034 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4035 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4036 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4037
sahilmgandhi 18:6a4db94011d3 4038 /* Register: PPI_CHENSET */
sahilmgandhi 18:6a4db94011d3 4039 /* Description: Channel enable set. */
sahilmgandhi 18:6a4db94011d3 4040
sahilmgandhi 18:6a4db94011d3 4041 /* Bit 31 : Enable PPI channel 31. */
sahilmgandhi 18:6a4db94011d3 4042 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 4043 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 4044 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4045 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4046 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4047
sahilmgandhi 18:6a4db94011d3 4048 /* Bit 30 : Enable PPI channel 30. */
sahilmgandhi 18:6a4db94011d3 4049 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 4050 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 4051 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4052 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4053 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4054
sahilmgandhi 18:6a4db94011d3 4055 /* Bit 29 : Enable PPI channel 29. */
sahilmgandhi 18:6a4db94011d3 4056 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 4057 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 4058 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4059 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4060 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4061
sahilmgandhi 18:6a4db94011d3 4062 /* Bit 28 : Enable PPI channel 28. */
sahilmgandhi 18:6a4db94011d3 4063 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 4064 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 4065 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4066 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4067 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4068
sahilmgandhi 18:6a4db94011d3 4069 /* Bit 27 : Enable PPI channel 27. */
sahilmgandhi 18:6a4db94011d3 4070 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 4071 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 4072 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4073 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4074 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4075
sahilmgandhi 18:6a4db94011d3 4076 /* Bit 26 : Enable PPI channel 26. */
sahilmgandhi 18:6a4db94011d3 4077 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 4078 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 4079 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4080 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4081 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4082
sahilmgandhi 18:6a4db94011d3 4083 /* Bit 25 : Enable PPI channel 25. */
sahilmgandhi 18:6a4db94011d3 4084 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 4085 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 4086 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4087 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4088 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4089
sahilmgandhi 18:6a4db94011d3 4090 /* Bit 24 : Enable PPI channel 24. */
sahilmgandhi 18:6a4db94011d3 4091 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 4092 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 4093 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4094 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4095 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4096
sahilmgandhi 18:6a4db94011d3 4097 /* Bit 23 : Enable PPI channel 23. */
sahilmgandhi 18:6a4db94011d3 4098 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 4099 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 4100 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4101 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4102 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4103
sahilmgandhi 18:6a4db94011d3 4104 /* Bit 22 : Enable PPI channel 22. */
sahilmgandhi 18:6a4db94011d3 4105 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 4106 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 4107 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4108 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4109 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4110
sahilmgandhi 18:6a4db94011d3 4111 /* Bit 21 : Enable PPI channel 21. */
sahilmgandhi 18:6a4db94011d3 4112 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 4113 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 4114 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4115 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4116 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4117
sahilmgandhi 18:6a4db94011d3 4118 /* Bit 20 : Enable PPI channel 20. */
sahilmgandhi 18:6a4db94011d3 4119 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 4120 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 4121 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4122 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4123 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4124
sahilmgandhi 18:6a4db94011d3 4125 /* Bit 15 : Enable PPI channel 15. */
sahilmgandhi 18:6a4db94011d3 4126 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 4127 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 4128 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4129 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4130 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4131
sahilmgandhi 18:6a4db94011d3 4132 /* Bit 14 : Enable PPI channel 14. */
sahilmgandhi 18:6a4db94011d3 4133 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 4134 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 4135 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4136 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4137 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4138
sahilmgandhi 18:6a4db94011d3 4139 /* Bit 13 : Enable PPI channel 13. */
sahilmgandhi 18:6a4db94011d3 4140 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 4141 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 4142 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4143 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4144 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4145
sahilmgandhi 18:6a4db94011d3 4146 /* Bit 12 : Enable PPI channel 12. */
sahilmgandhi 18:6a4db94011d3 4147 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 4148 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 4149 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4150 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4151 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4152
sahilmgandhi 18:6a4db94011d3 4153 /* Bit 11 : Enable PPI channel 11. */
sahilmgandhi 18:6a4db94011d3 4154 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 4155 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 4156 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4157 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4158 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4159
sahilmgandhi 18:6a4db94011d3 4160 /* Bit 10 : Enable PPI channel 10. */
sahilmgandhi 18:6a4db94011d3 4161 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 4162 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 4163 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4164 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4165 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4166
sahilmgandhi 18:6a4db94011d3 4167 /* Bit 9 : Enable PPI channel 9. */
sahilmgandhi 18:6a4db94011d3 4168 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 4169 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 4170 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4171 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4172 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4173
sahilmgandhi 18:6a4db94011d3 4174 /* Bit 8 : Enable PPI channel 8. */
sahilmgandhi 18:6a4db94011d3 4175 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 4176 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 4177 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4178 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4179 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4180
sahilmgandhi 18:6a4db94011d3 4181 /* Bit 7 : Enable PPI channel 7. */
sahilmgandhi 18:6a4db94011d3 4182 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 4183 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 4184 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4185 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4186 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4187
sahilmgandhi 18:6a4db94011d3 4188 /* Bit 6 : Enable PPI channel 6. */
sahilmgandhi 18:6a4db94011d3 4189 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 4190 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 4191 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4192 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4193 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4194
sahilmgandhi 18:6a4db94011d3 4195 /* Bit 5 : Enable PPI channel 5. */
sahilmgandhi 18:6a4db94011d3 4196 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4197 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4198 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4199 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4200 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4201
sahilmgandhi 18:6a4db94011d3 4202 /* Bit 4 : Enable PPI channel 4. */
sahilmgandhi 18:6a4db94011d3 4203 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4204 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4205 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4206 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4207 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4208
sahilmgandhi 18:6a4db94011d3 4209 /* Bit 3 : Enable PPI channel 3. */
sahilmgandhi 18:6a4db94011d3 4210 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4211 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4212 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4213 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4214 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4215
sahilmgandhi 18:6a4db94011d3 4216 /* Bit 2 : Enable PPI channel 2. */
sahilmgandhi 18:6a4db94011d3 4217 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4218 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4219 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4220 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4221 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4222
sahilmgandhi 18:6a4db94011d3 4223 /* Bit 1 : Enable PPI channel 1. */
sahilmgandhi 18:6a4db94011d3 4224 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4225 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4226 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4227 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4228 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4229
sahilmgandhi 18:6a4db94011d3 4230 /* Bit 0 : Enable PPI channel 0. */
sahilmgandhi 18:6a4db94011d3 4231 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4232 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4233 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4234 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4235 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
sahilmgandhi 18:6a4db94011d3 4236
sahilmgandhi 18:6a4db94011d3 4237 /* Register: PPI_CHENCLR */
sahilmgandhi 18:6a4db94011d3 4238 /* Description: Channel enable clear. */
sahilmgandhi 18:6a4db94011d3 4239
sahilmgandhi 18:6a4db94011d3 4240 /* Bit 31 : Disable PPI channel 31. */
sahilmgandhi 18:6a4db94011d3 4241 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 4242 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 4243 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4244 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4245 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4246
sahilmgandhi 18:6a4db94011d3 4247 /* Bit 30 : Disable PPI channel 30. */
sahilmgandhi 18:6a4db94011d3 4248 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 4249 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 4250 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4251 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4252 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4253
sahilmgandhi 18:6a4db94011d3 4254 /* Bit 29 : Disable PPI channel 29. */
sahilmgandhi 18:6a4db94011d3 4255 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 4256 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 4257 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4258 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4259 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4260
sahilmgandhi 18:6a4db94011d3 4261 /* Bit 28 : Disable PPI channel 28. */
sahilmgandhi 18:6a4db94011d3 4262 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 4263 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 4264 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4265 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4266 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4267
sahilmgandhi 18:6a4db94011d3 4268 /* Bit 27 : Disable PPI channel 27. */
sahilmgandhi 18:6a4db94011d3 4269 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 4270 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 4271 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4272 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4273 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4274
sahilmgandhi 18:6a4db94011d3 4275 /* Bit 26 : Disable PPI channel 26. */
sahilmgandhi 18:6a4db94011d3 4276 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 4277 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 4278 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4279 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4280 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4281
sahilmgandhi 18:6a4db94011d3 4282 /* Bit 25 : Disable PPI channel 25. */
sahilmgandhi 18:6a4db94011d3 4283 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 4284 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 4285 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4286 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4287 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4288
sahilmgandhi 18:6a4db94011d3 4289 /* Bit 24 : Disable PPI channel 24. */
sahilmgandhi 18:6a4db94011d3 4290 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 4291 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 4292 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4293 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4294 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4295
sahilmgandhi 18:6a4db94011d3 4296 /* Bit 23 : Disable PPI channel 23. */
sahilmgandhi 18:6a4db94011d3 4297 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 4298 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 4299 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4300 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4301 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4302
sahilmgandhi 18:6a4db94011d3 4303 /* Bit 22 : Disable PPI channel 22. */
sahilmgandhi 18:6a4db94011d3 4304 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 4305 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 4306 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4307 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4308 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4309
sahilmgandhi 18:6a4db94011d3 4310 /* Bit 21 : Disable PPI channel 21. */
sahilmgandhi 18:6a4db94011d3 4311 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 4312 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 4313 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4314 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4315 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4316
sahilmgandhi 18:6a4db94011d3 4317 /* Bit 20 : Disable PPI channel 20. */
sahilmgandhi 18:6a4db94011d3 4318 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 4319 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 4320 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4321 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4322 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4323
sahilmgandhi 18:6a4db94011d3 4324 /* Bit 15 : Disable PPI channel 15. */
sahilmgandhi 18:6a4db94011d3 4325 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 4326 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 4327 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4328 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4329 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4330
sahilmgandhi 18:6a4db94011d3 4331 /* Bit 14 : Disable PPI channel 14. */
sahilmgandhi 18:6a4db94011d3 4332 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 4333 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 4334 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4335 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4336 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4337
sahilmgandhi 18:6a4db94011d3 4338 /* Bit 13 : Disable PPI channel 13. */
sahilmgandhi 18:6a4db94011d3 4339 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 4340 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 4341 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4342 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4343 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4344
sahilmgandhi 18:6a4db94011d3 4345 /* Bit 12 : Disable PPI channel 12. */
sahilmgandhi 18:6a4db94011d3 4346 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 4347 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 4348 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4349 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4350 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4351
sahilmgandhi 18:6a4db94011d3 4352 /* Bit 11 : Disable PPI channel 11. */
sahilmgandhi 18:6a4db94011d3 4353 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 4354 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 4355 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4356 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4357 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4358
sahilmgandhi 18:6a4db94011d3 4359 /* Bit 10 : Disable PPI channel 10. */
sahilmgandhi 18:6a4db94011d3 4360 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 4361 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 4362 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4363 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4364 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4365
sahilmgandhi 18:6a4db94011d3 4366 /* Bit 9 : Disable PPI channel 9. */
sahilmgandhi 18:6a4db94011d3 4367 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 4368 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 4369 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4370 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4371 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4372
sahilmgandhi 18:6a4db94011d3 4373 /* Bit 8 : Disable PPI channel 8. */
sahilmgandhi 18:6a4db94011d3 4374 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 4375 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 4376 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4377 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4378 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4379
sahilmgandhi 18:6a4db94011d3 4380 /* Bit 7 : Disable PPI channel 7. */
sahilmgandhi 18:6a4db94011d3 4381 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 4382 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 4383 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4384 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4385 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4386
sahilmgandhi 18:6a4db94011d3 4387 /* Bit 6 : Disable PPI channel 6. */
sahilmgandhi 18:6a4db94011d3 4388 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 4389 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 4390 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4391 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4392 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4393
sahilmgandhi 18:6a4db94011d3 4394 /* Bit 5 : Disable PPI channel 5. */
sahilmgandhi 18:6a4db94011d3 4395 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4396 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4397 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4398 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4399 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4400
sahilmgandhi 18:6a4db94011d3 4401 /* Bit 4 : Disable PPI channel 4. */
sahilmgandhi 18:6a4db94011d3 4402 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4403 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4404 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4405 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4406 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4407
sahilmgandhi 18:6a4db94011d3 4408 /* Bit 3 : Disable PPI channel 3. */
sahilmgandhi 18:6a4db94011d3 4409 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4410 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4411 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4412 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4413 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4414
sahilmgandhi 18:6a4db94011d3 4415 /* Bit 2 : Disable PPI channel 2. */
sahilmgandhi 18:6a4db94011d3 4416 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4417 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4418 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4419 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4420 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4421
sahilmgandhi 18:6a4db94011d3 4422 /* Bit 1 : Disable PPI channel 1. */
sahilmgandhi 18:6a4db94011d3 4423 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4424 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4425 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4426 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4427 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4428
sahilmgandhi 18:6a4db94011d3 4429 /* Bit 0 : Disable PPI channel 0. */
sahilmgandhi 18:6a4db94011d3 4430 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4431 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4432 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
sahilmgandhi 18:6a4db94011d3 4433 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
sahilmgandhi 18:6a4db94011d3 4434 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
sahilmgandhi 18:6a4db94011d3 4435
sahilmgandhi 18:6a4db94011d3 4436 /* Register: PPI_CHG */
sahilmgandhi 18:6a4db94011d3 4437 /* Description: Channel group configuration. */
sahilmgandhi 18:6a4db94011d3 4438
sahilmgandhi 18:6a4db94011d3 4439 /* Bit 31 : Include CH31 in channel group. */
sahilmgandhi 18:6a4db94011d3 4440 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
sahilmgandhi 18:6a4db94011d3 4441 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
sahilmgandhi 18:6a4db94011d3 4442 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4443 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4444
sahilmgandhi 18:6a4db94011d3 4445 /* Bit 30 : Include CH30 in channel group. */
sahilmgandhi 18:6a4db94011d3 4446 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
sahilmgandhi 18:6a4db94011d3 4447 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
sahilmgandhi 18:6a4db94011d3 4448 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4449 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4450
sahilmgandhi 18:6a4db94011d3 4451 /* Bit 29 : Include CH29 in channel group. */
sahilmgandhi 18:6a4db94011d3 4452 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
sahilmgandhi 18:6a4db94011d3 4453 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
sahilmgandhi 18:6a4db94011d3 4454 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4455 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4456
sahilmgandhi 18:6a4db94011d3 4457 /* Bit 28 : Include CH28 in channel group. */
sahilmgandhi 18:6a4db94011d3 4458 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
sahilmgandhi 18:6a4db94011d3 4459 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
sahilmgandhi 18:6a4db94011d3 4460 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4461 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4462
sahilmgandhi 18:6a4db94011d3 4463 /* Bit 27 : Include CH27 in channel group. */
sahilmgandhi 18:6a4db94011d3 4464 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
sahilmgandhi 18:6a4db94011d3 4465 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
sahilmgandhi 18:6a4db94011d3 4466 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4467 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4468
sahilmgandhi 18:6a4db94011d3 4469 /* Bit 26 : Include CH26 in channel group. */
sahilmgandhi 18:6a4db94011d3 4470 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
sahilmgandhi 18:6a4db94011d3 4471 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
sahilmgandhi 18:6a4db94011d3 4472 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4473 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4474
sahilmgandhi 18:6a4db94011d3 4475 /* Bit 25 : Include CH25 in channel group. */
sahilmgandhi 18:6a4db94011d3 4476 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
sahilmgandhi 18:6a4db94011d3 4477 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
sahilmgandhi 18:6a4db94011d3 4478 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4479 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4480
sahilmgandhi 18:6a4db94011d3 4481 /* Bit 24 : Include CH24 in channel group. */
sahilmgandhi 18:6a4db94011d3 4482 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
sahilmgandhi 18:6a4db94011d3 4483 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
sahilmgandhi 18:6a4db94011d3 4484 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4485 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4486
sahilmgandhi 18:6a4db94011d3 4487 /* Bit 23 : Include CH23 in channel group. */
sahilmgandhi 18:6a4db94011d3 4488 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
sahilmgandhi 18:6a4db94011d3 4489 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
sahilmgandhi 18:6a4db94011d3 4490 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4491 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4492
sahilmgandhi 18:6a4db94011d3 4493 /* Bit 22 : Include CH22 in channel group. */
sahilmgandhi 18:6a4db94011d3 4494 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
sahilmgandhi 18:6a4db94011d3 4495 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
sahilmgandhi 18:6a4db94011d3 4496 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4497 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4498
sahilmgandhi 18:6a4db94011d3 4499 /* Bit 21 : Include CH21 in channel group. */
sahilmgandhi 18:6a4db94011d3 4500 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
sahilmgandhi 18:6a4db94011d3 4501 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
sahilmgandhi 18:6a4db94011d3 4502 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4503 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4504
sahilmgandhi 18:6a4db94011d3 4505 /* Bit 20 : Include CH20 in channel group. */
sahilmgandhi 18:6a4db94011d3 4506 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
sahilmgandhi 18:6a4db94011d3 4507 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
sahilmgandhi 18:6a4db94011d3 4508 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4509 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4510
sahilmgandhi 18:6a4db94011d3 4511 /* Bit 15 : Include CH15 in channel group. */
sahilmgandhi 18:6a4db94011d3 4512 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
sahilmgandhi 18:6a4db94011d3 4513 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
sahilmgandhi 18:6a4db94011d3 4514 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4515 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4516
sahilmgandhi 18:6a4db94011d3 4517 /* Bit 14 : Include CH14 in channel group. */
sahilmgandhi 18:6a4db94011d3 4518 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
sahilmgandhi 18:6a4db94011d3 4519 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
sahilmgandhi 18:6a4db94011d3 4520 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4521 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4522
sahilmgandhi 18:6a4db94011d3 4523 /* Bit 13 : Include CH13 in channel group. */
sahilmgandhi 18:6a4db94011d3 4524 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
sahilmgandhi 18:6a4db94011d3 4525 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
sahilmgandhi 18:6a4db94011d3 4526 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4527 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4528
sahilmgandhi 18:6a4db94011d3 4529 /* Bit 12 : Include CH12 in channel group. */
sahilmgandhi 18:6a4db94011d3 4530 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
sahilmgandhi 18:6a4db94011d3 4531 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
sahilmgandhi 18:6a4db94011d3 4532 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4533 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4534
sahilmgandhi 18:6a4db94011d3 4535 /* Bit 11 : Include CH11 in channel group. */
sahilmgandhi 18:6a4db94011d3 4536 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
sahilmgandhi 18:6a4db94011d3 4537 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
sahilmgandhi 18:6a4db94011d3 4538 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4539 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4540
sahilmgandhi 18:6a4db94011d3 4541 /* Bit 10 : Include CH10 in channel group. */
sahilmgandhi 18:6a4db94011d3 4542 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
sahilmgandhi 18:6a4db94011d3 4543 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
sahilmgandhi 18:6a4db94011d3 4544 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4545 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4546
sahilmgandhi 18:6a4db94011d3 4547 /* Bit 9 : Include CH9 in channel group. */
sahilmgandhi 18:6a4db94011d3 4548 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
sahilmgandhi 18:6a4db94011d3 4549 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
sahilmgandhi 18:6a4db94011d3 4550 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4551 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4552
sahilmgandhi 18:6a4db94011d3 4553 /* Bit 8 : Include CH8 in channel group. */
sahilmgandhi 18:6a4db94011d3 4554 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
sahilmgandhi 18:6a4db94011d3 4555 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
sahilmgandhi 18:6a4db94011d3 4556 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4557 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4558
sahilmgandhi 18:6a4db94011d3 4559 /* Bit 7 : Include CH7 in channel group. */
sahilmgandhi 18:6a4db94011d3 4560 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
sahilmgandhi 18:6a4db94011d3 4561 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
sahilmgandhi 18:6a4db94011d3 4562 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4563 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4564
sahilmgandhi 18:6a4db94011d3 4565 /* Bit 6 : Include CH6 in channel group. */
sahilmgandhi 18:6a4db94011d3 4566 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
sahilmgandhi 18:6a4db94011d3 4567 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
sahilmgandhi 18:6a4db94011d3 4568 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4569 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4570
sahilmgandhi 18:6a4db94011d3 4571 /* Bit 5 : Include CH5 in channel group. */
sahilmgandhi 18:6a4db94011d3 4572 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4573 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
sahilmgandhi 18:6a4db94011d3 4574 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4575 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4576
sahilmgandhi 18:6a4db94011d3 4577 /* Bit 4 : Include CH4 in channel group. */
sahilmgandhi 18:6a4db94011d3 4578 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4579 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
sahilmgandhi 18:6a4db94011d3 4580 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4581 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4582
sahilmgandhi 18:6a4db94011d3 4583 /* Bit 3 : Include CH3 in channel group. */
sahilmgandhi 18:6a4db94011d3 4584 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4585 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
sahilmgandhi 18:6a4db94011d3 4586 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4587 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4588
sahilmgandhi 18:6a4db94011d3 4589 /* Bit 2 : Include CH2 in channel group. */
sahilmgandhi 18:6a4db94011d3 4590 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4591 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
sahilmgandhi 18:6a4db94011d3 4592 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4593 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4594
sahilmgandhi 18:6a4db94011d3 4595 /* Bit 1 : Include CH1 in channel group. */
sahilmgandhi 18:6a4db94011d3 4596 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4597 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
sahilmgandhi 18:6a4db94011d3 4598 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4599 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4600
sahilmgandhi 18:6a4db94011d3 4601 /* Bit 0 : Include CH0 in channel group. */
sahilmgandhi 18:6a4db94011d3 4602 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4603 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
sahilmgandhi 18:6a4db94011d3 4604 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
sahilmgandhi 18:6a4db94011d3 4605 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
sahilmgandhi 18:6a4db94011d3 4606
sahilmgandhi 18:6a4db94011d3 4607
sahilmgandhi 18:6a4db94011d3 4608 /* Peripheral: QDEC */
sahilmgandhi 18:6a4db94011d3 4609 /* Description: Rotary decoder. */
sahilmgandhi 18:6a4db94011d3 4610
sahilmgandhi 18:6a4db94011d3 4611 /* Register: QDEC_SHORTS */
sahilmgandhi 18:6a4db94011d3 4612 /* Description: Shortcuts for the QDEC. */
sahilmgandhi 18:6a4db94011d3 4613
sahilmgandhi 18:6a4db94011d3 4614 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
sahilmgandhi 18:6a4db94011d3 4615 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 4616 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 4617 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4618 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4619
sahilmgandhi 18:6a4db94011d3 4620 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
sahilmgandhi 18:6a4db94011d3 4621 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
sahilmgandhi 18:6a4db94011d3 4622 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
sahilmgandhi 18:6a4db94011d3 4623 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4624 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4625
sahilmgandhi 18:6a4db94011d3 4626 /* Register: QDEC_INTENSET */
sahilmgandhi 18:6a4db94011d3 4627 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 4628
sahilmgandhi 18:6a4db94011d3 4629 /* Bit 2 : Enable interrupt on ACCOF event. */
sahilmgandhi 18:6a4db94011d3 4630 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 4631 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 4632 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4633 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4634 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4635
sahilmgandhi 18:6a4db94011d3 4636 /* Bit 1 : Enable interrupt on REPORTRDY event. */
sahilmgandhi 18:6a4db94011d3 4637 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 4638 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 4639 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4640 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4641 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4642
sahilmgandhi 18:6a4db94011d3 4643 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
sahilmgandhi 18:6a4db94011d3 4644 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 4645 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 4646 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4647 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4648 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4649
sahilmgandhi 18:6a4db94011d3 4650 /* Register: QDEC_INTENCLR */
sahilmgandhi 18:6a4db94011d3 4651 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 4652
sahilmgandhi 18:6a4db94011d3 4653 /* Bit 2 : Disable interrupt on ACCOF event. */
sahilmgandhi 18:6a4db94011d3 4654 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 4655 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
sahilmgandhi 18:6a4db94011d3 4656 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4657 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4658 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4659
sahilmgandhi 18:6a4db94011d3 4660 /* Bit 1 : Disable interrupt on REPORTRDY event. */
sahilmgandhi 18:6a4db94011d3 4661 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 4662 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
sahilmgandhi 18:6a4db94011d3 4663 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4664 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4665 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4666
sahilmgandhi 18:6a4db94011d3 4667 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
sahilmgandhi 18:6a4db94011d3 4668 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 4669 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
sahilmgandhi 18:6a4db94011d3 4670 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4671 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4672 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4673
sahilmgandhi 18:6a4db94011d3 4674 /* Register: QDEC_ENABLE */
sahilmgandhi 18:6a4db94011d3 4675 /* Description: Enable the QDEC. */
sahilmgandhi 18:6a4db94011d3 4676
sahilmgandhi 18:6a4db94011d3 4677 /* Bit 0 : Enable or disable QDEC. */
sahilmgandhi 18:6a4db94011d3 4678 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 4679 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 4680 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
sahilmgandhi 18:6a4db94011d3 4681 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
sahilmgandhi 18:6a4db94011d3 4682
sahilmgandhi 18:6a4db94011d3 4683 /* Register: QDEC_LEDPOL */
sahilmgandhi 18:6a4db94011d3 4684 /* Description: LED output pin polarity. */
sahilmgandhi 18:6a4db94011d3 4685
sahilmgandhi 18:6a4db94011d3 4686 /* Bit 0 : LED output pin polarity. */
sahilmgandhi 18:6a4db94011d3 4687 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
sahilmgandhi 18:6a4db94011d3 4688 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
sahilmgandhi 18:6a4db94011d3 4689 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
sahilmgandhi 18:6a4db94011d3 4690 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
sahilmgandhi 18:6a4db94011d3 4691
sahilmgandhi 18:6a4db94011d3 4692 /* Register: QDEC_SAMPLEPER */
sahilmgandhi 18:6a4db94011d3 4693 /* Description: Sample period. */
sahilmgandhi 18:6a4db94011d3 4694
sahilmgandhi 18:6a4db94011d3 4695 /* Bits 2..0 : Sample period. */
sahilmgandhi 18:6a4db94011d3 4696 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
sahilmgandhi 18:6a4db94011d3 4697 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
sahilmgandhi 18:6a4db94011d3 4698 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
sahilmgandhi 18:6a4db94011d3 4699 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
sahilmgandhi 18:6a4db94011d3 4700 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
sahilmgandhi 18:6a4db94011d3 4701 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
sahilmgandhi 18:6a4db94011d3 4702 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
sahilmgandhi 18:6a4db94011d3 4703 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
sahilmgandhi 18:6a4db94011d3 4704 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
sahilmgandhi 18:6a4db94011d3 4705 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
sahilmgandhi 18:6a4db94011d3 4706
sahilmgandhi 18:6a4db94011d3 4707 /* Register: QDEC_SAMPLE */
sahilmgandhi 18:6a4db94011d3 4708 /* Description: Motion sample value. */
sahilmgandhi 18:6a4db94011d3 4709
sahilmgandhi 18:6a4db94011d3 4710 /* Bits 31..0 : Last sample taken in compliment to 2. */
sahilmgandhi 18:6a4db94011d3 4711 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 4712 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
sahilmgandhi 18:6a4db94011d3 4713
sahilmgandhi 18:6a4db94011d3 4714 /* Register: QDEC_REPORTPER */
sahilmgandhi 18:6a4db94011d3 4715 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
sahilmgandhi 18:6a4db94011d3 4716
sahilmgandhi 18:6a4db94011d3 4717 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
sahilmgandhi 18:6a4db94011d3 4718 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
sahilmgandhi 18:6a4db94011d3 4719 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
sahilmgandhi 18:6a4db94011d3 4720 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
sahilmgandhi 18:6a4db94011d3 4721 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
sahilmgandhi 18:6a4db94011d3 4722 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
sahilmgandhi 18:6a4db94011d3 4723 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
sahilmgandhi 18:6a4db94011d3 4724 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
sahilmgandhi 18:6a4db94011d3 4725 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
sahilmgandhi 18:6a4db94011d3 4726 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
sahilmgandhi 18:6a4db94011d3 4727 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
sahilmgandhi 18:6a4db94011d3 4728
sahilmgandhi 18:6a4db94011d3 4729 /* Register: QDEC_DBFEN */
sahilmgandhi 18:6a4db94011d3 4730 /* Description: Enable debouncer input filters. */
sahilmgandhi 18:6a4db94011d3 4731
sahilmgandhi 18:6a4db94011d3 4732 /* Bit 0 : Enable debounce input filters. */
sahilmgandhi 18:6a4db94011d3 4733 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
sahilmgandhi 18:6a4db94011d3 4734 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
sahilmgandhi 18:6a4db94011d3 4735 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
sahilmgandhi 18:6a4db94011d3 4736 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
sahilmgandhi 18:6a4db94011d3 4737
sahilmgandhi 18:6a4db94011d3 4738 /* Register: QDEC_LEDPRE */
sahilmgandhi 18:6a4db94011d3 4739 /* Description: Time LED is switched ON before the sample. */
sahilmgandhi 18:6a4db94011d3 4740
sahilmgandhi 18:6a4db94011d3 4741 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
sahilmgandhi 18:6a4db94011d3 4742 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
sahilmgandhi 18:6a4db94011d3 4743 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
sahilmgandhi 18:6a4db94011d3 4744
sahilmgandhi 18:6a4db94011d3 4745 /* Register: QDEC_ACCDBL */
sahilmgandhi 18:6a4db94011d3 4746 /* Description: Accumulated double (error) transitions register. */
sahilmgandhi 18:6a4db94011d3 4747
sahilmgandhi 18:6a4db94011d3 4748 /* Bits 3..0 : Accumulated double (error) transitions. */
sahilmgandhi 18:6a4db94011d3 4749 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
sahilmgandhi 18:6a4db94011d3 4750 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
sahilmgandhi 18:6a4db94011d3 4751
sahilmgandhi 18:6a4db94011d3 4752 /* Register: QDEC_ACCDBLREAD */
sahilmgandhi 18:6a4db94011d3 4753 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
sahilmgandhi 18:6a4db94011d3 4754
sahilmgandhi 18:6a4db94011d3 4755 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
sahilmgandhi 18:6a4db94011d3 4756 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
sahilmgandhi 18:6a4db94011d3 4757 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
sahilmgandhi 18:6a4db94011d3 4758
sahilmgandhi 18:6a4db94011d3 4759 /* Register: QDEC_POWER */
sahilmgandhi 18:6a4db94011d3 4760 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 4761
sahilmgandhi 18:6a4db94011d3 4762 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 4763 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 4764 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 4765 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 4766 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 4767
sahilmgandhi 18:6a4db94011d3 4768
sahilmgandhi 18:6a4db94011d3 4769 /* Peripheral: RADIO */
sahilmgandhi 18:6a4db94011d3 4770 /* Description: The radio. */
sahilmgandhi 18:6a4db94011d3 4771
sahilmgandhi 18:6a4db94011d3 4772 /* Register: RADIO_SHORTS */
sahilmgandhi 18:6a4db94011d3 4773 /* Description: Shortcuts for the radio. */
sahilmgandhi 18:6a4db94011d3 4774
sahilmgandhi 18:6a4db94011d3 4775 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
sahilmgandhi 18:6a4db94011d3 4776 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
sahilmgandhi 18:6a4db94011d3 4777 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
sahilmgandhi 18:6a4db94011d3 4778 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4779 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4780
sahilmgandhi 18:6a4db94011d3 4781 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
sahilmgandhi 18:6a4db94011d3 4782 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
sahilmgandhi 18:6a4db94011d3 4783 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
sahilmgandhi 18:6a4db94011d3 4784 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4785 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4786
sahilmgandhi 18:6a4db94011d3 4787 /* Bit 5 : Shortcut between END event and START task. */
sahilmgandhi 18:6a4db94011d3 4788 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
sahilmgandhi 18:6a4db94011d3 4789 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
sahilmgandhi 18:6a4db94011d3 4790 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4791 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4792
sahilmgandhi 18:6a4db94011d3 4793 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
sahilmgandhi 18:6a4db94011d3 4794 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
sahilmgandhi 18:6a4db94011d3 4795 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
sahilmgandhi 18:6a4db94011d3 4796 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4797 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4798
sahilmgandhi 18:6a4db94011d3 4799 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
sahilmgandhi 18:6a4db94011d3 4800 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
sahilmgandhi 18:6a4db94011d3 4801 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
sahilmgandhi 18:6a4db94011d3 4802 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4803 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4804
sahilmgandhi 18:6a4db94011d3 4805 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
sahilmgandhi 18:6a4db94011d3 4806 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
sahilmgandhi 18:6a4db94011d3 4807 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
sahilmgandhi 18:6a4db94011d3 4808 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4809 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4810
sahilmgandhi 18:6a4db94011d3 4811 /* Bit 1 : Shortcut between END event and DISABLE task. */
sahilmgandhi 18:6a4db94011d3 4812 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
sahilmgandhi 18:6a4db94011d3 4813 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
sahilmgandhi 18:6a4db94011d3 4814 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4815 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4816
sahilmgandhi 18:6a4db94011d3 4817 /* Bit 0 : Shortcut between READY event and START task. */
sahilmgandhi 18:6a4db94011d3 4818 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
sahilmgandhi 18:6a4db94011d3 4819 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
sahilmgandhi 18:6a4db94011d3 4820 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 4821 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 4822
sahilmgandhi 18:6a4db94011d3 4823 /* Register: RADIO_INTENSET */
sahilmgandhi 18:6a4db94011d3 4824 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 4825
sahilmgandhi 18:6a4db94011d3 4826 /* Bit 10 : Enable interrupt on BCMATCH event. */
sahilmgandhi 18:6a4db94011d3 4827 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 4828 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 4829 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4830 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4831 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4832
sahilmgandhi 18:6a4db94011d3 4833 /* Bit 7 : Enable interrupt on RSSIEND event. */
sahilmgandhi 18:6a4db94011d3 4834 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 4835 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 4836 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4837 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4838 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4839
sahilmgandhi 18:6a4db94011d3 4840 /* Bit 6 : Enable interrupt on DEVMISS event. */
sahilmgandhi 18:6a4db94011d3 4841 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 4842 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 4843 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4844 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4845 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4846
sahilmgandhi 18:6a4db94011d3 4847 /* Bit 5 : Enable interrupt on DEVMATCH event. */
sahilmgandhi 18:6a4db94011d3 4848 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 4849 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 4850 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4851 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4852 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4853
sahilmgandhi 18:6a4db94011d3 4854 /* Bit 4 : Enable interrupt on DISABLED event. */
sahilmgandhi 18:6a4db94011d3 4855 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 4856 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 4857 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4858 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4859 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4860
sahilmgandhi 18:6a4db94011d3 4861 /* Bit 3 : Enable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 4862 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 4863 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 4864 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4865 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4866 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4867
sahilmgandhi 18:6a4db94011d3 4868 /* Bit 2 : Enable interrupt on PAYLOAD event. */
sahilmgandhi 18:6a4db94011d3 4869 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 4870 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 4871 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4872 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4873 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4874
sahilmgandhi 18:6a4db94011d3 4875 /* Bit 1 : Enable interrupt on ADDRESS event. */
sahilmgandhi 18:6a4db94011d3 4876 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 4877 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 4878 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4879 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4880 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4881
sahilmgandhi 18:6a4db94011d3 4882 /* Bit 0 : Enable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 4883 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 4884 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 4885 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4886 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4887 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4888
sahilmgandhi 18:6a4db94011d3 4889 /* Register: RADIO_INTENCLR */
sahilmgandhi 18:6a4db94011d3 4890 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 4891
sahilmgandhi 18:6a4db94011d3 4892 /* Bit 10 : Disable interrupt on BCMATCH event. */
sahilmgandhi 18:6a4db94011d3 4893 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 4894 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
sahilmgandhi 18:6a4db94011d3 4895 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4896 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4897 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4898
sahilmgandhi 18:6a4db94011d3 4899 /* Bit 7 : Disable interrupt on RSSIEND event. */
sahilmgandhi 18:6a4db94011d3 4900 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 4901 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
sahilmgandhi 18:6a4db94011d3 4902 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4903 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4904 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4905
sahilmgandhi 18:6a4db94011d3 4906 /* Bit 6 : Disable interrupt on DEVMISS event. */
sahilmgandhi 18:6a4db94011d3 4907 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 4908 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
sahilmgandhi 18:6a4db94011d3 4909 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4910 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4911 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4912
sahilmgandhi 18:6a4db94011d3 4913 /* Bit 5 : Disable interrupt on DEVMATCH event. */
sahilmgandhi 18:6a4db94011d3 4914 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 4915 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
sahilmgandhi 18:6a4db94011d3 4916 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4917 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4918 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4919
sahilmgandhi 18:6a4db94011d3 4920 /* Bit 4 : Disable interrupt on DISABLED event. */
sahilmgandhi 18:6a4db94011d3 4921 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 4922 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
sahilmgandhi 18:6a4db94011d3 4923 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4924 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4925 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4926
sahilmgandhi 18:6a4db94011d3 4927 /* Bit 3 : Disable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 4928 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 4929 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 4930 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4931 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4932 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4933
sahilmgandhi 18:6a4db94011d3 4934 /* Bit 2 : Disable interrupt on PAYLOAD event. */
sahilmgandhi 18:6a4db94011d3 4935 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 4936 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
sahilmgandhi 18:6a4db94011d3 4937 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4938 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4939 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4940
sahilmgandhi 18:6a4db94011d3 4941 /* Bit 1 : Disable interrupt on ADDRESS event. */
sahilmgandhi 18:6a4db94011d3 4942 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 4943 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 4944 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4945 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4946 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4947
sahilmgandhi 18:6a4db94011d3 4948 /* Bit 0 : Disable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 4949 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 4950 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 4951 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 4952 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 4953 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 4954
sahilmgandhi 18:6a4db94011d3 4955 /* Register: RADIO_CRCSTATUS */
sahilmgandhi 18:6a4db94011d3 4956 /* Description: CRC status of received packet. */
sahilmgandhi 18:6a4db94011d3 4957
sahilmgandhi 18:6a4db94011d3 4958 /* Bit 0 : CRC status of received packet. */
sahilmgandhi 18:6a4db94011d3 4959 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
sahilmgandhi 18:6a4db94011d3 4960 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
sahilmgandhi 18:6a4db94011d3 4961 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
sahilmgandhi 18:6a4db94011d3 4962 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
sahilmgandhi 18:6a4db94011d3 4963
sahilmgandhi 18:6a4db94011d3 4964 /* Register: RADIO_RXMATCH */
sahilmgandhi 18:6a4db94011d3 4965 /* Description: Received address. */
sahilmgandhi 18:6a4db94011d3 4966
sahilmgandhi 18:6a4db94011d3 4967 /* Bits 2..0 : Logical address in which previous packet was received. */
sahilmgandhi 18:6a4db94011d3 4968 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
sahilmgandhi 18:6a4db94011d3 4969 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
sahilmgandhi 18:6a4db94011d3 4970
sahilmgandhi 18:6a4db94011d3 4971 /* Register: RADIO_RXCRC */
sahilmgandhi 18:6a4db94011d3 4972 /* Description: Received CRC. */
sahilmgandhi 18:6a4db94011d3 4973
sahilmgandhi 18:6a4db94011d3 4974 /* Bits 23..0 : CRC field of previously received packet. */
sahilmgandhi 18:6a4db94011d3 4975 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
sahilmgandhi 18:6a4db94011d3 4976 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
sahilmgandhi 18:6a4db94011d3 4977
sahilmgandhi 18:6a4db94011d3 4978 /* Register: RADIO_DAI */
sahilmgandhi 18:6a4db94011d3 4979 /* Description: Device address match index. */
sahilmgandhi 18:6a4db94011d3 4980
sahilmgandhi 18:6a4db94011d3 4981 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
sahilmgandhi 18:6a4db94011d3 4982 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
sahilmgandhi 18:6a4db94011d3 4983 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
sahilmgandhi 18:6a4db94011d3 4984
sahilmgandhi 18:6a4db94011d3 4985 /* Register: RADIO_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 4986 /* Description: Frequency. */
sahilmgandhi 18:6a4db94011d3 4987
sahilmgandhi 18:6a4db94011d3 4988 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
sahilmgandhi 18:6a4db94011d3 4989 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 4990 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 4991
sahilmgandhi 18:6a4db94011d3 4992 /* Register: RADIO_TXPOWER */
sahilmgandhi 18:6a4db94011d3 4993 /* Description: Output power. */
sahilmgandhi 18:6a4db94011d3 4994
sahilmgandhi 18:6a4db94011d3 4995 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
sahilmgandhi 18:6a4db94011d3 4996 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
sahilmgandhi 18:6a4db94011d3 4997 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
sahilmgandhi 18:6a4db94011d3 4998 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
sahilmgandhi 18:6a4db94011d3 4999 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
sahilmgandhi 18:6a4db94011d3 5000 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
sahilmgandhi 18:6a4db94011d3 5001 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
sahilmgandhi 18:6a4db94011d3 5002 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
sahilmgandhi 18:6a4db94011d3 5003 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
sahilmgandhi 18:6a4db94011d3 5004 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
sahilmgandhi 18:6a4db94011d3 5005 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
sahilmgandhi 18:6a4db94011d3 5006
sahilmgandhi 18:6a4db94011d3 5007 /* Register: RADIO_MODE */
sahilmgandhi 18:6a4db94011d3 5008 /* Description: Data rate and modulation. */
sahilmgandhi 18:6a4db94011d3 5009
sahilmgandhi 18:6a4db94011d3 5010 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
sahilmgandhi 18:6a4db94011d3 5011 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 5012 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 5013 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
sahilmgandhi 18:6a4db94011d3 5014 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
sahilmgandhi 18:6a4db94011d3 5015 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
sahilmgandhi 18:6a4db94011d3 5016 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
sahilmgandhi 18:6a4db94011d3 5017
sahilmgandhi 18:6a4db94011d3 5018 /* Register: RADIO_PCNF0 */
sahilmgandhi 18:6a4db94011d3 5019 /* Description: Packet configuration 0. */
sahilmgandhi 18:6a4db94011d3 5020
sahilmgandhi 18:6a4db94011d3 5021 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5022 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
sahilmgandhi 18:6a4db94011d3 5023 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
sahilmgandhi 18:6a4db94011d3 5024
sahilmgandhi 18:6a4db94011d3 5025 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5026 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
sahilmgandhi 18:6a4db94011d3 5027 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
sahilmgandhi 18:6a4db94011d3 5028
sahilmgandhi 18:6a4db94011d3 5029 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5030 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
sahilmgandhi 18:6a4db94011d3 5031 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
sahilmgandhi 18:6a4db94011d3 5032
sahilmgandhi 18:6a4db94011d3 5033 /* Register: RADIO_PCNF1 */
sahilmgandhi 18:6a4db94011d3 5034 /* Description: Packet configuration 1. */
sahilmgandhi 18:6a4db94011d3 5035
sahilmgandhi 18:6a4db94011d3 5036 /* Bit 25 : Packet whitening enable. */
sahilmgandhi 18:6a4db94011d3 5037 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
sahilmgandhi 18:6a4db94011d3 5038 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
sahilmgandhi 18:6a4db94011d3 5039 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
sahilmgandhi 18:6a4db94011d3 5040 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
sahilmgandhi 18:6a4db94011d3 5041
sahilmgandhi 18:6a4db94011d3 5042 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5043 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
sahilmgandhi 18:6a4db94011d3 5044 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
sahilmgandhi 18:6a4db94011d3 5045 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
sahilmgandhi 18:6a4db94011d3 5046 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
sahilmgandhi 18:6a4db94011d3 5047
sahilmgandhi 18:6a4db94011d3 5048 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5049 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
sahilmgandhi 18:6a4db94011d3 5050 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
sahilmgandhi 18:6a4db94011d3 5051
sahilmgandhi 18:6a4db94011d3 5052 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5053 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
sahilmgandhi 18:6a4db94011d3 5054 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
sahilmgandhi 18:6a4db94011d3 5055
sahilmgandhi 18:6a4db94011d3 5056 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
sahilmgandhi 18:6a4db94011d3 5057 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
sahilmgandhi 18:6a4db94011d3 5058 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
sahilmgandhi 18:6a4db94011d3 5059
sahilmgandhi 18:6a4db94011d3 5060 /* Register: RADIO_PREFIX0 */
sahilmgandhi 18:6a4db94011d3 5061 /* Description: Prefixes bytes for logical addresses 0 to 3. */
sahilmgandhi 18:6a4db94011d3 5062
sahilmgandhi 18:6a4db94011d3 5063 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5064 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
sahilmgandhi 18:6a4db94011d3 5065 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
sahilmgandhi 18:6a4db94011d3 5066
sahilmgandhi 18:6a4db94011d3 5067 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5068 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
sahilmgandhi 18:6a4db94011d3 5069 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
sahilmgandhi 18:6a4db94011d3 5070
sahilmgandhi 18:6a4db94011d3 5071 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5072 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
sahilmgandhi 18:6a4db94011d3 5073 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
sahilmgandhi 18:6a4db94011d3 5074
sahilmgandhi 18:6a4db94011d3 5075 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5076 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
sahilmgandhi 18:6a4db94011d3 5077 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
sahilmgandhi 18:6a4db94011d3 5078
sahilmgandhi 18:6a4db94011d3 5079 /* Register: RADIO_PREFIX1 */
sahilmgandhi 18:6a4db94011d3 5080 /* Description: Prefixes bytes for logical addresses 4 to 7. */
sahilmgandhi 18:6a4db94011d3 5081
sahilmgandhi 18:6a4db94011d3 5082 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5083 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
sahilmgandhi 18:6a4db94011d3 5084 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
sahilmgandhi 18:6a4db94011d3 5085
sahilmgandhi 18:6a4db94011d3 5086 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5087 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
sahilmgandhi 18:6a4db94011d3 5088 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
sahilmgandhi 18:6a4db94011d3 5089
sahilmgandhi 18:6a4db94011d3 5090 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5091 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
sahilmgandhi 18:6a4db94011d3 5092 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
sahilmgandhi 18:6a4db94011d3 5093
sahilmgandhi 18:6a4db94011d3 5094 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5095 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
sahilmgandhi 18:6a4db94011d3 5096 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
sahilmgandhi 18:6a4db94011d3 5097
sahilmgandhi 18:6a4db94011d3 5098 /* Register: RADIO_TXADDRESS */
sahilmgandhi 18:6a4db94011d3 5099 /* Description: Transmit address select. */
sahilmgandhi 18:6a4db94011d3 5100
sahilmgandhi 18:6a4db94011d3 5101 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5102 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
sahilmgandhi 18:6a4db94011d3 5103 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
sahilmgandhi 18:6a4db94011d3 5104
sahilmgandhi 18:6a4db94011d3 5105 /* Register: RADIO_RXADDRESSES */
sahilmgandhi 18:6a4db94011d3 5106 /* Description: Receive address select. */
sahilmgandhi 18:6a4db94011d3 5107
sahilmgandhi 18:6a4db94011d3 5108 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5109 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
sahilmgandhi 18:6a4db94011d3 5110 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
sahilmgandhi 18:6a4db94011d3 5111 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5112 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5113
sahilmgandhi 18:6a4db94011d3 5114 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5115 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
sahilmgandhi 18:6a4db94011d3 5116 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
sahilmgandhi 18:6a4db94011d3 5117 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5118 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5119
sahilmgandhi 18:6a4db94011d3 5120 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5121 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
sahilmgandhi 18:6a4db94011d3 5122 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
sahilmgandhi 18:6a4db94011d3 5123 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5124 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5125
sahilmgandhi 18:6a4db94011d3 5126 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5127 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
sahilmgandhi 18:6a4db94011d3 5128 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
sahilmgandhi 18:6a4db94011d3 5129 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5130 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5131
sahilmgandhi 18:6a4db94011d3 5132 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5133 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
sahilmgandhi 18:6a4db94011d3 5134 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
sahilmgandhi 18:6a4db94011d3 5135 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5136 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5137
sahilmgandhi 18:6a4db94011d3 5138 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5139 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
sahilmgandhi 18:6a4db94011d3 5140 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
sahilmgandhi 18:6a4db94011d3 5141 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5142 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5143
sahilmgandhi 18:6a4db94011d3 5144 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5145 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
sahilmgandhi 18:6a4db94011d3 5146 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
sahilmgandhi 18:6a4db94011d3 5147 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5148 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5149
sahilmgandhi 18:6a4db94011d3 5150 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5151 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
sahilmgandhi 18:6a4db94011d3 5152 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
sahilmgandhi 18:6a4db94011d3 5153 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
sahilmgandhi 18:6a4db94011d3 5154 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
sahilmgandhi 18:6a4db94011d3 5155
sahilmgandhi 18:6a4db94011d3 5156 /* Register: RADIO_CRCCNF */
sahilmgandhi 18:6a4db94011d3 5157 /* Description: CRC configuration. */
sahilmgandhi 18:6a4db94011d3 5158
sahilmgandhi 18:6a4db94011d3 5159 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5160 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
sahilmgandhi 18:6a4db94011d3 5161 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
sahilmgandhi 18:6a4db94011d3 5162 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
sahilmgandhi 18:6a4db94011d3 5163 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
sahilmgandhi 18:6a4db94011d3 5164
sahilmgandhi 18:6a4db94011d3 5165 /* Bits 1..0 : CRC length. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5166 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
sahilmgandhi 18:6a4db94011d3 5167 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
sahilmgandhi 18:6a4db94011d3 5168 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
sahilmgandhi 18:6a4db94011d3 5169 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
sahilmgandhi 18:6a4db94011d3 5170 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
sahilmgandhi 18:6a4db94011d3 5171 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
sahilmgandhi 18:6a4db94011d3 5172
sahilmgandhi 18:6a4db94011d3 5173 /* Register: RADIO_CRCPOLY */
sahilmgandhi 18:6a4db94011d3 5174 /* Description: CRC polynomial. */
sahilmgandhi 18:6a4db94011d3 5175
sahilmgandhi 18:6a4db94011d3 5176 /* Bits 23..0 : CRC polynomial. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5177 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
sahilmgandhi 18:6a4db94011d3 5178 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
sahilmgandhi 18:6a4db94011d3 5179
sahilmgandhi 18:6a4db94011d3 5180 /* Register: RADIO_CRCINIT */
sahilmgandhi 18:6a4db94011d3 5181 /* Description: CRC initial value. */
sahilmgandhi 18:6a4db94011d3 5182
sahilmgandhi 18:6a4db94011d3 5183 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 5184 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
sahilmgandhi 18:6a4db94011d3 5185 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
sahilmgandhi 18:6a4db94011d3 5186
sahilmgandhi 18:6a4db94011d3 5187 /* Register: RADIO_TEST */
sahilmgandhi 18:6a4db94011d3 5188 /* Description: Test features enable register. */
sahilmgandhi 18:6a4db94011d3 5189
sahilmgandhi 18:6a4db94011d3 5190 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
sahilmgandhi 18:6a4db94011d3 5191 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
sahilmgandhi 18:6a4db94011d3 5192 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
sahilmgandhi 18:6a4db94011d3 5193 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
sahilmgandhi 18:6a4db94011d3 5194 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
sahilmgandhi 18:6a4db94011d3 5195
sahilmgandhi 18:6a4db94011d3 5196 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
sahilmgandhi 18:6a4db94011d3 5197 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
sahilmgandhi 18:6a4db94011d3 5198 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
sahilmgandhi 18:6a4db94011d3 5199 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
sahilmgandhi 18:6a4db94011d3 5200 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
sahilmgandhi 18:6a4db94011d3 5201
sahilmgandhi 18:6a4db94011d3 5202 /* Register: RADIO_TIFS */
sahilmgandhi 18:6a4db94011d3 5203 /* Description: Inter Frame Spacing in microseconds. */
sahilmgandhi 18:6a4db94011d3 5204
sahilmgandhi 18:6a4db94011d3 5205 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
sahilmgandhi 18:6a4db94011d3 5206 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
sahilmgandhi 18:6a4db94011d3 5207 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
sahilmgandhi 18:6a4db94011d3 5208
sahilmgandhi 18:6a4db94011d3 5209 /* Register: RADIO_RSSISAMPLE */
sahilmgandhi 18:6a4db94011d3 5210 /* Description: RSSI sample. */
sahilmgandhi 18:6a4db94011d3 5211
sahilmgandhi 18:6a4db94011d3 5212 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
sahilmgandhi 18:6a4db94011d3 5213 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
sahilmgandhi 18:6a4db94011d3 5214 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
sahilmgandhi 18:6a4db94011d3 5215
sahilmgandhi 18:6a4db94011d3 5216 /* Register: RADIO_STATE */
sahilmgandhi 18:6a4db94011d3 5217 /* Description: Current radio state. */
sahilmgandhi 18:6a4db94011d3 5218
sahilmgandhi 18:6a4db94011d3 5219 /* Bits 3..0 : Current radio state. */
sahilmgandhi 18:6a4db94011d3 5220 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
sahilmgandhi 18:6a4db94011d3 5221 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
sahilmgandhi 18:6a4db94011d3 5222 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
sahilmgandhi 18:6a4db94011d3 5223 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
sahilmgandhi 18:6a4db94011d3 5224 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
sahilmgandhi 18:6a4db94011d3 5225 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
sahilmgandhi 18:6a4db94011d3 5226 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
sahilmgandhi 18:6a4db94011d3 5227 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
sahilmgandhi 18:6a4db94011d3 5228 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
sahilmgandhi 18:6a4db94011d3 5229 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
sahilmgandhi 18:6a4db94011d3 5230 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
sahilmgandhi 18:6a4db94011d3 5231
sahilmgandhi 18:6a4db94011d3 5232 /* Register: RADIO_DATAWHITEIV */
sahilmgandhi 18:6a4db94011d3 5233 /* Description: Data whitening initial value. */
sahilmgandhi 18:6a4db94011d3 5234
sahilmgandhi 18:6a4db94011d3 5235 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
sahilmgandhi 18:6a4db94011d3 5236 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
sahilmgandhi 18:6a4db94011d3 5237 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
sahilmgandhi 18:6a4db94011d3 5238
sahilmgandhi 18:6a4db94011d3 5239 /* Register: RADIO_DAP */
sahilmgandhi 18:6a4db94011d3 5240 /* Description: Device address prefix. */
sahilmgandhi 18:6a4db94011d3 5241
sahilmgandhi 18:6a4db94011d3 5242 /* Bits 15..0 : Device address prefix. */
sahilmgandhi 18:6a4db94011d3 5243 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
sahilmgandhi 18:6a4db94011d3 5244 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
sahilmgandhi 18:6a4db94011d3 5245
sahilmgandhi 18:6a4db94011d3 5246 /* Register: RADIO_DACNF */
sahilmgandhi 18:6a4db94011d3 5247 /* Description: Device address match configuration. */
sahilmgandhi 18:6a4db94011d3 5248
sahilmgandhi 18:6a4db94011d3 5249 /* Bit 15 : TxAdd for device address 7. */
sahilmgandhi 18:6a4db94011d3 5250 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
sahilmgandhi 18:6a4db94011d3 5251 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
sahilmgandhi 18:6a4db94011d3 5252
sahilmgandhi 18:6a4db94011d3 5253 /* Bit 14 : TxAdd for device address 6. */
sahilmgandhi 18:6a4db94011d3 5254 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
sahilmgandhi 18:6a4db94011d3 5255 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
sahilmgandhi 18:6a4db94011d3 5256
sahilmgandhi 18:6a4db94011d3 5257 /* Bit 13 : TxAdd for device address 5. */
sahilmgandhi 18:6a4db94011d3 5258 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
sahilmgandhi 18:6a4db94011d3 5259 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
sahilmgandhi 18:6a4db94011d3 5260
sahilmgandhi 18:6a4db94011d3 5261 /* Bit 12 : TxAdd for device address 4. */
sahilmgandhi 18:6a4db94011d3 5262 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
sahilmgandhi 18:6a4db94011d3 5263 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
sahilmgandhi 18:6a4db94011d3 5264
sahilmgandhi 18:6a4db94011d3 5265 /* Bit 11 : TxAdd for device address 3. */
sahilmgandhi 18:6a4db94011d3 5266 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
sahilmgandhi 18:6a4db94011d3 5267 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
sahilmgandhi 18:6a4db94011d3 5268
sahilmgandhi 18:6a4db94011d3 5269 /* Bit 10 : TxAdd for device address 2. */
sahilmgandhi 18:6a4db94011d3 5270 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
sahilmgandhi 18:6a4db94011d3 5271 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
sahilmgandhi 18:6a4db94011d3 5272
sahilmgandhi 18:6a4db94011d3 5273 /* Bit 9 : TxAdd for device address 1. */
sahilmgandhi 18:6a4db94011d3 5274 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
sahilmgandhi 18:6a4db94011d3 5275 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
sahilmgandhi 18:6a4db94011d3 5276
sahilmgandhi 18:6a4db94011d3 5277 /* Bit 8 : TxAdd for device address 0. */
sahilmgandhi 18:6a4db94011d3 5278 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
sahilmgandhi 18:6a4db94011d3 5279 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
sahilmgandhi 18:6a4db94011d3 5280
sahilmgandhi 18:6a4db94011d3 5281 /* Bit 7 : Enable or disable device address matching using device address 7. */
sahilmgandhi 18:6a4db94011d3 5282 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
sahilmgandhi 18:6a4db94011d3 5283 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
sahilmgandhi 18:6a4db94011d3 5284 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5285 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5286
sahilmgandhi 18:6a4db94011d3 5287 /* Bit 6 : Enable or disable device address matching using device address 6. */
sahilmgandhi 18:6a4db94011d3 5288 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
sahilmgandhi 18:6a4db94011d3 5289 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
sahilmgandhi 18:6a4db94011d3 5290 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5291 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5292
sahilmgandhi 18:6a4db94011d3 5293 /* Bit 5 : Enable or disable device address matching using device address 5. */
sahilmgandhi 18:6a4db94011d3 5294 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
sahilmgandhi 18:6a4db94011d3 5295 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
sahilmgandhi 18:6a4db94011d3 5296 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5297 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5298
sahilmgandhi 18:6a4db94011d3 5299 /* Bit 4 : Enable or disable device address matching using device address 4. */
sahilmgandhi 18:6a4db94011d3 5300 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
sahilmgandhi 18:6a4db94011d3 5301 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
sahilmgandhi 18:6a4db94011d3 5302 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5303 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5304
sahilmgandhi 18:6a4db94011d3 5305 /* Bit 3 : Enable or disable device address matching using device address 3. */
sahilmgandhi 18:6a4db94011d3 5306 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
sahilmgandhi 18:6a4db94011d3 5307 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
sahilmgandhi 18:6a4db94011d3 5308 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5309 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5310
sahilmgandhi 18:6a4db94011d3 5311 /* Bit 2 : Enable or disable device address matching using device address 2. */
sahilmgandhi 18:6a4db94011d3 5312 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
sahilmgandhi 18:6a4db94011d3 5313 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
sahilmgandhi 18:6a4db94011d3 5314 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5315 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5316
sahilmgandhi 18:6a4db94011d3 5317 /* Bit 1 : Enable or disable device address matching using device address 1. */
sahilmgandhi 18:6a4db94011d3 5318 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
sahilmgandhi 18:6a4db94011d3 5319 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
sahilmgandhi 18:6a4db94011d3 5320 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5321 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5322
sahilmgandhi 18:6a4db94011d3 5323 /* Bit 0 : Enable or disable device address matching using device address 0. */
sahilmgandhi 18:6a4db94011d3 5324 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
sahilmgandhi 18:6a4db94011d3 5325 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
sahilmgandhi 18:6a4db94011d3 5326 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 5327 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 5328
sahilmgandhi 18:6a4db94011d3 5329 /* Register: RADIO_OVERRIDE0 */
sahilmgandhi 18:6a4db94011d3 5330 /* Description: Trim value override register 0. */
sahilmgandhi 18:6a4db94011d3 5331
sahilmgandhi 18:6a4db94011d3 5332 /* Bits 31..0 : Trim value override 0. */
sahilmgandhi 18:6a4db94011d3 5333 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
sahilmgandhi 18:6a4db94011d3 5334 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
sahilmgandhi 18:6a4db94011d3 5335
sahilmgandhi 18:6a4db94011d3 5336 /* Register: RADIO_OVERRIDE1 */
sahilmgandhi 18:6a4db94011d3 5337 /* Description: Trim value override register 1. */
sahilmgandhi 18:6a4db94011d3 5338
sahilmgandhi 18:6a4db94011d3 5339 /* Bits 31..0 : Trim value override 1. */
sahilmgandhi 18:6a4db94011d3 5340 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
sahilmgandhi 18:6a4db94011d3 5341 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
sahilmgandhi 18:6a4db94011d3 5342
sahilmgandhi 18:6a4db94011d3 5343 /* Register: RADIO_OVERRIDE2 */
sahilmgandhi 18:6a4db94011d3 5344 /* Description: Trim value override register 2. */
sahilmgandhi 18:6a4db94011d3 5345
sahilmgandhi 18:6a4db94011d3 5346 /* Bits 31..0 : Trim value override 2. */
sahilmgandhi 18:6a4db94011d3 5347 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
sahilmgandhi 18:6a4db94011d3 5348 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
sahilmgandhi 18:6a4db94011d3 5349
sahilmgandhi 18:6a4db94011d3 5350 /* Register: RADIO_OVERRIDE3 */
sahilmgandhi 18:6a4db94011d3 5351 /* Description: Trim value override register 3. */
sahilmgandhi 18:6a4db94011d3 5352
sahilmgandhi 18:6a4db94011d3 5353 /* Bits 31..0 : Trim value override 3. */
sahilmgandhi 18:6a4db94011d3 5354 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
sahilmgandhi 18:6a4db94011d3 5355 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
sahilmgandhi 18:6a4db94011d3 5356
sahilmgandhi 18:6a4db94011d3 5357 /* Register: RADIO_OVERRIDE4 */
sahilmgandhi 18:6a4db94011d3 5358 /* Description: Trim value override register 4. */
sahilmgandhi 18:6a4db94011d3 5359
sahilmgandhi 18:6a4db94011d3 5360 /* Bit 31 : Enable or disable override of default trim values. */
sahilmgandhi 18:6a4db94011d3 5361 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 5362 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 5363 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
sahilmgandhi 18:6a4db94011d3 5364 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
sahilmgandhi 18:6a4db94011d3 5365
sahilmgandhi 18:6a4db94011d3 5366 /* Bits 27..0 : Trim value override 4. */
sahilmgandhi 18:6a4db94011d3 5367 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
sahilmgandhi 18:6a4db94011d3 5368 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
sahilmgandhi 18:6a4db94011d3 5369
sahilmgandhi 18:6a4db94011d3 5370 /* Register: RADIO_POWER */
sahilmgandhi 18:6a4db94011d3 5371 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5372
sahilmgandhi 18:6a4db94011d3 5373 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5374 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 5375 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 5376 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 5377 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 5378
sahilmgandhi 18:6a4db94011d3 5379
sahilmgandhi 18:6a4db94011d3 5380 /* Peripheral: RNG */
sahilmgandhi 18:6a4db94011d3 5381 /* Description: Random Number Generator. */
sahilmgandhi 18:6a4db94011d3 5382
sahilmgandhi 18:6a4db94011d3 5383 /* Register: RNG_SHORTS */
sahilmgandhi 18:6a4db94011d3 5384 /* Description: Shortcuts for the RNG. */
sahilmgandhi 18:6a4db94011d3 5385
sahilmgandhi 18:6a4db94011d3 5386 /* Bit 0 : Shortcut between VALRDY event and STOP task. */
sahilmgandhi 18:6a4db94011d3 5387 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 5388 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
sahilmgandhi 18:6a4db94011d3 5389 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 5390 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 5391
sahilmgandhi 18:6a4db94011d3 5392 /* Register: RNG_INTENSET */
sahilmgandhi 18:6a4db94011d3 5393 /* Description: Interrupt enable set register */
sahilmgandhi 18:6a4db94011d3 5394
sahilmgandhi 18:6a4db94011d3 5395 /* Bit 0 : Enable interrupt on VALRDY event. */
sahilmgandhi 18:6a4db94011d3 5396 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 5397 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 5398 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5399 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5400 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5401
sahilmgandhi 18:6a4db94011d3 5402 /* Register: RNG_INTENCLR */
sahilmgandhi 18:6a4db94011d3 5403 /* Description: Interrupt enable clear register */
sahilmgandhi 18:6a4db94011d3 5404
sahilmgandhi 18:6a4db94011d3 5405 /* Bit 0 : Disable interrupt on VALRDY event. */
sahilmgandhi 18:6a4db94011d3 5406 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 5407 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
sahilmgandhi 18:6a4db94011d3 5408 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5409 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5410 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5411
sahilmgandhi 18:6a4db94011d3 5412 /* Register: RNG_CONFIG */
sahilmgandhi 18:6a4db94011d3 5413 /* Description: Configuration register. */
sahilmgandhi 18:6a4db94011d3 5414
sahilmgandhi 18:6a4db94011d3 5415 /* Bit 0 : Digital error correction enable. */
sahilmgandhi 18:6a4db94011d3 5416 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
sahilmgandhi 18:6a4db94011d3 5417 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
sahilmgandhi 18:6a4db94011d3 5418 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
sahilmgandhi 18:6a4db94011d3 5419 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
sahilmgandhi 18:6a4db94011d3 5420
sahilmgandhi 18:6a4db94011d3 5421 /* Register: RNG_VALUE */
sahilmgandhi 18:6a4db94011d3 5422 /* Description: RNG random number. */
sahilmgandhi 18:6a4db94011d3 5423
sahilmgandhi 18:6a4db94011d3 5424 /* Bits 7..0 : Generated random number. */
sahilmgandhi 18:6a4db94011d3 5425 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
sahilmgandhi 18:6a4db94011d3 5426 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
sahilmgandhi 18:6a4db94011d3 5427
sahilmgandhi 18:6a4db94011d3 5428 /* Register: RNG_POWER */
sahilmgandhi 18:6a4db94011d3 5429 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5430
sahilmgandhi 18:6a4db94011d3 5431 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5432 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 5433 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 5434 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 5435 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 5436
sahilmgandhi 18:6a4db94011d3 5437
sahilmgandhi 18:6a4db94011d3 5438 /* Peripheral: RTC */
sahilmgandhi 18:6a4db94011d3 5439 /* Description: Real time counter 0. */
sahilmgandhi 18:6a4db94011d3 5440
sahilmgandhi 18:6a4db94011d3 5441 /* Register: RTC_INTENSET */
sahilmgandhi 18:6a4db94011d3 5442 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 5443
sahilmgandhi 18:6a4db94011d3 5444 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
sahilmgandhi 18:6a4db94011d3 5445 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5446 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5447 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5448 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5449 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5450
sahilmgandhi 18:6a4db94011d3 5451 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
sahilmgandhi 18:6a4db94011d3 5452 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5453 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5454 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5455 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5456 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5457
sahilmgandhi 18:6a4db94011d3 5458 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
sahilmgandhi 18:6a4db94011d3 5459 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5460 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5461 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5462 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5463 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5464
sahilmgandhi 18:6a4db94011d3 5465 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
sahilmgandhi 18:6a4db94011d3 5466 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5467 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5468 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5469 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5470 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5471
sahilmgandhi 18:6a4db94011d3 5472 /* Bit 1 : Enable interrupt on OVRFLW event. */
sahilmgandhi 18:6a4db94011d3 5473 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5474 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5475 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5476 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5477 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5478
sahilmgandhi 18:6a4db94011d3 5479 /* Bit 0 : Enable interrupt on TICK event. */
sahilmgandhi 18:6a4db94011d3 5480 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 5481 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 5482 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5483 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5484 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5485
sahilmgandhi 18:6a4db94011d3 5486 /* Register: RTC_INTENCLR */
sahilmgandhi 18:6a4db94011d3 5487 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 5488
sahilmgandhi 18:6a4db94011d3 5489 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
sahilmgandhi 18:6a4db94011d3 5490 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5491 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5492 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5493 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5494 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5495
sahilmgandhi 18:6a4db94011d3 5496 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
sahilmgandhi 18:6a4db94011d3 5497 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5498 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5499 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5500 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5501 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5502
sahilmgandhi 18:6a4db94011d3 5503 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
sahilmgandhi 18:6a4db94011d3 5504 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5505 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5506 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5507 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5508 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5509
sahilmgandhi 18:6a4db94011d3 5510 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
sahilmgandhi 18:6a4db94011d3 5511 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5512 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5513 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5514 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5515 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5516
sahilmgandhi 18:6a4db94011d3 5517 /* Bit 1 : Disable interrupt on OVRFLW event. */
sahilmgandhi 18:6a4db94011d3 5518 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5519 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5520 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5521 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5522 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5523
sahilmgandhi 18:6a4db94011d3 5524 /* Bit 0 : Disable interrupt on TICK event. */
sahilmgandhi 18:6a4db94011d3 5525 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 5526 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 5527 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5528 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5529 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5530
sahilmgandhi 18:6a4db94011d3 5531 /* Register: RTC_EVTEN */
sahilmgandhi 18:6a4db94011d3 5532 /* Description: Configures event enable routing to PPI for each RTC event. */
sahilmgandhi 18:6a4db94011d3 5533
sahilmgandhi 18:6a4db94011d3 5534 /* Bit 19 : COMPARE[3] event enable. */
sahilmgandhi 18:6a4db94011d3 5535 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5536 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5537 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5538 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5539
sahilmgandhi 18:6a4db94011d3 5540 /* Bit 18 : COMPARE[2] event enable. */
sahilmgandhi 18:6a4db94011d3 5541 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5542 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5543 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5544 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5545
sahilmgandhi 18:6a4db94011d3 5546 /* Bit 17 : COMPARE[1] event enable. */
sahilmgandhi 18:6a4db94011d3 5547 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5548 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5549 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5550 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5551
sahilmgandhi 18:6a4db94011d3 5552 /* Bit 16 : COMPARE[0] event enable. */
sahilmgandhi 18:6a4db94011d3 5553 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5554 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5555 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5556 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5557
sahilmgandhi 18:6a4db94011d3 5558 /* Bit 1 : OVRFLW event enable. */
sahilmgandhi 18:6a4db94011d3 5559 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5560 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5561 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5562 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5563
sahilmgandhi 18:6a4db94011d3 5564 /* Bit 0 : TICK event enable. */
sahilmgandhi 18:6a4db94011d3 5565 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 5566 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 5567 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5568 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5569
sahilmgandhi 18:6a4db94011d3 5570 /* Register: RTC_EVTENSET */
sahilmgandhi 18:6a4db94011d3 5571 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
sahilmgandhi 18:6a4db94011d3 5572
sahilmgandhi 18:6a4db94011d3 5573 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
sahilmgandhi 18:6a4db94011d3 5574 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5575 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5576 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5577 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5578 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
sahilmgandhi 18:6a4db94011d3 5579
sahilmgandhi 18:6a4db94011d3 5580 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
sahilmgandhi 18:6a4db94011d3 5581 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5582 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5583 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5584 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5585 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
sahilmgandhi 18:6a4db94011d3 5586
sahilmgandhi 18:6a4db94011d3 5587 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
sahilmgandhi 18:6a4db94011d3 5588 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5589 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5590 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5591 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5592 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
sahilmgandhi 18:6a4db94011d3 5593
sahilmgandhi 18:6a4db94011d3 5594 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
sahilmgandhi 18:6a4db94011d3 5595 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5596 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5597 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5598 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5599 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
sahilmgandhi 18:6a4db94011d3 5600
sahilmgandhi 18:6a4db94011d3 5601 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
sahilmgandhi 18:6a4db94011d3 5602 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5603 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5604 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5605 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5606 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
sahilmgandhi 18:6a4db94011d3 5607
sahilmgandhi 18:6a4db94011d3 5608 /* Bit 0 : Enable routing to PPI of TICK event. */
sahilmgandhi 18:6a4db94011d3 5609 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 5610 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 5611 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5612 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5613 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
sahilmgandhi 18:6a4db94011d3 5614
sahilmgandhi 18:6a4db94011d3 5615 /* Register: RTC_EVTENCLR */
sahilmgandhi 18:6a4db94011d3 5616 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
sahilmgandhi 18:6a4db94011d3 5617
sahilmgandhi 18:6a4db94011d3 5618 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
sahilmgandhi 18:6a4db94011d3 5619 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5620 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 5621 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5622 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5623 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
sahilmgandhi 18:6a4db94011d3 5624
sahilmgandhi 18:6a4db94011d3 5625 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
sahilmgandhi 18:6a4db94011d3 5626 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5627 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 5628 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5629 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5630 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
sahilmgandhi 18:6a4db94011d3 5631
sahilmgandhi 18:6a4db94011d3 5632 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
sahilmgandhi 18:6a4db94011d3 5633 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5634 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 5635 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5636 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5637 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
sahilmgandhi 18:6a4db94011d3 5638
sahilmgandhi 18:6a4db94011d3 5639 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
sahilmgandhi 18:6a4db94011d3 5640 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5641 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 5642 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5643 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5644 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
sahilmgandhi 18:6a4db94011d3 5645
sahilmgandhi 18:6a4db94011d3 5646 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
sahilmgandhi 18:6a4db94011d3 5647 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5648 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
sahilmgandhi 18:6a4db94011d3 5649 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5650 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5651 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
sahilmgandhi 18:6a4db94011d3 5652
sahilmgandhi 18:6a4db94011d3 5653 /* Bit 0 : Disable routing to PPI of TICK event. */
sahilmgandhi 18:6a4db94011d3 5654 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
sahilmgandhi 18:6a4db94011d3 5655 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
sahilmgandhi 18:6a4db94011d3 5656 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
sahilmgandhi 18:6a4db94011d3 5657 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
sahilmgandhi 18:6a4db94011d3 5658 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
sahilmgandhi 18:6a4db94011d3 5659
sahilmgandhi 18:6a4db94011d3 5660 /* Register: RTC_COUNTER */
sahilmgandhi 18:6a4db94011d3 5661 /* Description: Current COUNTER value. */
sahilmgandhi 18:6a4db94011d3 5662
sahilmgandhi 18:6a4db94011d3 5663 /* Bits 23..0 : Counter value. */
sahilmgandhi 18:6a4db94011d3 5664 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
sahilmgandhi 18:6a4db94011d3 5665 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
sahilmgandhi 18:6a4db94011d3 5666
sahilmgandhi 18:6a4db94011d3 5667 /* Register: RTC_PRESCALER */
sahilmgandhi 18:6a4db94011d3 5668 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
sahilmgandhi 18:6a4db94011d3 5669
sahilmgandhi 18:6a4db94011d3 5670 /* Bits 11..0 : RTC PRESCALER value. */
sahilmgandhi 18:6a4db94011d3 5671 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 5672 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 5673
sahilmgandhi 18:6a4db94011d3 5674 /* Register: RTC_CC */
sahilmgandhi 18:6a4db94011d3 5675 /* Description: Capture/compare registers. */
sahilmgandhi 18:6a4db94011d3 5676
sahilmgandhi 18:6a4db94011d3 5677 /* Bits 23..0 : Compare value. */
sahilmgandhi 18:6a4db94011d3 5678 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
sahilmgandhi 18:6a4db94011d3 5679 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
sahilmgandhi 18:6a4db94011d3 5680
sahilmgandhi 18:6a4db94011d3 5681 /* Register: RTC_POWER */
sahilmgandhi 18:6a4db94011d3 5682 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5683
sahilmgandhi 18:6a4db94011d3 5684 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5685 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 5686 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 5687 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 5688 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 5689
sahilmgandhi 18:6a4db94011d3 5690
sahilmgandhi 18:6a4db94011d3 5691 /* Peripheral: SPI */
sahilmgandhi 18:6a4db94011d3 5692 /* Description: SPI master 0. */
sahilmgandhi 18:6a4db94011d3 5693
sahilmgandhi 18:6a4db94011d3 5694 /* Register: SPI_INTENSET */
sahilmgandhi 18:6a4db94011d3 5695 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 5696
sahilmgandhi 18:6a4db94011d3 5697 /* Bit 2 : Enable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 5698 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 5699 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 5700 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5701 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5702 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5703
sahilmgandhi 18:6a4db94011d3 5704 /* Register: SPI_INTENCLR */
sahilmgandhi 18:6a4db94011d3 5705 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 5706
sahilmgandhi 18:6a4db94011d3 5707 /* Bit 2 : Disable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 5708 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
sahilmgandhi 18:6a4db94011d3 5709 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
sahilmgandhi 18:6a4db94011d3 5710 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5711 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5712 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5713
sahilmgandhi 18:6a4db94011d3 5714 /* Register: SPI_ENABLE */
sahilmgandhi 18:6a4db94011d3 5715 /* Description: Enable SPI. */
sahilmgandhi 18:6a4db94011d3 5716
sahilmgandhi 18:6a4db94011d3 5717 /* Bits 2..0 : Enable or disable SPI. */
sahilmgandhi 18:6a4db94011d3 5718 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 5719 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 5720 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
sahilmgandhi 18:6a4db94011d3 5721 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
sahilmgandhi 18:6a4db94011d3 5722
sahilmgandhi 18:6a4db94011d3 5723 /* Register: SPI_RXD */
sahilmgandhi 18:6a4db94011d3 5724 /* Description: RX data. */
sahilmgandhi 18:6a4db94011d3 5725
sahilmgandhi 18:6a4db94011d3 5726 /* Bits 7..0 : RX data from last transfer. */
sahilmgandhi 18:6a4db94011d3 5727 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
sahilmgandhi 18:6a4db94011d3 5728 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
sahilmgandhi 18:6a4db94011d3 5729
sahilmgandhi 18:6a4db94011d3 5730 /* Register: SPI_TXD */
sahilmgandhi 18:6a4db94011d3 5731 /* Description: TX data. */
sahilmgandhi 18:6a4db94011d3 5732
sahilmgandhi 18:6a4db94011d3 5733 /* Bits 7..0 : TX data for next transfer. */
sahilmgandhi 18:6a4db94011d3 5734 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
sahilmgandhi 18:6a4db94011d3 5735 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
sahilmgandhi 18:6a4db94011d3 5736
sahilmgandhi 18:6a4db94011d3 5737 /* Register: SPI_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 5738 /* Description: SPI frequency */
sahilmgandhi 18:6a4db94011d3 5739
sahilmgandhi 18:6a4db94011d3 5740 /* Bits 31..0 : SPI data rate. */
sahilmgandhi 18:6a4db94011d3 5741 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 5742 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 5743 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
sahilmgandhi 18:6a4db94011d3 5744 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
sahilmgandhi 18:6a4db94011d3 5745 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
sahilmgandhi 18:6a4db94011d3 5746 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
sahilmgandhi 18:6a4db94011d3 5747 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
sahilmgandhi 18:6a4db94011d3 5748 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
sahilmgandhi 18:6a4db94011d3 5749 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
sahilmgandhi 18:6a4db94011d3 5750
sahilmgandhi 18:6a4db94011d3 5751 /* Register: SPI_CONFIG */
sahilmgandhi 18:6a4db94011d3 5752 /* Description: Configuration register. */
sahilmgandhi 18:6a4db94011d3 5753
sahilmgandhi 18:6a4db94011d3 5754 /* Bit 2 : Serial clock (SCK) polarity. */
sahilmgandhi 18:6a4db94011d3 5755 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
sahilmgandhi 18:6a4db94011d3 5756 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
sahilmgandhi 18:6a4db94011d3 5757 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
sahilmgandhi 18:6a4db94011d3 5758 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
sahilmgandhi 18:6a4db94011d3 5759
sahilmgandhi 18:6a4db94011d3 5760 /* Bit 1 : Serial clock (SCK) phase. */
sahilmgandhi 18:6a4db94011d3 5761 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
sahilmgandhi 18:6a4db94011d3 5762 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
sahilmgandhi 18:6a4db94011d3 5763 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
sahilmgandhi 18:6a4db94011d3 5764 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
sahilmgandhi 18:6a4db94011d3 5765
sahilmgandhi 18:6a4db94011d3 5766 /* Bit 0 : Bit order. */
sahilmgandhi 18:6a4db94011d3 5767 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
sahilmgandhi 18:6a4db94011d3 5768 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
sahilmgandhi 18:6a4db94011d3 5769 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
sahilmgandhi 18:6a4db94011d3 5770 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
sahilmgandhi 18:6a4db94011d3 5771
sahilmgandhi 18:6a4db94011d3 5772 /* Register: SPI_POWER */
sahilmgandhi 18:6a4db94011d3 5773 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5774
sahilmgandhi 18:6a4db94011d3 5775 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5776 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 5777 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 5778 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 5779 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 5780
sahilmgandhi 18:6a4db94011d3 5781
sahilmgandhi 18:6a4db94011d3 5782 /* Peripheral: SPIM */
sahilmgandhi 18:6a4db94011d3 5783 /* Description: SPI master with easyDMA 1. */
sahilmgandhi 18:6a4db94011d3 5784
sahilmgandhi 18:6a4db94011d3 5785 /* Register: SPIM_INTENSET */
sahilmgandhi 18:6a4db94011d3 5786 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 5787
sahilmgandhi 18:6a4db94011d3 5788 /* Bit 19 : Enable interrupt on STARTED event. */
sahilmgandhi 18:6a4db94011d3 5789 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 5790 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 5791 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5792 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5793 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5794
sahilmgandhi 18:6a4db94011d3 5795 /* Bit 8 : Enable interrupt on ENDTX event. */
sahilmgandhi 18:6a4db94011d3 5796 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 5797 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 5798 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5799 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5800 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5801
sahilmgandhi 18:6a4db94011d3 5802 /* Bit 4 : Enable interrupt on ENDRX event. */
sahilmgandhi 18:6a4db94011d3 5803 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5804 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5805 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5806 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5807 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5808
sahilmgandhi 18:6a4db94011d3 5809 /* Bit 1 : Enable interrupt on STOPPED event. */
sahilmgandhi 18:6a4db94011d3 5810 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 5811 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 5812 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5813 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5814 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5815
sahilmgandhi 18:6a4db94011d3 5816 /* Register: SPIM_INTENCLR */
sahilmgandhi 18:6a4db94011d3 5817 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 5818
sahilmgandhi 18:6a4db94011d3 5819 /* Bit 19 : Disable interrupt on STARTED event. */
sahilmgandhi 18:6a4db94011d3 5820 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
sahilmgandhi 18:6a4db94011d3 5821 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
sahilmgandhi 18:6a4db94011d3 5822 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5823 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5824 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5825
sahilmgandhi 18:6a4db94011d3 5826 /* Bit 8 : Disable interrupt on ENDTX event. */
sahilmgandhi 18:6a4db94011d3 5827 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 5828 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
sahilmgandhi 18:6a4db94011d3 5829 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5830 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5831 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5832
sahilmgandhi 18:6a4db94011d3 5833 /* Bit 4 : Disable interrupt on ENDRX event. */
sahilmgandhi 18:6a4db94011d3 5834 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5835 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5836 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5837 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5838 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5839
sahilmgandhi 18:6a4db94011d3 5840 /* Bit 1 : Disable interrupt on STOPPED event. */
sahilmgandhi 18:6a4db94011d3 5841 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 5842 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 5843 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5844 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5845 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5846
sahilmgandhi 18:6a4db94011d3 5847 /* Register: SPIM_ENABLE */
sahilmgandhi 18:6a4db94011d3 5848 /* Description: Enable SPIM. */
sahilmgandhi 18:6a4db94011d3 5849
sahilmgandhi 18:6a4db94011d3 5850 /* Bits 3..0 : Enable or disable SPIM. */
sahilmgandhi 18:6a4db94011d3 5851 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 5852 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 5853 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
sahilmgandhi 18:6a4db94011d3 5854 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
sahilmgandhi 18:6a4db94011d3 5855
sahilmgandhi 18:6a4db94011d3 5856 /* Register: SPIM_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 5857 /* Description: SPI frequency. */
sahilmgandhi 18:6a4db94011d3 5858
sahilmgandhi 18:6a4db94011d3 5859 /* Bits 31..0 : SPI master data rate. */
sahilmgandhi 18:6a4db94011d3 5860 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 5861 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 5862 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
sahilmgandhi 18:6a4db94011d3 5863 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
sahilmgandhi 18:6a4db94011d3 5864 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
sahilmgandhi 18:6a4db94011d3 5865 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
sahilmgandhi 18:6a4db94011d3 5866 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
sahilmgandhi 18:6a4db94011d3 5867 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
sahilmgandhi 18:6a4db94011d3 5868 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
sahilmgandhi 18:6a4db94011d3 5869
sahilmgandhi 18:6a4db94011d3 5870 /* Register: SPIM_RXD_PTR */
sahilmgandhi 18:6a4db94011d3 5871 /* Description: Data pointer. */
sahilmgandhi 18:6a4db94011d3 5872
sahilmgandhi 18:6a4db94011d3 5873 /* Bits 31..0 : Data pointer. */
sahilmgandhi 18:6a4db94011d3 5874 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 5875 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 5876
sahilmgandhi 18:6a4db94011d3 5877 /* Register: SPIM_RXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 5878 /* Description: Maximum number of buffer bytes to receive. */
sahilmgandhi 18:6a4db94011d3 5879
sahilmgandhi 18:6a4db94011d3 5880 /* Bits 7..0 : Maximum number of buffer bytes to receive. */
sahilmgandhi 18:6a4db94011d3 5881 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 5882 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 5883
sahilmgandhi 18:6a4db94011d3 5884 /* Register: SPIM_RXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 5885 /* Description: Number of bytes received in the last transaction. */
sahilmgandhi 18:6a4db94011d3 5886
sahilmgandhi 18:6a4db94011d3 5887 /* Bits 7..0 : Number of bytes received in the last transaction. */
sahilmgandhi 18:6a4db94011d3 5888 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 5889 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 5890
sahilmgandhi 18:6a4db94011d3 5891 /* Register: SPIM_TXD_PTR */
sahilmgandhi 18:6a4db94011d3 5892 /* Description: Data pointer. */
sahilmgandhi 18:6a4db94011d3 5893
sahilmgandhi 18:6a4db94011d3 5894 /* Bits 31..0 : Data pointer. */
sahilmgandhi 18:6a4db94011d3 5895 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
sahilmgandhi 18:6a4db94011d3 5896 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
sahilmgandhi 18:6a4db94011d3 5897
sahilmgandhi 18:6a4db94011d3 5898 /* Register: SPIM_TXD_MAXCNT */
sahilmgandhi 18:6a4db94011d3 5899 /* Description: Maximum number of buffer bytes to send. */
sahilmgandhi 18:6a4db94011d3 5900
sahilmgandhi 18:6a4db94011d3 5901 /* Bits 7..0 : Maximum number of buffer bytes to send. */
sahilmgandhi 18:6a4db94011d3 5902 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 5903 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
sahilmgandhi 18:6a4db94011d3 5904
sahilmgandhi 18:6a4db94011d3 5905 /* Register: SPIM_TXD_AMOUNT */
sahilmgandhi 18:6a4db94011d3 5906 /* Description: Number of bytes sent in the last transaction. */
sahilmgandhi 18:6a4db94011d3 5907
sahilmgandhi 18:6a4db94011d3 5908 /* Bits 7..0 : Number of bytes sent in the last transaction. */
sahilmgandhi 18:6a4db94011d3 5909 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 5910 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
sahilmgandhi 18:6a4db94011d3 5911
sahilmgandhi 18:6a4db94011d3 5912 /* Register: SPIM_CONFIG */
sahilmgandhi 18:6a4db94011d3 5913 /* Description: Configuration register. */
sahilmgandhi 18:6a4db94011d3 5914
sahilmgandhi 18:6a4db94011d3 5915 /* Bit 2 : Serial clock (SCK) polarity. */
sahilmgandhi 18:6a4db94011d3 5916 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
sahilmgandhi 18:6a4db94011d3 5917 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
sahilmgandhi 18:6a4db94011d3 5918 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
sahilmgandhi 18:6a4db94011d3 5919 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
sahilmgandhi 18:6a4db94011d3 5920
sahilmgandhi 18:6a4db94011d3 5921 /* Bit 1 : Serial clock (SCK) phase. */
sahilmgandhi 18:6a4db94011d3 5922 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
sahilmgandhi 18:6a4db94011d3 5923 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
sahilmgandhi 18:6a4db94011d3 5924 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
sahilmgandhi 18:6a4db94011d3 5925 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
sahilmgandhi 18:6a4db94011d3 5926
sahilmgandhi 18:6a4db94011d3 5927 /* Bit 0 : Bit order. */
sahilmgandhi 18:6a4db94011d3 5928 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
sahilmgandhi 18:6a4db94011d3 5929 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
sahilmgandhi 18:6a4db94011d3 5930 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
sahilmgandhi 18:6a4db94011d3 5931 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
sahilmgandhi 18:6a4db94011d3 5932
sahilmgandhi 18:6a4db94011d3 5933 /* Register: SPIM_ORC */
sahilmgandhi 18:6a4db94011d3 5934 /* Description: Over-read character. */
sahilmgandhi 18:6a4db94011d3 5935
sahilmgandhi 18:6a4db94011d3 5936 /* Bits 7..0 : Over-read character. */
sahilmgandhi 18:6a4db94011d3 5937 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
sahilmgandhi 18:6a4db94011d3 5938 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
sahilmgandhi 18:6a4db94011d3 5939
sahilmgandhi 18:6a4db94011d3 5940 /* Register: SPIM_POWER */
sahilmgandhi 18:6a4db94011d3 5941 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5942
sahilmgandhi 18:6a4db94011d3 5943 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 5944 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 5945 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 5946 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 5947 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 5948
sahilmgandhi 18:6a4db94011d3 5949
sahilmgandhi 18:6a4db94011d3 5950 /* Peripheral: SPIS */
sahilmgandhi 18:6a4db94011d3 5951 /* Description: SPI slave 1. */
sahilmgandhi 18:6a4db94011d3 5952
sahilmgandhi 18:6a4db94011d3 5953 /* Register: SPIS_SHORTS */
sahilmgandhi 18:6a4db94011d3 5954 /* Description: Shortcuts for SPIS. */
sahilmgandhi 18:6a4db94011d3 5955
sahilmgandhi 18:6a4db94011d3 5956 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
sahilmgandhi 18:6a4db94011d3 5957 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
sahilmgandhi 18:6a4db94011d3 5958 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
sahilmgandhi 18:6a4db94011d3 5959 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 5960 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 5961
sahilmgandhi 18:6a4db94011d3 5962 /* Register: SPIS_INTENSET */
sahilmgandhi 18:6a4db94011d3 5963 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 5964
sahilmgandhi 18:6a4db94011d3 5965 /* Bit 10 : Enable interrupt on ACQUIRED event. */
sahilmgandhi 18:6a4db94011d3 5966 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 5967 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 5968 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5969 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5970 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5971
sahilmgandhi 18:6a4db94011d3 5972 /* Bit 4 : enable interrupt on ENDRX event. */
sahilmgandhi 18:6a4db94011d3 5973 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5974 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5975 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5976 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5977 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5978
sahilmgandhi 18:6a4db94011d3 5979 /* Bit 1 : Enable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 5980 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 5981 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 5982 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5983 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5984 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5985
sahilmgandhi 18:6a4db94011d3 5986 /* Register: SPIS_INTENCLR */
sahilmgandhi 18:6a4db94011d3 5987 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 5988
sahilmgandhi 18:6a4db94011d3 5989 /* Bit 10 : Disable interrupt on ACQUIRED event. */
sahilmgandhi 18:6a4db94011d3 5990 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 5991 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
sahilmgandhi 18:6a4db94011d3 5992 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 5993 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 5994 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 5995
sahilmgandhi 18:6a4db94011d3 5996 /* Bit 4 : Disable interrupt on ENDRX event. */
sahilmgandhi 18:6a4db94011d3 5997 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5998 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
sahilmgandhi 18:6a4db94011d3 5999 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6000 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6001 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6002
sahilmgandhi 18:6a4db94011d3 6003 /* Bit 1 : Disable interrupt on END event. */
sahilmgandhi 18:6a4db94011d3 6004 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
sahilmgandhi 18:6a4db94011d3 6005 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
sahilmgandhi 18:6a4db94011d3 6006 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6007 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6008 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6009
sahilmgandhi 18:6a4db94011d3 6010 /* Register: SPIS_SEMSTAT */
sahilmgandhi 18:6a4db94011d3 6011 /* Description: Semaphore status. */
sahilmgandhi 18:6a4db94011d3 6012
sahilmgandhi 18:6a4db94011d3 6013 /* Bits 1..0 : Semaphore status. */
sahilmgandhi 18:6a4db94011d3 6014 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
sahilmgandhi 18:6a4db94011d3 6015 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
sahilmgandhi 18:6a4db94011d3 6016 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
sahilmgandhi 18:6a4db94011d3 6017 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
sahilmgandhi 18:6a4db94011d3 6018 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
sahilmgandhi 18:6a4db94011d3 6019 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
sahilmgandhi 18:6a4db94011d3 6020
sahilmgandhi 18:6a4db94011d3 6021 /* Register: SPIS_STATUS */
sahilmgandhi 18:6a4db94011d3 6022 /* Description: Status from last transaction. */
sahilmgandhi 18:6a4db94011d3 6023
sahilmgandhi 18:6a4db94011d3 6024 /* Bit 1 : RX buffer overflow detected, and prevented. */
sahilmgandhi 18:6a4db94011d3 6025 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
sahilmgandhi 18:6a4db94011d3 6026 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
sahilmgandhi 18:6a4db94011d3 6027 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6028 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6029 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
sahilmgandhi 18:6a4db94011d3 6030
sahilmgandhi 18:6a4db94011d3 6031 /* Bit 0 : TX buffer overread detected, and prevented. */
sahilmgandhi 18:6a4db94011d3 6032 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
sahilmgandhi 18:6a4db94011d3 6033 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
sahilmgandhi 18:6a4db94011d3 6034 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6035 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6036 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
sahilmgandhi 18:6a4db94011d3 6037
sahilmgandhi 18:6a4db94011d3 6038 /* Register: SPIS_ENABLE */
sahilmgandhi 18:6a4db94011d3 6039 /* Description: Enable SPIS. */
sahilmgandhi 18:6a4db94011d3 6040
sahilmgandhi 18:6a4db94011d3 6041 /* Bits 2..0 : Enable or disable SPIS. */
sahilmgandhi 18:6a4db94011d3 6042 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 6043 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 6044 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
sahilmgandhi 18:6a4db94011d3 6045 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
sahilmgandhi 18:6a4db94011d3 6046
sahilmgandhi 18:6a4db94011d3 6047 /* Register: SPIS_MAXRX */
sahilmgandhi 18:6a4db94011d3 6048 /* Description: Maximum number of bytes in the receive buffer. */
sahilmgandhi 18:6a4db94011d3 6049
sahilmgandhi 18:6a4db94011d3 6050 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
sahilmgandhi 18:6a4db94011d3 6051 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
sahilmgandhi 18:6a4db94011d3 6052 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
sahilmgandhi 18:6a4db94011d3 6053
sahilmgandhi 18:6a4db94011d3 6054 /* Register: SPIS_AMOUNTRX */
sahilmgandhi 18:6a4db94011d3 6055 /* Description: Number of bytes received in last granted transaction. */
sahilmgandhi 18:6a4db94011d3 6056
sahilmgandhi 18:6a4db94011d3 6057 /* Bits 7..0 : Number of bytes received in last granted transaction. */
sahilmgandhi 18:6a4db94011d3 6058 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
sahilmgandhi 18:6a4db94011d3 6059 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
sahilmgandhi 18:6a4db94011d3 6060
sahilmgandhi 18:6a4db94011d3 6061 /* Register: SPIS_MAXTX */
sahilmgandhi 18:6a4db94011d3 6062 /* Description: Maximum number of bytes in the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 6063
sahilmgandhi 18:6a4db94011d3 6064 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 6065 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
sahilmgandhi 18:6a4db94011d3 6066 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
sahilmgandhi 18:6a4db94011d3 6067
sahilmgandhi 18:6a4db94011d3 6068 /* Register: SPIS_AMOUNTTX */
sahilmgandhi 18:6a4db94011d3 6069 /* Description: Number of bytes transmitted in last granted transaction. */
sahilmgandhi 18:6a4db94011d3 6070
sahilmgandhi 18:6a4db94011d3 6071 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
sahilmgandhi 18:6a4db94011d3 6072 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
sahilmgandhi 18:6a4db94011d3 6073 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
sahilmgandhi 18:6a4db94011d3 6074
sahilmgandhi 18:6a4db94011d3 6075 /* Register: SPIS_CONFIG */
sahilmgandhi 18:6a4db94011d3 6076 /* Description: Configuration register. */
sahilmgandhi 18:6a4db94011d3 6077
sahilmgandhi 18:6a4db94011d3 6078 /* Bit 2 : Serial clock (SCK) polarity. */
sahilmgandhi 18:6a4db94011d3 6079 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
sahilmgandhi 18:6a4db94011d3 6080 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
sahilmgandhi 18:6a4db94011d3 6081 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
sahilmgandhi 18:6a4db94011d3 6082 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
sahilmgandhi 18:6a4db94011d3 6083
sahilmgandhi 18:6a4db94011d3 6084 /* Bit 1 : Serial clock (SCK) phase. */
sahilmgandhi 18:6a4db94011d3 6085 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
sahilmgandhi 18:6a4db94011d3 6086 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
sahilmgandhi 18:6a4db94011d3 6087 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
sahilmgandhi 18:6a4db94011d3 6088 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
sahilmgandhi 18:6a4db94011d3 6089
sahilmgandhi 18:6a4db94011d3 6090 /* Bit 0 : Bit order. */
sahilmgandhi 18:6a4db94011d3 6091 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
sahilmgandhi 18:6a4db94011d3 6092 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
sahilmgandhi 18:6a4db94011d3 6093 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
sahilmgandhi 18:6a4db94011d3 6094 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
sahilmgandhi 18:6a4db94011d3 6095
sahilmgandhi 18:6a4db94011d3 6096 /* Register: SPIS_DEF */
sahilmgandhi 18:6a4db94011d3 6097 /* Description: Default character. */
sahilmgandhi 18:6a4db94011d3 6098
sahilmgandhi 18:6a4db94011d3 6099 /* Bits 7..0 : Default character. */
sahilmgandhi 18:6a4db94011d3 6100 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
sahilmgandhi 18:6a4db94011d3 6101 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
sahilmgandhi 18:6a4db94011d3 6102
sahilmgandhi 18:6a4db94011d3 6103 /* Register: SPIS_ORC */
sahilmgandhi 18:6a4db94011d3 6104 /* Description: Over-read character. */
sahilmgandhi 18:6a4db94011d3 6105
sahilmgandhi 18:6a4db94011d3 6106 /* Bits 7..0 : Over-read character. */
sahilmgandhi 18:6a4db94011d3 6107 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
sahilmgandhi 18:6a4db94011d3 6108 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
sahilmgandhi 18:6a4db94011d3 6109
sahilmgandhi 18:6a4db94011d3 6110 /* Register: SPIS_POWER */
sahilmgandhi 18:6a4db94011d3 6111 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6112
sahilmgandhi 18:6a4db94011d3 6113 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6114 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 6115 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 6116 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 6117 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 6118
sahilmgandhi 18:6a4db94011d3 6119
sahilmgandhi 18:6a4db94011d3 6120 /* Peripheral: TEMP */
sahilmgandhi 18:6a4db94011d3 6121 /* Description: Temperature Sensor. */
sahilmgandhi 18:6a4db94011d3 6122
sahilmgandhi 18:6a4db94011d3 6123 /* Register: TEMP_INTENSET */
sahilmgandhi 18:6a4db94011d3 6124 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 6125
sahilmgandhi 18:6a4db94011d3 6126 /* Bit 0 : Enable interrupt on DATARDY event. */
sahilmgandhi 18:6a4db94011d3 6127 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 6128 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 6129 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6130 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6131 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6132
sahilmgandhi 18:6a4db94011d3 6133 /* Register: TEMP_INTENCLR */
sahilmgandhi 18:6a4db94011d3 6134 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 6135
sahilmgandhi 18:6a4db94011d3 6136 /* Bit 0 : Disable interrupt on DATARDY event. */
sahilmgandhi 18:6a4db94011d3 6137 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 6138 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
sahilmgandhi 18:6a4db94011d3 6139 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6140 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6141 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6142
sahilmgandhi 18:6a4db94011d3 6143 /* Register: TEMP_POWER */
sahilmgandhi 18:6a4db94011d3 6144 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6145
sahilmgandhi 18:6a4db94011d3 6146 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6147 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 6148 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 6149 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 6150 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 6151
sahilmgandhi 18:6a4db94011d3 6152
sahilmgandhi 18:6a4db94011d3 6153 /* Peripheral: TIMER */
sahilmgandhi 18:6a4db94011d3 6154 /* Description: Timer 0. */
sahilmgandhi 18:6a4db94011d3 6155
sahilmgandhi 18:6a4db94011d3 6156 /* Register: TIMER_SHORTS */
sahilmgandhi 18:6a4db94011d3 6157 /* Description: Shortcuts for Timer. */
sahilmgandhi 18:6a4db94011d3 6158
sahilmgandhi 18:6a4db94011d3 6159 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
sahilmgandhi 18:6a4db94011d3 6160 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
sahilmgandhi 18:6a4db94011d3 6161 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
sahilmgandhi 18:6a4db94011d3 6162 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6163 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6164
sahilmgandhi 18:6a4db94011d3 6165 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
sahilmgandhi 18:6a4db94011d3 6166 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
sahilmgandhi 18:6a4db94011d3 6167 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
sahilmgandhi 18:6a4db94011d3 6168 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6169 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6170
sahilmgandhi 18:6a4db94011d3 6171 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
sahilmgandhi 18:6a4db94011d3 6172 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
sahilmgandhi 18:6a4db94011d3 6173 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
sahilmgandhi 18:6a4db94011d3 6174 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6175 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6176
sahilmgandhi 18:6a4db94011d3 6177 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
sahilmgandhi 18:6a4db94011d3 6178 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
sahilmgandhi 18:6a4db94011d3 6179 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
sahilmgandhi 18:6a4db94011d3 6180 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6181 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6182
sahilmgandhi 18:6a4db94011d3 6183 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
sahilmgandhi 18:6a4db94011d3 6184 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6185 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6186 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6187 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6188
sahilmgandhi 18:6a4db94011d3 6189 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
sahilmgandhi 18:6a4db94011d3 6190 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6191 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6192 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6193 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6194
sahilmgandhi 18:6a4db94011d3 6195 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
sahilmgandhi 18:6a4db94011d3 6196 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6197 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6198 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6199 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6200
sahilmgandhi 18:6a4db94011d3 6201 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
sahilmgandhi 18:6a4db94011d3 6202 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6203 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
sahilmgandhi 18:6a4db94011d3 6204 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6205 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6206
sahilmgandhi 18:6a4db94011d3 6207 /* Register: TIMER_INTENSET */
sahilmgandhi 18:6a4db94011d3 6208 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 6209
sahilmgandhi 18:6a4db94011d3 6210 /* Bit 19 : Enable interrupt on COMPARE[3] */
sahilmgandhi 18:6a4db94011d3 6211 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 6212 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 6213 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6214 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6215 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6216
sahilmgandhi 18:6a4db94011d3 6217 /* Bit 18 : Enable interrupt on COMPARE[2] */
sahilmgandhi 18:6a4db94011d3 6218 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 6219 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 6220 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6221 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6222 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6223
sahilmgandhi 18:6a4db94011d3 6224 /* Bit 17 : Enable interrupt on COMPARE[1] */
sahilmgandhi 18:6a4db94011d3 6225 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 6226 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 6227 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6228 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6229 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6230
sahilmgandhi 18:6a4db94011d3 6231 /* Bit 16 : Enable interrupt on COMPARE[0] */
sahilmgandhi 18:6a4db94011d3 6232 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 6233 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 6234 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6235 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6236 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6237
sahilmgandhi 18:6a4db94011d3 6238 /* Register: TIMER_INTENCLR */
sahilmgandhi 18:6a4db94011d3 6239 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 6240
sahilmgandhi 18:6a4db94011d3 6241 /* Bit 19 : Disable interrupt on COMPARE[3] */
sahilmgandhi 18:6a4db94011d3 6242 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 6243 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
sahilmgandhi 18:6a4db94011d3 6244 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6245 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6246 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6247
sahilmgandhi 18:6a4db94011d3 6248 /* Bit 18 : Disable interrupt on COMPARE[2] */
sahilmgandhi 18:6a4db94011d3 6249 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 6250 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
sahilmgandhi 18:6a4db94011d3 6251 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6252 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6253 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6254
sahilmgandhi 18:6a4db94011d3 6255 /* Bit 17 : Disable interrupt on COMPARE[1] */
sahilmgandhi 18:6a4db94011d3 6256 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 6257 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
sahilmgandhi 18:6a4db94011d3 6258 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6259 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6260 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6261
sahilmgandhi 18:6a4db94011d3 6262 /* Bit 16 : Disable interrupt on COMPARE[0] */
sahilmgandhi 18:6a4db94011d3 6263 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 6264 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
sahilmgandhi 18:6a4db94011d3 6265 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6266 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6267 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6268
sahilmgandhi 18:6a4db94011d3 6269 /* Register: TIMER_MODE */
sahilmgandhi 18:6a4db94011d3 6270 /* Description: Timer Mode selection. */
sahilmgandhi 18:6a4db94011d3 6271
sahilmgandhi 18:6a4db94011d3 6272 /* Bit 0 : Select Normal or Counter mode. */
sahilmgandhi 18:6a4db94011d3 6273 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
sahilmgandhi 18:6a4db94011d3 6274 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
sahilmgandhi 18:6a4db94011d3 6275 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
sahilmgandhi 18:6a4db94011d3 6276 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
sahilmgandhi 18:6a4db94011d3 6277
sahilmgandhi 18:6a4db94011d3 6278 /* Register: TIMER_BITMODE */
sahilmgandhi 18:6a4db94011d3 6279 /* Description: Sets timer behaviour. */
sahilmgandhi 18:6a4db94011d3 6280
sahilmgandhi 18:6a4db94011d3 6281 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
sahilmgandhi 18:6a4db94011d3 6282 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
sahilmgandhi 18:6a4db94011d3 6283 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
sahilmgandhi 18:6a4db94011d3 6284 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
sahilmgandhi 18:6a4db94011d3 6285 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
sahilmgandhi 18:6a4db94011d3 6286 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
sahilmgandhi 18:6a4db94011d3 6287 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
sahilmgandhi 18:6a4db94011d3 6288
sahilmgandhi 18:6a4db94011d3 6289 /* Register: TIMER_PRESCALER */
sahilmgandhi 18:6a4db94011d3 6290 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
sahilmgandhi 18:6a4db94011d3 6291
sahilmgandhi 18:6a4db94011d3 6292 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
sahilmgandhi 18:6a4db94011d3 6293 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 6294 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
sahilmgandhi 18:6a4db94011d3 6295
sahilmgandhi 18:6a4db94011d3 6296 /* Register: TIMER_POWER */
sahilmgandhi 18:6a4db94011d3 6297 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6298
sahilmgandhi 18:6a4db94011d3 6299 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6300 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 6301 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 6302 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 6303 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 6304
sahilmgandhi 18:6a4db94011d3 6305
sahilmgandhi 18:6a4db94011d3 6306 /* Peripheral: TWI */
sahilmgandhi 18:6a4db94011d3 6307 /* Description: Two-wire interface master 0. */
sahilmgandhi 18:6a4db94011d3 6308
sahilmgandhi 18:6a4db94011d3 6309 /* Register: TWI_SHORTS */
sahilmgandhi 18:6a4db94011d3 6310 /* Description: Shortcuts for TWI. */
sahilmgandhi 18:6a4db94011d3 6311
sahilmgandhi 18:6a4db94011d3 6312 /* Bit 1 : Shortcut between BB event and the STOP task. */
sahilmgandhi 18:6a4db94011d3 6313 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
sahilmgandhi 18:6a4db94011d3 6314 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
sahilmgandhi 18:6a4db94011d3 6315 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6316 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6317
sahilmgandhi 18:6a4db94011d3 6318 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
sahilmgandhi 18:6a4db94011d3 6319 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 6320 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
sahilmgandhi 18:6a4db94011d3 6321 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6322 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6323
sahilmgandhi 18:6a4db94011d3 6324 /* Register: TWI_INTENSET */
sahilmgandhi 18:6a4db94011d3 6325 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 6326
sahilmgandhi 18:6a4db94011d3 6327 /* Bit 18 : Enable interrupt on SUSPENDED event. */
sahilmgandhi 18:6a4db94011d3 6328 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 6329 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 6330 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6331 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6332 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6333
sahilmgandhi 18:6a4db94011d3 6334 /* Bit 14 : Enable interrupt on BB event. */
sahilmgandhi 18:6a4db94011d3 6335 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
sahilmgandhi 18:6a4db94011d3 6336 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
sahilmgandhi 18:6a4db94011d3 6337 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6338 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6339 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6340
sahilmgandhi 18:6a4db94011d3 6341 /* Bit 9 : Enable interrupt on ERROR event. */
sahilmgandhi 18:6a4db94011d3 6342 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6343 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6344 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6345 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6346 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6347
sahilmgandhi 18:6a4db94011d3 6348 /* Bit 7 : Enable interrupt on TXDSENT event. */
sahilmgandhi 18:6a4db94011d3 6349 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 6350 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 6351 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6352 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6353 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6354
sahilmgandhi 18:6a4db94011d3 6355 /* Bit 2 : Enable interrupt on READY event. */
sahilmgandhi 18:6a4db94011d3 6356 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 6357 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 6358 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6359 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6360 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6361
sahilmgandhi 18:6a4db94011d3 6362 /* Bit 1 : Enable interrupt on STOPPED event. */
sahilmgandhi 18:6a4db94011d3 6363 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 6364 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 6365 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6366 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6367 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6368
sahilmgandhi 18:6a4db94011d3 6369 /* Register: TWI_INTENCLR */
sahilmgandhi 18:6a4db94011d3 6370 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 6371
sahilmgandhi 18:6a4db94011d3 6372 /* Bit 18 : Disable interrupt on SUSPENDED event. */
sahilmgandhi 18:6a4db94011d3 6373 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 6374 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
sahilmgandhi 18:6a4db94011d3 6375 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6376 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6377 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6378
sahilmgandhi 18:6a4db94011d3 6379 /* Bit 14 : Disable interrupt on BB event. */
sahilmgandhi 18:6a4db94011d3 6380 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
sahilmgandhi 18:6a4db94011d3 6381 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
sahilmgandhi 18:6a4db94011d3 6382 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6383 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6384 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6385
sahilmgandhi 18:6a4db94011d3 6386 /* Bit 9 : Disable interrupt on ERROR event. */
sahilmgandhi 18:6a4db94011d3 6387 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6388 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6389 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6390 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6391 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6392
sahilmgandhi 18:6a4db94011d3 6393 /* Bit 7 : Disable interrupt on TXDSENT event. */
sahilmgandhi 18:6a4db94011d3 6394 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 6395 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
sahilmgandhi 18:6a4db94011d3 6396 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6397 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6398 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6399
sahilmgandhi 18:6a4db94011d3 6400 /* Bit 2 : Disable interrupt on RXDREADY event. */
sahilmgandhi 18:6a4db94011d3 6401 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 6402 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
sahilmgandhi 18:6a4db94011d3 6403 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6404 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6405 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6406
sahilmgandhi 18:6a4db94011d3 6407 /* Bit 1 : Disable interrupt on STOPPED event. */
sahilmgandhi 18:6a4db94011d3 6408 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 6409 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
sahilmgandhi 18:6a4db94011d3 6410 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6411 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6412 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6413
sahilmgandhi 18:6a4db94011d3 6414 /* Register: TWI_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 6415 /* Description: Two-wire error source. Write error field to 1 to clear error. */
sahilmgandhi 18:6a4db94011d3 6416
sahilmgandhi 18:6a4db94011d3 6417 /* Bit 2 : NACK received after sending a data byte. */
sahilmgandhi 18:6a4db94011d3 6418 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
sahilmgandhi 18:6a4db94011d3 6419 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
sahilmgandhi 18:6a4db94011d3 6420 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6421 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6422 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6423
sahilmgandhi 18:6a4db94011d3 6424 /* Bit 1 : NACK received after sending the address. */
sahilmgandhi 18:6a4db94011d3 6425 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
sahilmgandhi 18:6a4db94011d3 6426 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
sahilmgandhi 18:6a4db94011d3 6427 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6428 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6429 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6430
sahilmgandhi 18:6a4db94011d3 6431 /* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
sahilmgandhi 18:6a4db94011d3 6432 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 6433 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 6434 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6435 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6436 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6437
sahilmgandhi 18:6a4db94011d3 6438 /* Register: TWI_ENABLE */
sahilmgandhi 18:6a4db94011d3 6439 /* Description: Enable two-wire master. */
sahilmgandhi 18:6a4db94011d3 6440
sahilmgandhi 18:6a4db94011d3 6441 /* Bits 2..0 : Enable or disable W2M */
sahilmgandhi 18:6a4db94011d3 6442 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 6443 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 6444 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 6445 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 6446
sahilmgandhi 18:6a4db94011d3 6447 /* Register: TWI_RXD */
sahilmgandhi 18:6a4db94011d3 6448 /* Description: RX data register. */
sahilmgandhi 18:6a4db94011d3 6449
sahilmgandhi 18:6a4db94011d3 6450 /* Bits 7..0 : RX data from last transfer. */
sahilmgandhi 18:6a4db94011d3 6451 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
sahilmgandhi 18:6a4db94011d3 6452 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
sahilmgandhi 18:6a4db94011d3 6453
sahilmgandhi 18:6a4db94011d3 6454 /* Register: TWI_TXD */
sahilmgandhi 18:6a4db94011d3 6455 /* Description: TX data register. */
sahilmgandhi 18:6a4db94011d3 6456
sahilmgandhi 18:6a4db94011d3 6457 /* Bits 7..0 : TX data for next transfer. */
sahilmgandhi 18:6a4db94011d3 6458 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
sahilmgandhi 18:6a4db94011d3 6459 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
sahilmgandhi 18:6a4db94011d3 6460
sahilmgandhi 18:6a4db94011d3 6461 /* Register: TWI_FREQUENCY */
sahilmgandhi 18:6a4db94011d3 6462 /* Description: Two-wire frequency. */
sahilmgandhi 18:6a4db94011d3 6463
sahilmgandhi 18:6a4db94011d3 6464 /* Bits 31..0 : Two-wire master clock frequency. */
sahilmgandhi 18:6a4db94011d3 6465 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 6466 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
sahilmgandhi 18:6a4db94011d3 6467 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
sahilmgandhi 18:6a4db94011d3 6468 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
sahilmgandhi 18:6a4db94011d3 6469 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
sahilmgandhi 18:6a4db94011d3 6470
sahilmgandhi 18:6a4db94011d3 6471 /* Register: TWI_ADDRESS */
sahilmgandhi 18:6a4db94011d3 6472 /* Description: Address used in the two-wire transfer. */
sahilmgandhi 18:6a4db94011d3 6473
sahilmgandhi 18:6a4db94011d3 6474 /* Bits 6..0 : Two-wire address. */
sahilmgandhi 18:6a4db94011d3 6475 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 6476 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
sahilmgandhi 18:6a4db94011d3 6477
sahilmgandhi 18:6a4db94011d3 6478 /* Register: TWI_POWER */
sahilmgandhi 18:6a4db94011d3 6479 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6480
sahilmgandhi 18:6a4db94011d3 6481 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6482 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 6483 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 6484 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 6485 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 6486
sahilmgandhi 18:6a4db94011d3 6487
sahilmgandhi 18:6a4db94011d3 6488 /* Peripheral: UART */
sahilmgandhi 18:6a4db94011d3 6489 /* Description: Universal Asynchronous Receiver/Transmitter. */
sahilmgandhi 18:6a4db94011d3 6490
sahilmgandhi 18:6a4db94011d3 6491 /* Register: UART_SHORTS */
sahilmgandhi 18:6a4db94011d3 6492 /* Description: Shortcuts for UART. */
sahilmgandhi 18:6a4db94011d3 6493
sahilmgandhi 18:6a4db94011d3 6494 /* Bit 4 : Shortcut between NCTS event and STOPRX task. */
sahilmgandhi 18:6a4db94011d3 6495 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
sahilmgandhi 18:6a4db94011d3 6496 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
sahilmgandhi 18:6a4db94011d3 6497 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6498 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6499
sahilmgandhi 18:6a4db94011d3 6500 /* Bit 3 : Shortcut between CTS event and STARTRX task. */
sahilmgandhi 18:6a4db94011d3 6501 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 6502 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
sahilmgandhi 18:6a4db94011d3 6503 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
sahilmgandhi 18:6a4db94011d3 6504 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
sahilmgandhi 18:6a4db94011d3 6505
sahilmgandhi 18:6a4db94011d3 6506 /* Register: UART_INTENSET */
sahilmgandhi 18:6a4db94011d3 6507 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 6508
sahilmgandhi 18:6a4db94011d3 6509 /* Bit 17 : Enable interrupt on RXTO event. */
sahilmgandhi 18:6a4db94011d3 6510 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 6511 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 6512 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6513 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6514 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6515
sahilmgandhi 18:6a4db94011d3 6516 /* Bit 9 : Enable interrupt on ERROR event. */
sahilmgandhi 18:6a4db94011d3 6517 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6518 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6519 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6520 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6521 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6522
sahilmgandhi 18:6a4db94011d3 6523 /* Bit 7 : Enable interrupt on TXRDY event. */
sahilmgandhi 18:6a4db94011d3 6524 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6525 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6526 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6527 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6528 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6529
sahilmgandhi 18:6a4db94011d3 6530 /* Bit 2 : Enable interrupt on RXRDY event. */
sahilmgandhi 18:6a4db94011d3 6531 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6532 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6533 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6534 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6535 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6536
sahilmgandhi 18:6a4db94011d3 6537 /* Bit 1 : Enable interrupt on NCTS event. */
sahilmgandhi 18:6a4db94011d3 6538 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 6539 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 6540 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6541 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6542 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6543
sahilmgandhi 18:6a4db94011d3 6544 /* Bit 0 : Enable interrupt on CTS event. */
sahilmgandhi 18:6a4db94011d3 6545 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 6546 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 6547 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6548 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6549 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6550
sahilmgandhi 18:6a4db94011d3 6551 /* Register: UART_INTENCLR */
sahilmgandhi 18:6a4db94011d3 6552 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 6553
sahilmgandhi 18:6a4db94011d3 6554 /* Bit 17 : Disable interrupt on RXTO event. */
sahilmgandhi 18:6a4db94011d3 6555 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
sahilmgandhi 18:6a4db94011d3 6556 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
sahilmgandhi 18:6a4db94011d3 6557 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6558 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6559 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6560
sahilmgandhi 18:6a4db94011d3 6561 /* Bit 9 : Disable interrupt on ERROR event. */
sahilmgandhi 18:6a4db94011d3 6562 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6563 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
sahilmgandhi 18:6a4db94011d3 6564 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6565 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6566 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6567
sahilmgandhi 18:6a4db94011d3 6568 /* Bit 7 : Disable interrupt on TXRDY event. */
sahilmgandhi 18:6a4db94011d3 6569 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6570 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6571 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6572 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6573 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6574
sahilmgandhi 18:6a4db94011d3 6575 /* Bit 2 : Disable interrupt on RXRDY event. */
sahilmgandhi 18:6a4db94011d3 6576 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6577 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
sahilmgandhi 18:6a4db94011d3 6578 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6579 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6580 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6581
sahilmgandhi 18:6a4db94011d3 6582 /* Bit 1 : Disable interrupt on NCTS event. */
sahilmgandhi 18:6a4db94011d3 6583 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
sahilmgandhi 18:6a4db94011d3 6584 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
sahilmgandhi 18:6a4db94011d3 6585 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6586 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6587 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6588
sahilmgandhi 18:6a4db94011d3 6589 /* Bit 0 : Disable interrupt on CTS event. */
sahilmgandhi 18:6a4db94011d3 6590 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
sahilmgandhi 18:6a4db94011d3 6591 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
sahilmgandhi 18:6a4db94011d3 6592 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6593 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6594 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6595
sahilmgandhi 18:6a4db94011d3 6596 /* Register: UART_ERRORSRC */
sahilmgandhi 18:6a4db94011d3 6597 /* Description: Error source. Write error field to 1 to clear error. */
sahilmgandhi 18:6a4db94011d3 6598
sahilmgandhi 18:6a4db94011d3 6599 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
sahilmgandhi 18:6a4db94011d3 6600 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
sahilmgandhi 18:6a4db94011d3 6601 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
sahilmgandhi 18:6a4db94011d3 6602 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6603 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6604 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6605
sahilmgandhi 18:6a4db94011d3 6606 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
sahilmgandhi 18:6a4db94011d3 6607 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
sahilmgandhi 18:6a4db94011d3 6608 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
sahilmgandhi 18:6a4db94011d3 6609 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6610 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6611 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6612
sahilmgandhi 18:6a4db94011d3 6613 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
sahilmgandhi 18:6a4db94011d3 6614 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6615 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6616 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6617 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6618 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6619
sahilmgandhi 18:6a4db94011d3 6620 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
sahilmgandhi 18:6a4db94011d3 6621 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 6622 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
sahilmgandhi 18:6a4db94011d3 6623 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
sahilmgandhi 18:6a4db94011d3 6624 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
sahilmgandhi 18:6a4db94011d3 6625 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
sahilmgandhi 18:6a4db94011d3 6626
sahilmgandhi 18:6a4db94011d3 6627 /* Register: UART_ENABLE */
sahilmgandhi 18:6a4db94011d3 6628 /* Description: Enable UART and acquire IOs. */
sahilmgandhi 18:6a4db94011d3 6629
sahilmgandhi 18:6a4db94011d3 6630 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
sahilmgandhi 18:6a4db94011d3 6631 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 6632 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
sahilmgandhi 18:6a4db94011d3 6633 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
sahilmgandhi 18:6a4db94011d3 6634 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
sahilmgandhi 18:6a4db94011d3 6635
sahilmgandhi 18:6a4db94011d3 6636 /* Register: UART_RXD */
sahilmgandhi 18:6a4db94011d3 6637 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
sahilmgandhi 18:6a4db94011d3 6638
sahilmgandhi 18:6a4db94011d3 6639 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
sahilmgandhi 18:6a4db94011d3 6640 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
sahilmgandhi 18:6a4db94011d3 6641 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
sahilmgandhi 18:6a4db94011d3 6642
sahilmgandhi 18:6a4db94011d3 6643 /* Register: UART_TXD */
sahilmgandhi 18:6a4db94011d3 6644 /* Description: TXD register. */
sahilmgandhi 18:6a4db94011d3 6645
sahilmgandhi 18:6a4db94011d3 6646 /* Bits 7..0 : TX data for transfer. */
sahilmgandhi 18:6a4db94011d3 6647 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
sahilmgandhi 18:6a4db94011d3 6648 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
sahilmgandhi 18:6a4db94011d3 6649
sahilmgandhi 18:6a4db94011d3 6650 /* Register: UART_BAUDRATE */
sahilmgandhi 18:6a4db94011d3 6651 /* Description: UART Baudrate. */
sahilmgandhi 18:6a4db94011d3 6652
sahilmgandhi 18:6a4db94011d3 6653 /* Bits 31..0 : UART baudrate. */
sahilmgandhi 18:6a4db94011d3 6654 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
sahilmgandhi 18:6a4db94011d3 6655 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
sahilmgandhi 18:6a4db94011d3 6656 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
sahilmgandhi 18:6a4db94011d3 6657 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
sahilmgandhi 18:6a4db94011d3 6658 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
sahilmgandhi 18:6a4db94011d3 6659 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
sahilmgandhi 18:6a4db94011d3 6660 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
sahilmgandhi 18:6a4db94011d3 6661 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
sahilmgandhi 18:6a4db94011d3 6662 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
sahilmgandhi 18:6a4db94011d3 6663 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
sahilmgandhi 18:6a4db94011d3 6664 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
sahilmgandhi 18:6a4db94011d3 6665 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
sahilmgandhi 18:6a4db94011d3 6666 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
sahilmgandhi 18:6a4db94011d3 6667 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
sahilmgandhi 18:6a4db94011d3 6668 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
sahilmgandhi 18:6a4db94011d3 6669 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
sahilmgandhi 18:6a4db94011d3 6670 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
sahilmgandhi 18:6a4db94011d3 6671 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
sahilmgandhi 18:6a4db94011d3 6672
sahilmgandhi 18:6a4db94011d3 6673 /* Register: UART_CONFIG */
sahilmgandhi 18:6a4db94011d3 6674 /* Description: Configuration of parity and hardware flow control register. */
sahilmgandhi 18:6a4db94011d3 6675
sahilmgandhi 18:6a4db94011d3 6676 /* Bits 3..1 : Include parity bit. */
sahilmgandhi 18:6a4db94011d3 6677 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6678 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
sahilmgandhi 18:6a4db94011d3 6679 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
sahilmgandhi 18:6a4db94011d3 6680 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
sahilmgandhi 18:6a4db94011d3 6681
sahilmgandhi 18:6a4db94011d3 6682 /* Bit 0 : Hardware flow control. */
sahilmgandhi 18:6a4db94011d3 6683 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
sahilmgandhi 18:6a4db94011d3 6684 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
sahilmgandhi 18:6a4db94011d3 6685 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
sahilmgandhi 18:6a4db94011d3 6686 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
sahilmgandhi 18:6a4db94011d3 6687
sahilmgandhi 18:6a4db94011d3 6688 /* Register: UART_POWER */
sahilmgandhi 18:6a4db94011d3 6689 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6690
sahilmgandhi 18:6a4db94011d3 6691 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6692 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 6693 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 6694 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 6695 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 6696
sahilmgandhi 18:6a4db94011d3 6697
sahilmgandhi 18:6a4db94011d3 6698 /* Peripheral: UICR */
sahilmgandhi 18:6a4db94011d3 6699 /* Description: User Information Configuration. */
sahilmgandhi 18:6a4db94011d3 6700
sahilmgandhi 18:6a4db94011d3 6701 /* Register: UICR_RBPCONF */
sahilmgandhi 18:6a4db94011d3 6702 /* Description: Readback protection configuration. */
sahilmgandhi 18:6a4db94011d3 6703
sahilmgandhi 18:6a4db94011d3 6704 /* Bits 15..8 : Readback protect all code in the device. */
sahilmgandhi 18:6a4db94011d3 6705 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
sahilmgandhi 18:6a4db94011d3 6706 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
sahilmgandhi 18:6a4db94011d3 6707 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 6708 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 6709
sahilmgandhi 18:6a4db94011d3 6710 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
sahilmgandhi 18:6a4db94011d3 6711 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
sahilmgandhi 18:6a4db94011d3 6712 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
sahilmgandhi 18:6a4db94011d3 6713 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
sahilmgandhi 18:6a4db94011d3 6714 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
sahilmgandhi 18:6a4db94011d3 6715
sahilmgandhi 18:6a4db94011d3 6716 /* Register: UICR_XTALFREQ */
sahilmgandhi 18:6a4db94011d3 6717 /* Description: Reset value for CLOCK XTALFREQ register. */
sahilmgandhi 18:6a4db94011d3 6718
sahilmgandhi 18:6a4db94011d3 6719 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
sahilmgandhi 18:6a4db94011d3 6720 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
sahilmgandhi 18:6a4db94011d3 6721 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
sahilmgandhi 18:6a4db94011d3 6722 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
sahilmgandhi 18:6a4db94011d3 6723 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
sahilmgandhi 18:6a4db94011d3 6724
sahilmgandhi 18:6a4db94011d3 6725 /* Register: UICR_FWID */
sahilmgandhi 18:6a4db94011d3 6726 /* Description: Firmware ID. */
sahilmgandhi 18:6a4db94011d3 6727
sahilmgandhi 18:6a4db94011d3 6728 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
sahilmgandhi 18:6a4db94011d3 6729 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
sahilmgandhi 18:6a4db94011d3 6730 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
sahilmgandhi 18:6a4db94011d3 6731
sahilmgandhi 18:6a4db94011d3 6732
sahilmgandhi 18:6a4db94011d3 6733 /* Peripheral: WDT */
sahilmgandhi 18:6a4db94011d3 6734 /* Description: Watchdog Timer. */
sahilmgandhi 18:6a4db94011d3 6735
sahilmgandhi 18:6a4db94011d3 6736 /* Register: WDT_INTENSET */
sahilmgandhi 18:6a4db94011d3 6737 /* Description: Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 6738
sahilmgandhi 18:6a4db94011d3 6739 /* Bit 0 : Enable interrupt on TIMEOUT event. */
sahilmgandhi 18:6a4db94011d3 6740 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 6741 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 6742 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6743 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6744 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6745
sahilmgandhi 18:6a4db94011d3 6746 /* Register: WDT_INTENCLR */
sahilmgandhi 18:6a4db94011d3 6747 /* Description: Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 6748
sahilmgandhi 18:6a4db94011d3 6749 /* Bit 0 : Disable interrupt on TIMEOUT event. */
sahilmgandhi 18:6a4db94011d3 6750 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 6751 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
sahilmgandhi 18:6a4db94011d3 6752 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
sahilmgandhi 18:6a4db94011d3 6753 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
sahilmgandhi 18:6a4db94011d3 6754 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
sahilmgandhi 18:6a4db94011d3 6755
sahilmgandhi 18:6a4db94011d3 6756 /* Register: WDT_RUNSTATUS */
sahilmgandhi 18:6a4db94011d3 6757 /* Description: Watchdog running status. */
sahilmgandhi 18:6a4db94011d3 6758
sahilmgandhi 18:6a4db94011d3 6759 /* Bit 0 : Watchdog running status. */
sahilmgandhi 18:6a4db94011d3 6760 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
sahilmgandhi 18:6a4db94011d3 6761 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
sahilmgandhi 18:6a4db94011d3 6762 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
sahilmgandhi 18:6a4db94011d3 6763 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
sahilmgandhi 18:6a4db94011d3 6764
sahilmgandhi 18:6a4db94011d3 6765 /* Register: WDT_REQSTATUS */
sahilmgandhi 18:6a4db94011d3 6766 /* Description: Request status. */
sahilmgandhi 18:6a4db94011d3 6767
sahilmgandhi 18:6a4db94011d3 6768 /* Bit 7 : Request status for RR[7]. */
sahilmgandhi 18:6a4db94011d3 6769 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
sahilmgandhi 18:6a4db94011d3 6770 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
sahilmgandhi 18:6a4db94011d3 6771 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6772 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6773
sahilmgandhi 18:6a4db94011d3 6774 /* Bit 6 : Request status for RR[6]. */
sahilmgandhi 18:6a4db94011d3 6775 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
sahilmgandhi 18:6a4db94011d3 6776 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
sahilmgandhi 18:6a4db94011d3 6777 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6778 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6779
sahilmgandhi 18:6a4db94011d3 6780 /* Bit 5 : Request status for RR[5]. */
sahilmgandhi 18:6a4db94011d3 6781 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
sahilmgandhi 18:6a4db94011d3 6782 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
sahilmgandhi 18:6a4db94011d3 6783 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6784 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6785
sahilmgandhi 18:6a4db94011d3 6786 /* Bit 4 : Request status for RR[4]. */
sahilmgandhi 18:6a4db94011d3 6787 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
sahilmgandhi 18:6a4db94011d3 6788 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
sahilmgandhi 18:6a4db94011d3 6789 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6790 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6791
sahilmgandhi 18:6a4db94011d3 6792 /* Bit 3 : Request status for RR[3]. */
sahilmgandhi 18:6a4db94011d3 6793 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
sahilmgandhi 18:6a4db94011d3 6794 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
sahilmgandhi 18:6a4db94011d3 6795 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6796 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6797
sahilmgandhi 18:6a4db94011d3 6798 /* Bit 2 : Request status for RR[2]. */
sahilmgandhi 18:6a4db94011d3 6799 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
sahilmgandhi 18:6a4db94011d3 6800 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
sahilmgandhi 18:6a4db94011d3 6801 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6802 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6803
sahilmgandhi 18:6a4db94011d3 6804 /* Bit 1 : Request status for RR[1]. */
sahilmgandhi 18:6a4db94011d3 6805 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
sahilmgandhi 18:6a4db94011d3 6806 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
sahilmgandhi 18:6a4db94011d3 6807 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6808 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6809
sahilmgandhi 18:6a4db94011d3 6810 /* Bit 0 : Request status for RR[0]. */
sahilmgandhi 18:6a4db94011d3 6811 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
sahilmgandhi 18:6a4db94011d3 6812 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
sahilmgandhi 18:6a4db94011d3 6813 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
sahilmgandhi 18:6a4db94011d3 6814 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
sahilmgandhi 18:6a4db94011d3 6815
sahilmgandhi 18:6a4db94011d3 6816 /* Register: WDT_RREN */
sahilmgandhi 18:6a4db94011d3 6817 /* Description: Reload request enable. */
sahilmgandhi 18:6a4db94011d3 6818
sahilmgandhi 18:6a4db94011d3 6819 /* Bit 7 : Enable or disable RR[7] register. */
sahilmgandhi 18:6a4db94011d3 6820 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
sahilmgandhi 18:6a4db94011d3 6821 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
sahilmgandhi 18:6a4db94011d3 6822 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6823 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6824
sahilmgandhi 18:6a4db94011d3 6825 /* Bit 6 : Enable or disable RR[6] register. */
sahilmgandhi 18:6a4db94011d3 6826 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
sahilmgandhi 18:6a4db94011d3 6827 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
sahilmgandhi 18:6a4db94011d3 6828 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6829 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6830
sahilmgandhi 18:6a4db94011d3 6831 /* Bit 5 : Enable or disable RR[5] register. */
sahilmgandhi 18:6a4db94011d3 6832 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
sahilmgandhi 18:6a4db94011d3 6833 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
sahilmgandhi 18:6a4db94011d3 6834 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6835 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6836
sahilmgandhi 18:6a4db94011d3 6837 /* Bit 4 : Enable or disable RR[4] register. */
sahilmgandhi 18:6a4db94011d3 6838 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
sahilmgandhi 18:6a4db94011d3 6839 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
sahilmgandhi 18:6a4db94011d3 6840 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6841 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6842
sahilmgandhi 18:6a4db94011d3 6843 /* Bit 3 : Enable or disable RR[3] register. */
sahilmgandhi 18:6a4db94011d3 6844 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
sahilmgandhi 18:6a4db94011d3 6845 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
sahilmgandhi 18:6a4db94011d3 6846 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6847 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6848
sahilmgandhi 18:6a4db94011d3 6849 /* Bit 2 : Enable or disable RR[2] register. */
sahilmgandhi 18:6a4db94011d3 6850 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
sahilmgandhi 18:6a4db94011d3 6851 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
sahilmgandhi 18:6a4db94011d3 6852 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6853 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6854
sahilmgandhi 18:6a4db94011d3 6855 /* Bit 1 : Enable or disable RR[1] register. */
sahilmgandhi 18:6a4db94011d3 6856 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
sahilmgandhi 18:6a4db94011d3 6857 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
sahilmgandhi 18:6a4db94011d3 6858 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6859 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6860
sahilmgandhi 18:6a4db94011d3 6861 /* Bit 0 : Enable or disable RR[0] register. */
sahilmgandhi 18:6a4db94011d3 6862 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
sahilmgandhi 18:6a4db94011d3 6863 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
sahilmgandhi 18:6a4db94011d3 6864 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
sahilmgandhi 18:6a4db94011d3 6865 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
sahilmgandhi 18:6a4db94011d3 6866
sahilmgandhi 18:6a4db94011d3 6867 /* Register: WDT_CONFIG */
sahilmgandhi 18:6a4db94011d3 6868 /* Description: Configuration register. */
sahilmgandhi 18:6a4db94011d3 6869
sahilmgandhi 18:6a4db94011d3 6870 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
sahilmgandhi 18:6a4db94011d3 6871 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
sahilmgandhi 18:6a4db94011d3 6872 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
sahilmgandhi 18:6a4db94011d3 6873 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
sahilmgandhi 18:6a4db94011d3 6874 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
sahilmgandhi 18:6a4db94011d3 6875
sahilmgandhi 18:6a4db94011d3 6876 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
sahilmgandhi 18:6a4db94011d3 6877 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
sahilmgandhi 18:6a4db94011d3 6878 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
sahilmgandhi 18:6a4db94011d3 6879 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
sahilmgandhi 18:6a4db94011d3 6880 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
sahilmgandhi 18:6a4db94011d3 6881
sahilmgandhi 18:6a4db94011d3 6882 /* Register: WDT_RR */
sahilmgandhi 18:6a4db94011d3 6883 /* Description: Reload requests registers. */
sahilmgandhi 18:6a4db94011d3 6884
sahilmgandhi 18:6a4db94011d3 6885 /* Bits 31..0 : Reload register. */
sahilmgandhi 18:6a4db94011d3 6886 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
sahilmgandhi 18:6a4db94011d3 6887 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
sahilmgandhi 18:6a4db94011d3 6888 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
sahilmgandhi 18:6a4db94011d3 6889
sahilmgandhi 18:6a4db94011d3 6890 /* Register: WDT_POWER */
sahilmgandhi 18:6a4db94011d3 6891 /* Description: Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6892
sahilmgandhi 18:6a4db94011d3 6893 /* Bit 0 : Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 6894 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
sahilmgandhi 18:6a4db94011d3 6895 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
sahilmgandhi 18:6a4db94011d3 6896 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
sahilmgandhi 18:6a4db94011d3 6897 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
sahilmgandhi 18:6a4db94011d3 6898
sahilmgandhi 18:6a4db94011d3 6899
sahilmgandhi 18:6a4db94011d3 6900 /*lint --flb "Leave library region" */
sahilmgandhi 18:6a4db94011d3 6901 #endif