MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "us_ticker_api.h"
sahilmgandhi 18:6a4db94011d3 18 #include "PeripheralNames.h"
sahilmgandhi 18:6a4db94011d3 19 #include "clk_freqs.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 static void pit_init(void);
sahilmgandhi 18:6a4db94011d3 22 static void lptmr_init(void);
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 static int us_ticker_inited = 0;
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 void us_ticker_init(void) {
sahilmgandhi 18:6a4db94011d3 27 if (us_ticker_inited) return;
sahilmgandhi 18:6a4db94011d3 28 us_ticker_inited = 1;
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 pit_init();
sahilmgandhi 18:6a4db94011d3 31 lptmr_init();
sahilmgandhi 18:6a4db94011d3 32 }
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 35 * Timer for us timing.
sahilmgandhi 18:6a4db94011d3 36 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 37 static void pit_init(void) {
sahilmgandhi 18:6a4db94011d3 38 SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
sahilmgandhi 18:6a4db94011d3 39 PIT->MCR = 0; // Enable PIT
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 // Channel 1
sahilmgandhi 18:6a4db94011d3 42 PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
sahilmgandhi 18:6a4db94011d3 43 PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK; // Chain to timer 0, disable Interrupts
sahilmgandhi 18:6a4db94011d3 44 PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 // Use channel 0 as a prescaler for channel 1
sahilmgandhi 18:6a4db94011d3 47 PIT->CHANNEL[0].LDVAL = (bus_frequency() + 500000) / 1000000 - 1;
sahilmgandhi 18:6a4db94011d3 48 PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
sahilmgandhi 18:6a4db94011d3 49 }
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 uint32_t us_ticker_read() {
sahilmgandhi 18:6a4db94011d3 52 if (!us_ticker_inited)
sahilmgandhi 18:6a4db94011d3 53 us_ticker_init();
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 // The PIT is a countdown timer
sahilmgandhi 18:6a4db94011d3 56 return ~(PIT->CHANNEL[1].CVAL);
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 60 * Timer Event
sahilmgandhi 18:6a4db94011d3 61 *
sahilmgandhi 18:6a4db94011d3 62 * It schedules interrupts at given (32bit)us interval of time.
sahilmgandhi 18:6a4db94011d3 63 * It is implemented used the 16bit Low Power Timer that remains powered in all
sahilmgandhi 18:6a4db94011d3 64 * power modes.
sahilmgandhi 18:6a4db94011d3 65 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 66 static void lptmr_isr(void);
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 static void lptmr_init(void) {
sahilmgandhi 18:6a4db94011d3 69 uint32_t extosc;
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /* Clock the timer */
sahilmgandhi 18:6a4db94011d3 72 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Reset */
sahilmgandhi 18:6a4db94011d3 75 LPTMR0->CSR = 0;
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 #if defined(TARGET_KL43Z)
sahilmgandhi 18:6a4db94011d3 78 /* Set interrupt handler */
sahilmgandhi 18:6a4db94011d3 79 NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
sahilmgandhi 18:6a4db94011d3 80 NVIC_EnableIRQ(LPTMR0_IRQn);
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
sahilmgandhi 18:6a4db94011d3 84 extosc = mcgirc_frequency();
sahilmgandhi 18:6a4db94011d3 85 #else
sahilmgandhi 18:6a4db94011d3 86 /* Set interrupt handler */
sahilmgandhi 18:6a4db94011d3 87 NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
sahilmgandhi 18:6a4db94011d3 88 NVIC_EnableIRQ(LPTimer_IRQn);
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /* Clock at (1)MHz -> (1)tick/us */
sahilmgandhi 18:6a4db94011d3 91 /* Check if the external oscillator can be divided to 1MHz */
sahilmgandhi 18:6a4db94011d3 92 extosc = extosc_frequency();
sahilmgandhi 18:6a4db94011d3 93 #endif
sahilmgandhi 18:6a4db94011d3 94 if (extosc != 0) { //If external oscillator found
sahilmgandhi 18:6a4db94011d3 95 if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
sahilmgandhi 18:6a4db94011d3 96 extosc /= 1000000;
sahilmgandhi 18:6a4db94011d3 97 if (extosc == 1) { //1MHz, set timerprescaler in bypass mode
sahilmgandhi 18:6a4db94011d3 98 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK;
sahilmgandhi 18:6a4db94011d3 99 return;
sahilmgandhi 18:6a4db94011d3 100 } else { //See if we can divide it to 1MHz
sahilmgandhi 18:6a4db94011d3 101 uint32_t divider = 0;
sahilmgandhi 18:6a4db94011d3 102 extosc >>= 1;
sahilmgandhi 18:6a4db94011d3 103 while (1) {
sahilmgandhi 18:6a4db94011d3 104 if (extosc == 1) {
sahilmgandhi 18:6a4db94011d3 105 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider);
sahilmgandhi 18:6a4db94011d3 106 return;
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 if (extosc % 2 != 0) //If we can't divide by two anymore
sahilmgandhi 18:6a4db94011d3 109 break;
sahilmgandhi 18:6a4db94011d3 110 divider++;
sahilmgandhi 18:6a4db94011d3 111 extosc >>= 1;
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115 }
sahilmgandhi 18:6a4db94011d3 116 #if defined(TARGET_KL43Z)
sahilmgandhi 18:6a4db94011d3 117 //No suitable actual IRC oscillator clock -> Set it to (8MHz / divider)
sahilmgandhi 18:6a4db94011d3 118 MCG->SC &= ~MCG_SC_FCRDIV_MASK;
sahilmgandhi 18:6a4db94011d3 119 MCG->MC &= ~MCG->MC & MCG_MC_LIRC_DIV2_MASK;
sahilmgandhi 18:6a4db94011d3 120 LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(2);
sahilmgandhi 18:6a4db94011d3 121 #else
sahilmgandhi 18:6a4db94011d3 122 //No suitable external oscillator clock -> Use fast internal oscillator (4MHz / divider)
sahilmgandhi 18:6a4db94011d3 123 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
sahilmgandhi 18:6a4db94011d3 124 MCG->C2 |= MCG_C2_IRCS_MASK;
sahilmgandhi 18:6a4db94011d3 125 LPTMR0->PSR = LPTMR_PSR_PCS(0);
sahilmgandhi 18:6a4db94011d3 126 switch (MCG->SC & MCG_SC_FCRDIV_MASK) {
sahilmgandhi 18:6a4db94011d3 127 case MCG_SC_FCRDIV(0): //4MHz
sahilmgandhi 18:6a4db94011d3 128 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(1);
sahilmgandhi 18:6a4db94011d3 129 break;
sahilmgandhi 18:6a4db94011d3 130 case MCG_SC_FCRDIV(1): //2MHz
sahilmgandhi 18:6a4db94011d3 131 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(0);
sahilmgandhi 18:6a4db94011d3 132 break;
sahilmgandhi 18:6a4db94011d3 133 default: //1MHz or anything else, in which case we put it on 1MHz
sahilmgandhi 18:6a4db94011d3 134 MCG->SC &= ~MCG_SC_FCRDIV_MASK;
sahilmgandhi 18:6a4db94011d3 135 MCG->SC |= MCG_SC_FCRDIV(2);
sahilmgandhi 18:6a4db94011d3 136 LPTMR0->PSR |= LPTMR_PSR_PBYP_MASK;
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138 #endif
sahilmgandhi 18:6a4db94011d3 139 }
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 void us_ticker_disable_interrupt(void) {
sahilmgandhi 18:6a4db94011d3 142 LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 void us_ticker_clear_interrupt(void) {
sahilmgandhi 18:6a4db94011d3 146 // we already clear interrupt in lptmr_isr
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 static uint32_t us_ticker_int_counter = 0;
sahilmgandhi 18:6a4db94011d3 150 static uint16_t us_ticker_int_remainder = 0;
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 static void lptmr_set(unsigned short count) {
sahilmgandhi 18:6a4db94011d3 153 /* Reset */
sahilmgandhi 18:6a4db94011d3 154 LPTMR0->CSR = 0;
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /* Set the compare register */
sahilmgandhi 18:6a4db94011d3 157 LPTMR0->CMR = count;
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 /* Enable interrupt */
sahilmgandhi 18:6a4db94011d3 160 LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /* Start the timer */
sahilmgandhi 18:6a4db94011d3 163 LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 static void lptmr_isr(void) {
sahilmgandhi 18:6a4db94011d3 167 // write 1 to TCF to clear the LPT timer compare flag
sahilmgandhi 18:6a4db94011d3 168 LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 if (us_ticker_int_counter > 0) {
sahilmgandhi 18:6a4db94011d3 171 lptmr_set(0xFFFF);
sahilmgandhi 18:6a4db94011d3 172 us_ticker_int_counter--;
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 } else {
sahilmgandhi 18:6a4db94011d3 175 if (us_ticker_int_remainder > 0) {
sahilmgandhi 18:6a4db94011d3 176 lptmr_set(us_ticker_int_remainder);
sahilmgandhi 18:6a4db94011d3 177 us_ticker_int_remainder = 0;
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 } else {
sahilmgandhi 18:6a4db94011d3 180 // This function is going to disable the interrupts if there are
sahilmgandhi 18:6a4db94011d3 181 // no other events in the queue
sahilmgandhi 18:6a4db94011d3 182 us_ticker_irq_handler();
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184 }
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 void us_ticker_set_interrupt(timestamp_t timestamp) {
sahilmgandhi 18:6a4db94011d3 188 int delta = (int)((uint32_t)timestamp - us_ticker_read());
sahilmgandhi 18:6a4db94011d3 189 if (delta <= 0) {
sahilmgandhi 18:6a4db94011d3 190 // This event was in the past. Force it into the very near
sahilmgandhi 18:6a4db94011d3 191 // future instead.
sahilmgandhi 18:6a4db94011d3 192 delta = 1;
sahilmgandhi 18:6a4db94011d3 193 }
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 us_ticker_int_counter = (uint32_t)(delta >> 16);
sahilmgandhi 18:6a4db94011d3 196 us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
sahilmgandhi 18:6a4db94011d3 197 if (us_ticker_int_counter > 0) {
sahilmgandhi 18:6a4db94011d3 198 lptmr_set(0xFFFF);
sahilmgandhi 18:6a4db94011d3 199 us_ticker_int_counter--;
sahilmgandhi 18:6a4db94011d3 200 } else {
sahilmgandhi 18:6a4db94011d3 201 lptmr_set(us_ticker_int_remainder);
sahilmgandhi 18:6a4db94011d3 202 us_ticker_int_remainder = 0;
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204 }