MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 21 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #define CHANNEL_NUM 96
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 26 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #define IRQ_DISABLED (0)
sahilmgandhi 18:6a4db94011d3 29 #define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
sahilmgandhi 18:6a4db94011d3 30 #define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
sahilmgandhi 18:6a4db94011d3 31 #define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001};
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 static void handle_interrupt_in(PORT_Type *port, int ch_base) {
sahilmgandhi 18:6a4db94011d3 36 uint32_t isfr;
sahilmgandhi 18:6a4db94011d3 37 uint8_t location;
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 while((isfr = port->ISFR) != 0) {
sahilmgandhi 18:6a4db94011d3 40 location = 0;
sahilmgandhi 18:6a4db94011d3 41 for (int i = 0; i < 5; i++) {
sahilmgandhi 18:6a4db94011d3 42 if (!(isfr & (search_bits[i] << location)))
sahilmgandhi 18:6a4db94011d3 43 location += 1 << (4 - i);
sahilmgandhi 18:6a4db94011d3 44 }
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 uint32_t id = channel_ids[ch_base + location];
sahilmgandhi 18:6a4db94011d3 47 if (id == 0) {
sahilmgandhi 18:6a4db94011d3 48 continue;
sahilmgandhi 18:6a4db94011d3 49 }
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 FGPIO_Type *gpio;
sahilmgandhi 18:6a4db94011d3 52 gpio_irq_event event = IRQ_NONE;
sahilmgandhi 18:6a4db94011d3 53 switch (port->PCR[location] & PORT_PCR_IRQC_MASK) {
sahilmgandhi 18:6a4db94011d3 54 case IRQ_RAISING_EDGE:
sahilmgandhi 18:6a4db94011d3 55 event = IRQ_RISE;
sahilmgandhi 18:6a4db94011d3 56 break;
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 case IRQ_FALLING_EDGE:
sahilmgandhi 18:6a4db94011d3 59 event = IRQ_FALL;
sahilmgandhi 18:6a4db94011d3 60 break;
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 case IRQ_EITHER_EDGE:
sahilmgandhi 18:6a4db94011d3 63 if (port == PORTA) {
sahilmgandhi 18:6a4db94011d3 64 gpio = FPTA;
sahilmgandhi 18:6a4db94011d3 65 } else if (port == PORTC) {
sahilmgandhi 18:6a4db94011d3 66 gpio = FPTC;
sahilmgandhi 18:6a4db94011d3 67 } else {
sahilmgandhi 18:6a4db94011d3 68 gpio = FPTD;
sahilmgandhi 18:6a4db94011d3 69 }
sahilmgandhi 18:6a4db94011d3 70 event = (gpio->PDIR & (1<<location)) ? (IRQ_RISE) : (IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 71 break;
sahilmgandhi 18:6a4db94011d3 72 }
sahilmgandhi 18:6a4db94011d3 73 if (event != IRQ_NONE) {
sahilmgandhi 18:6a4db94011d3 74 irq_handler(id, event);
sahilmgandhi 18:6a4db94011d3 75 }
sahilmgandhi 18:6a4db94011d3 76 port->ISFR = 1 << location;
sahilmgandhi 18:6a4db94011d3 77 }
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 void gpio_irqA(void) {
sahilmgandhi 18:6a4db94011d3 81 handle_interrupt_in(PORTA, 0);
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /* PORTC and PORTD share same vector */
sahilmgandhi 18:6a4db94011d3 85 void gpio_irqCD(void) {
sahilmgandhi 18:6a4db94011d3 86 if ((SIM->SCGC5 & SIM_SCGC5_PORTC_MASK) && (PORTC->ISFR)) {
sahilmgandhi 18:6a4db94011d3 87 handle_interrupt_in(PORTC, 32);
sahilmgandhi 18:6a4db94011d3 88 } else if ((SIM->SCGC5 & SIM_SCGC5_PORTD_MASK) && (PORTD->ISFR)) {
sahilmgandhi 18:6a4db94011d3 89 handle_interrupt_in(PORTD, 64);
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91 }
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 94 if (pin == NC)
sahilmgandhi 18:6a4db94011d3 95 return -1;
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 obj->port = pin >> PORT_SHIFT;
sahilmgandhi 18:6a4db94011d3 100 obj->pin = (pin & 0x7F) >> 2;
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 uint32_t ch_base, vector;
sahilmgandhi 18:6a4db94011d3 103 IRQn_Type irq_n;
sahilmgandhi 18:6a4db94011d3 104 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 105 case PortA:
sahilmgandhi 18:6a4db94011d3 106 ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
sahilmgandhi 18:6a4db94011d3 107 break;
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 case PortC:
sahilmgandhi 18:6a4db94011d3 110 ch_base = 32; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD;
sahilmgandhi 18:6a4db94011d3 111 break;
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 case PortD:
sahilmgandhi 18:6a4db94011d3 114 ch_base = 64; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD;
sahilmgandhi 18:6a4db94011d3 115 break;
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 default:
sahilmgandhi 18:6a4db94011d3 118 error("gpio_irq only supported on port A,C and D");
sahilmgandhi 18:6a4db94011d3 119 break;
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121 NVIC_SetVector(irq_n, vector);
sahilmgandhi 18:6a4db94011d3 122 NVIC_EnableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 obj->ch = ch_base + obj->pin;
sahilmgandhi 18:6a4db94011d3 125 channel_ids[obj->ch] = id;
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 return 0;
sahilmgandhi 18:6a4db94011d3 128 }
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 131 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 132 }
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 135 PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 uint32_t irq_settings = IRQ_DISABLED;
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
sahilmgandhi 18:6a4db94011d3 140 case IRQ_DISABLED:
sahilmgandhi 18:6a4db94011d3 141 if (enable) {
sahilmgandhi 18:6a4db94011d3 142 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144 break;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 case IRQ_RAISING_EDGE:
sahilmgandhi 18:6a4db94011d3 147 if (enable) {
sahilmgandhi 18:6a4db94011d3 148 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
sahilmgandhi 18:6a4db94011d3 149 } else {
sahilmgandhi 18:6a4db94011d3 150 if (event == IRQ_FALL)
sahilmgandhi 18:6a4db94011d3 151 irq_settings = IRQ_RAISING_EDGE;
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 break;
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 case IRQ_FALLING_EDGE:
sahilmgandhi 18:6a4db94011d3 156 if (enable) {
sahilmgandhi 18:6a4db94011d3 157 irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
sahilmgandhi 18:6a4db94011d3 158 } else {
sahilmgandhi 18:6a4db94011d3 159 if (event == IRQ_RISE)
sahilmgandhi 18:6a4db94011d3 160 irq_settings = IRQ_FALLING_EDGE;
sahilmgandhi 18:6a4db94011d3 161 }
sahilmgandhi 18:6a4db94011d3 162 break;
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 case IRQ_EITHER_EDGE:
sahilmgandhi 18:6a4db94011d3 165 if (enable) {
sahilmgandhi 18:6a4db94011d3 166 irq_settings = IRQ_EITHER_EDGE;
sahilmgandhi 18:6a4db94011d3 167 } else {
sahilmgandhi 18:6a4db94011d3 168 irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170 break;
sahilmgandhi 18:6a4db94011d3 171 }
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 // Interrupt configuration and clear interrupt
sahilmgandhi 18:6a4db94011d3 174 port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
sahilmgandhi 18:6a4db94011d3 175 }
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 178 if (obj->port == PortA) {
sahilmgandhi 18:6a4db94011d3 179 NVIC_EnableIRQ(PORTA_IRQn);
sahilmgandhi 18:6a4db94011d3 180 } else {
sahilmgandhi 18:6a4db94011d3 181 NVIC_EnableIRQ(PORTC_PORTD_IRQn);
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 186 if (obj->port == PortA) {
sahilmgandhi 18:6a4db94011d3 187 NVIC_DisableIRQ(PORTA_IRQn);
sahilmgandhi 18:6a4db94011d3 188 } else {
sahilmgandhi 18:6a4db94011d3 189 NVIC_DisableIRQ(PORTC_PORTD_IRQn);
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191 }