MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 ; * ---------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2 ; * @file: startup_MKL26Z4.s
sahilmgandhi 18:6a4db94011d3 3 ; * @purpose: CMSIS Cortex-M0P Core Device Startup File
sahilmgandhi 18:6a4db94011d3 4 ; * MKL26Z4
sahilmgandhi 18:6a4db94011d3 5 ; * @version: 1.7
sahilmgandhi 18:6a4db94011d3 6 ; * @date: 2015-2-18
sahilmgandhi 18:6a4db94011d3 7 ; * @build: b150218
sahilmgandhi 18:6a4db94011d3 8 ; * ---------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9 ; *
sahilmgandhi 18:6a4db94011d3 10 ; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
sahilmgandhi 18:6a4db94011d3 11 ; * All rights reserved.
sahilmgandhi 18:6a4db94011d3 12 ; *
sahilmgandhi 18:6a4db94011d3 13 ; * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 ; * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 ; *
sahilmgandhi 18:6a4db94011d3 16 ; * o Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 17 ; * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 18 ; *
sahilmgandhi 18:6a4db94011d3 19 ; * o Redistributions in binary form must reproduce the above copyright notice, this
sahilmgandhi 18:6a4db94011d3 20 ; * list of conditions and the following disclaimer in the documentation and/or
sahilmgandhi 18:6a4db94011d3 21 ; * other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 22 ; *
sahilmgandhi 18:6a4db94011d3 23 ; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
sahilmgandhi 18:6a4db94011d3 24 ; * contributors may be used to endorse or promote products derived from this
sahilmgandhi 18:6a4db94011d3 25 ; * software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 26 ; *
sahilmgandhi 18:6a4db94011d3 27 ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 28 ; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 29 ; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 30 ; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 31 ; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 32 ; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 33 ; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 34 ; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 35 ; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 36 ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 37 ; *
sahilmgandhi 18:6a4db94011d3 38 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 39 ; *
sahilmgandhi 18:6a4db94011d3 40 ; *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 PRESERVE8
sahilmgandhi 18:6a4db94011d3 44 THUMB
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 ; Vector Table Mapped to Address 0 at Reset
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 AREA RESET, DATA, READONLY
sahilmgandhi 18:6a4db94011d3 50 EXPORT __Vectors
sahilmgandhi 18:6a4db94011d3 51 EXPORT __Vectors_End
sahilmgandhi 18:6a4db94011d3 52 EXPORT __Vectors_Size
sahilmgandhi 18:6a4db94011d3 53 IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
sahilmgandhi 18:6a4db94011d3 56 DCD Reset_Handler ; Reset Handler
sahilmgandhi 18:6a4db94011d3 57 DCD NMI_Handler ;NMI Handler
sahilmgandhi 18:6a4db94011d3 58 DCD HardFault_Handler ;Hard Fault Handler
sahilmgandhi 18:6a4db94011d3 59 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 60 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 61 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 62 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 63 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 64 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 65 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 66 DCD SVC_Handler ;SVCall Handler
sahilmgandhi 18:6a4db94011d3 67 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 68 DCD 0 ;Reserved
sahilmgandhi 18:6a4db94011d3 69 DCD PendSV_Handler ;PendSV Handler
sahilmgandhi 18:6a4db94011d3 70 DCD SysTick_Handler ;SysTick Handler
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 ;External Interrupts
sahilmgandhi 18:6a4db94011d3 73 DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt
sahilmgandhi 18:6a4db94011d3 74 DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt
sahilmgandhi 18:6a4db94011d3 75 DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt
sahilmgandhi 18:6a4db94011d3 76 DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt
sahilmgandhi 18:6a4db94011d3 77 DCD Reserved20_IRQHandler ;Reserved interrupt
sahilmgandhi 18:6a4db94011d3 78 DCD FTFA_IRQHandler ;FTFA command complete and read collision
sahilmgandhi 18:6a4db94011d3 79 DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning
sahilmgandhi 18:6a4db94011d3 80 DCD LLWU_IRQHandler ;Low Leakage Wakeup
sahilmgandhi 18:6a4db94011d3 81 DCD I2C0_IRQHandler ;I2C0 interrupt
sahilmgandhi 18:6a4db94011d3 82 DCD I2C1_IRQHandler ;I2C1 interrupt
sahilmgandhi 18:6a4db94011d3 83 DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
sahilmgandhi 18:6a4db94011d3 84 DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
sahilmgandhi 18:6a4db94011d3 85 DCD UART0_IRQHandler ;UART0 status and error
sahilmgandhi 18:6a4db94011d3 86 DCD UART1_IRQHandler ;UART1 status and error
sahilmgandhi 18:6a4db94011d3 87 DCD UART2_IRQHandler ;UART2 status and error
sahilmgandhi 18:6a4db94011d3 88 DCD ADC0_IRQHandler ;ADC0 interrupt
sahilmgandhi 18:6a4db94011d3 89 DCD CMP0_IRQHandler ;CMP0 interrupt
sahilmgandhi 18:6a4db94011d3 90 DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
sahilmgandhi 18:6a4db94011d3 91 DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
sahilmgandhi 18:6a4db94011d3 92 DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
sahilmgandhi 18:6a4db94011d3 93 DCD RTC_IRQHandler ;RTC alarm interrupt
sahilmgandhi 18:6a4db94011d3 94 DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
sahilmgandhi 18:6a4db94011d3 95 DCD PIT_IRQHandler ;PIT single interrupt vector for all channels
sahilmgandhi 18:6a4db94011d3 96 DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources
sahilmgandhi 18:6a4db94011d3 97 DCD USB0_IRQHandler ;USB0 OTG
sahilmgandhi 18:6a4db94011d3 98 DCD DAC0_IRQHandler ;DAC0 interrupt
sahilmgandhi 18:6a4db94011d3 99 DCD TSI0_IRQHandler ;TSI0 interrupt
sahilmgandhi 18:6a4db94011d3 100 DCD MCG_IRQHandler ;MCG interrupt
sahilmgandhi 18:6a4db94011d3 101 DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
sahilmgandhi 18:6a4db94011d3 102 DCD Reserved45_IRQHandler ;Reserved interrupt
sahilmgandhi 18:6a4db94011d3 103 DCD PORTA_IRQHandler ;PORTA pin detect
sahilmgandhi 18:6a4db94011d3 104 DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect
sahilmgandhi 18:6a4db94011d3 105 __Vectors_End
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 __Vectors_Size EQU __Vectors_End - __Vectors
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 ; <h> Flash Configuration
sahilmgandhi 18:6a4db94011d3 110 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
sahilmgandhi 18:6a4db94011d3 111 ; <i> and security information that allows the MCU to restrict access to the FTFL module.
sahilmgandhi 18:6a4db94011d3 112 ; <h> Backdoor Comparison Key
sahilmgandhi 18:6a4db94011d3 113 ; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 114 ; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 115 ; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 116 ; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 117 ; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 118 ; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 119 ; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 120 ; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
sahilmgandhi 18:6a4db94011d3 121 BackDoorK0 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 122 BackDoorK1 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 123 BackDoorK2 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 124 BackDoorK3 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 125 BackDoorK4 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 126 BackDoorK5 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 127 BackDoorK6 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 128 BackDoorK7 EQU 0xFF
sahilmgandhi 18:6a4db94011d3 129 ; </h>
sahilmgandhi 18:6a4db94011d3 130 ; <h> Program flash protection bytes (FPROT)
sahilmgandhi 18:6a4db94011d3 131 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
sahilmgandhi 18:6a4db94011d3 132 ; <i> Each bit protects a 1/32 region of the program flash memory.
sahilmgandhi 18:6a4db94011d3 133 ; <h> FPROT0
sahilmgandhi 18:6a4db94011d3 134 ; <i> Program Flash Region Protect Register 0
sahilmgandhi 18:6a4db94011d3 135 ; <i> 1/32 - 8/32 region
sahilmgandhi 18:6a4db94011d3 136 ; <o.0> FPROT0.0
sahilmgandhi 18:6a4db94011d3 137 ; <o.1> FPROT0.1
sahilmgandhi 18:6a4db94011d3 138 ; <o.2> FPROT0.2
sahilmgandhi 18:6a4db94011d3 139 ; <o.3> FPROT0.3
sahilmgandhi 18:6a4db94011d3 140 ; <o.4> FPROT0.4
sahilmgandhi 18:6a4db94011d3 141 ; <o.5> FPROT0.5
sahilmgandhi 18:6a4db94011d3 142 ; <o.6> FPROT0.6
sahilmgandhi 18:6a4db94011d3 143 ; <o.7> FPROT0.7
sahilmgandhi 18:6a4db94011d3 144 nFPROT0 EQU 0x00
sahilmgandhi 18:6a4db94011d3 145 FPROT0 EQU nFPROT0:EOR:0xFF
sahilmgandhi 18:6a4db94011d3 146 ; </h>
sahilmgandhi 18:6a4db94011d3 147 ; <h> FPROT1
sahilmgandhi 18:6a4db94011d3 148 ; <i> Program Flash Region Protect Register 1
sahilmgandhi 18:6a4db94011d3 149 ; <i> 9/32 - 16/32 region
sahilmgandhi 18:6a4db94011d3 150 ; <o.0> FPROT1.0
sahilmgandhi 18:6a4db94011d3 151 ; <o.1> FPROT1.1
sahilmgandhi 18:6a4db94011d3 152 ; <o.2> FPROT1.2
sahilmgandhi 18:6a4db94011d3 153 ; <o.3> FPROT1.3
sahilmgandhi 18:6a4db94011d3 154 ; <o.4> FPROT1.4
sahilmgandhi 18:6a4db94011d3 155 ; <o.5> FPROT1.5
sahilmgandhi 18:6a4db94011d3 156 ; <o.6> FPROT1.6
sahilmgandhi 18:6a4db94011d3 157 ; <o.7> FPROT1.7
sahilmgandhi 18:6a4db94011d3 158 nFPROT1 EQU 0x00
sahilmgandhi 18:6a4db94011d3 159 FPROT1 EQU nFPROT1:EOR:0xFF
sahilmgandhi 18:6a4db94011d3 160 ; </h>
sahilmgandhi 18:6a4db94011d3 161 ; <h> FPROT2
sahilmgandhi 18:6a4db94011d3 162 ; <i> Program Flash Region Protect Register 2
sahilmgandhi 18:6a4db94011d3 163 ; <i> 17/32 - 24/32 region
sahilmgandhi 18:6a4db94011d3 164 ; <o.0> FPROT2.0
sahilmgandhi 18:6a4db94011d3 165 ; <o.1> FPROT2.1
sahilmgandhi 18:6a4db94011d3 166 ; <o.2> FPROT2.2
sahilmgandhi 18:6a4db94011d3 167 ; <o.3> FPROT2.3
sahilmgandhi 18:6a4db94011d3 168 ; <o.4> FPROT2.4
sahilmgandhi 18:6a4db94011d3 169 ; <o.5> FPROT2.5
sahilmgandhi 18:6a4db94011d3 170 ; <o.6> FPROT2.6
sahilmgandhi 18:6a4db94011d3 171 ; <o.7> FPROT2.7
sahilmgandhi 18:6a4db94011d3 172 nFPROT2 EQU 0x00
sahilmgandhi 18:6a4db94011d3 173 FPROT2 EQU nFPROT2:EOR:0xFF
sahilmgandhi 18:6a4db94011d3 174 ; </h>
sahilmgandhi 18:6a4db94011d3 175 ; <h> FPROT3
sahilmgandhi 18:6a4db94011d3 176 ; <i> Program Flash Region Protect Register 3
sahilmgandhi 18:6a4db94011d3 177 ; <i> 25/32 - 32/32 region
sahilmgandhi 18:6a4db94011d3 178 ; <o.0> FPROT3.0
sahilmgandhi 18:6a4db94011d3 179 ; <o.1> FPROT3.1
sahilmgandhi 18:6a4db94011d3 180 ; <o.2> FPROT3.2
sahilmgandhi 18:6a4db94011d3 181 ; <o.3> FPROT3.3
sahilmgandhi 18:6a4db94011d3 182 ; <o.4> FPROT3.4
sahilmgandhi 18:6a4db94011d3 183 ; <o.5> FPROT3.5
sahilmgandhi 18:6a4db94011d3 184 ; <o.6> FPROT3.6
sahilmgandhi 18:6a4db94011d3 185 ; <o.7> FPROT3.7
sahilmgandhi 18:6a4db94011d3 186 nFPROT3 EQU 0x00
sahilmgandhi 18:6a4db94011d3 187 FPROT3 EQU nFPROT3:EOR:0xFF
sahilmgandhi 18:6a4db94011d3 188 ; </h>
sahilmgandhi 18:6a4db94011d3 189 ; </h>
sahilmgandhi 18:6a4db94011d3 190 ; <h> Flash nonvolatile option byte (FOPT)
sahilmgandhi 18:6a4db94011d3 191 ; <i> Allows the user to customize the operation of the MCU at boot time.
sahilmgandhi 18:6a4db94011d3 192 ; <o.0> LPBOOT0
sahilmgandhi 18:6a4db94011d3 193 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
sahilmgandhi 18:6a4db94011d3 194 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
sahilmgandhi 18:6a4db94011d3 195 ; <o.2> NMI_DIS
sahilmgandhi 18:6a4db94011d3 196 ; <0=> NMI interrupts are always blocked
sahilmgandhi 18:6a4db94011d3 197 ; <1=> NMI_b pin/interrupts reset default to enabled
sahilmgandhi 18:6a4db94011d3 198 ; <o.3> RESET_PIN_CFG
sahilmgandhi 18:6a4db94011d3 199 ; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
sahilmgandhi 18:6a4db94011d3 200 ; <1=> RESET_b pin is dedicated
sahilmgandhi 18:6a4db94011d3 201 ; <o.4> LPBOOT1
sahilmgandhi 18:6a4db94011d3 202 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
sahilmgandhi 18:6a4db94011d3 203 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
sahilmgandhi 18:6a4db94011d3 204 ; <o.5> FAST_INIT
sahilmgandhi 18:6a4db94011d3 205 ; <0=> Slower initialization
sahilmgandhi 18:6a4db94011d3 206 ; <1=> Fast Initialization
sahilmgandhi 18:6a4db94011d3 207 FOPT EQU 0xFF
sahilmgandhi 18:6a4db94011d3 208 ; </h>
sahilmgandhi 18:6a4db94011d3 209 ; <h> Flash security byte (FSEC)
sahilmgandhi 18:6a4db94011d3 210 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
sahilmgandhi 18:6a4db94011d3 211 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
sahilmgandhi 18:6a4db94011d3 212 ; <o.0..1> SEC
sahilmgandhi 18:6a4db94011d3 213 ; <2=> MCU security status is unsecure
sahilmgandhi 18:6a4db94011d3 214 ; <3=> MCU security status is secure
sahilmgandhi 18:6a4db94011d3 215 ; <i> Flash Security
sahilmgandhi 18:6a4db94011d3 216 ; <o.2..3> FSLACC
sahilmgandhi 18:6a4db94011d3 217 ; <2=> Freescale factory access denied
sahilmgandhi 18:6a4db94011d3 218 ; <3=> Freescale factory access granted
sahilmgandhi 18:6a4db94011d3 219 ; <i> Freescale Failure Analysis Access Code
sahilmgandhi 18:6a4db94011d3 220 ; <o.4..5> MEEN
sahilmgandhi 18:6a4db94011d3 221 ; <2=> Mass erase is disabled
sahilmgandhi 18:6a4db94011d3 222 ; <3=> Mass erase is enabled
sahilmgandhi 18:6a4db94011d3 223 ; <o.6..7> KEYEN
sahilmgandhi 18:6a4db94011d3 224 ; <2=> Backdoor key access enabled
sahilmgandhi 18:6a4db94011d3 225 ; <3=> Backdoor key access disabled
sahilmgandhi 18:6a4db94011d3 226 ; <i> Backdoor Key Security Enable
sahilmgandhi 18:6a4db94011d3 227 FSEC EQU 0xFE
sahilmgandhi 18:6a4db94011d3 228 ; </h>
sahilmgandhi 18:6a4db94011d3 229 ; </h>
sahilmgandhi 18:6a4db94011d3 230 IF :LNOT::DEF:RAM_TARGET
sahilmgandhi 18:6a4db94011d3 231 AREA FlashConfig, DATA, READONLY
sahilmgandhi 18:6a4db94011d3 232 __FlashConfig
sahilmgandhi 18:6a4db94011d3 233 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
sahilmgandhi 18:6a4db94011d3 234 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
sahilmgandhi 18:6a4db94011d3 235 DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
sahilmgandhi 18:6a4db94011d3 236 DCB FSEC , FOPT , 0xFF , 0xFF
sahilmgandhi 18:6a4db94011d3 237 ENDIF
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 AREA |.text|, CODE, READONLY
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 ; Reset Handler
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 Reset_Handler PROC
sahilmgandhi 18:6a4db94011d3 245 EXPORT Reset_Handler [WEAK]
sahilmgandhi 18:6a4db94011d3 246 IMPORT SystemInit
sahilmgandhi 18:6a4db94011d3 247 IMPORT init_data_bss
sahilmgandhi 18:6a4db94011d3 248 IMPORT __main
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 IF :LNOT::DEF:RAM_TARGET
sahilmgandhi 18:6a4db94011d3 251 LDR R0, =FlashConfig ; dummy read, workaround for flashConfig
sahilmgandhi 18:6a4db94011d3 252 ENDIF
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 CPSID I ; Mask interrupts
sahilmgandhi 18:6a4db94011d3 255 LDR R0, =SystemInit
sahilmgandhi 18:6a4db94011d3 256 BLX R0
sahilmgandhi 18:6a4db94011d3 257 LDR R0, =init_data_bss
sahilmgandhi 18:6a4db94011d3 258 BLX R0
sahilmgandhi 18:6a4db94011d3 259 CPSIE i ; Unmask interrupts
sahilmgandhi 18:6a4db94011d3 260 LDR R0, =__main
sahilmgandhi 18:6a4db94011d3 261 BX R0
sahilmgandhi 18:6a4db94011d3 262 ENDP
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 ; Dummy Exception Handlers (infinite loops which can be modified)
sahilmgandhi 18:6a4db94011d3 266 NMI_Handler\
sahilmgandhi 18:6a4db94011d3 267 PROC
sahilmgandhi 18:6a4db94011d3 268 EXPORT NMI_Handler [WEAK]
sahilmgandhi 18:6a4db94011d3 269 B .
sahilmgandhi 18:6a4db94011d3 270 ENDP
sahilmgandhi 18:6a4db94011d3 271 HardFault_Handler\
sahilmgandhi 18:6a4db94011d3 272 PROC
sahilmgandhi 18:6a4db94011d3 273 EXPORT HardFault_Handler [WEAK]
sahilmgandhi 18:6a4db94011d3 274 B .
sahilmgandhi 18:6a4db94011d3 275 ENDP
sahilmgandhi 18:6a4db94011d3 276 SVC_Handler\
sahilmgandhi 18:6a4db94011d3 277 PROC
sahilmgandhi 18:6a4db94011d3 278 EXPORT SVC_Handler [WEAK]
sahilmgandhi 18:6a4db94011d3 279 B .
sahilmgandhi 18:6a4db94011d3 280 ENDP
sahilmgandhi 18:6a4db94011d3 281 PendSV_Handler\
sahilmgandhi 18:6a4db94011d3 282 PROC
sahilmgandhi 18:6a4db94011d3 283 EXPORT PendSV_Handler [WEAK]
sahilmgandhi 18:6a4db94011d3 284 B .
sahilmgandhi 18:6a4db94011d3 285 ENDP
sahilmgandhi 18:6a4db94011d3 286 SysTick_Handler\
sahilmgandhi 18:6a4db94011d3 287 PROC
sahilmgandhi 18:6a4db94011d3 288 EXPORT SysTick_Handler [WEAK]
sahilmgandhi 18:6a4db94011d3 289 B .
sahilmgandhi 18:6a4db94011d3 290 ENDP
sahilmgandhi 18:6a4db94011d3 291 Default_Handler\
sahilmgandhi 18:6a4db94011d3 292 PROC
sahilmgandhi 18:6a4db94011d3 293 EXPORT DMA0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 294 EXPORT DMA1_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 295 EXPORT DMA2_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 296 EXPORT DMA3_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 297 EXPORT Reserved20_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 298 EXPORT FTFA_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 299 EXPORT LVD_LVW_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 300 EXPORT LLWU_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 301 EXPORT I2C0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 302 EXPORT I2C1_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 303 EXPORT SPI0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 304 EXPORT SPI1_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 305 EXPORT UART0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 306 EXPORT UART1_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 307 EXPORT UART2_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 308 EXPORT ADC0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 309 EXPORT CMP0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 310 EXPORT TPM0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 311 EXPORT TPM1_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 312 EXPORT TPM2_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 313 EXPORT RTC_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 314 EXPORT RTC_Seconds_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 315 EXPORT PIT_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 316 EXPORT I2S0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 317 EXPORT USB0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 318 EXPORT DAC0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 319 EXPORT TSI0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 320 EXPORT MCG_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 321 EXPORT LPTMR0_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 322 EXPORT Reserved45_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 323 EXPORT PORTA_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 324 EXPORT PORTC_PORTD_IRQHandler [WEAK]
sahilmgandhi 18:6a4db94011d3 325 EXPORT DefaultISR [WEAK]
sahilmgandhi 18:6a4db94011d3 326 DMA0_IRQHandler
sahilmgandhi 18:6a4db94011d3 327 DMA1_IRQHandler
sahilmgandhi 18:6a4db94011d3 328 DMA2_IRQHandler
sahilmgandhi 18:6a4db94011d3 329 DMA3_IRQHandler
sahilmgandhi 18:6a4db94011d3 330 Reserved20_IRQHandler
sahilmgandhi 18:6a4db94011d3 331 FTFA_IRQHandler
sahilmgandhi 18:6a4db94011d3 332 LVD_LVW_IRQHandler
sahilmgandhi 18:6a4db94011d3 333 LLWU_IRQHandler
sahilmgandhi 18:6a4db94011d3 334 I2C0_IRQHandler
sahilmgandhi 18:6a4db94011d3 335 I2C1_IRQHandler
sahilmgandhi 18:6a4db94011d3 336 SPI0_IRQHandler
sahilmgandhi 18:6a4db94011d3 337 SPI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 338 UART0_IRQHandler
sahilmgandhi 18:6a4db94011d3 339 UART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 340 UART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 341 ADC0_IRQHandler
sahilmgandhi 18:6a4db94011d3 342 CMP0_IRQHandler
sahilmgandhi 18:6a4db94011d3 343 TPM0_IRQHandler
sahilmgandhi 18:6a4db94011d3 344 TPM1_IRQHandler
sahilmgandhi 18:6a4db94011d3 345 TPM2_IRQHandler
sahilmgandhi 18:6a4db94011d3 346 RTC_IRQHandler
sahilmgandhi 18:6a4db94011d3 347 RTC_Seconds_IRQHandler
sahilmgandhi 18:6a4db94011d3 348 PIT_IRQHandler
sahilmgandhi 18:6a4db94011d3 349 I2S0_IRQHandler
sahilmgandhi 18:6a4db94011d3 350 USB0_IRQHandler
sahilmgandhi 18:6a4db94011d3 351 DAC0_IRQHandler
sahilmgandhi 18:6a4db94011d3 352 TSI0_IRQHandler
sahilmgandhi 18:6a4db94011d3 353 MCG_IRQHandler
sahilmgandhi 18:6a4db94011d3 354 LPTMR0_IRQHandler
sahilmgandhi 18:6a4db94011d3 355 Reserved45_IRQHandler
sahilmgandhi 18:6a4db94011d3 356 PORTA_IRQHandler
sahilmgandhi 18:6a4db94011d3 357 PORTC_PORTD_IRQHandler
sahilmgandhi 18:6a4db94011d3 358 DefaultISR
sahilmgandhi 18:6a4db94011d3 359 LDR R0, =DefaultISR
sahilmgandhi 18:6a4db94011d3 360 BX R0
sahilmgandhi 18:6a4db94011d3 361 ENDP
sahilmgandhi 18:6a4db94011d3 362 ALIGN
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 END