MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/MKL26Z4.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 ** ###################################################################
sahilmgandhi 18:6a4db94011d3 3 ** Processors: MKL26Z128VFM4
sahilmgandhi 18:6a4db94011d3 4 ** MKL26Z64VFM4
sahilmgandhi 18:6a4db94011d3 5 ** MKL26Z32VM4
sahilmgandhi 18:6a4db94011d3 6 ** MKL26Z128VFT4
sahilmgandhi 18:6a4db94011d3 7 ** MKL26Z64VFT4
sahilmgandhi 18:6a4db94011d3 8 ** MKL26Z32VFT4
sahilmgandhi 18:6a4db94011d3 9 ** MKL26Z256VLH4
sahilmgandhi 18:6a4db94011d3 10 ** MKL26Z128VLH4
sahilmgandhi 18:6a4db94011d3 11 ** MKL26Z64VLH4
sahilmgandhi 18:6a4db94011d3 12 ** MKL26Z32VLH4
sahilmgandhi 18:6a4db94011d3 13 ** MKL26Z256VLK4
sahilmgandhi 18:6a4db94011d3 14 ** MKL26Z256VLL4
sahilmgandhi 18:6a4db94011d3 15 ** MKL26Z128VLL4
sahilmgandhi 18:6a4db94011d3 16 ** MKL26Z256VMC4
sahilmgandhi 18:6a4db94011d3 17 ** MKL26Z128VMC4
sahilmgandhi 18:6a4db94011d3 18 **
sahilmgandhi 18:6a4db94011d3 19 ** Compilers: ARM Compiler
sahilmgandhi 18:6a4db94011d3 20 ** Freescale C/C++ for Embedded ARM
sahilmgandhi 18:6a4db94011d3 21 ** GNU C Compiler
sahilmgandhi 18:6a4db94011d3 22 ** IAR ANSI C/C++ Compiler for ARM
sahilmgandhi 18:6a4db94011d3 23 **
sahilmgandhi 18:6a4db94011d3 24 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
sahilmgandhi 18:6a4db94011d3 25 ** Version: rev. 1.0, 2012-12-12
sahilmgandhi 18:6a4db94011d3 26 **
sahilmgandhi 18:6a4db94011d3 27 ** Abstract:
sahilmgandhi 18:6a4db94011d3 28 ** CMSIS Peripheral Access Layer for MKL26Z4
sahilmgandhi 18:6a4db94011d3 29 **
sahilmgandhi 18:6a4db94011d3 30 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 31 **
sahilmgandhi 18:6a4db94011d3 32 ** http: www.freescale.com
sahilmgandhi 18:6a4db94011d3 33 ** mail: support@freescale.com
sahilmgandhi 18:6a4db94011d3 34 **
sahilmgandhi 18:6a4db94011d3 35 ** Revisions:
sahilmgandhi 18:6a4db94011d3 36 ** - rev. 1.0 (2012-12-12)
sahilmgandhi 18:6a4db94011d3 37 ** Initial version.
sahilmgandhi 18:6a4db94011d3 38 **
sahilmgandhi 18:6a4db94011d3 39 ** ###################################################################
sahilmgandhi 18:6a4db94011d3 40 */
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /**
sahilmgandhi 18:6a4db94011d3 43 * @file MKL26Z4.h
sahilmgandhi 18:6a4db94011d3 44 * @version 1.0
sahilmgandhi 18:6a4db94011d3 45 * @date 2012-12-12
sahilmgandhi 18:6a4db94011d3 46 * @brief CMSIS Peripheral Access Layer for MKL26Z4
sahilmgandhi 18:6a4db94011d3 47 *
sahilmgandhi 18:6a4db94011d3 48 * CMSIS Peripheral Access Layer for MKL26Z4
sahilmgandhi 18:6a4db94011d3 49 */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #if !defined(MKL26Z4_H_)
sahilmgandhi 18:6a4db94011d3 52 #define MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /** Memory map major version (memory maps with equal major version number are
sahilmgandhi 18:6a4db94011d3 55 * compatible) */
sahilmgandhi 18:6a4db94011d3 56 #define MCU_MEM_MAP_VERSION 0x0100u
sahilmgandhi 18:6a4db94011d3 57 /** Memory map minor version */
sahilmgandhi 18:6a4db94011d3 58 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 62 -- Interrupt vector numbers
sahilmgandhi 18:6a4db94011d3 63 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /**
sahilmgandhi 18:6a4db94011d3 66 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
sahilmgandhi 18:6a4db94011d3 67 * @{
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /** Interrupt Number Definitions */
sahilmgandhi 18:6a4db94011d3 71 typedef enum IRQn {
sahilmgandhi 18:6a4db94011d3 72 /* Core interrupts */
sahilmgandhi 18:6a4db94011d3 73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /* Device specific interrupts */
sahilmgandhi 18:6a4db94011d3 80 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
sahilmgandhi 18:6a4db94011d3 81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
sahilmgandhi 18:6a4db94011d3 82 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
sahilmgandhi 18:6a4db94011d3 83 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
sahilmgandhi 18:6a4db94011d3 84 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
sahilmgandhi 18:6a4db94011d3 85 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
sahilmgandhi 18:6a4db94011d3 86 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
sahilmgandhi 18:6a4db94011d3 87 LLW_IRQn = 7, /**< Low Leakage Wakeup */
sahilmgandhi 18:6a4db94011d3 88 I2C0_IRQn = 8, /**< I2C0 interrupt */
sahilmgandhi 18:6a4db94011d3 89 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
sahilmgandhi 18:6a4db94011d3 90 SPI0_IRQn = 10, /**< SPI0 interrupt */
sahilmgandhi 18:6a4db94011d3 91 SPI1_IRQn = 11, /**< SPI1 interrupt */
sahilmgandhi 18:6a4db94011d3 92 UART0_IRQn = 12, /**< UART0 status/error interrupt */
sahilmgandhi 18:6a4db94011d3 93 UART1_IRQn = 13, /**< UART1 status/error interrupt */
sahilmgandhi 18:6a4db94011d3 94 UART2_IRQn = 14, /**< UART2 status/error interrupt */
sahilmgandhi 18:6a4db94011d3 95 ADC0_IRQn = 15, /**< ADC0 interrupt */
sahilmgandhi 18:6a4db94011d3 96 CMP0_IRQn = 16, /**< CMP0 interrupt */
sahilmgandhi 18:6a4db94011d3 97 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
sahilmgandhi 18:6a4db94011d3 98 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
sahilmgandhi 18:6a4db94011d3 99 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
sahilmgandhi 18:6a4db94011d3 100 RTC_IRQn = 20, /**< RTC interrupt */
sahilmgandhi 18:6a4db94011d3 101 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
sahilmgandhi 18:6a4db94011d3 102 PIT_IRQn = 22, /**< PIT timer interrupt */
sahilmgandhi 18:6a4db94011d3 103 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
sahilmgandhi 18:6a4db94011d3 104 USB0_IRQn = 24, /**< USB0 interrupt */
sahilmgandhi 18:6a4db94011d3 105 DAC0_IRQn = 25, /**< DAC0 interrupt */
sahilmgandhi 18:6a4db94011d3 106 TSI0_IRQn = 26, /**< TSI0 interrupt */
sahilmgandhi 18:6a4db94011d3 107 MCG_IRQn = 27, /**< MCG interrupt */
sahilmgandhi 18:6a4db94011d3 108 LPTimer_IRQn = 28, /**< LPTimer interrupt */
sahilmgandhi 18:6a4db94011d3 109 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
sahilmgandhi 18:6a4db94011d3 110 PORTA_IRQn = 30, /**< Port A interrupt */
sahilmgandhi 18:6a4db94011d3 111 PORTD_IRQn = 31 /**< Port D interrupt */
sahilmgandhi 18:6a4db94011d3 112 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /**
sahilmgandhi 18:6a4db94011d3 115 * @}
sahilmgandhi 18:6a4db94011d3 116 */ /* end of group Interrupt_vector_numbers */
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 120 -- Cortex M0 Core Configuration
sahilmgandhi 18:6a4db94011d3 121 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /**
sahilmgandhi 18:6a4db94011d3 124 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
sahilmgandhi 18:6a4db94011d3 125 * @{
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
sahilmgandhi 18:6a4db94011d3 129 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
sahilmgandhi 18:6a4db94011d3 130 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
sahilmgandhi 18:6a4db94011d3 131 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
sahilmgandhi 18:6a4db94011d3 132 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
sahilmgandhi 18:6a4db94011d3 135 #include "system_MKL26Z4.h" /* Device specific configuration file */
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /**
sahilmgandhi 18:6a4db94011d3 138 * @}
sahilmgandhi 18:6a4db94011d3 139 */ /* end of group Cortex_Core_Configuration */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 143 -- Device Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 144 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /**
sahilmgandhi 18:6a4db94011d3 147 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 148 * @{
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /*
sahilmgandhi 18:6a4db94011d3 153 ** Start of section using anonymous unions
sahilmgandhi 18:6a4db94011d3 154 */
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 #if defined(__ARMCC_VERSION)
sahilmgandhi 18:6a4db94011d3 157 #pragma push
sahilmgandhi 18:6a4db94011d3 158 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 159 #elif defined(__CWCC__)
sahilmgandhi 18:6a4db94011d3 160 #pragma push
sahilmgandhi 18:6a4db94011d3 161 #pragma cpp_extensions on
sahilmgandhi 18:6a4db94011d3 162 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 163 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 164 #elif defined(__IAR_SYSTEMS_ICC__)
sahilmgandhi 18:6a4db94011d3 165 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 166 #else
sahilmgandhi 18:6a4db94011d3 167 #error Not supported compiler type
sahilmgandhi 18:6a4db94011d3 168 #endif
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 171 -- ADC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 172 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /**
sahilmgandhi 18:6a4db94011d3 175 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 176 * @{
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** ADC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 180 typedef struct {
sahilmgandhi 18:6a4db94011d3 181 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 182 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 183 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 184 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 185 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 186 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 187 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 188 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 189 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 190 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 191 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 192 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 193 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 194 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 195 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 196 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 197 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 198 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 199 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 200 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 201 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 206 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 207 } ADC_Type;
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 210 -- ADC Register Masks
sahilmgandhi 18:6a4db94011d3 211 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 /**
sahilmgandhi 18:6a4db94011d3 214 * @addtogroup ADC_Register_Masks ADC Register Masks
sahilmgandhi 18:6a4db94011d3 215 * @{
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /* SC1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 219 #define ADC_SC1_ADCH_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 220 #define ADC_SC1_ADCH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 221 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
sahilmgandhi 18:6a4db94011d3 222 #define ADC_SC1_DIFF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 223 #define ADC_SC1_DIFF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 224 #define ADC_SC1_AIEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 225 #define ADC_SC1_AIEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 226 #define ADC_SC1_COCO_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 227 #define ADC_SC1_COCO_SHIFT 7
sahilmgandhi 18:6a4db94011d3 228 /* CFG1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 229 #define ADC_CFG1_ADICLK_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 230 #define ADC_CFG1_ADICLK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 231 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
sahilmgandhi 18:6a4db94011d3 232 #define ADC_CFG1_MODE_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 233 #define ADC_CFG1_MODE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 234 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
sahilmgandhi 18:6a4db94011d3 235 #define ADC_CFG1_ADLSMP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 236 #define ADC_CFG1_ADLSMP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 237 #define ADC_CFG1_ADIV_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 238 #define ADC_CFG1_ADIV_SHIFT 5
sahilmgandhi 18:6a4db94011d3 239 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
sahilmgandhi 18:6a4db94011d3 240 #define ADC_CFG1_ADLPC_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 241 #define ADC_CFG1_ADLPC_SHIFT 7
sahilmgandhi 18:6a4db94011d3 242 /* CFG2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 243 #define ADC_CFG2_ADLSTS_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 244 #define ADC_CFG2_ADLSTS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 245 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
sahilmgandhi 18:6a4db94011d3 246 #define ADC_CFG2_ADHSC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 247 #define ADC_CFG2_ADHSC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 248 #define ADC_CFG2_ADACKEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 249 #define ADC_CFG2_ADACKEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 250 #define ADC_CFG2_MUXSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 251 #define ADC_CFG2_MUXSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 252 /* R Bit Fields */
sahilmgandhi 18:6a4db94011d3 253 #define ADC_R_D_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 254 #define ADC_R_D_SHIFT 0
sahilmgandhi 18:6a4db94011d3 255 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
sahilmgandhi 18:6a4db94011d3 256 /* CV1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 257 #define ADC_CV1_CV_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 258 #define ADC_CV1_CV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 259 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
sahilmgandhi 18:6a4db94011d3 260 /* CV2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 261 #define ADC_CV2_CV_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 262 #define ADC_CV2_CV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 263 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
sahilmgandhi 18:6a4db94011d3 264 /* SC2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 265 #define ADC_SC2_REFSEL_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 266 #define ADC_SC2_REFSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 267 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
sahilmgandhi 18:6a4db94011d3 268 #define ADC_SC2_DMAEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 269 #define ADC_SC2_DMAEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 270 #define ADC_SC2_ACREN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 271 #define ADC_SC2_ACREN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 272 #define ADC_SC2_ACFGT_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 273 #define ADC_SC2_ACFGT_SHIFT 4
sahilmgandhi 18:6a4db94011d3 274 #define ADC_SC2_ACFE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 275 #define ADC_SC2_ACFE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 276 #define ADC_SC2_ADTRG_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 277 #define ADC_SC2_ADTRG_SHIFT 6
sahilmgandhi 18:6a4db94011d3 278 #define ADC_SC2_ADACT_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 279 #define ADC_SC2_ADACT_SHIFT 7
sahilmgandhi 18:6a4db94011d3 280 /* SC3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 281 #define ADC_SC3_AVGS_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 282 #define ADC_SC3_AVGS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 283 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
sahilmgandhi 18:6a4db94011d3 284 #define ADC_SC3_AVGE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 285 #define ADC_SC3_AVGE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 286 #define ADC_SC3_ADCO_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 287 #define ADC_SC3_ADCO_SHIFT 3
sahilmgandhi 18:6a4db94011d3 288 #define ADC_SC3_CALF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 289 #define ADC_SC3_CALF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 290 #define ADC_SC3_CAL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 291 #define ADC_SC3_CAL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 292 /* OFS Bit Fields */
sahilmgandhi 18:6a4db94011d3 293 #define ADC_OFS_OFS_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 294 #define ADC_OFS_OFS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 295 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
sahilmgandhi 18:6a4db94011d3 296 /* PG Bit Fields */
sahilmgandhi 18:6a4db94011d3 297 #define ADC_PG_PG_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 298 #define ADC_PG_PG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 299 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
sahilmgandhi 18:6a4db94011d3 300 /* MG Bit Fields */
sahilmgandhi 18:6a4db94011d3 301 #define ADC_MG_MG_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 302 #define ADC_MG_MG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 303 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
sahilmgandhi 18:6a4db94011d3 304 /* CLPD Bit Fields */
sahilmgandhi 18:6a4db94011d3 305 #define ADC_CLPD_CLPD_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 306 #define ADC_CLPD_CLPD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 307 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
sahilmgandhi 18:6a4db94011d3 308 /* CLPS Bit Fields */
sahilmgandhi 18:6a4db94011d3 309 #define ADC_CLPS_CLPS_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 310 #define ADC_CLPS_CLPS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 311 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
sahilmgandhi 18:6a4db94011d3 312 /* CLP4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 313 #define ADC_CLP4_CLP4_MASK 0x3FFu
sahilmgandhi 18:6a4db94011d3 314 #define ADC_CLP4_CLP4_SHIFT 0
sahilmgandhi 18:6a4db94011d3 315 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
sahilmgandhi 18:6a4db94011d3 316 /* CLP3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 317 #define ADC_CLP3_CLP3_MASK 0x1FFu
sahilmgandhi 18:6a4db94011d3 318 #define ADC_CLP3_CLP3_SHIFT 0
sahilmgandhi 18:6a4db94011d3 319 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
sahilmgandhi 18:6a4db94011d3 320 /* CLP2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 321 #define ADC_CLP2_CLP2_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 322 #define ADC_CLP2_CLP2_SHIFT 0
sahilmgandhi 18:6a4db94011d3 323 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
sahilmgandhi 18:6a4db94011d3 324 /* CLP1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 325 #define ADC_CLP1_CLP1_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 326 #define ADC_CLP1_CLP1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 327 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
sahilmgandhi 18:6a4db94011d3 328 /* CLP0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 329 #define ADC_CLP0_CLP0_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 330 #define ADC_CLP0_CLP0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 331 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
sahilmgandhi 18:6a4db94011d3 332 /* CLMD Bit Fields */
sahilmgandhi 18:6a4db94011d3 333 #define ADC_CLMD_CLMD_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 334 #define ADC_CLMD_CLMD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 335 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
sahilmgandhi 18:6a4db94011d3 336 /* CLMS Bit Fields */
sahilmgandhi 18:6a4db94011d3 337 #define ADC_CLMS_CLMS_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 338 #define ADC_CLMS_CLMS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 339 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
sahilmgandhi 18:6a4db94011d3 340 /* CLM4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 341 #define ADC_CLM4_CLM4_MASK 0x3FFu
sahilmgandhi 18:6a4db94011d3 342 #define ADC_CLM4_CLM4_SHIFT 0
sahilmgandhi 18:6a4db94011d3 343 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
sahilmgandhi 18:6a4db94011d3 344 /* CLM3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 345 #define ADC_CLM3_CLM3_MASK 0x1FFu
sahilmgandhi 18:6a4db94011d3 346 #define ADC_CLM3_CLM3_SHIFT 0
sahilmgandhi 18:6a4db94011d3 347 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
sahilmgandhi 18:6a4db94011d3 348 /* CLM2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 349 #define ADC_CLM2_CLM2_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 350 #define ADC_CLM2_CLM2_SHIFT 0
sahilmgandhi 18:6a4db94011d3 351 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
sahilmgandhi 18:6a4db94011d3 352 /* CLM1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 353 #define ADC_CLM1_CLM1_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 354 #define ADC_CLM1_CLM1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 355 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
sahilmgandhi 18:6a4db94011d3 356 /* CLM0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 357 #define ADC_CLM0_CLM0_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 358 #define ADC_CLM0_CLM0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 359 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /**
sahilmgandhi 18:6a4db94011d3 362 * @}
sahilmgandhi 18:6a4db94011d3 363 */ /* end of group ADC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* ADC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 367 /** Peripheral ADC0 base address */
sahilmgandhi 18:6a4db94011d3 368 #define ADC0_BASE (0x4003B000u)
sahilmgandhi 18:6a4db94011d3 369 /** Peripheral ADC0 base pointer */
sahilmgandhi 18:6a4db94011d3 370 #define ADC0 ((ADC_Type *)ADC0_BASE)
sahilmgandhi 18:6a4db94011d3 371 /** Array initializer of ADC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 372 #define ADC_BASES { ADC0 }
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 /**
sahilmgandhi 18:6a4db94011d3 375 * @}
sahilmgandhi 18:6a4db94011d3 376 */ /* end of group ADC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 380 -- CMP Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 381 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 /**
sahilmgandhi 18:6a4db94011d3 384 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 385 * @{
sahilmgandhi 18:6a4db94011d3 386 */
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 /** CMP - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 389 typedef struct {
sahilmgandhi 18:6a4db94011d3 390 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 391 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 392 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 393 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 394 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 395 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 396 } CMP_Type;
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 399 -- CMP Register Masks
sahilmgandhi 18:6a4db94011d3 400 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 401
sahilmgandhi 18:6a4db94011d3 402 /**
sahilmgandhi 18:6a4db94011d3 403 * @addtogroup CMP_Register_Masks CMP Register Masks
sahilmgandhi 18:6a4db94011d3 404 * @{
sahilmgandhi 18:6a4db94011d3 405 */
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /* CR0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 408 #define CMP_CR0_HYSTCTR_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 409 #define CMP_CR0_HYSTCTR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 410 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
sahilmgandhi 18:6a4db94011d3 411 #define CMP_CR0_FILTER_CNT_MASK 0x70u
sahilmgandhi 18:6a4db94011d3 412 #define CMP_CR0_FILTER_CNT_SHIFT 4
sahilmgandhi 18:6a4db94011d3 413 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
sahilmgandhi 18:6a4db94011d3 414 /* CR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 415 #define CMP_CR1_EN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 416 #define CMP_CR1_EN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 417 #define CMP_CR1_OPE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 418 #define CMP_CR1_OPE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 419 #define CMP_CR1_COS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 420 #define CMP_CR1_COS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 421 #define CMP_CR1_INV_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 422 #define CMP_CR1_INV_SHIFT 3
sahilmgandhi 18:6a4db94011d3 423 #define CMP_CR1_PMODE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 424 #define CMP_CR1_PMODE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 425 #define CMP_CR1_TRIGM_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 426 #define CMP_CR1_TRIGM_SHIFT 5
sahilmgandhi 18:6a4db94011d3 427 #define CMP_CR1_WE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 428 #define CMP_CR1_WE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 429 #define CMP_CR1_SE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 430 #define CMP_CR1_SE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 431 /* FPR Bit Fields */
sahilmgandhi 18:6a4db94011d3 432 #define CMP_FPR_FILT_PER_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 433 #define CMP_FPR_FILT_PER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 434 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
sahilmgandhi 18:6a4db94011d3 435 /* SCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 436 #define CMP_SCR_COUT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 437 #define CMP_SCR_COUT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 438 #define CMP_SCR_CFF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 439 #define CMP_SCR_CFF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 440 #define CMP_SCR_CFR_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 441 #define CMP_SCR_CFR_SHIFT 2
sahilmgandhi 18:6a4db94011d3 442 #define CMP_SCR_IEF_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 443 #define CMP_SCR_IEF_SHIFT 3
sahilmgandhi 18:6a4db94011d3 444 #define CMP_SCR_IER_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 445 #define CMP_SCR_IER_SHIFT 4
sahilmgandhi 18:6a4db94011d3 446 #define CMP_SCR_DMAEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 447 #define CMP_SCR_DMAEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 448 /* DACCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 449 #define CMP_DACCR_VOSEL_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 450 #define CMP_DACCR_VOSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 451 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
sahilmgandhi 18:6a4db94011d3 452 #define CMP_DACCR_VRSEL_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 453 #define CMP_DACCR_VRSEL_SHIFT 6
sahilmgandhi 18:6a4db94011d3 454 #define CMP_DACCR_DACEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 455 #define CMP_DACCR_DACEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 456 /* MUXCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 457 #define CMP_MUXCR_MSEL_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 458 #define CMP_MUXCR_MSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 459 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
sahilmgandhi 18:6a4db94011d3 460 #define CMP_MUXCR_PSEL_MASK 0x38u
sahilmgandhi 18:6a4db94011d3 461 #define CMP_MUXCR_PSEL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 462 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
sahilmgandhi 18:6a4db94011d3 463 #define CMP_MUXCR_PSTM_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 464 #define CMP_MUXCR_PSTM_SHIFT 7
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /**
sahilmgandhi 18:6a4db94011d3 467 * @}
sahilmgandhi 18:6a4db94011d3 468 */ /* end of group CMP_Register_Masks */
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 /* CMP - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 472 /** Peripheral CMP0 base address */
sahilmgandhi 18:6a4db94011d3 473 #define CMP0_BASE (0x40073000u)
sahilmgandhi 18:6a4db94011d3 474 /** Peripheral CMP0 base pointer */
sahilmgandhi 18:6a4db94011d3 475 #define CMP0 ((CMP_Type *)CMP0_BASE)
sahilmgandhi 18:6a4db94011d3 476 /** Array initializer of CMP peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 477 #define CMP_BASES { CMP0 }
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 /**
sahilmgandhi 18:6a4db94011d3 480 * @}
sahilmgandhi 18:6a4db94011d3 481 */ /* end of group CMP_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 485 -- DAC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 486 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /**
sahilmgandhi 18:6a4db94011d3 489 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 490 * @{
sahilmgandhi 18:6a4db94011d3 491 */
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 /** DAC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 494 typedef struct {
sahilmgandhi 18:6a4db94011d3 495 struct { /* offset: 0x0, array step: 0x2 */
sahilmgandhi 18:6a4db94011d3 496 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
sahilmgandhi 18:6a4db94011d3 497 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
sahilmgandhi 18:6a4db94011d3 498 } DAT[2];
sahilmgandhi 18:6a4db94011d3 499 uint8_t RESERVED_0[28];
sahilmgandhi 18:6a4db94011d3 500 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 501 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
sahilmgandhi 18:6a4db94011d3 502 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
sahilmgandhi 18:6a4db94011d3 503 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
sahilmgandhi 18:6a4db94011d3 504 } DAC_Type;
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 507 -- DAC Register Masks
sahilmgandhi 18:6a4db94011d3 508 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 /**
sahilmgandhi 18:6a4db94011d3 511 * @addtogroup DAC_Register_Masks DAC Register Masks
sahilmgandhi 18:6a4db94011d3 512 * @{
sahilmgandhi 18:6a4db94011d3 513 */
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 /* DATL Bit Fields */
sahilmgandhi 18:6a4db94011d3 516 #define DAC_DATL_DATA0_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 517 #define DAC_DATL_DATA0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 518 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
sahilmgandhi 18:6a4db94011d3 519 /* DATH Bit Fields */
sahilmgandhi 18:6a4db94011d3 520 #define DAC_DATH_DATA1_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 521 #define DAC_DATH_DATA1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 522 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
sahilmgandhi 18:6a4db94011d3 523 /* SR Bit Fields */
sahilmgandhi 18:6a4db94011d3 524 #define DAC_SR_DACBFRPBF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 525 #define DAC_SR_DACBFRPBF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 526 #define DAC_SR_DACBFRPTF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 527 #define DAC_SR_DACBFRPTF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 528 /* C0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 529 #define DAC_C0_DACBBIEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 530 #define DAC_C0_DACBBIEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 531 #define DAC_C0_DACBTIEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 532 #define DAC_C0_DACBTIEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 533 #define DAC_C0_LPEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 534 #define DAC_C0_LPEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 535 #define DAC_C0_DACSWTRG_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 536 #define DAC_C0_DACSWTRG_SHIFT 4
sahilmgandhi 18:6a4db94011d3 537 #define DAC_C0_DACTRGSEL_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 538 #define DAC_C0_DACTRGSEL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 539 #define DAC_C0_DACRFS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 540 #define DAC_C0_DACRFS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 541 #define DAC_C0_DACEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 542 #define DAC_C0_DACEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 543 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 544 #define DAC_C1_DACBFEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 545 #define DAC_C1_DACBFEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 546 #define DAC_C1_DACBFMD_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 547 #define DAC_C1_DACBFMD_SHIFT 2
sahilmgandhi 18:6a4db94011d3 548 #define DAC_C1_DMAEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 549 #define DAC_C1_DMAEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 550 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 551 #define DAC_C2_DACBFUP_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 552 #define DAC_C2_DACBFUP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 553 #define DAC_C2_DACBFRP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 554 #define DAC_C2_DACBFRP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /**
sahilmgandhi 18:6a4db94011d3 557 * @}
sahilmgandhi 18:6a4db94011d3 558 */ /* end of group DAC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /* DAC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 562 /** Peripheral DAC0 base address */
sahilmgandhi 18:6a4db94011d3 563 #define DAC0_BASE (0x4003F000u)
sahilmgandhi 18:6a4db94011d3 564 /** Peripheral DAC0 base pointer */
sahilmgandhi 18:6a4db94011d3 565 #define DAC0 ((DAC_Type *)DAC0_BASE)
sahilmgandhi 18:6a4db94011d3 566 /** Array initializer of DAC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 567 #define DAC_BASES { DAC0 }
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /**
sahilmgandhi 18:6a4db94011d3 570 * @}
sahilmgandhi 18:6a4db94011d3 571 */ /* end of group DAC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 575 -- DMA Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 576 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 /**
sahilmgandhi 18:6a4db94011d3 579 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 580 * @{
sahilmgandhi 18:6a4db94011d3 581 */
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /** DMA - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 584 typedef struct {
sahilmgandhi 18:6a4db94011d3 585 uint8_t RESERVED_0[256];
sahilmgandhi 18:6a4db94011d3 586 struct { /* offset: 0x100, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 589 union { /* offset: 0x108, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 591 struct { /* offset: 0x108, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 592 uint8_t RESERVED_0[3];
sahilmgandhi 18:6a4db94011d3 593 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 594 } DMA_DSR_ACCESS8BIT;
sahilmgandhi 18:6a4db94011d3 595 };
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 597 } DMA[4];
sahilmgandhi 18:6a4db94011d3 598 } DMA_Type;
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 601 -- DMA Register Masks
sahilmgandhi 18:6a4db94011d3 602 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 603
sahilmgandhi 18:6a4db94011d3 604 /**
sahilmgandhi 18:6a4db94011d3 605 * @addtogroup DMA_Register_Masks DMA Register Masks
sahilmgandhi 18:6a4db94011d3 606 * @{
sahilmgandhi 18:6a4db94011d3 607 */
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 /* SAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 610 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 611 #define DMA_SAR_SAR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 612 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
sahilmgandhi 18:6a4db94011d3 613 /* DAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 614 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 615 #define DMA_DAR_DAR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 616 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
sahilmgandhi 18:6a4db94011d3 617 /* DSR_BCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 618 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
sahilmgandhi 18:6a4db94011d3 619 #define DMA_DSR_BCR_BCR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 620 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
sahilmgandhi 18:6a4db94011d3 621 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 622 #define DMA_DSR_BCR_DONE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 623 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 624 #define DMA_DSR_BCR_BSY_SHIFT 25
sahilmgandhi 18:6a4db94011d3 625 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 626 #define DMA_DSR_BCR_REQ_SHIFT 26
sahilmgandhi 18:6a4db94011d3 627 #define DMA_DSR_BCR_BED_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 628 #define DMA_DSR_BCR_BED_SHIFT 28
sahilmgandhi 18:6a4db94011d3 629 #define DMA_DSR_BCR_BES_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 630 #define DMA_DSR_BCR_BES_SHIFT 29
sahilmgandhi 18:6a4db94011d3 631 #define DMA_DSR_BCR_CE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 632 #define DMA_DSR_BCR_CE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 633 /* DCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 634 #define DMA_DCR_LCH2_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 635 #define DMA_DCR_LCH2_SHIFT 0
sahilmgandhi 18:6a4db94011d3 636 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
sahilmgandhi 18:6a4db94011d3 637 #define DMA_DCR_LCH1_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 638 #define DMA_DCR_LCH1_SHIFT 2
sahilmgandhi 18:6a4db94011d3 639 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
sahilmgandhi 18:6a4db94011d3 640 #define DMA_DCR_LINKCC_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 641 #define DMA_DCR_LINKCC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 642 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
sahilmgandhi 18:6a4db94011d3 643 #define DMA_DCR_D_REQ_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 644 #define DMA_DCR_D_REQ_SHIFT 7
sahilmgandhi 18:6a4db94011d3 645 #define DMA_DCR_DMOD_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 646 #define DMA_DCR_DMOD_SHIFT 8
sahilmgandhi 18:6a4db94011d3 647 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
sahilmgandhi 18:6a4db94011d3 648 #define DMA_DCR_SMOD_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 649 #define DMA_DCR_SMOD_SHIFT 12
sahilmgandhi 18:6a4db94011d3 650 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
sahilmgandhi 18:6a4db94011d3 651 #define DMA_DCR_START_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 652 #define DMA_DCR_START_SHIFT 16
sahilmgandhi 18:6a4db94011d3 653 #define DMA_DCR_DSIZE_MASK 0x60000u
sahilmgandhi 18:6a4db94011d3 654 #define DMA_DCR_DSIZE_SHIFT 17
sahilmgandhi 18:6a4db94011d3 655 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 656 #define DMA_DCR_DINC_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 657 #define DMA_DCR_DINC_SHIFT 19
sahilmgandhi 18:6a4db94011d3 658 #define DMA_DCR_SSIZE_MASK 0x300000u
sahilmgandhi 18:6a4db94011d3 659 #define DMA_DCR_SSIZE_SHIFT 20
sahilmgandhi 18:6a4db94011d3 660 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 661 #define DMA_DCR_SINC_MASK 0x400000u
sahilmgandhi 18:6a4db94011d3 662 #define DMA_DCR_SINC_SHIFT 22
sahilmgandhi 18:6a4db94011d3 663 #define DMA_DCR_EADREQ_MASK 0x800000u
sahilmgandhi 18:6a4db94011d3 664 #define DMA_DCR_EADREQ_SHIFT 23
sahilmgandhi 18:6a4db94011d3 665 #define DMA_DCR_AA_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 666 #define DMA_DCR_AA_SHIFT 28
sahilmgandhi 18:6a4db94011d3 667 #define DMA_DCR_CS_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 668 #define DMA_DCR_CS_SHIFT 29
sahilmgandhi 18:6a4db94011d3 669 #define DMA_DCR_ERQ_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 670 #define DMA_DCR_ERQ_SHIFT 30
sahilmgandhi 18:6a4db94011d3 671 #define DMA_DCR_EINT_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 672 #define DMA_DCR_EINT_SHIFT 31
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 /**
sahilmgandhi 18:6a4db94011d3 675 * @}
sahilmgandhi 18:6a4db94011d3 676 */ /* end of group DMA_Register_Masks */
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 /* DMA - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 680 /** Peripheral DMA base address */
sahilmgandhi 18:6a4db94011d3 681 #define DMA_BASE (0x40008000u)
sahilmgandhi 18:6a4db94011d3 682 /** Peripheral DMA base pointer */
sahilmgandhi 18:6a4db94011d3 683 #define DMA0 ((DMA_Type *)DMA_BASE)
sahilmgandhi 18:6a4db94011d3 684 /** Array initializer of DMA peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 685 #define DMA_BASES { DMA0 }
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 /**
sahilmgandhi 18:6a4db94011d3 688 * @}
sahilmgandhi 18:6a4db94011d3 689 */ /* end of group DMA_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 693 -- DMAMUX Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 694 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /**
sahilmgandhi 18:6a4db94011d3 697 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 698 * @{
sahilmgandhi 18:6a4db94011d3 699 */
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 /** DMAMUX - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 702 typedef struct {
sahilmgandhi 18:6a4db94011d3 703 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
sahilmgandhi 18:6a4db94011d3 704 } DMAMUX_Type;
sahilmgandhi 18:6a4db94011d3 705
sahilmgandhi 18:6a4db94011d3 706 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 707 -- DMAMUX Register Masks
sahilmgandhi 18:6a4db94011d3 708 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 /**
sahilmgandhi 18:6a4db94011d3 711 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
sahilmgandhi 18:6a4db94011d3 712 * @{
sahilmgandhi 18:6a4db94011d3 713 */
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 /* CHCFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 716 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 717 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 718 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
sahilmgandhi 18:6a4db94011d3 719 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 720 #define DMAMUX_CHCFG_TRIG_SHIFT 6
sahilmgandhi 18:6a4db94011d3 721 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 722 #define DMAMUX_CHCFG_ENBL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 /**
sahilmgandhi 18:6a4db94011d3 725 * @}
sahilmgandhi 18:6a4db94011d3 726 */ /* end of group DMAMUX_Register_Masks */
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 /* DMAMUX - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 730 /** Peripheral DMAMUX0 base address */
sahilmgandhi 18:6a4db94011d3 731 #define DMAMUX0_BASE (0x40021000u)
sahilmgandhi 18:6a4db94011d3 732 /** Peripheral DMAMUX0 base pointer */
sahilmgandhi 18:6a4db94011d3 733 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
sahilmgandhi 18:6a4db94011d3 734 /** Array initializer of DMAMUX peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 735 #define DMAMUX_BASES { DMAMUX0 }
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /**
sahilmgandhi 18:6a4db94011d3 738 * @}
sahilmgandhi 18:6a4db94011d3 739 */ /* end of group DMAMUX_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741
sahilmgandhi 18:6a4db94011d3 742 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 743 -- FGPIO Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 744 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 /**
sahilmgandhi 18:6a4db94011d3 747 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 748 * @{
sahilmgandhi 18:6a4db94011d3 749 */
sahilmgandhi 18:6a4db94011d3 750
sahilmgandhi 18:6a4db94011d3 751 /** FGPIO - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 752 typedef struct {
sahilmgandhi 18:6a4db94011d3 753 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 754 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 755 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 756 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 757 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 758 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 759 } FGPIO_Type;
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 762 -- FGPIO Register Masks
sahilmgandhi 18:6a4db94011d3 763 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 /**
sahilmgandhi 18:6a4db94011d3 766 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
sahilmgandhi 18:6a4db94011d3 767 * @{
sahilmgandhi 18:6a4db94011d3 768 */
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /* PDOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 771 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 772 #define FGPIO_PDOR_PDO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 773 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
sahilmgandhi 18:6a4db94011d3 774 /* PSOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 775 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 776 #define FGPIO_PSOR_PTSO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 777 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
sahilmgandhi 18:6a4db94011d3 778 /* PCOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 779 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 780 #define FGPIO_PCOR_PTCO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 781 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
sahilmgandhi 18:6a4db94011d3 782 /* PTOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 783 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 784 #define FGPIO_PTOR_PTTO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 785 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
sahilmgandhi 18:6a4db94011d3 786 /* PDIR Bit Fields */
sahilmgandhi 18:6a4db94011d3 787 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 788 #define FGPIO_PDIR_PDI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 789 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
sahilmgandhi 18:6a4db94011d3 790 /* PDDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 791 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 792 #define FGPIO_PDDR_PDD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 793 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 /**
sahilmgandhi 18:6a4db94011d3 796 * @}
sahilmgandhi 18:6a4db94011d3 797 */ /* end of group FGPIO_Register_Masks */
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 /* FGPIO - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 801 /** Peripheral FPTA base address */
sahilmgandhi 18:6a4db94011d3 802 #define FPTA_BASE (0xF80FF000u)
sahilmgandhi 18:6a4db94011d3 803 /** Peripheral FPTA base pointer */
sahilmgandhi 18:6a4db94011d3 804 #define FPTA ((FGPIO_Type *)FPTA_BASE)
sahilmgandhi 18:6a4db94011d3 805 /** Peripheral FPTB base address */
sahilmgandhi 18:6a4db94011d3 806 #define FPTB_BASE (0xF80FF040u)
sahilmgandhi 18:6a4db94011d3 807 /** Peripheral FPTB base pointer */
sahilmgandhi 18:6a4db94011d3 808 #define FPTB ((FGPIO_Type *)FPTB_BASE)
sahilmgandhi 18:6a4db94011d3 809 /** Peripheral FPTC base address */
sahilmgandhi 18:6a4db94011d3 810 #define FPTC_BASE (0xF80FF080u)
sahilmgandhi 18:6a4db94011d3 811 /** Peripheral FPTC base pointer */
sahilmgandhi 18:6a4db94011d3 812 #define FPTC ((FGPIO_Type *)FPTC_BASE)
sahilmgandhi 18:6a4db94011d3 813 /** Peripheral FPTD base address */
sahilmgandhi 18:6a4db94011d3 814 #define FPTD_BASE (0xF80FF0C0u)
sahilmgandhi 18:6a4db94011d3 815 /** Peripheral FPTD base pointer */
sahilmgandhi 18:6a4db94011d3 816 #define FPTD ((FGPIO_Type *)FPTD_BASE)
sahilmgandhi 18:6a4db94011d3 817 /** Peripheral FPTE base address */
sahilmgandhi 18:6a4db94011d3 818 #define FPTE_BASE (0xF80FF100u)
sahilmgandhi 18:6a4db94011d3 819 /** Peripheral FPTE base pointer */
sahilmgandhi 18:6a4db94011d3 820 #define FPTE ((FGPIO_Type *)FPTE_BASE)
sahilmgandhi 18:6a4db94011d3 821 /** Array initializer of FGPIO peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 822 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 /**
sahilmgandhi 18:6a4db94011d3 825 * @}
sahilmgandhi 18:6a4db94011d3 826 */ /* end of group FGPIO_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828
sahilmgandhi 18:6a4db94011d3 829 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 830 -- FTFA Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 831 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 /**
sahilmgandhi 18:6a4db94011d3 834 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 835 * @{
sahilmgandhi 18:6a4db94011d3 836 */
sahilmgandhi 18:6a4db94011d3 837
sahilmgandhi 18:6a4db94011d3 838 /** FTFA - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 839 typedef struct {
sahilmgandhi 18:6a4db94011d3 840 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 841 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 842 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 843 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 844 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 845 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 846 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 847 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 848 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 849 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 850 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 851 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 852 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 853 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 854 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
sahilmgandhi 18:6a4db94011d3 855 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
sahilmgandhi 18:6a4db94011d3 856 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 857 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
sahilmgandhi 18:6a4db94011d3 858 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
sahilmgandhi 18:6a4db94011d3 859 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
sahilmgandhi 18:6a4db94011d3 860 } FTFA_Type;
sahilmgandhi 18:6a4db94011d3 861
sahilmgandhi 18:6a4db94011d3 862 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 863 -- FTFA Register Masks
sahilmgandhi 18:6a4db94011d3 864 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /**
sahilmgandhi 18:6a4db94011d3 867 * @addtogroup FTFA_Register_Masks FTFA Register Masks
sahilmgandhi 18:6a4db94011d3 868 * @{
sahilmgandhi 18:6a4db94011d3 869 */
sahilmgandhi 18:6a4db94011d3 870
sahilmgandhi 18:6a4db94011d3 871 /* FSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 872 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 873 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 874 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 875 #define FTFA_FSTAT_FPVIOL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 876 #define FTFA_FSTAT_ACCERR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 877 #define FTFA_FSTAT_ACCERR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 878 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 879 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
sahilmgandhi 18:6a4db94011d3 880 #define FTFA_FSTAT_CCIF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 881 #define FTFA_FSTAT_CCIF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 882 /* FCNFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 883 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 884 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 885 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 886 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
sahilmgandhi 18:6a4db94011d3 887 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 888 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 889 #define FTFA_FCNFG_CCIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 890 #define FTFA_FCNFG_CCIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 891 /* FSEC Bit Fields */
sahilmgandhi 18:6a4db94011d3 892 #define FTFA_FSEC_SEC_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 893 #define FTFA_FSEC_SEC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 894 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
sahilmgandhi 18:6a4db94011d3 895 #define FTFA_FSEC_FSLACC_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 896 #define FTFA_FSEC_FSLACC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 897 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
sahilmgandhi 18:6a4db94011d3 898 #define FTFA_FSEC_MEEN_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 899 #define FTFA_FSEC_MEEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 900 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
sahilmgandhi 18:6a4db94011d3 901 #define FTFA_FSEC_KEYEN_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 902 #define FTFA_FSEC_KEYEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 903 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
sahilmgandhi 18:6a4db94011d3 904 /* FOPT Bit Fields */
sahilmgandhi 18:6a4db94011d3 905 #define FTFA_FOPT_OPT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 906 #define FTFA_FOPT_OPT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 907 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
sahilmgandhi 18:6a4db94011d3 908 /* FCCOB3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 909 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 910 #define FTFA_FCCOB3_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 911 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 912 /* FCCOB2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 913 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 914 #define FTFA_FCCOB2_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 915 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 916 /* FCCOB1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 917 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 918 #define FTFA_FCCOB1_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 919 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 920 /* FCCOB0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 921 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 922 #define FTFA_FCCOB0_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 923 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 924 /* FCCOB7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 925 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 926 #define FTFA_FCCOB7_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 927 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 928 /* FCCOB6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 929 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 930 #define FTFA_FCCOB6_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 931 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 932 /* FCCOB5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 933 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 934 #define FTFA_FCCOB5_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 935 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 936 /* FCCOB4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 937 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 938 #define FTFA_FCCOB4_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 939 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 940 /* FCCOBB Bit Fields */
sahilmgandhi 18:6a4db94011d3 941 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 942 #define FTFA_FCCOBB_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 943 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 944 /* FCCOBA Bit Fields */
sahilmgandhi 18:6a4db94011d3 945 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 946 #define FTFA_FCCOBA_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 947 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 948 /* FCCOB9 Bit Fields */
sahilmgandhi 18:6a4db94011d3 949 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 950 #define FTFA_FCCOB9_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 951 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 952 /* FCCOB8 Bit Fields */
sahilmgandhi 18:6a4db94011d3 953 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 954 #define FTFA_FCCOB8_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 955 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 956 /* FPROT3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 957 #define FTFA_FPROT3_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 958 #define FTFA_FPROT3_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 959 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 960 /* FPROT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 961 #define FTFA_FPROT2_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 962 #define FTFA_FPROT2_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 963 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 964 /* FPROT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 965 #define FTFA_FPROT1_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 966 #define FTFA_FPROT1_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 967 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 968 /* FPROT0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 969 #define FTFA_FPROT0_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 970 #define FTFA_FPROT0_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 971 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 972
sahilmgandhi 18:6a4db94011d3 973 /**
sahilmgandhi 18:6a4db94011d3 974 * @}
sahilmgandhi 18:6a4db94011d3 975 */ /* end of group FTFA_Register_Masks */
sahilmgandhi 18:6a4db94011d3 976
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 /* FTFA - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 979 /** Peripheral FTFA base address */
sahilmgandhi 18:6a4db94011d3 980 #define FTFA_BASE (0x40020000u)
sahilmgandhi 18:6a4db94011d3 981 /** Peripheral FTFA base pointer */
sahilmgandhi 18:6a4db94011d3 982 #define FTFA ((FTFA_Type *)FTFA_BASE)
sahilmgandhi 18:6a4db94011d3 983 /** Array initializer of FTFA peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 984 #define FTFA_BASES { FTFA }
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /**
sahilmgandhi 18:6a4db94011d3 987 * @}
sahilmgandhi 18:6a4db94011d3 988 */ /* end of group FTFA_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 989
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 992 -- GPIO Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 993 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995 /**
sahilmgandhi 18:6a4db94011d3 996 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 997 * @{
sahilmgandhi 18:6a4db94011d3 998 */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /** GPIO - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1001 typedef struct {
sahilmgandhi 18:6a4db94011d3 1002 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1003 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1004 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1005 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 1006 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 1007 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 1008 } GPIO_Type;
sahilmgandhi 18:6a4db94011d3 1009
sahilmgandhi 18:6a4db94011d3 1010 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1011 -- GPIO Register Masks
sahilmgandhi 18:6a4db94011d3 1012 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1013
sahilmgandhi 18:6a4db94011d3 1014 /**
sahilmgandhi 18:6a4db94011d3 1015 * @addtogroup GPIO_Register_Masks GPIO Register Masks
sahilmgandhi 18:6a4db94011d3 1016 * @{
sahilmgandhi 18:6a4db94011d3 1017 */
sahilmgandhi 18:6a4db94011d3 1018
sahilmgandhi 18:6a4db94011d3 1019 /* PDOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1020 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1021 #define GPIO_PDOR_PDO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1022 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
sahilmgandhi 18:6a4db94011d3 1023 /* PSOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1024 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1025 #define GPIO_PSOR_PTSO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1026 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
sahilmgandhi 18:6a4db94011d3 1027 /* PCOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1028 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1029 #define GPIO_PCOR_PTCO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1030 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
sahilmgandhi 18:6a4db94011d3 1031 /* PTOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1032 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1033 #define GPIO_PTOR_PTTO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1034 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
sahilmgandhi 18:6a4db94011d3 1035 /* PDIR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1036 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1037 #define GPIO_PDIR_PDI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1038 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
sahilmgandhi 18:6a4db94011d3 1039 /* PDDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1040 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1041 #define GPIO_PDDR_PDD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1042 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
sahilmgandhi 18:6a4db94011d3 1043
sahilmgandhi 18:6a4db94011d3 1044 /**
sahilmgandhi 18:6a4db94011d3 1045 * @}
sahilmgandhi 18:6a4db94011d3 1046 */ /* end of group GPIO_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1047
sahilmgandhi 18:6a4db94011d3 1048
sahilmgandhi 18:6a4db94011d3 1049 /* GPIO - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1050 /** Peripheral PTA base address */
sahilmgandhi 18:6a4db94011d3 1051 #define PTA_BASE (0x400FF000u)
sahilmgandhi 18:6a4db94011d3 1052 /** Peripheral PTA base pointer */
sahilmgandhi 18:6a4db94011d3 1053 #define PTA ((GPIO_Type *)PTA_BASE)
sahilmgandhi 18:6a4db94011d3 1054 /** Peripheral PTB base address */
sahilmgandhi 18:6a4db94011d3 1055 #define PTB_BASE (0x400FF040u)
sahilmgandhi 18:6a4db94011d3 1056 /** Peripheral PTB base pointer */
sahilmgandhi 18:6a4db94011d3 1057 #define PTB ((GPIO_Type *)PTB_BASE)
sahilmgandhi 18:6a4db94011d3 1058 /** Peripheral PTC base address */
sahilmgandhi 18:6a4db94011d3 1059 #define PTC_BASE (0x400FF080u)
sahilmgandhi 18:6a4db94011d3 1060 /** Peripheral PTC base pointer */
sahilmgandhi 18:6a4db94011d3 1061 #define PTC ((GPIO_Type *)PTC_BASE)
sahilmgandhi 18:6a4db94011d3 1062 /** Peripheral PTD base address */
sahilmgandhi 18:6a4db94011d3 1063 #define PTD_BASE (0x400FF0C0u)
sahilmgandhi 18:6a4db94011d3 1064 /** Peripheral PTD base pointer */
sahilmgandhi 18:6a4db94011d3 1065 #define PTD ((GPIO_Type *)PTD_BASE)
sahilmgandhi 18:6a4db94011d3 1066 /** Peripheral PTE base address */
sahilmgandhi 18:6a4db94011d3 1067 #define PTE_BASE (0x400FF100u)
sahilmgandhi 18:6a4db94011d3 1068 /** Peripheral PTE base pointer */
sahilmgandhi 18:6a4db94011d3 1069 #define PTE ((GPIO_Type *)PTE_BASE)
sahilmgandhi 18:6a4db94011d3 1070 /** Array initializer of GPIO peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1071 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
sahilmgandhi 18:6a4db94011d3 1072
sahilmgandhi 18:6a4db94011d3 1073 /**
sahilmgandhi 18:6a4db94011d3 1074 * @}
sahilmgandhi 18:6a4db94011d3 1075 */ /* end of group GPIO_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1076
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1079 -- I2C Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1080 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082 /**
sahilmgandhi 18:6a4db94011d3 1083 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1084 * @{
sahilmgandhi 18:6a4db94011d3 1085 */
sahilmgandhi 18:6a4db94011d3 1086
sahilmgandhi 18:6a4db94011d3 1087 /** I2C - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1088 typedef struct {
sahilmgandhi 18:6a4db94011d3 1089 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1090 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 1091 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 1092 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 1093 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1094 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 1095 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 1096 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 1097 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1098 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 1099 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 1100 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 1101 } I2C_Type;
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1104 -- I2C Register Masks
sahilmgandhi 18:6a4db94011d3 1105 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1106
sahilmgandhi 18:6a4db94011d3 1107 /**
sahilmgandhi 18:6a4db94011d3 1108 * @addtogroup I2C_Register_Masks I2C Register Masks
sahilmgandhi 18:6a4db94011d3 1109 * @{
sahilmgandhi 18:6a4db94011d3 1110 */
sahilmgandhi 18:6a4db94011d3 1111
sahilmgandhi 18:6a4db94011d3 1112 /* A1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1113 #define I2C_A1_AD_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 1114 #define I2C_A1_AD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1115 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
sahilmgandhi 18:6a4db94011d3 1116 /* F Bit Fields */
sahilmgandhi 18:6a4db94011d3 1117 #define I2C_F_ICR_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 1118 #define I2C_F_ICR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1119 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
sahilmgandhi 18:6a4db94011d3 1120 #define I2C_F_MULT_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1121 #define I2C_F_MULT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1122 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
sahilmgandhi 18:6a4db94011d3 1123 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1124 #define I2C_C1_DMAEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1125 #define I2C_C1_DMAEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1126 #define I2C_C1_WUEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1127 #define I2C_C1_WUEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1128 #define I2C_C1_RSTA_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1129 #define I2C_C1_RSTA_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1130 #define I2C_C1_TXAK_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1131 #define I2C_C1_TXAK_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1132 #define I2C_C1_TX_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1133 #define I2C_C1_TX_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1134 #define I2C_C1_MST_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1135 #define I2C_C1_MST_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1136 #define I2C_C1_IICIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1137 #define I2C_C1_IICIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1138 #define I2C_C1_IICEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1139 #define I2C_C1_IICEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1140 /* S Bit Fields */
sahilmgandhi 18:6a4db94011d3 1141 #define I2C_S_RXAK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1142 #define I2C_S_RXAK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1143 #define I2C_S_IICIF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1144 #define I2C_S_IICIF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1145 #define I2C_S_SRW_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1146 #define I2C_S_SRW_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1147 #define I2C_S_RAM_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1148 #define I2C_S_RAM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1149 #define I2C_S_ARBL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1150 #define I2C_S_ARBL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1151 #define I2C_S_BUSY_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1152 #define I2C_S_BUSY_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1153 #define I2C_S_IAAS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1154 #define I2C_S_IAAS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1155 #define I2C_S_TCF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1156 #define I2C_S_TCF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1157 /* D Bit Fields */
sahilmgandhi 18:6a4db94011d3 1158 #define I2C_D_DATA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1159 #define I2C_D_DATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1160 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
sahilmgandhi 18:6a4db94011d3 1161 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1162 #define I2C_C2_AD_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 1163 #define I2C_C2_AD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1164 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
sahilmgandhi 18:6a4db94011d3 1165 #define I2C_C2_RMEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1166 #define I2C_C2_RMEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1167 #define I2C_C2_SBRC_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1168 #define I2C_C2_SBRC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1169 #define I2C_C2_HDRS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1170 #define I2C_C2_HDRS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1171 #define I2C_C2_ADEXT_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1172 #define I2C_C2_ADEXT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1173 #define I2C_C2_GCAEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1174 #define I2C_C2_GCAEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1175 /* FLT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1176 #define I2C_FLT_FLT_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 1177 #define I2C_FLT_FLT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1178 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
sahilmgandhi 18:6a4db94011d3 1179 #define I2C_FLT_STOPIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1180 #define I2C_FLT_STOPIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1181 #define I2C_FLT_STOPF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1182 #define I2C_FLT_STOPF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1183 #define I2C_FLT_SHEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1184 #define I2C_FLT_SHEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1185 /* RA Bit Fields */
sahilmgandhi 18:6a4db94011d3 1186 #define I2C_RA_RAD_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 1187 #define I2C_RA_RAD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1188 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
sahilmgandhi 18:6a4db94011d3 1189 /* SMB Bit Fields */
sahilmgandhi 18:6a4db94011d3 1190 #define I2C_SMB_SHTF2IE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1191 #define I2C_SMB_SHTF2IE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1192 #define I2C_SMB_SHTF2_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1193 #define I2C_SMB_SHTF2_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1194 #define I2C_SMB_SHTF1_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1195 #define I2C_SMB_SHTF1_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1196 #define I2C_SMB_SLTF_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1197 #define I2C_SMB_SLTF_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1198 #define I2C_SMB_TCKSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1199 #define I2C_SMB_TCKSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1200 #define I2C_SMB_SIICAEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1201 #define I2C_SMB_SIICAEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1202 #define I2C_SMB_ALERTEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1203 #define I2C_SMB_ALERTEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1204 #define I2C_SMB_FACK_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1205 #define I2C_SMB_FACK_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1206 /* A2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1207 #define I2C_A2_SAD_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 1208 #define I2C_A2_SAD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1209 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
sahilmgandhi 18:6a4db94011d3 1210 /* SLTH Bit Fields */
sahilmgandhi 18:6a4db94011d3 1211 #define I2C_SLTH_SSLT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1212 #define I2C_SLTH_SSLT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1213 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
sahilmgandhi 18:6a4db94011d3 1214 /* SLTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 1215 #define I2C_SLTL_SSLT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1216 #define I2C_SLTL_SSLT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1217 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
sahilmgandhi 18:6a4db94011d3 1218
sahilmgandhi 18:6a4db94011d3 1219 /**
sahilmgandhi 18:6a4db94011d3 1220 * @}
sahilmgandhi 18:6a4db94011d3 1221 */ /* end of group I2C_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1222
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 /* I2C - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1225 /** Peripheral I2C0 base address */
sahilmgandhi 18:6a4db94011d3 1226 #define I2C0_BASE (0x40066000u)
sahilmgandhi 18:6a4db94011d3 1227 /** Peripheral I2C0 base pointer */
sahilmgandhi 18:6a4db94011d3 1228 #define I2C0 ((I2C_Type *)I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 1229 /** Peripheral I2C1 base address */
sahilmgandhi 18:6a4db94011d3 1230 #define I2C1_BASE (0x40067000u)
sahilmgandhi 18:6a4db94011d3 1231 /** Peripheral I2C1 base pointer */
sahilmgandhi 18:6a4db94011d3 1232 #define I2C1 ((I2C_Type *)I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 1233 /** Array initializer of I2C peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1234 #define I2C_BASES { I2C0, I2C1 }
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236 /**
sahilmgandhi 18:6a4db94011d3 1237 * @}
sahilmgandhi 18:6a4db94011d3 1238 */ /* end of group I2C_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1239
sahilmgandhi 18:6a4db94011d3 1240
sahilmgandhi 18:6a4db94011d3 1241 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1242 -- I2S Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1243 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1244
sahilmgandhi 18:6a4db94011d3 1245 /**
sahilmgandhi 18:6a4db94011d3 1246 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1247 * @{
sahilmgandhi 18:6a4db94011d3 1248 */
sahilmgandhi 18:6a4db94011d3 1249
sahilmgandhi 18:6a4db94011d3 1250 /** I2S - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1251 typedef struct {
sahilmgandhi 18:6a4db94011d3 1252 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1253 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 1254 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1255 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 1256 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 1257 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 1258 uint8_t RESERVED_1[8];
sahilmgandhi 18:6a4db94011d3 1259 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 1260 uint8_t RESERVED_2[60];
sahilmgandhi 18:6a4db94011d3 1261 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 1262 uint8_t RESERVED_3[28];
sahilmgandhi 18:6a4db94011d3 1263 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 1264 uint8_t RESERVED_4[4];
sahilmgandhi 18:6a4db94011d3 1265 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 1266 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 1267 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 1268 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 1269 uint8_t RESERVED_5[8];
sahilmgandhi 18:6a4db94011d3 1270 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 1271 uint8_t RESERVED_6[60];
sahilmgandhi 18:6a4db94011d3 1272 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
sahilmgandhi 18:6a4db94011d3 1273 uint8_t RESERVED_7[28];
sahilmgandhi 18:6a4db94011d3 1274 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
sahilmgandhi 18:6a4db94011d3 1275 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
sahilmgandhi 18:6a4db94011d3 1276 } I2S_Type;
sahilmgandhi 18:6a4db94011d3 1277
sahilmgandhi 18:6a4db94011d3 1278 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1279 -- I2S Register Masks
sahilmgandhi 18:6a4db94011d3 1280 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1281
sahilmgandhi 18:6a4db94011d3 1282 /**
sahilmgandhi 18:6a4db94011d3 1283 * @addtogroup I2S_Register_Masks I2S Register Masks
sahilmgandhi 18:6a4db94011d3 1284 * @{
sahilmgandhi 18:6a4db94011d3 1285 */
sahilmgandhi 18:6a4db94011d3 1286
sahilmgandhi 18:6a4db94011d3 1287 /* TCSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1288 #define I2S_TCSR_FWDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1289 #define I2S_TCSR_FWDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1290 #define I2S_TCSR_FWIE_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 1291 #define I2S_TCSR_FWIE_SHIFT 9
sahilmgandhi 18:6a4db94011d3 1292 #define I2S_TCSR_FEIE_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 1293 #define I2S_TCSR_FEIE_SHIFT 10
sahilmgandhi 18:6a4db94011d3 1294 #define I2S_TCSR_SEIE_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 1295 #define I2S_TCSR_SEIE_SHIFT 11
sahilmgandhi 18:6a4db94011d3 1296 #define I2S_TCSR_WSIE_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 1297 #define I2S_TCSR_WSIE_SHIFT 12
sahilmgandhi 18:6a4db94011d3 1298 #define I2S_TCSR_FWF_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 1299 #define I2S_TCSR_FWF_SHIFT 17
sahilmgandhi 18:6a4db94011d3 1300 #define I2S_TCSR_FEF_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 1301 #define I2S_TCSR_FEF_SHIFT 18
sahilmgandhi 18:6a4db94011d3 1302 #define I2S_TCSR_SEF_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 1303 #define I2S_TCSR_SEF_SHIFT 19
sahilmgandhi 18:6a4db94011d3 1304 #define I2S_TCSR_WSF_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 1305 #define I2S_TCSR_WSF_SHIFT 20
sahilmgandhi 18:6a4db94011d3 1306 #define I2S_TCSR_SR_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 1307 #define I2S_TCSR_SR_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1308 #define I2S_TCSR_FR_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 1309 #define I2S_TCSR_FR_SHIFT 25
sahilmgandhi 18:6a4db94011d3 1310 #define I2S_TCSR_BCE_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 1311 #define I2S_TCSR_BCE_SHIFT 28
sahilmgandhi 18:6a4db94011d3 1312 #define I2S_TCSR_DBGE_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 1313 #define I2S_TCSR_DBGE_SHIFT 29
sahilmgandhi 18:6a4db94011d3 1314 #define I2S_TCSR_STOPE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 1315 #define I2S_TCSR_STOPE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 1316 #define I2S_TCSR_TE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 1317 #define I2S_TCSR_TE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 1318 /* TCR2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1319 #define I2S_TCR2_DIV_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1320 #define I2S_TCR2_DIV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1321 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
sahilmgandhi 18:6a4db94011d3 1322 #define I2S_TCR2_BCD_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 1323 #define I2S_TCR2_BCD_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1324 #define I2S_TCR2_BCP_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 1325 #define I2S_TCR2_BCP_SHIFT 25
sahilmgandhi 18:6a4db94011d3 1326 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
sahilmgandhi 18:6a4db94011d3 1327 #define I2S_TCR2_CLKMODE_SHIFT 26
sahilmgandhi 18:6a4db94011d3 1328 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
sahilmgandhi 18:6a4db94011d3 1329 /* TCR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1330 #define I2S_TCR3_WDFL_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1331 #define I2S_TCR3_WDFL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1332 #define I2S_TCR3_TCE_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1333 #define I2S_TCR3_TCE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1334 /* TCR4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1335 #define I2S_TCR4_FSD_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1336 #define I2S_TCR4_FSD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1337 #define I2S_TCR4_FSP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1338 #define I2S_TCR4_FSP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1339 #define I2S_TCR4_FSE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1340 #define I2S_TCR4_FSE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1341 #define I2S_TCR4_MF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1342 #define I2S_TCR4_MF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1343 #define I2S_TCR4_SYWD_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 1344 #define I2S_TCR4_SYWD_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1345 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
sahilmgandhi 18:6a4db94011d3 1346 #define I2S_TCR4_FRSZ_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1347 #define I2S_TCR4_FRSZ_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1348 /* TCR5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1349 #define I2S_TCR5_FBT_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 1350 #define I2S_TCR5_FBT_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1351 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
sahilmgandhi 18:6a4db94011d3 1352 #define I2S_TCR5_W0W_MASK 0x1F0000u
sahilmgandhi 18:6a4db94011d3 1353 #define I2S_TCR5_W0W_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1354 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
sahilmgandhi 18:6a4db94011d3 1355 #define I2S_TCR5_WNW_MASK 0x1F000000u
sahilmgandhi 18:6a4db94011d3 1356 #define I2S_TCR5_WNW_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1357 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
sahilmgandhi 18:6a4db94011d3 1358 /* TDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1359 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1360 #define I2S_TDR_TDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1361 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
sahilmgandhi 18:6a4db94011d3 1362 /* TMR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1363 #define I2S_TMR_TWM_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1364 #define I2S_TMR_TWM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1365 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
sahilmgandhi 18:6a4db94011d3 1366 /* RCSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1367 #define I2S_RCSR_FWDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1368 #define I2S_RCSR_FWDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1369 #define I2S_RCSR_FWIE_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 1370 #define I2S_RCSR_FWIE_SHIFT 9
sahilmgandhi 18:6a4db94011d3 1371 #define I2S_RCSR_FEIE_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 1372 #define I2S_RCSR_FEIE_SHIFT 10
sahilmgandhi 18:6a4db94011d3 1373 #define I2S_RCSR_SEIE_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 1374 #define I2S_RCSR_SEIE_SHIFT 11
sahilmgandhi 18:6a4db94011d3 1375 #define I2S_RCSR_WSIE_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 1376 #define I2S_RCSR_WSIE_SHIFT 12
sahilmgandhi 18:6a4db94011d3 1377 #define I2S_RCSR_FWF_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 1378 #define I2S_RCSR_FWF_SHIFT 17
sahilmgandhi 18:6a4db94011d3 1379 #define I2S_RCSR_FEF_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 1380 #define I2S_RCSR_FEF_SHIFT 18
sahilmgandhi 18:6a4db94011d3 1381 #define I2S_RCSR_SEF_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 1382 #define I2S_RCSR_SEF_SHIFT 19
sahilmgandhi 18:6a4db94011d3 1383 #define I2S_RCSR_WSF_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 1384 #define I2S_RCSR_WSF_SHIFT 20
sahilmgandhi 18:6a4db94011d3 1385 #define I2S_RCSR_SR_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 1386 #define I2S_RCSR_SR_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1387 #define I2S_RCSR_FR_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 1388 #define I2S_RCSR_FR_SHIFT 25
sahilmgandhi 18:6a4db94011d3 1389 #define I2S_RCSR_BCE_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 1390 #define I2S_RCSR_BCE_SHIFT 28
sahilmgandhi 18:6a4db94011d3 1391 #define I2S_RCSR_DBGE_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 1392 #define I2S_RCSR_DBGE_SHIFT 29
sahilmgandhi 18:6a4db94011d3 1393 #define I2S_RCSR_STOPE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 1394 #define I2S_RCSR_STOPE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 1395 #define I2S_RCSR_RE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 1396 #define I2S_RCSR_RE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 1397 /* RCR2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1398 #define I2S_RCR2_DIV_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1399 #define I2S_RCR2_DIV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1400 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
sahilmgandhi 18:6a4db94011d3 1401 #define I2S_RCR2_BCD_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 1402 #define I2S_RCR2_BCD_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1403 #define I2S_RCR2_BCP_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 1404 #define I2S_RCR2_BCP_SHIFT 25
sahilmgandhi 18:6a4db94011d3 1405 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
sahilmgandhi 18:6a4db94011d3 1406 #define I2S_RCR2_CLKMODE_SHIFT 26
sahilmgandhi 18:6a4db94011d3 1407 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
sahilmgandhi 18:6a4db94011d3 1408 /* RCR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1409 #define I2S_RCR3_WDFL_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1410 #define I2S_RCR3_WDFL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1411 #define I2S_RCR3_RCE_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1412 #define I2S_RCR3_RCE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1413 /* RCR4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1414 #define I2S_RCR4_FSD_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1415 #define I2S_RCR4_FSD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1416 #define I2S_RCR4_FSP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1417 #define I2S_RCR4_FSP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1418 #define I2S_RCR4_FSE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1419 #define I2S_RCR4_FSE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1420 #define I2S_RCR4_MF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1421 #define I2S_RCR4_MF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1422 #define I2S_RCR4_SYWD_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 1423 #define I2S_RCR4_SYWD_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1424 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
sahilmgandhi 18:6a4db94011d3 1425 #define I2S_RCR4_FRSZ_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1426 #define I2S_RCR4_FRSZ_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1427 /* RCR5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1428 #define I2S_RCR5_FBT_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 1429 #define I2S_RCR5_FBT_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1430 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
sahilmgandhi 18:6a4db94011d3 1431 #define I2S_RCR5_W0W_MASK 0x1F0000u
sahilmgandhi 18:6a4db94011d3 1432 #define I2S_RCR5_W0W_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1433 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
sahilmgandhi 18:6a4db94011d3 1434 #define I2S_RCR5_WNW_MASK 0x1F000000u
sahilmgandhi 18:6a4db94011d3 1435 #define I2S_RCR5_WNW_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1436 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
sahilmgandhi 18:6a4db94011d3 1437 /* RDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1438 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1439 #define I2S_RDR_RDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1440 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
sahilmgandhi 18:6a4db94011d3 1441 /* RMR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1442 #define I2S_RMR_RWM_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1443 #define I2S_RMR_RWM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1444 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
sahilmgandhi 18:6a4db94011d3 1445 /* MCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1446 #define I2S_MCR_MICS_MASK 0x3000000u
sahilmgandhi 18:6a4db94011d3 1447 #define I2S_MCR_MICS_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1448 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
sahilmgandhi 18:6a4db94011d3 1449 #define I2S_MCR_MOE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 1450 #define I2S_MCR_MOE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 1451 #define I2S_MCR_DUF_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 1452 #define I2S_MCR_DUF_SHIFT 31
sahilmgandhi 18:6a4db94011d3 1453 /* MDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1454 #define I2S_MDR_DIVIDE_MASK 0xFFFu
sahilmgandhi 18:6a4db94011d3 1455 #define I2S_MDR_DIVIDE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1456 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
sahilmgandhi 18:6a4db94011d3 1457 #define I2S_MDR_FRACT_MASK 0xFF000u
sahilmgandhi 18:6a4db94011d3 1458 #define I2S_MDR_FRACT_SHIFT 12
sahilmgandhi 18:6a4db94011d3 1459 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
sahilmgandhi 18:6a4db94011d3 1460
sahilmgandhi 18:6a4db94011d3 1461 /**
sahilmgandhi 18:6a4db94011d3 1462 * @}
sahilmgandhi 18:6a4db94011d3 1463 */ /* end of group I2S_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1464
sahilmgandhi 18:6a4db94011d3 1465
sahilmgandhi 18:6a4db94011d3 1466 /* I2S - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1467 /** Peripheral I2S0 base address */
sahilmgandhi 18:6a4db94011d3 1468 #define I2S0_BASE (0x4002F000u)
sahilmgandhi 18:6a4db94011d3 1469 /** Peripheral I2S0 base pointer */
sahilmgandhi 18:6a4db94011d3 1470 #define I2S0 ((I2S_Type *)I2S0_BASE)
sahilmgandhi 18:6a4db94011d3 1471 /** Array initializer of I2S peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1472 #define I2S_BASES { I2S0 }
sahilmgandhi 18:6a4db94011d3 1473
sahilmgandhi 18:6a4db94011d3 1474 /**
sahilmgandhi 18:6a4db94011d3 1475 * @}
sahilmgandhi 18:6a4db94011d3 1476 */ /* end of group I2S_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1477
sahilmgandhi 18:6a4db94011d3 1478
sahilmgandhi 18:6a4db94011d3 1479 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1480 -- LLWU Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1481 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1482
sahilmgandhi 18:6a4db94011d3 1483 /**
sahilmgandhi 18:6a4db94011d3 1484 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1485 * @{
sahilmgandhi 18:6a4db94011d3 1486 */
sahilmgandhi 18:6a4db94011d3 1487
sahilmgandhi 18:6a4db94011d3 1488 /** LLWU - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1489 typedef struct {
sahilmgandhi 18:6a4db94011d3 1490 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1491 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 1492 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 1493 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 1494 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1495 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 1496 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 1497 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 1498 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1499 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 1500 } LLWU_Type;
sahilmgandhi 18:6a4db94011d3 1501
sahilmgandhi 18:6a4db94011d3 1502 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1503 -- LLWU Register Masks
sahilmgandhi 18:6a4db94011d3 1504 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1505
sahilmgandhi 18:6a4db94011d3 1506 /**
sahilmgandhi 18:6a4db94011d3 1507 * @addtogroup LLWU_Register_Masks LLWU Register Masks
sahilmgandhi 18:6a4db94011d3 1508 * @{
sahilmgandhi 18:6a4db94011d3 1509 */
sahilmgandhi 18:6a4db94011d3 1510
sahilmgandhi 18:6a4db94011d3 1511 /* PE1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1512 #define LLWU_PE1_WUPE0_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1513 #define LLWU_PE1_WUPE0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1514 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
sahilmgandhi 18:6a4db94011d3 1515 #define LLWU_PE1_WUPE1_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1516 #define LLWU_PE1_WUPE1_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1517 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
sahilmgandhi 18:6a4db94011d3 1518 #define LLWU_PE1_WUPE2_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1519 #define LLWU_PE1_WUPE2_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1520 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
sahilmgandhi 18:6a4db94011d3 1521 #define LLWU_PE1_WUPE3_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1522 #define LLWU_PE1_WUPE3_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1523 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
sahilmgandhi 18:6a4db94011d3 1524 /* PE2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1525 #define LLWU_PE2_WUPE4_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1526 #define LLWU_PE2_WUPE4_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1527 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
sahilmgandhi 18:6a4db94011d3 1528 #define LLWU_PE2_WUPE5_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1529 #define LLWU_PE2_WUPE5_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1530 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
sahilmgandhi 18:6a4db94011d3 1531 #define LLWU_PE2_WUPE6_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1532 #define LLWU_PE2_WUPE6_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1533 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
sahilmgandhi 18:6a4db94011d3 1534 #define LLWU_PE2_WUPE7_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1535 #define LLWU_PE2_WUPE7_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1536 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
sahilmgandhi 18:6a4db94011d3 1537 /* PE3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1538 #define LLWU_PE3_WUPE8_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1539 #define LLWU_PE3_WUPE8_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1540 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
sahilmgandhi 18:6a4db94011d3 1541 #define LLWU_PE3_WUPE9_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1542 #define LLWU_PE3_WUPE9_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1543 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
sahilmgandhi 18:6a4db94011d3 1544 #define LLWU_PE3_WUPE10_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1545 #define LLWU_PE3_WUPE10_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1546 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
sahilmgandhi 18:6a4db94011d3 1547 #define LLWU_PE3_WUPE11_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1548 #define LLWU_PE3_WUPE11_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1549 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
sahilmgandhi 18:6a4db94011d3 1550 /* PE4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1551 #define LLWU_PE4_WUPE12_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1552 #define LLWU_PE4_WUPE12_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1553 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
sahilmgandhi 18:6a4db94011d3 1554 #define LLWU_PE4_WUPE13_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1555 #define LLWU_PE4_WUPE13_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1556 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
sahilmgandhi 18:6a4db94011d3 1557 #define LLWU_PE4_WUPE14_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1558 #define LLWU_PE4_WUPE14_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1559 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
sahilmgandhi 18:6a4db94011d3 1560 #define LLWU_PE4_WUPE15_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1561 #define LLWU_PE4_WUPE15_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1562 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
sahilmgandhi 18:6a4db94011d3 1563 /* ME Bit Fields */
sahilmgandhi 18:6a4db94011d3 1564 #define LLWU_ME_WUME0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1565 #define LLWU_ME_WUME0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1566 #define LLWU_ME_WUME1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1567 #define LLWU_ME_WUME1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1568 #define LLWU_ME_WUME2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1569 #define LLWU_ME_WUME2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1570 #define LLWU_ME_WUME3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1571 #define LLWU_ME_WUME3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1572 #define LLWU_ME_WUME4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1573 #define LLWU_ME_WUME4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1574 #define LLWU_ME_WUME5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1575 #define LLWU_ME_WUME5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1576 #define LLWU_ME_WUME6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1577 #define LLWU_ME_WUME6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1578 #define LLWU_ME_WUME7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1579 #define LLWU_ME_WUME7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1580 /* F1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1581 #define LLWU_F1_WUF0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1582 #define LLWU_F1_WUF0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1583 #define LLWU_F1_WUF1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1584 #define LLWU_F1_WUF1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1585 #define LLWU_F1_WUF2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1586 #define LLWU_F1_WUF2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1587 #define LLWU_F1_WUF3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1588 #define LLWU_F1_WUF3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1589 #define LLWU_F1_WUF4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1590 #define LLWU_F1_WUF4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1591 #define LLWU_F1_WUF5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1592 #define LLWU_F1_WUF5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1593 #define LLWU_F1_WUF6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1594 #define LLWU_F1_WUF6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1595 #define LLWU_F1_WUF7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1596 #define LLWU_F1_WUF7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1597 /* F2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1598 #define LLWU_F2_WUF8_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1599 #define LLWU_F2_WUF8_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1600 #define LLWU_F2_WUF9_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1601 #define LLWU_F2_WUF9_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1602 #define LLWU_F2_WUF10_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1603 #define LLWU_F2_WUF10_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1604 #define LLWU_F2_WUF11_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1605 #define LLWU_F2_WUF11_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1606 #define LLWU_F2_WUF12_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1607 #define LLWU_F2_WUF12_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1608 #define LLWU_F2_WUF13_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1609 #define LLWU_F2_WUF13_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1610 #define LLWU_F2_WUF14_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1611 #define LLWU_F2_WUF14_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1612 #define LLWU_F2_WUF15_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1613 #define LLWU_F2_WUF15_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1614 /* F3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1615 #define LLWU_F3_MWUF0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1616 #define LLWU_F3_MWUF0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1617 #define LLWU_F3_MWUF1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1618 #define LLWU_F3_MWUF1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1619 #define LLWU_F3_MWUF2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1620 #define LLWU_F3_MWUF2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1621 #define LLWU_F3_MWUF3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1622 #define LLWU_F3_MWUF3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1623 #define LLWU_F3_MWUF4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1624 #define LLWU_F3_MWUF4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1625 #define LLWU_F3_MWUF5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1626 #define LLWU_F3_MWUF5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1627 #define LLWU_F3_MWUF6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1628 #define LLWU_F3_MWUF6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1629 #define LLWU_F3_MWUF7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1630 #define LLWU_F3_MWUF7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1631 /* FILT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1632 #define LLWU_FILT1_FILTSEL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1633 #define LLWU_FILT1_FILTSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1634 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 1635 #define LLWU_FILT1_FILTE_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 1636 #define LLWU_FILT1_FILTE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1637 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
sahilmgandhi 18:6a4db94011d3 1638 #define LLWU_FILT1_FILTF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1639 #define LLWU_FILT1_FILTF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1640 /* FILT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1641 #define LLWU_FILT2_FILTSEL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1642 #define LLWU_FILT2_FILTSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1643 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 1644 #define LLWU_FILT2_FILTE_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 1645 #define LLWU_FILT2_FILTE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1646 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
sahilmgandhi 18:6a4db94011d3 1647 #define LLWU_FILT2_FILTF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1648 #define LLWU_FILT2_FILTF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1649
sahilmgandhi 18:6a4db94011d3 1650 /**
sahilmgandhi 18:6a4db94011d3 1651 * @}
sahilmgandhi 18:6a4db94011d3 1652 */ /* end of group LLWU_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1653
sahilmgandhi 18:6a4db94011d3 1654
sahilmgandhi 18:6a4db94011d3 1655 /* LLWU - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1656 /** Peripheral LLWU base address */
sahilmgandhi 18:6a4db94011d3 1657 #define LLWU_BASE (0x4007C000u)
sahilmgandhi 18:6a4db94011d3 1658 /** Peripheral LLWU base pointer */
sahilmgandhi 18:6a4db94011d3 1659 #define LLWU ((LLWU_Type *)LLWU_BASE)
sahilmgandhi 18:6a4db94011d3 1660 /** Array initializer of LLWU peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1661 #define LLWU_BASES { LLWU }
sahilmgandhi 18:6a4db94011d3 1662
sahilmgandhi 18:6a4db94011d3 1663 /**
sahilmgandhi 18:6a4db94011d3 1664 * @}
sahilmgandhi 18:6a4db94011d3 1665 */ /* end of group LLWU_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1666
sahilmgandhi 18:6a4db94011d3 1667
sahilmgandhi 18:6a4db94011d3 1668 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1669 -- LPTMR Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1670 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1671
sahilmgandhi 18:6a4db94011d3 1672 /**
sahilmgandhi 18:6a4db94011d3 1673 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1674 * @{
sahilmgandhi 18:6a4db94011d3 1675 */
sahilmgandhi 18:6a4db94011d3 1676
sahilmgandhi 18:6a4db94011d3 1677 /** LPTMR - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1678 typedef struct {
sahilmgandhi 18:6a4db94011d3 1679 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1680 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1681 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1682 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 1683 } LPTMR_Type;
sahilmgandhi 18:6a4db94011d3 1684
sahilmgandhi 18:6a4db94011d3 1685 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1686 -- LPTMR Register Masks
sahilmgandhi 18:6a4db94011d3 1687 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1688
sahilmgandhi 18:6a4db94011d3 1689 /**
sahilmgandhi 18:6a4db94011d3 1690 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
sahilmgandhi 18:6a4db94011d3 1691 * @{
sahilmgandhi 18:6a4db94011d3 1692 */
sahilmgandhi 18:6a4db94011d3 1693
sahilmgandhi 18:6a4db94011d3 1694 /* CSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1695 #define LPTMR_CSR_TEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1696 #define LPTMR_CSR_TEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1697 #define LPTMR_CSR_TMS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1698 #define LPTMR_CSR_TMS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1699 #define LPTMR_CSR_TFC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1700 #define LPTMR_CSR_TFC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1701 #define LPTMR_CSR_TPP_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1702 #define LPTMR_CSR_TPP_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1703 #define LPTMR_CSR_TPS_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1704 #define LPTMR_CSR_TPS_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1705 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
sahilmgandhi 18:6a4db94011d3 1706 #define LPTMR_CSR_TIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1707 #define LPTMR_CSR_TIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1708 #define LPTMR_CSR_TCF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1709 #define LPTMR_CSR_TCF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1710 /* PSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1711 #define LPTMR_PSR_PCS_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1712 #define LPTMR_PSR_PCS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1713 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
sahilmgandhi 18:6a4db94011d3 1714 #define LPTMR_PSR_PBYP_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1715 #define LPTMR_PSR_PBYP_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1716 #define LPTMR_PSR_PRESCALE_MASK 0x78u
sahilmgandhi 18:6a4db94011d3 1717 #define LPTMR_PSR_PRESCALE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1718 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
sahilmgandhi 18:6a4db94011d3 1719 /* CMR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1720 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1721 #define LPTMR_CMR_COMPARE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1722 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
sahilmgandhi 18:6a4db94011d3 1723 /* CNR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1724 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1725 #define LPTMR_CNR_COUNTER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1726 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
sahilmgandhi 18:6a4db94011d3 1727
sahilmgandhi 18:6a4db94011d3 1728 /**
sahilmgandhi 18:6a4db94011d3 1729 * @}
sahilmgandhi 18:6a4db94011d3 1730 */ /* end of group LPTMR_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1731
sahilmgandhi 18:6a4db94011d3 1732
sahilmgandhi 18:6a4db94011d3 1733 /* LPTMR - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1734 /** Peripheral LPTMR0 base address */
sahilmgandhi 18:6a4db94011d3 1735 #define LPTMR0_BASE (0x40040000u)
sahilmgandhi 18:6a4db94011d3 1736 /** Peripheral LPTMR0 base pointer */
sahilmgandhi 18:6a4db94011d3 1737 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
sahilmgandhi 18:6a4db94011d3 1738 /** Array initializer of LPTMR peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1739 #define LPTMR_BASES { LPTMR0 }
sahilmgandhi 18:6a4db94011d3 1740
sahilmgandhi 18:6a4db94011d3 1741 /**
sahilmgandhi 18:6a4db94011d3 1742 * @}
sahilmgandhi 18:6a4db94011d3 1743 */ /* end of group LPTMR_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1744
sahilmgandhi 18:6a4db94011d3 1745
sahilmgandhi 18:6a4db94011d3 1746 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1747 -- MCG Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1748 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1749
sahilmgandhi 18:6a4db94011d3 1750 /**
sahilmgandhi 18:6a4db94011d3 1751 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1752 * @{
sahilmgandhi 18:6a4db94011d3 1753 */
sahilmgandhi 18:6a4db94011d3 1754
sahilmgandhi 18:6a4db94011d3 1755 /** MCG - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1756 typedef struct {
sahilmgandhi 18:6a4db94011d3 1757 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1758 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 1759 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 1760 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 1761 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1762 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 1763 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 1764 uint8_t RESERVED_0[1];
sahilmgandhi 18:6a4db94011d3 1765 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1766 uint8_t RESERVED_1[1];
sahilmgandhi 18:6a4db94011d3 1767 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 1768 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 1769 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 1770 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 1771 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
sahilmgandhi 18:6a4db94011d3 1772 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
sahilmgandhi 18:6a4db94011d3 1773 } MCG_Type;
sahilmgandhi 18:6a4db94011d3 1774
sahilmgandhi 18:6a4db94011d3 1775 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1776 -- MCG Register Masks
sahilmgandhi 18:6a4db94011d3 1777 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1778
sahilmgandhi 18:6a4db94011d3 1779 /**
sahilmgandhi 18:6a4db94011d3 1780 * @addtogroup MCG_Register_Masks MCG Register Masks
sahilmgandhi 18:6a4db94011d3 1781 * @{
sahilmgandhi 18:6a4db94011d3 1782 */
sahilmgandhi 18:6a4db94011d3 1783
sahilmgandhi 18:6a4db94011d3 1784 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1785 #define MCG_C1_IREFSTEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1786 #define MCG_C1_IREFSTEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1787 #define MCG_C1_IRCLKEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1788 #define MCG_C1_IRCLKEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1789 #define MCG_C1_IREFS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1790 #define MCG_C1_IREFS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1791 #define MCG_C1_FRDIV_MASK 0x38u
sahilmgandhi 18:6a4db94011d3 1792 #define MCG_C1_FRDIV_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1793 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
sahilmgandhi 18:6a4db94011d3 1794 #define MCG_C1_CLKS_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1795 #define MCG_C1_CLKS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1796 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
sahilmgandhi 18:6a4db94011d3 1797 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1798 #define MCG_C2_IRCS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1799 #define MCG_C2_IRCS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1800 #define MCG_C2_LP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1801 #define MCG_C2_LP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1802 #define MCG_C2_EREFS0_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1803 #define MCG_C2_EREFS0_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1804 #define MCG_C2_HGO0_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1805 #define MCG_C2_HGO0_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1806 #define MCG_C2_RANGE0_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1807 #define MCG_C2_RANGE0_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1808 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
sahilmgandhi 18:6a4db94011d3 1809 #define MCG_C2_FCFTRIM_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1810 #define MCG_C2_FCFTRIM_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1811 #define MCG_C2_LOCRE0_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1812 #define MCG_C2_LOCRE0_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1813 /* C3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1814 #define MCG_C3_SCTRIM_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1815 #define MCG_C3_SCTRIM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1816 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
sahilmgandhi 18:6a4db94011d3 1817 /* C4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1818 #define MCG_C4_SCFTRIM_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1819 #define MCG_C4_SCFTRIM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1820 #define MCG_C4_FCTRIM_MASK 0x1Eu
sahilmgandhi 18:6a4db94011d3 1821 #define MCG_C4_FCTRIM_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1822 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
sahilmgandhi 18:6a4db94011d3 1823 #define MCG_C4_DRST_DRS_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 1824 #define MCG_C4_DRST_DRS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1825 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
sahilmgandhi 18:6a4db94011d3 1826 #define MCG_C4_DMX32_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1827 #define MCG_C4_DMX32_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1828 /* C5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1829 #define MCG_C5_PRDIV0_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 1830 #define MCG_C5_PRDIV0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1831 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
sahilmgandhi 18:6a4db94011d3 1832 #define MCG_C5_PLLSTEN0_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1833 #define MCG_C5_PLLSTEN0_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1834 #define MCG_C5_PLLCLKEN0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1835 #define MCG_C5_PLLCLKEN0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1836 /* C6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1837 #define MCG_C6_VDIV0_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 1838 #define MCG_C6_VDIV0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1839 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
sahilmgandhi 18:6a4db94011d3 1840 #define MCG_C6_CME0_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1841 #define MCG_C6_CME0_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1842 #define MCG_C6_PLLS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1843 #define MCG_C6_PLLS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1844 #define MCG_C6_LOLIE0_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1845 #define MCG_C6_LOLIE0_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1846 /* S Bit Fields */
sahilmgandhi 18:6a4db94011d3 1847 #define MCG_S_IRCST_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1848 #define MCG_S_IRCST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1849 #define MCG_S_OSCINIT0_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1850 #define MCG_S_OSCINIT0_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1851 #define MCG_S_CLKST_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1852 #define MCG_S_CLKST_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1853 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
sahilmgandhi 18:6a4db94011d3 1854 #define MCG_S_IREFST_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1855 #define MCG_S_IREFST_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1856 #define MCG_S_PLLST_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1857 #define MCG_S_PLLST_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1858 #define MCG_S_LOCK0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1859 #define MCG_S_LOCK0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1860 #define MCG_S_LOLS_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1861 #define MCG_S_LOLS_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1862 /* SC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1863 #define MCG_SC_LOCS0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1864 #define MCG_SC_LOCS0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1865 #define MCG_SC_FCRDIV_MASK 0xEu
sahilmgandhi 18:6a4db94011d3 1866 #define MCG_SC_FCRDIV_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1867 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
sahilmgandhi 18:6a4db94011d3 1868 #define MCG_SC_FLTPRSRV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1869 #define MCG_SC_FLTPRSRV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1870 #define MCG_SC_ATMF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1871 #define MCG_SC_ATMF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1872 #define MCG_SC_ATMS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1873 #define MCG_SC_ATMS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1874 #define MCG_SC_ATME_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1875 #define MCG_SC_ATME_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1876 /* ATCVH Bit Fields */
sahilmgandhi 18:6a4db94011d3 1877 #define MCG_ATCVH_ATCVH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1878 #define MCG_ATCVH_ATCVH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1879 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
sahilmgandhi 18:6a4db94011d3 1880 /* ATCVL Bit Fields */
sahilmgandhi 18:6a4db94011d3 1881 #define MCG_ATCVL_ATCVL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1882 #define MCG_ATCVL_ATCVL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1883 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
sahilmgandhi 18:6a4db94011d3 1884 /* C8 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1885 #define MCG_C8_LOLRE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1886 #define MCG_C8_LOLRE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1887
sahilmgandhi 18:6a4db94011d3 1888 /**
sahilmgandhi 18:6a4db94011d3 1889 * @}
sahilmgandhi 18:6a4db94011d3 1890 */ /* end of group MCG_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1891
sahilmgandhi 18:6a4db94011d3 1892
sahilmgandhi 18:6a4db94011d3 1893 /* MCG - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1894 /** Peripheral MCG base address */
sahilmgandhi 18:6a4db94011d3 1895 #define MCG_BASE (0x40064000u)
sahilmgandhi 18:6a4db94011d3 1896 /** Peripheral MCG base pointer */
sahilmgandhi 18:6a4db94011d3 1897 #define MCG ((MCG_Type *)MCG_BASE)
sahilmgandhi 18:6a4db94011d3 1898 /** Array initializer of MCG peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1899 #define MCG_BASES { MCG }
sahilmgandhi 18:6a4db94011d3 1900
sahilmgandhi 18:6a4db94011d3 1901 /**
sahilmgandhi 18:6a4db94011d3 1902 * @}
sahilmgandhi 18:6a4db94011d3 1903 */ /* end of group MCG_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1904
sahilmgandhi 18:6a4db94011d3 1905
sahilmgandhi 18:6a4db94011d3 1906 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1907 -- MCM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1908 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1909
sahilmgandhi 18:6a4db94011d3 1910 /**
sahilmgandhi 18:6a4db94011d3 1911 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1912 * @{
sahilmgandhi 18:6a4db94011d3 1913 */
sahilmgandhi 18:6a4db94011d3 1914
sahilmgandhi 18:6a4db94011d3 1915 /** MCM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1916 typedef struct {
sahilmgandhi 18:6a4db94011d3 1917 uint8_t RESERVED_0[8];
sahilmgandhi 18:6a4db94011d3 1918 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1919 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 1920 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 1921 uint8_t RESERVED_1[48];
sahilmgandhi 18:6a4db94011d3 1922 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 1923 } MCM_Type;
sahilmgandhi 18:6a4db94011d3 1924
sahilmgandhi 18:6a4db94011d3 1925 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1926 -- MCM Register Masks
sahilmgandhi 18:6a4db94011d3 1927 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1928
sahilmgandhi 18:6a4db94011d3 1929 /**
sahilmgandhi 18:6a4db94011d3 1930 * @addtogroup MCM_Register_Masks MCM Register Masks
sahilmgandhi 18:6a4db94011d3 1931 * @{
sahilmgandhi 18:6a4db94011d3 1932 */
sahilmgandhi 18:6a4db94011d3 1933
sahilmgandhi 18:6a4db94011d3 1934 /* PLASC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1935 #define MCM_PLASC_ASC_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1936 #define MCM_PLASC_ASC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1937 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
sahilmgandhi 18:6a4db94011d3 1938 /* PLAMC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1939 #define MCM_PLAMC_AMC_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1940 #define MCM_PLAMC_AMC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1941 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
sahilmgandhi 18:6a4db94011d3 1942 /* PLACR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1943 #define MCM_PLACR_ARB_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 1944 #define MCM_PLACR_ARB_SHIFT 9
sahilmgandhi 18:6a4db94011d3 1945 #define MCM_PLACR_CFCC_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 1946 #define MCM_PLACR_CFCC_SHIFT 10
sahilmgandhi 18:6a4db94011d3 1947 #define MCM_PLACR_DFCDA_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 1948 #define MCM_PLACR_DFCDA_SHIFT 11
sahilmgandhi 18:6a4db94011d3 1949 #define MCM_PLACR_DFCIC_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 1950 #define MCM_PLACR_DFCIC_SHIFT 12
sahilmgandhi 18:6a4db94011d3 1951 #define MCM_PLACR_DFCC_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 1952 #define MCM_PLACR_DFCC_SHIFT 13
sahilmgandhi 18:6a4db94011d3 1953 #define MCM_PLACR_EFDS_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 1954 #define MCM_PLACR_EFDS_SHIFT 14
sahilmgandhi 18:6a4db94011d3 1955 #define MCM_PLACR_DFCS_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 1956 #define MCM_PLACR_DFCS_SHIFT 15
sahilmgandhi 18:6a4db94011d3 1957 #define MCM_PLACR_ESFC_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1958 #define MCM_PLACR_ESFC_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1959 /* CPO Bit Fields */
sahilmgandhi 18:6a4db94011d3 1960 #define MCM_CPO_CPOREQ_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1961 #define MCM_CPO_CPOREQ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1962 #define MCM_CPO_CPOACK_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1963 #define MCM_CPO_CPOACK_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1964 #define MCM_CPO_CPOWOI_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1965 #define MCM_CPO_CPOWOI_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1966
sahilmgandhi 18:6a4db94011d3 1967 /**
sahilmgandhi 18:6a4db94011d3 1968 * @}
sahilmgandhi 18:6a4db94011d3 1969 */ /* end of group MCM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1970
sahilmgandhi 18:6a4db94011d3 1971
sahilmgandhi 18:6a4db94011d3 1972 /* MCM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1973 /** Peripheral MCM base address */
sahilmgandhi 18:6a4db94011d3 1974 #define MCM_BASE (0xF0003000u)
sahilmgandhi 18:6a4db94011d3 1975 /** Peripheral MCM base pointer */
sahilmgandhi 18:6a4db94011d3 1976 #define MCM ((MCM_Type *)MCM_BASE)
sahilmgandhi 18:6a4db94011d3 1977 /** Array initializer of MCM peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 1978 #define MCM_BASES { MCM }
sahilmgandhi 18:6a4db94011d3 1979
sahilmgandhi 18:6a4db94011d3 1980 /**
sahilmgandhi 18:6a4db94011d3 1981 * @}
sahilmgandhi 18:6a4db94011d3 1982 */ /* end of group MCM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1983
sahilmgandhi 18:6a4db94011d3 1984
sahilmgandhi 18:6a4db94011d3 1985 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1986 -- MTB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1987 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1988
sahilmgandhi 18:6a4db94011d3 1989 /**
sahilmgandhi 18:6a4db94011d3 1990 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1991 * @{
sahilmgandhi 18:6a4db94011d3 1992 */
sahilmgandhi 18:6a4db94011d3 1993
sahilmgandhi 18:6a4db94011d3 1994 /** MTB - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1995 typedef struct {
sahilmgandhi 18:6a4db94011d3 1996 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1997 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1998 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1999 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2000 uint8_t RESERVED_0[3824];
sahilmgandhi 18:6a4db94011d3 2001 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
sahilmgandhi 18:6a4db94011d3 2002 uint8_t RESERVED_1[156];
sahilmgandhi 18:6a4db94011d3 2003 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
sahilmgandhi 18:6a4db94011d3 2004 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
sahilmgandhi 18:6a4db94011d3 2005 uint8_t RESERVED_2[8];
sahilmgandhi 18:6a4db94011d3 2006 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
sahilmgandhi 18:6a4db94011d3 2007 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
sahilmgandhi 18:6a4db94011d3 2008 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
sahilmgandhi 18:6a4db94011d3 2009 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
sahilmgandhi 18:6a4db94011d3 2010 uint8_t RESERVED_3[8];
sahilmgandhi 18:6a4db94011d3 2011 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
sahilmgandhi 18:6a4db94011d3 2012 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
sahilmgandhi 18:6a4db94011d3 2013 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2014 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2015 } MTB_Type;
sahilmgandhi 18:6a4db94011d3 2016
sahilmgandhi 18:6a4db94011d3 2017 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2018 -- MTB Register Masks
sahilmgandhi 18:6a4db94011d3 2019 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2020
sahilmgandhi 18:6a4db94011d3 2021 /**
sahilmgandhi 18:6a4db94011d3 2022 * @addtogroup MTB_Register_Masks MTB Register Masks
sahilmgandhi 18:6a4db94011d3 2023 * @{
sahilmgandhi 18:6a4db94011d3 2024 */
sahilmgandhi 18:6a4db94011d3 2025
sahilmgandhi 18:6a4db94011d3 2026 /* POSITION Bit Fields */
sahilmgandhi 18:6a4db94011d3 2027 #define MTB_POSITION_WRAP_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2028 #define MTB_POSITION_WRAP_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2029 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
sahilmgandhi 18:6a4db94011d3 2030 #define MTB_POSITION_POINTER_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2031 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
sahilmgandhi 18:6a4db94011d3 2032 /* MASTER Bit Fields */
sahilmgandhi 18:6a4db94011d3 2033 #define MTB_MASTER_MASK_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2034 #define MTB_MASTER_MASK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2035 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
sahilmgandhi 18:6a4db94011d3 2036 #define MTB_MASTER_TSTARTEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2037 #define MTB_MASTER_TSTARTEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2038 #define MTB_MASTER_TSTOPEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2039 #define MTB_MASTER_TSTOPEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2040 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2041 #define MTB_MASTER_SFRWPRIV_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2042 #define MTB_MASTER_RAMPRIV_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2043 #define MTB_MASTER_RAMPRIV_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2044 #define MTB_MASTER_HALTREQ_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2045 #define MTB_MASTER_HALTREQ_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2046 #define MTB_MASTER_EN_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 2047 #define MTB_MASTER_EN_SHIFT 31
sahilmgandhi 18:6a4db94011d3 2048 /* FLOW Bit Fields */
sahilmgandhi 18:6a4db94011d3 2049 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2050 #define MTB_FLOW_AUTOSTOP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2051 #define MTB_FLOW_AUTOHALT_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2052 #define MTB_FLOW_AUTOHALT_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2053 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
sahilmgandhi 18:6a4db94011d3 2054 #define MTB_FLOW_WATERMARK_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2055 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
sahilmgandhi 18:6a4db94011d3 2056 /* BASE Bit Fields */
sahilmgandhi 18:6a4db94011d3 2057 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2058 #define MTB_BASE_BASEADDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2059 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
sahilmgandhi 18:6a4db94011d3 2060 /* MODECTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2061 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2062 #define MTB_MODECTRL_MODECTRL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2063 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
sahilmgandhi 18:6a4db94011d3 2064 /* TAGSET Bit Fields */
sahilmgandhi 18:6a4db94011d3 2065 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2066 #define MTB_TAGSET_TAGSET_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2067 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
sahilmgandhi 18:6a4db94011d3 2068 /* TAGCLEAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2069 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2070 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2071 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
sahilmgandhi 18:6a4db94011d3 2072 /* LOCKACCESS Bit Fields */
sahilmgandhi 18:6a4db94011d3 2073 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2074 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2075 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
sahilmgandhi 18:6a4db94011d3 2076 /* LOCKSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 2077 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2078 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2079 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
sahilmgandhi 18:6a4db94011d3 2080 /* AUTHSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 2081 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2082 #define MTB_AUTHSTAT_BIT0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2083 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2084 #define MTB_AUTHSTAT_BIT1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2085 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2086 #define MTB_AUTHSTAT_BIT2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2087 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2088 #define MTB_AUTHSTAT_BIT3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2089 /* DEVICEARCH Bit Fields */
sahilmgandhi 18:6a4db94011d3 2090 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2091 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2092 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
sahilmgandhi 18:6a4db94011d3 2093 /* DEVICECFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 2094 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2095 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2096 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
sahilmgandhi 18:6a4db94011d3 2097 /* DEVICETYPID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2098 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2099 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2100 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
sahilmgandhi 18:6a4db94011d3 2101 /* PERIPHID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2102 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2103 #define MTB_PERIPHID_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2104 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2105 /* COMPID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2106 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2107 #define MTB_COMPID_COMPID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2108 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
sahilmgandhi 18:6a4db94011d3 2109
sahilmgandhi 18:6a4db94011d3 2110 /**
sahilmgandhi 18:6a4db94011d3 2111 * @}
sahilmgandhi 18:6a4db94011d3 2112 */ /* end of group MTB_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2113
sahilmgandhi 18:6a4db94011d3 2114
sahilmgandhi 18:6a4db94011d3 2115 /* MTB - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2116 /** Peripheral MTB base address */
sahilmgandhi 18:6a4db94011d3 2117 #define MTB_BASE (0xF0000000u)
sahilmgandhi 18:6a4db94011d3 2118 /** Peripheral MTB base pointer */
sahilmgandhi 18:6a4db94011d3 2119 #define MTB ((MTB_Type *)MTB_BASE)
sahilmgandhi 18:6a4db94011d3 2120 /** Array initializer of MTB peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2121 #define MTB_BASES { MTB }
sahilmgandhi 18:6a4db94011d3 2122
sahilmgandhi 18:6a4db94011d3 2123 /**
sahilmgandhi 18:6a4db94011d3 2124 * @}
sahilmgandhi 18:6a4db94011d3 2125 */ /* end of group MTB_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2126
sahilmgandhi 18:6a4db94011d3 2127
sahilmgandhi 18:6a4db94011d3 2128 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2129 -- MTBDWT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2130 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2131
sahilmgandhi 18:6a4db94011d3 2132 /**
sahilmgandhi 18:6a4db94011d3 2133 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2134 * @{
sahilmgandhi 18:6a4db94011d3 2135 */
sahilmgandhi 18:6a4db94011d3 2136
sahilmgandhi 18:6a4db94011d3 2137 /** MTBDWT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2138 typedef struct {
sahilmgandhi 18:6a4db94011d3 2139 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2140 uint8_t RESERVED_0[28];
sahilmgandhi 18:6a4db94011d3 2141 struct { /* offset: 0x20, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2142 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2143 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2144 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2145 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 2146 } COMPARATOR[2];
sahilmgandhi 18:6a4db94011d3 2147 uint8_t RESERVED_1[448];
sahilmgandhi 18:6a4db94011d3 2148 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
sahilmgandhi 18:6a4db94011d3 2149 uint8_t RESERVED_2[3524];
sahilmgandhi 18:6a4db94011d3 2150 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
sahilmgandhi 18:6a4db94011d3 2151 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
sahilmgandhi 18:6a4db94011d3 2152 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2153 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2154 } MTBDWT_Type;
sahilmgandhi 18:6a4db94011d3 2155
sahilmgandhi 18:6a4db94011d3 2156 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2157 -- MTBDWT Register Masks
sahilmgandhi 18:6a4db94011d3 2158 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2159
sahilmgandhi 18:6a4db94011d3 2160 /**
sahilmgandhi 18:6a4db94011d3 2161 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
sahilmgandhi 18:6a4db94011d3 2162 * @{
sahilmgandhi 18:6a4db94011d3 2163 */
sahilmgandhi 18:6a4db94011d3 2164
sahilmgandhi 18:6a4db94011d3 2165 /* CTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2166 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2167 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2168 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
sahilmgandhi 18:6a4db94011d3 2169 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 2170 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
sahilmgandhi 18:6a4db94011d3 2171 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
sahilmgandhi 18:6a4db94011d3 2172 /* COMP Bit Fields */
sahilmgandhi 18:6a4db94011d3 2173 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2174 #define MTBDWT_COMP_COMP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2175 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
sahilmgandhi 18:6a4db94011d3 2176 /* MASK Bit Fields */
sahilmgandhi 18:6a4db94011d3 2177 #define MTBDWT_MASK_MASK_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2178 #define MTBDWT_MASK_MASK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2179 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
sahilmgandhi 18:6a4db94011d3 2180 /* FCT Bit Fields */
sahilmgandhi 18:6a4db94011d3 2181 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 2182 #define MTBDWT_FCT_FUNCTION_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2183 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
sahilmgandhi 18:6a4db94011d3 2184 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2185 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2186 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
sahilmgandhi 18:6a4db94011d3 2187 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2188 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 2189 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 2190 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2191 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
sahilmgandhi 18:6a4db94011d3 2192 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 2193 #define MTBDWT_FCT_MATCHED_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2194 /* TBCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2195 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2196 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2197 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2198 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2199 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 2200 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
sahilmgandhi 18:6a4db94011d3 2201 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
sahilmgandhi 18:6a4db94011d3 2202 /* DEVICECFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 2203 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2204 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2205 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
sahilmgandhi 18:6a4db94011d3 2206 /* DEVICETYPID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2207 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2208 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2209 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
sahilmgandhi 18:6a4db94011d3 2210 /* PERIPHID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2211 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2212 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2213 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2214 /* COMPID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2215 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2216 #define MTBDWT_COMPID_COMPID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2217 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
sahilmgandhi 18:6a4db94011d3 2218
sahilmgandhi 18:6a4db94011d3 2219 /**
sahilmgandhi 18:6a4db94011d3 2220 * @}
sahilmgandhi 18:6a4db94011d3 2221 */ /* end of group MTBDWT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2222
sahilmgandhi 18:6a4db94011d3 2223
sahilmgandhi 18:6a4db94011d3 2224 /* MTBDWT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2225 /** Peripheral MTBDWT base address */
sahilmgandhi 18:6a4db94011d3 2226 #define MTBDWT_BASE (0xF0001000u)
sahilmgandhi 18:6a4db94011d3 2227 /** Peripheral MTBDWT base pointer */
sahilmgandhi 18:6a4db94011d3 2228 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
sahilmgandhi 18:6a4db94011d3 2229 /** Array initializer of MTBDWT peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2230 #define MTBDWT_BASES { MTBDWT }
sahilmgandhi 18:6a4db94011d3 2231
sahilmgandhi 18:6a4db94011d3 2232 /**
sahilmgandhi 18:6a4db94011d3 2233 * @}
sahilmgandhi 18:6a4db94011d3 2234 */ /* end of group MTBDWT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2235
sahilmgandhi 18:6a4db94011d3 2236
sahilmgandhi 18:6a4db94011d3 2237 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2238 -- NV Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2239 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2240
sahilmgandhi 18:6a4db94011d3 2241 /**
sahilmgandhi 18:6a4db94011d3 2242 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2243 * @{
sahilmgandhi 18:6a4db94011d3 2244 */
sahilmgandhi 18:6a4db94011d3 2245
sahilmgandhi 18:6a4db94011d3 2246 /** NV - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2247 typedef struct {
sahilmgandhi 18:6a4db94011d3 2248 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2249 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 2250 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 2251 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 2252 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2253 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 2254 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 2255 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 2256 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2257 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 2258 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 2259 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 2260 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2261 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 2262 } NV_Type;
sahilmgandhi 18:6a4db94011d3 2263
sahilmgandhi 18:6a4db94011d3 2264 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2265 -- NV Register Masks
sahilmgandhi 18:6a4db94011d3 2266 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2267
sahilmgandhi 18:6a4db94011d3 2268 /**
sahilmgandhi 18:6a4db94011d3 2269 * @addtogroup NV_Register_Masks NV Register Masks
sahilmgandhi 18:6a4db94011d3 2270 * @{
sahilmgandhi 18:6a4db94011d3 2271 */
sahilmgandhi 18:6a4db94011d3 2272
sahilmgandhi 18:6a4db94011d3 2273 /* BACKKEY3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2274 #define NV_BACKKEY3_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2275 #define NV_BACKKEY3_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2276 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2277 /* BACKKEY2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2278 #define NV_BACKKEY2_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2279 #define NV_BACKKEY2_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2280 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2281 /* BACKKEY1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2282 #define NV_BACKKEY1_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2283 #define NV_BACKKEY1_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2284 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2285 /* BACKKEY0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2286 #define NV_BACKKEY0_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2287 #define NV_BACKKEY0_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2288 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2289 /* BACKKEY7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2290 #define NV_BACKKEY7_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2291 #define NV_BACKKEY7_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2292 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2293 /* BACKKEY6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2294 #define NV_BACKKEY6_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2295 #define NV_BACKKEY6_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2296 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2297 /* BACKKEY5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2298 #define NV_BACKKEY5_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2299 #define NV_BACKKEY5_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2300 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2301 /* BACKKEY4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2302 #define NV_BACKKEY4_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2303 #define NV_BACKKEY4_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2304 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 2305 /* FPROT3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2306 #define NV_FPROT3_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2307 #define NV_FPROT3_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2308 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 2309 /* FPROT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2310 #define NV_FPROT2_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2311 #define NV_FPROT2_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2312 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 2313 /* FPROT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2314 #define NV_FPROT1_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2315 #define NV_FPROT1_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2316 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 2317 /* FPROT0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2318 #define NV_FPROT0_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2319 #define NV_FPROT0_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2320 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 2321 /* FSEC Bit Fields */
sahilmgandhi 18:6a4db94011d3 2322 #define NV_FSEC_SEC_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2323 #define NV_FSEC_SEC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2324 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
sahilmgandhi 18:6a4db94011d3 2325 #define NV_FSEC_FSLACC_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 2326 #define NV_FSEC_FSLACC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2327 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
sahilmgandhi 18:6a4db94011d3 2328 #define NV_FSEC_MEEN_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 2329 #define NV_FSEC_MEEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2330 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
sahilmgandhi 18:6a4db94011d3 2331 #define NV_FSEC_KEYEN_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2332 #define NV_FSEC_KEYEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2333 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
sahilmgandhi 18:6a4db94011d3 2334 /* FOPT Bit Fields */
sahilmgandhi 18:6a4db94011d3 2335 #define NV_FOPT_LPBOOT0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2336 #define NV_FOPT_LPBOOT0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2337 #define NV_FOPT_NMI_DIS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2338 #define NV_FOPT_NMI_DIS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2339 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2340 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2341 #define NV_FOPT_LPBOOT1_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2342 #define NV_FOPT_LPBOOT1_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2343 #define NV_FOPT_FAST_INIT_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2344 #define NV_FOPT_FAST_INIT_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2345
sahilmgandhi 18:6a4db94011d3 2346 /**
sahilmgandhi 18:6a4db94011d3 2347 * @}
sahilmgandhi 18:6a4db94011d3 2348 */ /* end of group NV_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2349
sahilmgandhi 18:6a4db94011d3 2350
sahilmgandhi 18:6a4db94011d3 2351 /* NV - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2352 /** Peripheral FTFA_FlashConfig base address */
sahilmgandhi 18:6a4db94011d3 2353 #define FTFA_FlashConfig_BASE (0x400u)
sahilmgandhi 18:6a4db94011d3 2354 /** Peripheral FTFA_FlashConfig base pointer */
sahilmgandhi 18:6a4db94011d3 2355 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
sahilmgandhi 18:6a4db94011d3 2356 /** Array initializer of NV peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2357 #define NV_BASES { FTFA_FlashConfig }
sahilmgandhi 18:6a4db94011d3 2358
sahilmgandhi 18:6a4db94011d3 2359 /**
sahilmgandhi 18:6a4db94011d3 2360 * @}
sahilmgandhi 18:6a4db94011d3 2361 */ /* end of group NV_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2362
sahilmgandhi 18:6a4db94011d3 2363
sahilmgandhi 18:6a4db94011d3 2364 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2365 -- OSC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2366 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2367
sahilmgandhi 18:6a4db94011d3 2368 /**
sahilmgandhi 18:6a4db94011d3 2369 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2370 * @{
sahilmgandhi 18:6a4db94011d3 2371 */
sahilmgandhi 18:6a4db94011d3 2372
sahilmgandhi 18:6a4db94011d3 2373 /** OSC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2374 typedef struct {
sahilmgandhi 18:6a4db94011d3 2375 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2376 } OSC_Type;
sahilmgandhi 18:6a4db94011d3 2377
sahilmgandhi 18:6a4db94011d3 2378 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2379 -- OSC Register Masks
sahilmgandhi 18:6a4db94011d3 2380 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2381
sahilmgandhi 18:6a4db94011d3 2382 /**
sahilmgandhi 18:6a4db94011d3 2383 * @addtogroup OSC_Register_Masks OSC Register Masks
sahilmgandhi 18:6a4db94011d3 2384 * @{
sahilmgandhi 18:6a4db94011d3 2385 */
sahilmgandhi 18:6a4db94011d3 2386
sahilmgandhi 18:6a4db94011d3 2387 /* CR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2388 #define OSC_CR_SC16P_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2389 #define OSC_CR_SC16P_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2390 #define OSC_CR_SC8P_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2391 #define OSC_CR_SC8P_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2392 #define OSC_CR_SC4P_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2393 #define OSC_CR_SC4P_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2394 #define OSC_CR_SC2P_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2395 #define OSC_CR_SC2P_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2396 #define OSC_CR_EREFSTEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2397 #define OSC_CR_EREFSTEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2398 #define OSC_CR_ERCLKEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2399 #define OSC_CR_ERCLKEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2400
sahilmgandhi 18:6a4db94011d3 2401 /**
sahilmgandhi 18:6a4db94011d3 2402 * @}
sahilmgandhi 18:6a4db94011d3 2403 */ /* end of group OSC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2404
sahilmgandhi 18:6a4db94011d3 2405
sahilmgandhi 18:6a4db94011d3 2406 /* OSC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2407 /** Peripheral OSC0 base address */
sahilmgandhi 18:6a4db94011d3 2408 #define OSC0_BASE (0x40065000u)
sahilmgandhi 18:6a4db94011d3 2409 /** Peripheral OSC0 base pointer */
sahilmgandhi 18:6a4db94011d3 2410 #define OSC0 ((OSC_Type *)OSC0_BASE)
sahilmgandhi 18:6a4db94011d3 2411 /** Array initializer of OSC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2412 #define OSC_BASES { OSC0 }
sahilmgandhi 18:6a4db94011d3 2413
sahilmgandhi 18:6a4db94011d3 2414 /**
sahilmgandhi 18:6a4db94011d3 2415 * @}
sahilmgandhi 18:6a4db94011d3 2416 */ /* end of group OSC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2417
sahilmgandhi 18:6a4db94011d3 2418
sahilmgandhi 18:6a4db94011d3 2419 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2420 -- PIT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2421 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2422
sahilmgandhi 18:6a4db94011d3 2423 /**
sahilmgandhi 18:6a4db94011d3 2424 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2425 * @{
sahilmgandhi 18:6a4db94011d3 2426 */
sahilmgandhi 18:6a4db94011d3 2427
sahilmgandhi 18:6a4db94011d3 2428 /** PIT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2429 typedef struct {
sahilmgandhi 18:6a4db94011d3 2430 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2431 uint8_t RESERVED_0[220];
sahilmgandhi 18:6a4db94011d3 2432 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
sahilmgandhi 18:6a4db94011d3 2433 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
sahilmgandhi 18:6a4db94011d3 2434 uint8_t RESERVED_1[24];
sahilmgandhi 18:6a4db94011d3 2435 struct { /* offset: 0x100, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2436 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2437 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2438 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2439 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 2440 } CHANNEL[2];
sahilmgandhi 18:6a4db94011d3 2441 } PIT_Type;
sahilmgandhi 18:6a4db94011d3 2442
sahilmgandhi 18:6a4db94011d3 2443 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2444 -- PIT Register Masks
sahilmgandhi 18:6a4db94011d3 2445 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2446
sahilmgandhi 18:6a4db94011d3 2447 /**
sahilmgandhi 18:6a4db94011d3 2448 * @addtogroup PIT_Register_Masks PIT Register Masks
sahilmgandhi 18:6a4db94011d3 2449 * @{
sahilmgandhi 18:6a4db94011d3 2450 */
sahilmgandhi 18:6a4db94011d3 2451
sahilmgandhi 18:6a4db94011d3 2452 /* MCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2453 #define PIT_MCR_FRZ_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2454 #define PIT_MCR_FRZ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2455 #define PIT_MCR_MDIS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2456 #define PIT_MCR_MDIS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2457 /* LTMR64H Bit Fields */
sahilmgandhi 18:6a4db94011d3 2458 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2459 #define PIT_LTMR64H_LTH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2460 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
sahilmgandhi 18:6a4db94011d3 2461 /* LTMR64L Bit Fields */
sahilmgandhi 18:6a4db94011d3 2462 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2463 #define PIT_LTMR64L_LTL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2464 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
sahilmgandhi 18:6a4db94011d3 2465 /* LDVAL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2466 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2467 #define PIT_LDVAL_TSV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2468 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
sahilmgandhi 18:6a4db94011d3 2469 /* CVAL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2470 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2471 #define PIT_CVAL_TVL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2472 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
sahilmgandhi 18:6a4db94011d3 2473 /* TCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2474 #define PIT_TCTRL_TEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2475 #define PIT_TCTRL_TEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2476 #define PIT_TCTRL_TIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2477 #define PIT_TCTRL_TIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2478 #define PIT_TCTRL_CHN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2479 #define PIT_TCTRL_CHN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2480 /* TFLG Bit Fields */
sahilmgandhi 18:6a4db94011d3 2481 #define PIT_TFLG_TIF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2482 #define PIT_TFLG_TIF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2483
sahilmgandhi 18:6a4db94011d3 2484 /**
sahilmgandhi 18:6a4db94011d3 2485 * @}
sahilmgandhi 18:6a4db94011d3 2486 */ /* end of group PIT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2487
sahilmgandhi 18:6a4db94011d3 2488
sahilmgandhi 18:6a4db94011d3 2489 /* PIT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2490 /** Peripheral PIT base address */
sahilmgandhi 18:6a4db94011d3 2491 #define PIT_BASE (0x40037000u)
sahilmgandhi 18:6a4db94011d3 2492 /** Peripheral PIT base pointer */
sahilmgandhi 18:6a4db94011d3 2493 #define PIT ((PIT_Type *)PIT_BASE)
sahilmgandhi 18:6a4db94011d3 2494 /** Array initializer of PIT peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2495 #define PIT_BASES { PIT }
sahilmgandhi 18:6a4db94011d3 2496
sahilmgandhi 18:6a4db94011d3 2497 /**
sahilmgandhi 18:6a4db94011d3 2498 * @}
sahilmgandhi 18:6a4db94011d3 2499 */ /* end of group PIT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2500
sahilmgandhi 18:6a4db94011d3 2501
sahilmgandhi 18:6a4db94011d3 2502 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2503 -- PMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2504 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2505
sahilmgandhi 18:6a4db94011d3 2506 /**
sahilmgandhi 18:6a4db94011d3 2507 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2508 * @{
sahilmgandhi 18:6a4db94011d3 2509 */
sahilmgandhi 18:6a4db94011d3 2510
sahilmgandhi 18:6a4db94011d3 2511 /** PMC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2512 typedef struct {
sahilmgandhi 18:6a4db94011d3 2513 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2514 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 2515 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 2516 } PMC_Type;
sahilmgandhi 18:6a4db94011d3 2517
sahilmgandhi 18:6a4db94011d3 2518 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2519 -- PMC Register Masks
sahilmgandhi 18:6a4db94011d3 2520 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2521
sahilmgandhi 18:6a4db94011d3 2522 /**
sahilmgandhi 18:6a4db94011d3 2523 * @addtogroup PMC_Register_Masks PMC Register Masks
sahilmgandhi 18:6a4db94011d3 2524 * @{
sahilmgandhi 18:6a4db94011d3 2525 */
sahilmgandhi 18:6a4db94011d3 2526
sahilmgandhi 18:6a4db94011d3 2527 /* LVDSC1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2528 #define PMC_LVDSC1_LVDV_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2529 #define PMC_LVDSC1_LVDV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2530 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
sahilmgandhi 18:6a4db94011d3 2531 #define PMC_LVDSC1_LVDRE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2532 #define PMC_LVDSC1_LVDRE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2533 #define PMC_LVDSC1_LVDIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2534 #define PMC_LVDSC1_LVDIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2535 #define PMC_LVDSC1_LVDACK_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2536 #define PMC_LVDSC1_LVDACK_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2537 #define PMC_LVDSC1_LVDF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2538 #define PMC_LVDSC1_LVDF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2539 /* LVDSC2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2540 #define PMC_LVDSC2_LVWV_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2541 #define PMC_LVDSC2_LVWV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2542 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
sahilmgandhi 18:6a4db94011d3 2543 #define PMC_LVDSC2_LVWIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2544 #define PMC_LVDSC2_LVWIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2545 #define PMC_LVDSC2_LVWACK_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2546 #define PMC_LVDSC2_LVWACK_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2547 #define PMC_LVDSC2_LVWF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2548 #define PMC_LVDSC2_LVWF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2549 /* REGSC Bit Fields */
sahilmgandhi 18:6a4db94011d3 2550 #define PMC_REGSC_BGBE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2551 #define PMC_REGSC_BGBE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2552 #define PMC_REGSC_REGONS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2553 #define PMC_REGSC_REGONS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2554 #define PMC_REGSC_ACKISO_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2555 #define PMC_REGSC_ACKISO_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2556 #define PMC_REGSC_BGEN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2557 #define PMC_REGSC_BGEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2558
sahilmgandhi 18:6a4db94011d3 2559 /**
sahilmgandhi 18:6a4db94011d3 2560 * @}
sahilmgandhi 18:6a4db94011d3 2561 */ /* end of group PMC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2562
sahilmgandhi 18:6a4db94011d3 2563
sahilmgandhi 18:6a4db94011d3 2564 /* PMC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2565 /** Peripheral PMC base address */
sahilmgandhi 18:6a4db94011d3 2566 #define PMC_BASE (0x4007D000u)
sahilmgandhi 18:6a4db94011d3 2567 /** Peripheral PMC base pointer */
sahilmgandhi 18:6a4db94011d3 2568 #define PMC ((PMC_Type *)PMC_BASE)
sahilmgandhi 18:6a4db94011d3 2569 /** Array initializer of PMC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2570 #define PMC_BASES { PMC }
sahilmgandhi 18:6a4db94011d3 2571
sahilmgandhi 18:6a4db94011d3 2572 /**
sahilmgandhi 18:6a4db94011d3 2573 * @}
sahilmgandhi 18:6a4db94011d3 2574 */ /* end of group PMC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2575
sahilmgandhi 18:6a4db94011d3 2576
sahilmgandhi 18:6a4db94011d3 2577 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2578 -- PORT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2579 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2580
sahilmgandhi 18:6a4db94011d3 2581 /**
sahilmgandhi 18:6a4db94011d3 2582 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2583 * @{
sahilmgandhi 18:6a4db94011d3 2584 */
sahilmgandhi 18:6a4db94011d3 2585
sahilmgandhi 18:6a4db94011d3 2586 /** PORT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2587 typedef struct {
sahilmgandhi 18:6a4db94011d3 2588 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2589 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 2590 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 2591 uint8_t RESERVED_0[24];
sahilmgandhi 18:6a4db94011d3 2592 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
sahilmgandhi 18:6a4db94011d3 2593 } PORT_Type;
sahilmgandhi 18:6a4db94011d3 2594
sahilmgandhi 18:6a4db94011d3 2595 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2596 -- PORT Register Masks
sahilmgandhi 18:6a4db94011d3 2597 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2598
sahilmgandhi 18:6a4db94011d3 2599 /**
sahilmgandhi 18:6a4db94011d3 2600 * @addtogroup PORT_Register_Masks PORT Register Masks
sahilmgandhi 18:6a4db94011d3 2601 * @{
sahilmgandhi 18:6a4db94011d3 2602 */
sahilmgandhi 18:6a4db94011d3 2603
sahilmgandhi 18:6a4db94011d3 2604 /* PCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2605 #define PORT_PCR_PS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2606 #define PORT_PCR_PS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2607 #define PORT_PCR_PE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2608 #define PORT_PCR_PE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2609 #define PORT_PCR_SRE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2610 #define PORT_PCR_SRE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2611 #define PORT_PCR_PFE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2612 #define PORT_PCR_PFE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2613 #define PORT_PCR_DSE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2614 #define PORT_PCR_DSE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2615 #define PORT_PCR_MUX_MASK 0x700u
sahilmgandhi 18:6a4db94011d3 2616 #define PORT_PCR_MUX_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2617 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
sahilmgandhi 18:6a4db94011d3 2618 #define PORT_PCR_IRQC_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 2619 #define PORT_PCR_IRQC_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2620 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
sahilmgandhi 18:6a4db94011d3 2621 #define PORT_PCR_ISF_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 2622 #define PORT_PCR_ISF_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2623 /* GPCLR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2624 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 2625 #define PORT_GPCLR_GPWD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2626 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
sahilmgandhi 18:6a4db94011d3 2627 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 2628 #define PORT_GPCLR_GPWE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2629 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
sahilmgandhi 18:6a4db94011d3 2630 /* GPCHR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2631 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 2632 #define PORT_GPCHR_GPWD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2633 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
sahilmgandhi 18:6a4db94011d3 2634 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 2635 #define PORT_GPCHR_GPWE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2636 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
sahilmgandhi 18:6a4db94011d3 2637 /* ISFR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2638 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2639 #define PORT_ISFR_ISF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2640 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
sahilmgandhi 18:6a4db94011d3 2641
sahilmgandhi 18:6a4db94011d3 2642 /**
sahilmgandhi 18:6a4db94011d3 2643 * @}
sahilmgandhi 18:6a4db94011d3 2644 */ /* end of group PORT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2645
sahilmgandhi 18:6a4db94011d3 2646
sahilmgandhi 18:6a4db94011d3 2647 /* PORT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2648 /** Peripheral PORTA base address */
sahilmgandhi 18:6a4db94011d3 2649 #define PORTA_BASE (0x40049000u)
sahilmgandhi 18:6a4db94011d3 2650 /** Peripheral PORTA base pointer */
sahilmgandhi 18:6a4db94011d3 2651 #define PORTA ((PORT_Type *)PORTA_BASE)
sahilmgandhi 18:6a4db94011d3 2652 /** Peripheral PORTB base address */
sahilmgandhi 18:6a4db94011d3 2653 #define PORTB_BASE (0x4004A000u)
sahilmgandhi 18:6a4db94011d3 2654 /** Peripheral PORTB base pointer */
sahilmgandhi 18:6a4db94011d3 2655 #define PORTB ((PORT_Type *)PORTB_BASE)
sahilmgandhi 18:6a4db94011d3 2656 /** Peripheral PORTC base address */
sahilmgandhi 18:6a4db94011d3 2657 #define PORTC_BASE (0x4004B000u)
sahilmgandhi 18:6a4db94011d3 2658 /** Peripheral PORTC base pointer */
sahilmgandhi 18:6a4db94011d3 2659 #define PORTC ((PORT_Type *)PORTC_BASE)
sahilmgandhi 18:6a4db94011d3 2660 /** Peripheral PORTD base address */
sahilmgandhi 18:6a4db94011d3 2661 #define PORTD_BASE (0x4004C000u)
sahilmgandhi 18:6a4db94011d3 2662 /** Peripheral PORTD base pointer */
sahilmgandhi 18:6a4db94011d3 2663 #define PORTD ((PORT_Type *)PORTD_BASE)
sahilmgandhi 18:6a4db94011d3 2664 /** Peripheral PORTE base address */
sahilmgandhi 18:6a4db94011d3 2665 #define PORTE_BASE (0x4004D000u)
sahilmgandhi 18:6a4db94011d3 2666 /** Peripheral PORTE base pointer */
sahilmgandhi 18:6a4db94011d3 2667 #define PORTE ((PORT_Type *)PORTE_BASE)
sahilmgandhi 18:6a4db94011d3 2668 /** Array initializer of PORT peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2669 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
sahilmgandhi 18:6a4db94011d3 2670
sahilmgandhi 18:6a4db94011d3 2671 /**
sahilmgandhi 18:6a4db94011d3 2672 * @}
sahilmgandhi 18:6a4db94011d3 2673 */ /* end of group PORT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2674
sahilmgandhi 18:6a4db94011d3 2675
sahilmgandhi 18:6a4db94011d3 2676 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2677 -- RCM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2678 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2679
sahilmgandhi 18:6a4db94011d3 2680 /**
sahilmgandhi 18:6a4db94011d3 2681 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2682 * @{
sahilmgandhi 18:6a4db94011d3 2683 */
sahilmgandhi 18:6a4db94011d3 2684
sahilmgandhi 18:6a4db94011d3 2685 /** RCM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2686 typedef struct {
sahilmgandhi 18:6a4db94011d3 2687 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2688 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 2689 uint8_t RESERVED_0[2];
sahilmgandhi 18:6a4db94011d3 2690 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2691 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 2692 } RCM_Type;
sahilmgandhi 18:6a4db94011d3 2693
sahilmgandhi 18:6a4db94011d3 2694 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2695 -- RCM Register Masks
sahilmgandhi 18:6a4db94011d3 2696 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2697
sahilmgandhi 18:6a4db94011d3 2698 /**
sahilmgandhi 18:6a4db94011d3 2699 * @addtogroup RCM_Register_Masks RCM Register Masks
sahilmgandhi 18:6a4db94011d3 2700 * @{
sahilmgandhi 18:6a4db94011d3 2701 */
sahilmgandhi 18:6a4db94011d3 2702
sahilmgandhi 18:6a4db94011d3 2703 /* SRS0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2704 #define RCM_SRS0_WAKEUP_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2705 #define RCM_SRS0_WAKEUP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2706 #define RCM_SRS0_LVD_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2707 #define RCM_SRS0_LVD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2708 #define RCM_SRS0_LOC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2709 #define RCM_SRS0_LOC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2710 #define RCM_SRS0_LOL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2711 #define RCM_SRS0_LOL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2712 #define RCM_SRS0_WDOG_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2713 #define RCM_SRS0_WDOG_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2714 #define RCM_SRS0_PIN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2715 #define RCM_SRS0_PIN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2716 #define RCM_SRS0_POR_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2717 #define RCM_SRS0_POR_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2718 /* SRS1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2719 #define RCM_SRS1_LOCKUP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2720 #define RCM_SRS1_LOCKUP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2721 #define RCM_SRS1_SW_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2722 #define RCM_SRS1_SW_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2723 #define RCM_SRS1_MDM_AP_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2724 #define RCM_SRS1_MDM_AP_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2725 #define RCM_SRS1_SACKERR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2726 #define RCM_SRS1_SACKERR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2727 /* RPFC Bit Fields */
sahilmgandhi 18:6a4db94011d3 2728 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2729 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2730 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
sahilmgandhi 18:6a4db94011d3 2731 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2732 #define RCM_RPFC_RSTFLTSS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2733 /* RPFW Bit Fields */
sahilmgandhi 18:6a4db94011d3 2734 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2735 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2736 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 2737
sahilmgandhi 18:6a4db94011d3 2738 /**
sahilmgandhi 18:6a4db94011d3 2739 * @}
sahilmgandhi 18:6a4db94011d3 2740 */ /* end of group RCM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2741
sahilmgandhi 18:6a4db94011d3 2742
sahilmgandhi 18:6a4db94011d3 2743 /* RCM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2744 /** Peripheral RCM base address */
sahilmgandhi 18:6a4db94011d3 2745 #define RCM_BASE (0x4007F000u)
sahilmgandhi 18:6a4db94011d3 2746 /** Peripheral RCM base pointer */
sahilmgandhi 18:6a4db94011d3 2747 #define RCM ((RCM_Type *)RCM_BASE)
sahilmgandhi 18:6a4db94011d3 2748 /** Array initializer of RCM peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2749 #define RCM_BASES { RCM }
sahilmgandhi 18:6a4db94011d3 2750
sahilmgandhi 18:6a4db94011d3 2751 /**
sahilmgandhi 18:6a4db94011d3 2752 * @}
sahilmgandhi 18:6a4db94011d3 2753 */ /* end of group RCM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2754
sahilmgandhi 18:6a4db94011d3 2755
sahilmgandhi 18:6a4db94011d3 2756 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2757 -- ROM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2758 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2759
sahilmgandhi 18:6a4db94011d3 2760 /**
sahilmgandhi 18:6a4db94011d3 2761 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2762 * @{
sahilmgandhi 18:6a4db94011d3 2763 */
sahilmgandhi 18:6a4db94011d3 2764
sahilmgandhi 18:6a4db94011d3 2765 /** ROM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2766 typedef struct {
sahilmgandhi 18:6a4db94011d3 2767 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2768 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2769 uint8_t RESERVED_0[4028];
sahilmgandhi 18:6a4db94011d3 2770 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
sahilmgandhi 18:6a4db94011d3 2771 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
sahilmgandhi 18:6a4db94011d3 2772 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
sahilmgandhi 18:6a4db94011d3 2773 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
sahilmgandhi 18:6a4db94011d3 2774 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
sahilmgandhi 18:6a4db94011d3 2775 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
sahilmgandhi 18:6a4db94011d3 2776 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
sahilmgandhi 18:6a4db94011d3 2777 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
sahilmgandhi 18:6a4db94011d3 2778 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
sahilmgandhi 18:6a4db94011d3 2779 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2780 } ROM_Type;
sahilmgandhi 18:6a4db94011d3 2781
sahilmgandhi 18:6a4db94011d3 2782 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2783 -- ROM Register Masks
sahilmgandhi 18:6a4db94011d3 2784 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2785
sahilmgandhi 18:6a4db94011d3 2786 /**
sahilmgandhi 18:6a4db94011d3 2787 * @addtogroup ROM_Register_Masks ROM Register Masks
sahilmgandhi 18:6a4db94011d3 2788 * @{
sahilmgandhi 18:6a4db94011d3 2789 */
sahilmgandhi 18:6a4db94011d3 2790
sahilmgandhi 18:6a4db94011d3 2791 /* ENTRY Bit Fields */
sahilmgandhi 18:6a4db94011d3 2792 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2793 #define ROM_ENTRY_ENTRY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2794 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
sahilmgandhi 18:6a4db94011d3 2795 /* TABLEMARK Bit Fields */
sahilmgandhi 18:6a4db94011d3 2796 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2797 #define ROM_TABLEMARK_MARK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2798 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
sahilmgandhi 18:6a4db94011d3 2799 /* SYSACCESS Bit Fields */
sahilmgandhi 18:6a4db94011d3 2800 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2801 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2802 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
sahilmgandhi 18:6a4db94011d3 2803 /* PERIPHID4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2804 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2805 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2806 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2807 /* PERIPHID5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2808 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2809 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2810 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2811 /* PERIPHID6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2812 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2813 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2814 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2815 /* PERIPHID7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2816 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2817 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2818 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2819 /* PERIPHID0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2820 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2821 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2822 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2823 /* PERIPHID1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2824 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2825 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2826 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2827 /* PERIPHID2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2828 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2829 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2830 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2831 /* PERIPHID3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2832 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2833 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2834 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
sahilmgandhi 18:6a4db94011d3 2835 /* COMPID Bit Fields */
sahilmgandhi 18:6a4db94011d3 2836 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2837 #define ROM_COMPID_COMPID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2838 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
sahilmgandhi 18:6a4db94011d3 2839
sahilmgandhi 18:6a4db94011d3 2840 /**
sahilmgandhi 18:6a4db94011d3 2841 * @}
sahilmgandhi 18:6a4db94011d3 2842 */ /* end of group ROM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2843
sahilmgandhi 18:6a4db94011d3 2844
sahilmgandhi 18:6a4db94011d3 2845 /* ROM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2846 /** Peripheral ROM base address */
sahilmgandhi 18:6a4db94011d3 2847 #define ROM_BASE (0xF0002000u)
sahilmgandhi 18:6a4db94011d3 2848 /** Peripheral ROM base pointer */
sahilmgandhi 18:6a4db94011d3 2849 #define ROM ((ROM_Type *)ROM_BASE)
sahilmgandhi 18:6a4db94011d3 2850 /** Array initializer of ROM peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2851 #define ROM_BASES { ROM }
sahilmgandhi 18:6a4db94011d3 2852
sahilmgandhi 18:6a4db94011d3 2853 /**
sahilmgandhi 18:6a4db94011d3 2854 * @}
sahilmgandhi 18:6a4db94011d3 2855 */ /* end of group ROM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2856
sahilmgandhi 18:6a4db94011d3 2857
sahilmgandhi 18:6a4db94011d3 2858 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2859 -- RTC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2860 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2861
sahilmgandhi 18:6a4db94011d3 2862 /**
sahilmgandhi 18:6a4db94011d3 2863 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2864 * @{
sahilmgandhi 18:6a4db94011d3 2865 */
sahilmgandhi 18:6a4db94011d3 2866
sahilmgandhi 18:6a4db94011d3 2867 /** RTC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2868 typedef struct {
sahilmgandhi 18:6a4db94011d3 2869 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2870 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2871 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2872 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2873 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 2874 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 2875 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 2876 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 2877 } RTC_Type;
sahilmgandhi 18:6a4db94011d3 2878
sahilmgandhi 18:6a4db94011d3 2879 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2880 -- RTC Register Masks
sahilmgandhi 18:6a4db94011d3 2881 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2882
sahilmgandhi 18:6a4db94011d3 2883 /**
sahilmgandhi 18:6a4db94011d3 2884 * @addtogroup RTC_Register_Masks RTC Register Masks
sahilmgandhi 18:6a4db94011d3 2885 * @{
sahilmgandhi 18:6a4db94011d3 2886 */
sahilmgandhi 18:6a4db94011d3 2887
sahilmgandhi 18:6a4db94011d3 2888 /* TSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2889 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2890 #define RTC_TSR_TSR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2891 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
sahilmgandhi 18:6a4db94011d3 2892 /* TPR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2893 #define RTC_TPR_TPR_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 2894 #define RTC_TPR_TPR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2895 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
sahilmgandhi 18:6a4db94011d3 2896 /* TAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2897 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2898 #define RTC_TAR_TAR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2899 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
sahilmgandhi 18:6a4db94011d3 2900 /* TCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2901 #define RTC_TCR_TCR_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2902 #define RTC_TCR_TCR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2903 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
sahilmgandhi 18:6a4db94011d3 2904 #define RTC_TCR_CIR_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 2905 #define RTC_TCR_CIR_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2906 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
sahilmgandhi 18:6a4db94011d3 2907 #define RTC_TCR_TCV_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 2908 #define RTC_TCR_TCV_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2909 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
sahilmgandhi 18:6a4db94011d3 2910 #define RTC_TCR_CIC_MASK 0xFF000000u
sahilmgandhi 18:6a4db94011d3 2911 #define RTC_TCR_CIC_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2912 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
sahilmgandhi 18:6a4db94011d3 2913 /* CR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2914 #define RTC_CR_SWR_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2915 #define RTC_CR_SWR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2916 #define RTC_CR_WPE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2917 #define RTC_CR_WPE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2918 #define RTC_CR_SUP_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2919 #define RTC_CR_SUP_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2920 #define RTC_CR_UM_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2921 #define RTC_CR_UM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2922 #define RTC_CR_OSCE_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2923 #define RTC_CR_OSCE_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2924 #define RTC_CR_CLKO_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2925 #define RTC_CR_CLKO_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2926 #define RTC_CR_SC16P_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 2927 #define RTC_CR_SC16P_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2928 #define RTC_CR_SC8P_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 2929 #define RTC_CR_SC8P_SHIFT 11
sahilmgandhi 18:6a4db94011d3 2930 #define RTC_CR_SC4P_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 2931 #define RTC_CR_SC4P_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2932 #define RTC_CR_SC2P_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 2933 #define RTC_CR_SC2P_SHIFT 13
sahilmgandhi 18:6a4db94011d3 2934 /* SR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2935 #define RTC_SR_TIF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2936 #define RTC_SR_TIF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2937 #define RTC_SR_TOF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2938 #define RTC_SR_TOF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2939 #define RTC_SR_TAF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2940 #define RTC_SR_TAF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2941 #define RTC_SR_TCE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2942 #define RTC_SR_TCE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2943 /* LR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2944 #define RTC_LR_TCL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2945 #define RTC_LR_TCL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2946 #define RTC_LR_CRL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2947 #define RTC_LR_CRL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2948 #define RTC_LR_SRL_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2949 #define RTC_LR_SRL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2950 #define RTC_LR_LRL_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2951 #define RTC_LR_LRL_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2952 /* IER Bit Fields */
sahilmgandhi 18:6a4db94011d3 2953 #define RTC_IER_TIIE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2954 #define RTC_IER_TIIE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2955 #define RTC_IER_TOIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2956 #define RTC_IER_TOIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2957 #define RTC_IER_TAIE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2958 #define RTC_IER_TAIE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2959 #define RTC_IER_TSIE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2960 #define RTC_IER_TSIE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2961 #define RTC_IER_WPON_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2962 #define RTC_IER_WPON_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2963
sahilmgandhi 18:6a4db94011d3 2964 /**
sahilmgandhi 18:6a4db94011d3 2965 * @}
sahilmgandhi 18:6a4db94011d3 2966 */ /* end of group RTC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2967
sahilmgandhi 18:6a4db94011d3 2968
sahilmgandhi 18:6a4db94011d3 2969 /* RTC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2970 /** Peripheral RTC base address */
sahilmgandhi 18:6a4db94011d3 2971 #define RTC_BASE (0x4003D000u)
sahilmgandhi 18:6a4db94011d3 2972 /** Peripheral RTC base pointer */
sahilmgandhi 18:6a4db94011d3 2973 #define RTC ((RTC_Type *)RTC_BASE)
sahilmgandhi 18:6a4db94011d3 2974 /** Array initializer of RTC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 2975 #define RTC_BASES { RTC }
sahilmgandhi 18:6a4db94011d3 2976
sahilmgandhi 18:6a4db94011d3 2977 /**
sahilmgandhi 18:6a4db94011d3 2978 * @}
sahilmgandhi 18:6a4db94011d3 2979 */ /* end of group RTC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2980
sahilmgandhi 18:6a4db94011d3 2981
sahilmgandhi 18:6a4db94011d3 2982 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2983 -- SIM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2984 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2985
sahilmgandhi 18:6a4db94011d3 2986 /**
sahilmgandhi 18:6a4db94011d3 2987 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2988 * @{
sahilmgandhi 18:6a4db94011d3 2989 */
sahilmgandhi 18:6a4db94011d3 2990
sahilmgandhi 18:6a4db94011d3 2991 /** SIM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2992 typedef struct {
sahilmgandhi 18:6a4db94011d3 2993 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2994 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2995 uint8_t RESERVED_0[4092];
sahilmgandhi 18:6a4db94011d3 2996 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
sahilmgandhi 18:6a4db94011d3 2997 uint8_t RESERVED_1[4];
sahilmgandhi 18:6a4db94011d3 2998 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
sahilmgandhi 18:6a4db94011d3 2999 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
sahilmgandhi 18:6a4db94011d3 3000 uint8_t RESERVED_2[4];
sahilmgandhi 18:6a4db94011d3 3001 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
sahilmgandhi 18:6a4db94011d3 3002 uint8_t RESERVED_3[8];
sahilmgandhi 18:6a4db94011d3 3003 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
sahilmgandhi 18:6a4db94011d3 3004 uint8_t RESERVED_4[12];
sahilmgandhi 18:6a4db94011d3 3005 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
sahilmgandhi 18:6a4db94011d3 3006 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
sahilmgandhi 18:6a4db94011d3 3007 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
sahilmgandhi 18:6a4db94011d3 3008 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
sahilmgandhi 18:6a4db94011d3 3009 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
sahilmgandhi 18:6a4db94011d3 3010 uint8_t RESERVED_5[4];
sahilmgandhi 18:6a4db94011d3 3011 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
sahilmgandhi 18:6a4db94011d3 3012 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
sahilmgandhi 18:6a4db94011d3 3013 uint8_t RESERVED_6[4];
sahilmgandhi 18:6a4db94011d3 3014 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
sahilmgandhi 18:6a4db94011d3 3015 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
sahilmgandhi 18:6a4db94011d3 3016 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
sahilmgandhi 18:6a4db94011d3 3017 uint8_t RESERVED_7[156];
sahilmgandhi 18:6a4db94011d3 3018 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
sahilmgandhi 18:6a4db94011d3 3019 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
sahilmgandhi 18:6a4db94011d3 3020 } SIM_Type;
sahilmgandhi 18:6a4db94011d3 3021
sahilmgandhi 18:6a4db94011d3 3022 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3023 -- SIM Register Masks
sahilmgandhi 18:6a4db94011d3 3024 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3025
sahilmgandhi 18:6a4db94011d3 3026 /**
sahilmgandhi 18:6a4db94011d3 3027 * @addtogroup SIM_Register_Masks SIM Register Masks
sahilmgandhi 18:6a4db94011d3 3028 * @{
sahilmgandhi 18:6a4db94011d3 3029 */
sahilmgandhi 18:6a4db94011d3 3030
sahilmgandhi 18:6a4db94011d3 3031 /* SOPT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3032 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 3033 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3034 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
sahilmgandhi 18:6a4db94011d3 3035 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 3036 #define SIM_SOPT1_USBVSTBY_SHIFT 29
sahilmgandhi 18:6a4db94011d3 3037 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 3038 #define SIM_SOPT1_USBSSTBY_SHIFT 30
sahilmgandhi 18:6a4db94011d3 3039 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 3040 #define SIM_SOPT1_USBREGEN_SHIFT 31
sahilmgandhi 18:6a4db94011d3 3041 /* SOPT1CFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 3042 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 3043 #define SIM_SOPT1CFG_URWE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3044 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 3045 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
sahilmgandhi 18:6a4db94011d3 3046 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 3047 #define SIM_SOPT1CFG_USSWE_SHIFT 26
sahilmgandhi 18:6a4db94011d3 3048 /* SOPT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3049 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3050 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3051 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
sahilmgandhi 18:6a4db94011d3 3052 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3053 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 3054 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 3055 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3056 #define SIM_SOPT2_USBSRC_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 3057 #define SIM_SOPT2_USBSRC_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3058 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
sahilmgandhi 18:6a4db94011d3 3059 #define SIM_SOPT2_TPMSRC_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3060 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
sahilmgandhi 18:6a4db94011d3 3061 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
sahilmgandhi 18:6a4db94011d3 3062 #define SIM_SOPT2_UART0SRC_SHIFT 26
sahilmgandhi 18:6a4db94011d3 3063 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
sahilmgandhi 18:6a4db94011d3 3064 /* SOPT4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3065 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 3066 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3067 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
sahilmgandhi 18:6a4db94011d3 3068 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 3069 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
sahilmgandhi 18:6a4db94011d3 3070 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 3071 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3072 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 3073 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
sahilmgandhi 18:6a4db94011d3 3074 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 3075 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
sahilmgandhi 18:6a4db94011d3 3076 /* SOPT5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3077 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 3078 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3079 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
sahilmgandhi 18:6a4db94011d3 3080 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3081 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3082 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 3083 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3084 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
sahilmgandhi 18:6a4db94011d3 3085 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3086 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3087 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 3088 #define SIM_SOPT5_UART0ODE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3089 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 3090 #define SIM_SOPT5_UART1ODE_SHIFT 17
sahilmgandhi 18:6a4db94011d3 3091 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 3092 #define SIM_SOPT5_UART2ODE_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3093 /* SOPT7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3094 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 3095 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3096 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
sahilmgandhi 18:6a4db94011d3 3097 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3098 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3099 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3100 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3101 /* SDID Bit Fields */
sahilmgandhi 18:6a4db94011d3 3102 #define SIM_SDID_PINID_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 3103 #define SIM_SDID_PINID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3104 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
sahilmgandhi 18:6a4db94011d3 3105 #define SIM_SDID_DIEID_MASK 0xF80u
sahilmgandhi 18:6a4db94011d3 3106 #define SIM_SDID_DIEID_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3107 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
sahilmgandhi 18:6a4db94011d3 3108 #define SIM_SDID_REVID_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 3109 #define SIM_SDID_REVID_SHIFT 12
sahilmgandhi 18:6a4db94011d3 3110 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
sahilmgandhi 18:6a4db94011d3 3111 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 3112 #define SIM_SDID_SRAMSIZE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3113 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 3114 #define SIM_SDID_SERIESID_MASK 0xF00000u
sahilmgandhi 18:6a4db94011d3 3115 #define SIM_SDID_SERIESID_SHIFT 20
sahilmgandhi 18:6a4db94011d3 3116 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
sahilmgandhi 18:6a4db94011d3 3117 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 3118 #define SIM_SDID_SUBFAMID_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3119 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
sahilmgandhi 18:6a4db94011d3 3120 #define SIM_SDID_FAMID_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 3121 #define SIM_SDID_FAMID_SHIFT 28
sahilmgandhi 18:6a4db94011d3 3122 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
sahilmgandhi 18:6a4db94011d3 3123 /* SCGC4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3124 #define SIM_SCGC4_I2C0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3125 #define SIM_SCGC4_I2C0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3126 #define SIM_SCGC4_I2C1_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3127 #define SIM_SCGC4_I2C1_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3128 #define SIM_SCGC4_UART0_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 3129 #define SIM_SCGC4_UART0_SHIFT 10
sahilmgandhi 18:6a4db94011d3 3130 #define SIM_SCGC4_UART1_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 3131 #define SIM_SCGC4_UART1_SHIFT 11
sahilmgandhi 18:6a4db94011d3 3132 #define SIM_SCGC4_UART2_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 3133 #define SIM_SCGC4_UART2_SHIFT 12
sahilmgandhi 18:6a4db94011d3 3134 #define SIM_SCGC4_USBOTG_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 3135 #define SIM_SCGC4_USBOTG_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3136 #define SIM_SCGC4_CMP_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 3137 #define SIM_SCGC4_CMP_SHIFT 19
sahilmgandhi 18:6a4db94011d3 3138 #define SIM_SCGC4_SPI0_MASK 0x400000u
sahilmgandhi 18:6a4db94011d3 3139 #define SIM_SCGC4_SPI0_SHIFT 22
sahilmgandhi 18:6a4db94011d3 3140 #define SIM_SCGC4_SPI1_MASK 0x800000u
sahilmgandhi 18:6a4db94011d3 3141 #define SIM_SCGC4_SPI1_SHIFT 23
sahilmgandhi 18:6a4db94011d3 3142 /* SCGC5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3143 #define SIM_SCGC5_LPTMR_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3144 #define SIM_SCGC5_LPTMR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3145 #define SIM_SCGC5_TSI_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3146 #define SIM_SCGC5_TSI_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3147 #define SIM_SCGC5_PORTA_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 3148 #define SIM_SCGC5_PORTA_SHIFT 9
sahilmgandhi 18:6a4db94011d3 3149 #define SIM_SCGC5_PORTB_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 3150 #define SIM_SCGC5_PORTB_SHIFT 10
sahilmgandhi 18:6a4db94011d3 3151 #define SIM_SCGC5_PORTC_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 3152 #define SIM_SCGC5_PORTC_SHIFT 11
sahilmgandhi 18:6a4db94011d3 3153 #define SIM_SCGC5_PORTD_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 3154 #define SIM_SCGC5_PORTD_SHIFT 12
sahilmgandhi 18:6a4db94011d3 3155 #define SIM_SCGC5_PORTE_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 3156 #define SIM_SCGC5_PORTE_SHIFT 13
sahilmgandhi 18:6a4db94011d3 3157 /* SCGC6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3158 #define SIM_SCGC6_FTF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3159 #define SIM_SCGC6_FTF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3160 #define SIM_SCGC6_DMAMUX_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3161 #define SIM_SCGC6_DMAMUX_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3162 #define SIM_SCGC6_I2S_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 3163 #define SIM_SCGC6_I2S_SHIFT 15
sahilmgandhi 18:6a4db94011d3 3164 #define SIM_SCGC6_PIT_MASK 0x800000u
sahilmgandhi 18:6a4db94011d3 3165 #define SIM_SCGC6_PIT_SHIFT 23
sahilmgandhi 18:6a4db94011d3 3166 #define SIM_SCGC6_TPM0_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 3167 #define SIM_SCGC6_TPM0_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3168 #define SIM_SCGC6_TPM1_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 3169 #define SIM_SCGC6_TPM1_SHIFT 25
sahilmgandhi 18:6a4db94011d3 3170 #define SIM_SCGC6_TPM2_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 3171 #define SIM_SCGC6_TPM2_SHIFT 26
sahilmgandhi 18:6a4db94011d3 3172 #define SIM_SCGC6_ADC0_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 3173 #define SIM_SCGC6_ADC0_SHIFT 27
sahilmgandhi 18:6a4db94011d3 3174 #define SIM_SCGC6_RTC_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 3175 #define SIM_SCGC6_RTC_SHIFT 29
sahilmgandhi 18:6a4db94011d3 3176 #define SIM_SCGC6_DAC0_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 3177 #define SIM_SCGC6_DAC0_SHIFT 31
sahilmgandhi 18:6a4db94011d3 3178 /* SCGC7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3179 #define SIM_SCGC7_DMA_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 3180 #define SIM_SCGC7_DMA_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3181 /* CLKDIV1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3182 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
sahilmgandhi 18:6a4db94011d3 3183 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3184 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
sahilmgandhi 18:6a4db94011d3 3185 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 3186 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
sahilmgandhi 18:6a4db94011d3 3187 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
sahilmgandhi 18:6a4db94011d3 3188 /* FCFG1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3189 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3190 #define SIM_FCFG1_FLASHDIS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3191 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3192 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3193 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 3194 #define SIM_FCFG1_PFSIZE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3195 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 3196 /* FCFG2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3197 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
sahilmgandhi 18:6a4db94011d3 3198 #define SIM_FCFG2_MAXADDR1_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3199 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
sahilmgandhi 18:6a4db94011d3 3200 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
sahilmgandhi 18:6a4db94011d3 3201 #define SIM_FCFG2_MAXADDR0_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3202 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
sahilmgandhi 18:6a4db94011d3 3203 /* UIDMH Bit Fields */
sahilmgandhi 18:6a4db94011d3 3204 #define SIM_UIDMH_UID_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3205 #define SIM_UIDMH_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3206 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
sahilmgandhi 18:6a4db94011d3 3207 /* UIDML Bit Fields */
sahilmgandhi 18:6a4db94011d3 3208 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3209 #define SIM_UIDML_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3210 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
sahilmgandhi 18:6a4db94011d3 3211 /* UIDL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3212 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3213 #define SIM_UIDL_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3214 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
sahilmgandhi 18:6a4db94011d3 3215 /* COPC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3216 #define SIM_COPC_COPW_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3217 #define SIM_COPC_COPW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3218 #define SIM_COPC_COPCLKS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3219 #define SIM_COPC_COPCLKS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3220 #define SIM_COPC_COPT_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 3221 #define SIM_COPC_COPT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3222 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
sahilmgandhi 18:6a4db94011d3 3223 /* SRVCOP Bit Fields */
sahilmgandhi 18:6a4db94011d3 3224 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3225 #define SIM_SRVCOP_SRVCOP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3226 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
sahilmgandhi 18:6a4db94011d3 3227
sahilmgandhi 18:6a4db94011d3 3228 /**
sahilmgandhi 18:6a4db94011d3 3229 * @}
sahilmgandhi 18:6a4db94011d3 3230 */ /* end of group SIM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3231
sahilmgandhi 18:6a4db94011d3 3232
sahilmgandhi 18:6a4db94011d3 3233 /* SIM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3234 /** Peripheral SIM base address */
sahilmgandhi 18:6a4db94011d3 3235 #define SIM_BASE (0x40047000u)
sahilmgandhi 18:6a4db94011d3 3236 /** Peripheral SIM base pointer */
sahilmgandhi 18:6a4db94011d3 3237 #define SIM ((SIM_Type *)SIM_BASE)
sahilmgandhi 18:6a4db94011d3 3238 /** Array initializer of SIM peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 3239 #define SIM_BASES { SIM }
sahilmgandhi 18:6a4db94011d3 3240
sahilmgandhi 18:6a4db94011d3 3241 /**
sahilmgandhi 18:6a4db94011d3 3242 * @}
sahilmgandhi 18:6a4db94011d3 3243 */ /* end of group SIM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3244
sahilmgandhi 18:6a4db94011d3 3245
sahilmgandhi 18:6a4db94011d3 3246 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3247 -- SMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3248 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3249
sahilmgandhi 18:6a4db94011d3 3250 /**
sahilmgandhi 18:6a4db94011d3 3251 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3252 * @{
sahilmgandhi 18:6a4db94011d3 3253 */
sahilmgandhi 18:6a4db94011d3 3254
sahilmgandhi 18:6a4db94011d3 3255 /** SMC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3256 typedef struct {
sahilmgandhi 18:6a4db94011d3 3257 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3258 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3259 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3260 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 3261 } SMC_Type;
sahilmgandhi 18:6a4db94011d3 3262
sahilmgandhi 18:6a4db94011d3 3263 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3264 -- SMC Register Masks
sahilmgandhi 18:6a4db94011d3 3265 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3266
sahilmgandhi 18:6a4db94011d3 3267 /**
sahilmgandhi 18:6a4db94011d3 3268 * @addtogroup SMC_Register_Masks SMC Register Masks
sahilmgandhi 18:6a4db94011d3 3269 * @{
sahilmgandhi 18:6a4db94011d3 3270 */
sahilmgandhi 18:6a4db94011d3 3271
sahilmgandhi 18:6a4db94011d3 3272 /* PMPROT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3273 #define SMC_PMPROT_AVLLS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3274 #define SMC_PMPROT_AVLLS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3275 #define SMC_PMPROT_ALLS_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3276 #define SMC_PMPROT_ALLS_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3277 #define SMC_PMPROT_AVLP_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3278 #define SMC_PMPROT_AVLP_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3279 /* PMCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3280 #define SMC_PMCTRL_STOPM_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 3281 #define SMC_PMCTRL_STOPM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3282 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
sahilmgandhi 18:6a4db94011d3 3283 #define SMC_PMCTRL_STOPA_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3284 #define SMC_PMCTRL_STOPA_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3285 #define SMC_PMCTRL_RUNM_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 3286 #define SMC_PMCTRL_RUNM_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3287 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
sahilmgandhi 18:6a4db94011d3 3288 /* STOPCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3289 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 3290 #define SMC_STOPCTRL_VLLSM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3291 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
sahilmgandhi 18:6a4db94011d3 3292 #define SMC_STOPCTRL_PORPO_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3293 #define SMC_STOPCTRL_PORPO_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3294 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 3295 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3296 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
sahilmgandhi 18:6a4db94011d3 3297 /* PMSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3298 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 3299 #define SMC_PMSTAT_PMSTAT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3300 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
sahilmgandhi 18:6a4db94011d3 3301
sahilmgandhi 18:6a4db94011d3 3302 /**
sahilmgandhi 18:6a4db94011d3 3303 * @}
sahilmgandhi 18:6a4db94011d3 3304 */ /* end of group SMC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3305
sahilmgandhi 18:6a4db94011d3 3306
sahilmgandhi 18:6a4db94011d3 3307 /* SMC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3308 /** Peripheral SMC base address */
sahilmgandhi 18:6a4db94011d3 3309 #define SMC_BASE (0x4007E000u)
sahilmgandhi 18:6a4db94011d3 3310 /** Peripheral SMC base pointer */
sahilmgandhi 18:6a4db94011d3 3311 #define SMC ((SMC_Type *)SMC_BASE)
sahilmgandhi 18:6a4db94011d3 3312 /** Array initializer of SMC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 3313 #define SMC_BASES { SMC }
sahilmgandhi 18:6a4db94011d3 3314
sahilmgandhi 18:6a4db94011d3 3315 /**
sahilmgandhi 18:6a4db94011d3 3316 * @}
sahilmgandhi 18:6a4db94011d3 3317 */ /* end of group SMC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3318
sahilmgandhi 18:6a4db94011d3 3319
sahilmgandhi 18:6a4db94011d3 3320 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3321 -- SPI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3322 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3323
sahilmgandhi 18:6a4db94011d3 3324 /**
sahilmgandhi 18:6a4db94011d3 3325 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3326 * @{
sahilmgandhi 18:6a4db94011d3 3327 */
sahilmgandhi 18:6a4db94011d3 3328
sahilmgandhi 18:6a4db94011d3 3329 /** SPI - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3330 typedef struct {
sahilmgandhi 18:6a4db94011d3 3331 __I uint8_t S; /**< SPI status register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3332 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3333 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3334 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 3335 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3336 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 3337 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 3338 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 3339 uint8_t RESERVED_0[2];
sahilmgandhi 18:6a4db94011d3 3340 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 3341 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 3342 } SPI_Type;
sahilmgandhi 18:6a4db94011d3 3343
sahilmgandhi 18:6a4db94011d3 3344 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3345 -- SPI Register Masks
sahilmgandhi 18:6a4db94011d3 3346 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3347
sahilmgandhi 18:6a4db94011d3 3348 /**
sahilmgandhi 18:6a4db94011d3 3349 * @addtogroup SPI_Register_Masks SPI Register Masks
sahilmgandhi 18:6a4db94011d3 3350 * @{
sahilmgandhi 18:6a4db94011d3 3351 */
sahilmgandhi 18:6a4db94011d3 3352
sahilmgandhi 18:6a4db94011d3 3353 /* S Bit Fields */
sahilmgandhi 18:6a4db94011d3 3354 #define SPI_S_RFIFOEF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3355 #define SPI_S_RFIFOEF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3356 #define SPI_S_TXFULLF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3357 #define SPI_S_TXFULLF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3358 #define SPI_S_TNEAREF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3359 #define SPI_S_TNEAREF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3360 #define SPI_S_RNFULLF_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3361 #define SPI_S_RNFULLF_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3362 #define SPI_S_MODF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3363 #define SPI_S_MODF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3364 #define SPI_S_SPTEF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3365 #define SPI_S_SPTEF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3366 #define SPI_S_SPMF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3367 #define SPI_S_SPMF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3368 #define SPI_S_SPRF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3369 #define SPI_S_SPRF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3370 /* BR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3371 #define SPI_BR_SPR_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 3372 #define SPI_BR_SPR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3373 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
sahilmgandhi 18:6a4db94011d3 3374 #define SPI_BR_SPPR_MASK 0x70u
sahilmgandhi 18:6a4db94011d3 3375 #define SPI_BR_SPPR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3376 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
sahilmgandhi 18:6a4db94011d3 3377 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3378 #define SPI_C2_SPC0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3379 #define SPI_C2_SPC0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3380 #define SPI_C2_SPISWAI_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3381 #define SPI_C2_SPISWAI_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3382 #define SPI_C2_RXDMAE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3383 #define SPI_C2_RXDMAE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3384 #define SPI_C2_BIDIROE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3385 #define SPI_C2_BIDIROE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3386 #define SPI_C2_MODFEN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3387 #define SPI_C2_MODFEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3388 #define SPI_C2_TXDMAE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3389 #define SPI_C2_TXDMAE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3390 #define SPI_C2_SPIMODE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3391 #define SPI_C2_SPIMODE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3392 #define SPI_C2_SPMIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3393 #define SPI_C2_SPMIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3394 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3395 #define SPI_C1_LSBFE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3396 #define SPI_C1_LSBFE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3397 #define SPI_C1_SSOE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3398 #define SPI_C1_SSOE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3399 #define SPI_C1_CPHA_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3400 #define SPI_C1_CPHA_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3401 #define SPI_C1_CPOL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3402 #define SPI_C1_CPOL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3403 #define SPI_C1_MSTR_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3404 #define SPI_C1_MSTR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3405 #define SPI_C1_SPTIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3406 #define SPI_C1_SPTIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3407 #define SPI_C1_SPE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3408 #define SPI_C1_SPE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3409 #define SPI_C1_SPIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3410 #define SPI_C1_SPIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3411 /* ML Bit Fields */
sahilmgandhi 18:6a4db94011d3 3412 #define SPI_ML_Bits_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3413 #define SPI_ML_Bits_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3414 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
sahilmgandhi 18:6a4db94011d3 3415 /* MH Bit Fields */
sahilmgandhi 18:6a4db94011d3 3416 #define SPI_MH_Bits_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3417 #define SPI_MH_Bits_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3418 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
sahilmgandhi 18:6a4db94011d3 3419 /* DL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3420 #define SPI_DL_Bits_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3421 #define SPI_DL_Bits_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3422 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
sahilmgandhi 18:6a4db94011d3 3423 /* DH Bit Fields */
sahilmgandhi 18:6a4db94011d3 3424 #define SPI_DH_Bits_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3425 #define SPI_DH_Bits_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3426 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
sahilmgandhi 18:6a4db94011d3 3427 /* CI Bit Fields */
sahilmgandhi 18:6a4db94011d3 3428 #define SPI_CI_SPRFCI_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3429 #define SPI_CI_SPRFCI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3430 #define SPI_CI_SPTEFCI_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3431 #define SPI_CI_SPTEFCI_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3432 #define SPI_CI_RNFULLFCI_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3433 #define SPI_CI_RNFULLFCI_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3434 #define SPI_CI_TNEAREFCI_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3435 #define SPI_CI_TNEAREFCI_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3436 #define SPI_CI_RXFOF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3437 #define SPI_CI_RXFOF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3438 #define SPI_CI_TXFOF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3439 #define SPI_CI_TXFOF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3440 #define SPI_CI_RXFERR_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3441 #define SPI_CI_RXFERR_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3442 #define SPI_CI_TXFERR_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3443 #define SPI_CI_TXFERR_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3444 /* C3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3445 #define SPI_C3_FIFOMODE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3446 #define SPI_C3_FIFOMODE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3447 #define SPI_C3_RNFULLIEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3448 #define SPI_C3_RNFULLIEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3449 #define SPI_C3_TNEARIEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3450 #define SPI_C3_TNEARIEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3451 #define SPI_C3_INTCLR_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3452 #define SPI_C3_INTCLR_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3453 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3454 #define SPI_C3_RNFULLF_MARK_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3455 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3456 #define SPI_C3_TNEAREF_MARK_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3457
sahilmgandhi 18:6a4db94011d3 3458 /**
sahilmgandhi 18:6a4db94011d3 3459 * @}
sahilmgandhi 18:6a4db94011d3 3460 */ /* end of group SPI_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3461
sahilmgandhi 18:6a4db94011d3 3462
sahilmgandhi 18:6a4db94011d3 3463 /* SPI - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3464 /** Peripheral SPI0 base address */
sahilmgandhi 18:6a4db94011d3 3465 #define SPI0_BASE (0x40076000u)
sahilmgandhi 18:6a4db94011d3 3466 /** Peripheral SPI0 base pointer */
sahilmgandhi 18:6a4db94011d3 3467 #define SPI0 ((SPI_Type *)SPI0_BASE)
sahilmgandhi 18:6a4db94011d3 3468 /** Peripheral SPI1 base address */
sahilmgandhi 18:6a4db94011d3 3469 #define SPI1_BASE (0x40077000u)
sahilmgandhi 18:6a4db94011d3 3470 /** Peripheral SPI1 base pointer */
sahilmgandhi 18:6a4db94011d3 3471 #define SPI1 ((SPI_Type *)SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 3472 /** Array initializer of SPI peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 3473 #define SPI_BASES { SPI0, SPI1 }
sahilmgandhi 18:6a4db94011d3 3474
sahilmgandhi 18:6a4db94011d3 3475 /**
sahilmgandhi 18:6a4db94011d3 3476 * @}
sahilmgandhi 18:6a4db94011d3 3477 */ /* end of group SPI_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3478
sahilmgandhi 18:6a4db94011d3 3479
sahilmgandhi 18:6a4db94011d3 3480 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3481 -- TPM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3482 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3483
sahilmgandhi 18:6a4db94011d3 3484 /**
sahilmgandhi 18:6a4db94011d3 3485 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3486 * @{
sahilmgandhi 18:6a4db94011d3 3487 */
sahilmgandhi 18:6a4db94011d3 3488
sahilmgandhi 18:6a4db94011d3 3489 /** TPM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3490 typedef struct {
sahilmgandhi 18:6a4db94011d3 3491 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3492 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3493 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3494 struct { /* offset: 0xC, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 3495 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 3496 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 3497 } CONTROLS[6];
sahilmgandhi 18:6a4db94011d3 3498 uint8_t RESERVED_0[20];
sahilmgandhi 18:6a4db94011d3 3499 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 3500 uint8_t RESERVED_1[48];
sahilmgandhi 18:6a4db94011d3 3501 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 3502 } TPM_Type;
sahilmgandhi 18:6a4db94011d3 3503
sahilmgandhi 18:6a4db94011d3 3504 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3505 -- TPM Register Masks
sahilmgandhi 18:6a4db94011d3 3506 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3507
sahilmgandhi 18:6a4db94011d3 3508 /**
sahilmgandhi 18:6a4db94011d3 3509 * @addtogroup TPM_Register_Masks TPM Register Masks
sahilmgandhi 18:6a4db94011d3 3510 * @{
sahilmgandhi 18:6a4db94011d3 3511 */
sahilmgandhi 18:6a4db94011d3 3512
sahilmgandhi 18:6a4db94011d3 3513 /* SC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3514 #define TPM_SC_PS_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 3515 #define TPM_SC_PS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3516 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
sahilmgandhi 18:6a4db94011d3 3517 #define TPM_SC_CMOD_MASK 0x18u
sahilmgandhi 18:6a4db94011d3 3518 #define TPM_SC_CMOD_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3519 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
sahilmgandhi 18:6a4db94011d3 3520 #define TPM_SC_CPWMS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3521 #define TPM_SC_CPWMS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3522 #define TPM_SC_TOIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3523 #define TPM_SC_TOIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3524 #define TPM_SC_TOF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3525 #define TPM_SC_TOF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3526 #define TPM_SC_DMA_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 3527 #define TPM_SC_DMA_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3528 /* CNT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3529 #define TPM_CNT_COUNT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3530 #define TPM_CNT_COUNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3531 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
sahilmgandhi 18:6a4db94011d3 3532 /* MOD Bit Fields */
sahilmgandhi 18:6a4db94011d3 3533 #define TPM_MOD_MOD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3534 #define TPM_MOD_MOD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3535 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
sahilmgandhi 18:6a4db94011d3 3536 /* CnSC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3537 #define TPM_CnSC_DMA_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3538 #define TPM_CnSC_DMA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3539 #define TPM_CnSC_ELSA_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3540 #define TPM_CnSC_ELSA_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3541 #define TPM_CnSC_ELSB_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3542 #define TPM_CnSC_ELSB_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3543 #define TPM_CnSC_MSA_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3544 #define TPM_CnSC_MSA_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3545 #define TPM_CnSC_MSB_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3546 #define TPM_CnSC_MSB_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3547 #define TPM_CnSC_CHIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3548 #define TPM_CnSC_CHIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3549 #define TPM_CnSC_CHF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3550 #define TPM_CnSC_CHF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3551 /* CnV Bit Fields */
sahilmgandhi 18:6a4db94011d3 3552 #define TPM_CnV_VAL_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3553 #define TPM_CnV_VAL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3554 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
sahilmgandhi 18:6a4db94011d3 3555 /* STATUS Bit Fields */
sahilmgandhi 18:6a4db94011d3 3556 #define TPM_STATUS_CH0F_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3557 #define TPM_STATUS_CH0F_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3558 #define TPM_STATUS_CH1F_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3559 #define TPM_STATUS_CH1F_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3560 #define TPM_STATUS_CH2F_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3561 #define TPM_STATUS_CH2F_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3562 #define TPM_STATUS_CH3F_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3563 #define TPM_STATUS_CH3F_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3564 #define TPM_STATUS_CH4F_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3565 #define TPM_STATUS_CH4F_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3566 #define TPM_STATUS_CH5F_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3567 #define TPM_STATUS_CH5F_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3568 #define TPM_STATUS_TOF_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 3569 #define TPM_STATUS_TOF_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3570 /* CONF Bit Fields */
sahilmgandhi 18:6a4db94011d3 3571 #define TPM_CONF_DOZEEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3572 #define TPM_CONF_DOZEEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3573 #define TPM_CONF_DBGMODE_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 3574 #define TPM_CONF_DBGMODE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3575 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
sahilmgandhi 18:6a4db94011d3 3576 #define TPM_CONF_GTBEEN_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 3577 #define TPM_CONF_GTBEEN_SHIFT 9
sahilmgandhi 18:6a4db94011d3 3578 #define TPM_CONF_CSOT_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 3579 #define TPM_CONF_CSOT_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3580 #define TPM_CONF_CSOO_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 3581 #define TPM_CONF_CSOO_SHIFT 17
sahilmgandhi 18:6a4db94011d3 3582 #define TPM_CONF_CROT_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 3583 #define TPM_CONF_CROT_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3584 #define TPM_CONF_TRGSEL_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 3585 #define TPM_CONF_TRGSEL_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3586 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
sahilmgandhi 18:6a4db94011d3 3587
sahilmgandhi 18:6a4db94011d3 3588 /**
sahilmgandhi 18:6a4db94011d3 3589 * @}
sahilmgandhi 18:6a4db94011d3 3590 */ /* end of group TPM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3591
sahilmgandhi 18:6a4db94011d3 3592
sahilmgandhi 18:6a4db94011d3 3593 /* TPM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3594 /** Peripheral TPM0 base address */
sahilmgandhi 18:6a4db94011d3 3595 #define TPM0_BASE (0x40038000u)
sahilmgandhi 18:6a4db94011d3 3596 /** Peripheral TPM0 base pointer */
sahilmgandhi 18:6a4db94011d3 3597 #define TPM0 ((TPM_Type *)TPM0_BASE)
sahilmgandhi 18:6a4db94011d3 3598 /** Peripheral TPM1 base address */
sahilmgandhi 18:6a4db94011d3 3599 #define TPM1_BASE (0x40039000u)
sahilmgandhi 18:6a4db94011d3 3600 /** Peripheral TPM1 base pointer */
sahilmgandhi 18:6a4db94011d3 3601 #define TPM1 ((TPM_Type *)TPM1_BASE)
sahilmgandhi 18:6a4db94011d3 3602 /** Peripheral TPM2 base address */
sahilmgandhi 18:6a4db94011d3 3603 #define TPM2_BASE (0x4003A000u)
sahilmgandhi 18:6a4db94011d3 3604 /** Peripheral TPM2 base pointer */
sahilmgandhi 18:6a4db94011d3 3605 #define TPM2 ((TPM_Type *)TPM2_BASE)
sahilmgandhi 18:6a4db94011d3 3606 /** Array initializer of TPM peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 3607 #define TPM_BASES { TPM0, TPM1, TPM2 }
sahilmgandhi 18:6a4db94011d3 3608
sahilmgandhi 18:6a4db94011d3 3609 /**
sahilmgandhi 18:6a4db94011d3 3610 * @}
sahilmgandhi 18:6a4db94011d3 3611 */ /* end of group TPM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3612
sahilmgandhi 18:6a4db94011d3 3613
sahilmgandhi 18:6a4db94011d3 3614 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3615 -- TSI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3616 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3617
sahilmgandhi 18:6a4db94011d3 3618 /**
sahilmgandhi 18:6a4db94011d3 3619 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3620 * @{
sahilmgandhi 18:6a4db94011d3 3621 */
sahilmgandhi 18:6a4db94011d3 3622
sahilmgandhi 18:6a4db94011d3 3623 /** TSI - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3624 typedef struct {
sahilmgandhi 18:6a4db94011d3 3625 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3626 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3627 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3628 } TSI_Type;
sahilmgandhi 18:6a4db94011d3 3629
sahilmgandhi 18:6a4db94011d3 3630 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3631 -- TSI Register Masks
sahilmgandhi 18:6a4db94011d3 3632 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3633
sahilmgandhi 18:6a4db94011d3 3634 /**
sahilmgandhi 18:6a4db94011d3 3635 * @addtogroup TSI_Register_Masks TSI Register Masks
sahilmgandhi 18:6a4db94011d3 3636 * @{
sahilmgandhi 18:6a4db94011d3 3637 */
sahilmgandhi 18:6a4db94011d3 3638
sahilmgandhi 18:6a4db94011d3 3639 /* GENCS Bit Fields */
sahilmgandhi 18:6a4db94011d3 3640 #define TSI_GENCS_CURSW_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3641 #define TSI_GENCS_CURSW_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3642 #define TSI_GENCS_EOSF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3643 #define TSI_GENCS_EOSF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3644 #define TSI_GENCS_SCNIP_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3645 #define TSI_GENCS_SCNIP_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3646 #define TSI_GENCS_STM_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3647 #define TSI_GENCS_STM_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3648 #define TSI_GENCS_STPE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3649 #define TSI_GENCS_STPE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3650 #define TSI_GENCS_TSIIEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3651 #define TSI_GENCS_TSIIEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3652 #define TSI_GENCS_TSIEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3653 #define TSI_GENCS_TSIEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3654 #define TSI_GENCS_NSCN_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 3655 #define TSI_GENCS_NSCN_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3656 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
sahilmgandhi 18:6a4db94011d3 3657 #define TSI_GENCS_PS_MASK 0xE000u
sahilmgandhi 18:6a4db94011d3 3658 #define TSI_GENCS_PS_SHIFT 13
sahilmgandhi 18:6a4db94011d3 3659 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
sahilmgandhi 18:6a4db94011d3 3660 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
sahilmgandhi 18:6a4db94011d3 3661 #define TSI_GENCS_EXTCHRG_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3662 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
sahilmgandhi 18:6a4db94011d3 3663 #define TSI_GENCS_DVOLT_MASK 0x180000u
sahilmgandhi 18:6a4db94011d3 3664 #define TSI_GENCS_DVOLT_SHIFT 19
sahilmgandhi 18:6a4db94011d3 3665 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
sahilmgandhi 18:6a4db94011d3 3666 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
sahilmgandhi 18:6a4db94011d3 3667 #define TSI_GENCS_REFCHRG_SHIFT 21
sahilmgandhi 18:6a4db94011d3 3668 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
sahilmgandhi 18:6a4db94011d3 3669 #define TSI_GENCS_MODE_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 3670 #define TSI_GENCS_MODE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3671 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
sahilmgandhi 18:6a4db94011d3 3672 #define TSI_GENCS_ESOR_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 3673 #define TSI_GENCS_ESOR_SHIFT 28
sahilmgandhi 18:6a4db94011d3 3674 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 3675 #define TSI_GENCS_OUTRGF_SHIFT 31
sahilmgandhi 18:6a4db94011d3 3676 /* DATA Bit Fields */
sahilmgandhi 18:6a4db94011d3 3677 #define TSI_DATA_TSICNT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3678 #define TSI_DATA_TSICNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3679 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
sahilmgandhi 18:6a4db94011d3 3680 #define TSI_DATA_SWTS_MASK 0x400000u
sahilmgandhi 18:6a4db94011d3 3681 #define TSI_DATA_SWTS_SHIFT 22
sahilmgandhi 18:6a4db94011d3 3682 #define TSI_DATA_DMAEN_MASK 0x800000u
sahilmgandhi 18:6a4db94011d3 3683 #define TSI_DATA_DMAEN_SHIFT 23
sahilmgandhi 18:6a4db94011d3 3684 #define TSI_DATA_TSICH_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 3685 #define TSI_DATA_TSICH_SHIFT 28
sahilmgandhi 18:6a4db94011d3 3686 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
sahilmgandhi 18:6a4db94011d3 3687 /* TSHD Bit Fields */
sahilmgandhi 18:6a4db94011d3 3688 #define TSI_TSHD_THRESL_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3689 #define TSI_TSHD_THRESL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3690 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
sahilmgandhi 18:6a4db94011d3 3691 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 3692 #define TSI_TSHD_THRESH_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3693 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
sahilmgandhi 18:6a4db94011d3 3694
sahilmgandhi 18:6a4db94011d3 3695 /**
sahilmgandhi 18:6a4db94011d3 3696 * @}
sahilmgandhi 18:6a4db94011d3 3697 */ /* end of group TSI_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3698
sahilmgandhi 18:6a4db94011d3 3699
sahilmgandhi 18:6a4db94011d3 3700 /* TSI - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3701 /** Peripheral TSI0 base address */
sahilmgandhi 18:6a4db94011d3 3702 #define TSI0_BASE (0x40045000u)
sahilmgandhi 18:6a4db94011d3 3703 /** Peripheral TSI0 base pointer */
sahilmgandhi 18:6a4db94011d3 3704 #define TSI0 ((TSI_Type *)TSI0_BASE)
sahilmgandhi 18:6a4db94011d3 3705 /** Array initializer of TSI peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 3706 #define TSI_BASES { TSI0 }
sahilmgandhi 18:6a4db94011d3 3707
sahilmgandhi 18:6a4db94011d3 3708 /**
sahilmgandhi 18:6a4db94011d3 3709 * @}
sahilmgandhi 18:6a4db94011d3 3710 */ /* end of group TSI_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3711
sahilmgandhi 18:6a4db94011d3 3712
sahilmgandhi 18:6a4db94011d3 3713 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3714 -- UART Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3715 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3716
sahilmgandhi 18:6a4db94011d3 3717 /**
sahilmgandhi 18:6a4db94011d3 3718 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3719 * @{
sahilmgandhi 18:6a4db94011d3 3720 */
sahilmgandhi 18:6a4db94011d3 3721
sahilmgandhi 18:6a4db94011d3 3722 /** UART - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3723 typedef struct {
sahilmgandhi 18:6a4db94011d3 3724 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3725 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3726 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3727 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 3728 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3729 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 3730 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 3731 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 3732 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3733 } UART_Type;
sahilmgandhi 18:6a4db94011d3 3734
sahilmgandhi 18:6a4db94011d3 3735 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3736 -- UART Register Masks
sahilmgandhi 18:6a4db94011d3 3737 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3738
sahilmgandhi 18:6a4db94011d3 3739 /**
sahilmgandhi 18:6a4db94011d3 3740 * @addtogroup UART_Register_Masks UART Register Masks
sahilmgandhi 18:6a4db94011d3 3741 * @{
sahilmgandhi 18:6a4db94011d3 3742 */
sahilmgandhi 18:6a4db94011d3 3743
sahilmgandhi 18:6a4db94011d3 3744 /* BDH Bit Fields */
sahilmgandhi 18:6a4db94011d3 3745 #define UART_BDH_SBR_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 3746 #define UART_BDH_SBR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3747 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
sahilmgandhi 18:6a4db94011d3 3748 #define UART_BDH_SBNS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3749 #define UART_BDH_SBNS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3750 #define UART_BDH_RXEDGIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3751 #define UART_BDH_RXEDGIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3752 #define UART_BDH_LBKDIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3753 #define UART_BDH_LBKDIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3754 /* BDL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3755 #define UART_BDL_SBR_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3756 #define UART_BDL_SBR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3757 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
sahilmgandhi 18:6a4db94011d3 3758 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3759 #define UART_C1_PT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3760 #define UART_C1_PT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3761 #define UART_C1_PE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3762 #define UART_C1_PE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3763 #define UART_C1_ILT_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3764 #define UART_C1_ILT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3765 #define UART_C1_WAKE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3766 #define UART_C1_WAKE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3767 #define UART_C1_M_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3768 #define UART_C1_M_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3769 #define UART_C1_RSRC_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3770 #define UART_C1_RSRC_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3771 #define UART_C1_UARTSWAI_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3772 #define UART_C1_UARTSWAI_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3773 #define UART_C1_LOOPS_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3774 #define UART_C1_LOOPS_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3775 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3776 #define UART_C2_SBK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3777 #define UART_C2_SBK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3778 #define UART_C2_RWU_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3779 #define UART_C2_RWU_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3780 #define UART_C2_RE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3781 #define UART_C2_RE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3782 #define UART_C2_TE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3783 #define UART_C2_TE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3784 #define UART_C2_ILIE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3785 #define UART_C2_ILIE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3786 #define UART_C2_RIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3787 #define UART_C2_RIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3788 #define UART_C2_TCIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3789 #define UART_C2_TCIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3790 #define UART_C2_TIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3791 #define UART_C2_TIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3792 /* S1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3793 #define UART_S1_PF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3794 #define UART_S1_PF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3795 #define UART_S1_FE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3796 #define UART_S1_FE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3797 #define UART_S1_NF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3798 #define UART_S1_NF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3799 #define UART_S1_OR_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3800 #define UART_S1_OR_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3801 #define UART_S1_IDLE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3802 #define UART_S1_IDLE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3803 #define UART_S1_RDRF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3804 #define UART_S1_RDRF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3805 #define UART_S1_TC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3806 #define UART_S1_TC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3807 #define UART_S1_TDRE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3808 #define UART_S1_TDRE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3809 /* S2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3810 #define UART_S2_RAF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3811 #define UART_S2_RAF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3812 #define UART_S2_LBKDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3813 #define UART_S2_LBKDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3814 #define UART_S2_BRK13_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3815 #define UART_S2_BRK13_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3816 #define UART_S2_RWUID_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3817 #define UART_S2_RWUID_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3818 #define UART_S2_RXINV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3819 #define UART_S2_RXINV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3820 #define UART_S2_RXEDGIF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3821 #define UART_S2_RXEDGIF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3822 #define UART_S2_LBKDIF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3823 #define UART_S2_LBKDIF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3824 /* C3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3825 #define UART_C3_PEIE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3826 #define UART_C3_PEIE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3827 #define UART_C3_FEIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3828 #define UART_C3_FEIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3829 #define UART_C3_NEIE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3830 #define UART_C3_NEIE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3831 #define UART_C3_ORIE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3832 #define UART_C3_ORIE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3833 #define UART_C3_TXINV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3834 #define UART_C3_TXINV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3835 #define UART_C3_TXDIR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3836 #define UART_C3_TXDIR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3837 #define UART_C3_T8_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3838 #define UART_C3_T8_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3839 #define UART_C3_R8_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3840 #define UART_C3_R8_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3841 /* D Bit Fields */
sahilmgandhi 18:6a4db94011d3 3842 #define UART_D_R0T0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3843 #define UART_D_R0T0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3844 #define UART_D_R1T1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3845 #define UART_D_R1T1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3846 #define UART_D_R2T2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3847 #define UART_D_R2T2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3848 #define UART_D_R3T3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3849 #define UART_D_R3T3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3850 #define UART_D_R4T4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3851 #define UART_D_R4T4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3852 #define UART_D_R5T5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3853 #define UART_D_R5T5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3854 #define UART_D_R6T6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3855 #define UART_D_R6T6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3856 #define UART_D_R7T7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3857 #define UART_D_R7T7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3858 /* C4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3859 #define UART_C4_RDMAS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3860 #define UART_C4_RDMAS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3861 #define UART_C4_TDMAS_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3862 #define UART_C4_TDMAS_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3863
sahilmgandhi 18:6a4db94011d3 3864 /**
sahilmgandhi 18:6a4db94011d3 3865 * @}
sahilmgandhi 18:6a4db94011d3 3866 */ /* end of group UART_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3867
sahilmgandhi 18:6a4db94011d3 3868
sahilmgandhi 18:6a4db94011d3 3869 /* UART - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3870 /** Peripheral UART1 base address */
sahilmgandhi 18:6a4db94011d3 3871 #define UART1_BASE (0x4006B000u)
sahilmgandhi 18:6a4db94011d3 3872 /** Peripheral UART1 base pointer */
sahilmgandhi 18:6a4db94011d3 3873 #define UART1 ((UART_Type *)UART1_BASE)
sahilmgandhi 18:6a4db94011d3 3874 /** Peripheral UART2 base address */
sahilmgandhi 18:6a4db94011d3 3875 #define UART2_BASE (0x4006C000u)
sahilmgandhi 18:6a4db94011d3 3876 /** Peripheral UART2 base pointer */
sahilmgandhi 18:6a4db94011d3 3877 #define UART2 ((UART_Type *)UART2_BASE)
sahilmgandhi 18:6a4db94011d3 3878 /** Array initializer of UART peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 3879 #define UART_BASES { UART1, UART2 }
sahilmgandhi 18:6a4db94011d3 3880
sahilmgandhi 18:6a4db94011d3 3881 /**
sahilmgandhi 18:6a4db94011d3 3882 * @}
sahilmgandhi 18:6a4db94011d3 3883 */ /* end of group UART_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3884
sahilmgandhi 18:6a4db94011d3 3885
sahilmgandhi 18:6a4db94011d3 3886 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3887 -- UART0 Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3888 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3889
sahilmgandhi 18:6a4db94011d3 3890 /**
sahilmgandhi 18:6a4db94011d3 3891 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3892 * @{
sahilmgandhi 18:6a4db94011d3 3893 */
sahilmgandhi 18:6a4db94011d3 3894
sahilmgandhi 18:6a4db94011d3 3895 /** UART0 - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3896 typedef struct {
sahilmgandhi 18:6a4db94011d3 3897 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3898 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3899 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3900 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 3901 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3902 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 3903 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 3904 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 3905 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3906 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 3907 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 3908 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 3909 } UART0_Type;
sahilmgandhi 18:6a4db94011d3 3910
sahilmgandhi 18:6a4db94011d3 3911 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3912 -- UART0 Register Masks
sahilmgandhi 18:6a4db94011d3 3913 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3914
sahilmgandhi 18:6a4db94011d3 3915 /**
sahilmgandhi 18:6a4db94011d3 3916 * @addtogroup UART0_Register_Masks UART0 Register Masks
sahilmgandhi 18:6a4db94011d3 3917 * @{
sahilmgandhi 18:6a4db94011d3 3918 */
sahilmgandhi 18:6a4db94011d3 3919
sahilmgandhi 18:6a4db94011d3 3920 /* BDH Bit Fields */
sahilmgandhi 18:6a4db94011d3 3921 #define UART0_BDH_SBR_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 3922 #define UART0_BDH_SBR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3923 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
sahilmgandhi 18:6a4db94011d3 3924 #define UART0_BDH_SBNS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3925 #define UART0_BDH_SBNS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3926 #define UART0_BDH_RXEDGIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3927 #define UART0_BDH_RXEDGIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3928 #define UART0_BDH_LBKDIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3929 #define UART0_BDH_LBKDIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3930 /* BDL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3931 #define UART0_BDL_SBR_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3932 #define UART0_BDL_SBR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3933 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
sahilmgandhi 18:6a4db94011d3 3934 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3935 #define UART0_C1_PT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3936 #define UART0_C1_PT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3937 #define UART0_C1_PE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3938 #define UART0_C1_PE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3939 #define UART0_C1_ILT_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3940 #define UART0_C1_ILT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3941 #define UART0_C1_WAKE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3942 #define UART0_C1_WAKE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3943 #define UART0_C1_M_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3944 #define UART0_C1_M_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3945 #define UART0_C1_RSRC_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3946 #define UART0_C1_RSRC_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3947 #define UART0_C1_DOZEEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3948 #define UART0_C1_DOZEEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3949 #define UART0_C1_LOOPS_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3950 #define UART0_C1_LOOPS_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3951 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3952 #define UART0_C2_SBK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3953 #define UART0_C2_SBK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3954 #define UART0_C2_RWU_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3955 #define UART0_C2_RWU_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3956 #define UART0_C2_RE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3957 #define UART0_C2_RE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3958 #define UART0_C2_TE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3959 #define UART0_C2_TE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3960 #define UART0_C2_ILIE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3961 #define UART0_C2_ILIE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3962 #define UART0_C2_RIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3963 #define UART0_C2_RIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3964 #define UART0_C2_TCIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3965 #define UART0_C2_TCIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3966 #define UART0_C2_TIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3967 #define UART0_C2_TIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3968 /* S1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3969 #define UART0_S1_PF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3970 #define UART0_S1_PF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3971 #define UART0_S1_FE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3972 #define UART0_S1_FE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3973 #define UART0_S1_NF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3974 #define UART0_S1_NF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3975 #define UART0_S1_OR_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3976 #define UART0_S1_OR_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3977 #define UART0_S1_IDLE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3978 #define UART0_S1_IDLE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3979 #define UART0_S1_RDRF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3980 #define UART0_S1_RDRF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3981 #define UART0_S1_TC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3982 #define UART0_S1_TC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3983 #define UART0_S1_TDRE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3984 #define UART0_S1_TDRE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3985 /* S2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3986 #define UART0_S2_RAF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3987 #define UART0_S2_RAF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3988 #define UART0_S2_LBKDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3989 #define UART0_S2_LBKDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3990 #define UART0_S2_BRK13_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3991 #define UART0_S2_BRK13_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3992 #define UART0_S2_RWUID_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3993 #define UART0_S2_RWUID_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3994 #define UART0_S2_RXINV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3995 #define UART0_S2_RXINV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3996 #define UART0_S2_MSBF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3997 #define UART0_S2_MSBF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3998 #define UART0_S2_RXEDGIF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3999 #define UART0_S2_RXEDGIF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4000 #define UART0_S2_LBKDIF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4001 #define UART0_S2_LBKDIF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4002 /* C3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4003 #define UART0_C3_PEIE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4004 #define UART0_C3_PEIE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4005 #define UART0_C3_FEIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4006 #define UART0_C3_FEIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4007 #define UART0_C3_NEIE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4008 #define UART0_C3_NEIE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4009 #define UART0_C3_ORIE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4010 #define UART0_C3_ORIE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4011 #define UART0_C3_TXINV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4012 #define UART0_C3_TXINV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4013 #define UART0_C3_TXDIR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4014 #define UART0_C3_TXDIR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4015 #define UART0_C3_R9T8_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4016 #define UART0_C3_R9T8_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4017 #define UART0_C3_R8T9_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4018 #define UART0_C3_R8T9_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4019 /* D Bit Fields */
sahilmgandhi 18:6a4db94011d3 4020 #define UART0_D_R0T0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4021 #define UART0_D_R0T0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4022 #define UART0_D_R1T1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4023 #define UART0_D_R1T1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4024 #define UART0_D_R2T2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4025 #define UART0_D_R2T2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4026 #define UART0_D_R3T3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4027 #define UART0_D_R3T3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4028 #define UART0_D_R4T4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4029 #define UART0_D_R4T4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4030 #define UART0_D_R5T5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4031 #define UART0_D_R5T5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4032 #define UART0_D_R6T6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4033 #define UART0_D_R6T6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4034 #define UART0_D_R7T7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4035 #define UART0_D_R7T7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4036 /* MA1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4037 #define UART0_MA1_MA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4038 #define UART0_MA1_MA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4039 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
sahilmgandhi 18:6a4db94011d3 4040 /* MA2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4041 #define UART0_MA2_MA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4042 #define UART0_MA2_MA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4043 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
sahilmgandhi 18:6a4db94011d3 4044 /* C4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4045 #define UART0_C4_OSR_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 4046 #define UART0_C4_OSR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4047 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
sahilmgandhi 18:6a4db94011d3 4048 #define UART0_C4_M10_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4049 #define UART0_C4_M10_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4050 #define UART0_C4_MAEN2_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4051 #define UART0_C4_MAEN2_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4052 #define UART0_C4_MAEN1_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4053 #define UART0_C4_MAEN1_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4054 /* C5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4055 #define UART0_C5_RESYNCDIS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4056 #define UART0_C5_RESYNCDIS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4057 #define UART0_C5_BOTHEDGE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4058 #define UART0_C5_BOTHEDGE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4059 #define UART0_C5_RDMAE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4060 #define UART0_C5_RDMAE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4061 #define UART0_C5_TDMAE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4062 #define UART0_C5_TDMAE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4063
sahilmgandhi 18:6a4db94011d3 4064 /**
sahilmgandhi 18:6a4db94011d3 4065 * @}
sahilmgandhi 18:6a4db94011d3 4066 */ /* end of group UART0_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4067
sahilmgandhi 18:6a4db94011d3 4068
sahilmgandhi 18:6a4db94011d3 4069 /* UART0 - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4070 /** Peripheral UART0 base address */
sahilmgandhi 18:6a4db94011d3 4071 #define UART0_BASE (0x4006A000u)
sahilmgandhi 18:6a4db94011d3 4072 /** Peripheral UART0 base pointer */
sahilmgandhi 18:6a4db94011d3 4073 #define UART0 ((UART0_Type *)UART0_BASE)
sahilmgandhi 18:6a4db94011d3 4074 /** Array initializer of UART0 peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 4075 #define UART0_BASES { UART0 }
sahilmgandhi 18:6a4db94011d3 4076
sahilmgandhi 18:6a4db94011d3 4077 /**
sahilmgandhi 18:6a4db94011d3 4078 * @}
sahilmgandhi 18:6a4db94011d3 4079 */ /* end of group UART0_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4080
sahilmgandhi 18:6a4db94011d3 4081
sahilmgandhi 18:6a4db94011d3 4082 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4083 -- USB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4084 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4085
sahilmgandhi 18:6a4db94011d3 4086 /**
sahilmgandhi 18:6a4db94011d3 4087 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4088 * @{
sahilmgandhi 18:6a4db94011d3 4089 */
sahilmgandhi 18:6a4db94011d3 4090
sahilmgandhi 18:6a4db94011d3 4091 /** USB - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 4092 typedef struct {
sahilmgandhi 18:6a4db94011d3 4093 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 4094 uint8_t RESERVED_0[3];
sahilmgandhi 18:6a4db94011d3 4095 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 4096 uint8_t RESERVED_1[3];
sahilmgandhi 18:6a4db94011d3 4097 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 4098 uint8_t RESERVED_2[3];
sahilmgandhi 18:6a4db94011d3 4099 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 4100 uint8_t RESERVED_3[3];
sahilmgandhi 18:6a4db94011d3 4101 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 4102 uint8_t RESERVED_4[3];
sahilmgandhi 18:6a4db94011d3 4103 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 4104 uint8_t RESERVED_5[3];
sahilmgandhi 18:6a4db94011d3 4105 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 4106 uint8_t RESERVED_6[3];
sahilmgandhi 18:6a4db94011d3 4107 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 4108 uint8_t RESERVED_7[99];
sahilmgandhi 18:6a4db94011d3 4109 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 4110 uint8_t RESERVED_8[3];
sahilmgandhi 18:6a4db94011d3 4111 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 4112 uint8_t RESERVED_9[3];
sahilmgandhi 18:6a4db94011d3 4113 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 4114 uint8_t RESERVED_10[3];
sahilmgandhi 18:6a4db94011d3 4115 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 4116 uint8_t RESERVED_11[3];
sahilmgandhi 18:6a4db94011d3 4117 __I uint8_t STAT; /**< Status register, offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 4118 uint8_t RESERVED_12[3];
sahilmgandhi 18:6a4db94011d3 4119 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 4120 uint8_t RESERVED_13[3];
sahilmgandhi 18:6a4db94011d3 4121 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
sahilmgandhi 18:6a4db94011d3 4122 uint8_t RESERVED_14[3];
sahilmgandhi 18:6a4db94011d3 4123 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
sahilmgandhi 18:6a4db94011d3 4124 uint8_t RESERVED_15[3];
sahilmgandhi 18:6a4db94011d3 4125 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
sahilmgandhi 18:6a4db94011d3 4126 uint8_t RESERVED_16[3];
sahilmgandhi 18:6a4db94011d3 4127 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
sahilmgandhi 18:6a4db94011d3 4128 uint8_t RESERVED_17[3];
sahilmgandhi 18:6a4db94011d3 4129 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
sahilmgandhi 18:6a4db94011d3 4130 uint8_t RESERVED_18[3];
sahilmgandhi 18:6a4db94011d3 4131 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
sahilmgandhi 18:6a4db94011d3 4132 uint8_t RESERVED_19[3];
sahilmgandhi 18:6a4db94011d3 4133 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
sahilmgandhi 18:6a4db94011d3 4134 uint8_t RESERVED_20[3];
sahilmgandhi 18:6a4db94011d3 4135 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
sahilmgandhi 18:6a4db94011d3 4136 uint8_t RESERVED_21[11];
sahilmgandhi 18:6a4db94011d3 4137 struct { /* offset: 0xC0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 4138 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 4139 uint8_t RESERVED_0[3];
sahilmgandhi 18:6a4db94011d3 4140 } ENDPOINT[16];
sahilmgandhi 18:6a4db94011d3 4141 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
sahilmgandhi 18:6a4db94011d3 4142 uint8_t RESERVED_22[3];
sahilmgandhi 18:6a4db94011d3 4143 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
sahilmgandhi 18:6a4db94011d3 4144 uint8_t RESERVED_23[3];
sahilmgandhi 18:6a4db94011d3 4145 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
sahilmgandhi 18:6a4db94011d3 4146 uint8_t RESERVED_24[3];
sahilmgandhi 18:6a4db94011d3 4147 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
sahilmgandhi 18:6a4db94011d3 4148 uint8_t RESERVED_25[7];
sahilmgandhi 18:6a4db94011d3 4149 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
sahilmgandhi 18:6a4db94011d3 4150 } USB_Type;
sahilmgandhi 18:6a4db94011d3 4151
sahilmgandhi 18:6a4db94011d3 4152 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4153 -- USB Register Masks
sahilmgandhi 18:6a4db94011d3 4154 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4155
sahilmgandhi 18:6a4db94011d3 4156 /**
sahilmgandhi 18:6a4db94011d3 4157 * @addtogroup USB_Register_Masks USB Register Masks
sahilmgandhi 18:6a4db94011d3 4158 * @{
sahilmgandhi 18:6a4db94011d3 4159 */
sahilmgandhi 18:6a4db94011d3 4160
sahilmgandhi 18:6a4db94011d3 4161 /* PERID Bit Fields */
sahilmgandhi 18:6a4db94011d3 4162 #define USB_PERID_ID_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 4163 #define USB_PERID_ID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4164 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
sahilmgandhi 18:6a4db94011d3 4165 /* IDCOMP Bit Fields */
sahilmgandhi 18:6a4db94011d3 4166 #define USB_IDCOMP_NID_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 4167 #define USB_IDCOMP_NID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4168 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
sahilmgandhi 18:6a4db94011d3 4169 /* REV Bit Fields */
sahilmgandhi 18:6a4db94011d3 4170 #define USB_REV_REV_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4171 #define USB_REV_REV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4172 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
sahilmgandhi 18:6a4db94011d3 4173 /* ADDINFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 4174 #define USB_ADDINFO_IEHOST_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4175 #define USB_ADDINFO_IEHOST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4176 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
sahilmgandhi 18:6a4db94011d3 4177 #define USB_ADDINFO_IRQNUM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4178 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
sahilmgandhi 18:6a4db94011d3 4179 /* OTGISTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4180 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4181 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4182 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4183 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4184 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4185 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4186 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4187 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4188 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4189 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4190 #define USB_OTGISTAT_IDCHG_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4191 #define USB_OTGISTAT_IDCHG_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4192 /* OTGICR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4193 #define USB_OTGICR_AVBUSEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4194 #define USB_OTGICR_AVBUSEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4195 #define USB_OTGICR_BSESSEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4196 #define USB_OTGICR_BSESSEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4197 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4198 #define USB_OTGICR_SESSVLDEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4199 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4200 #define USB_OTGICR_LINESTATEEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4201 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4202 #define USB_OTGICR_ONEMSECEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4203 #define USB_OTGICR_IDEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4204 #define USB_OTGICR_IDEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4205 /* OTGSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4206 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4207 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4208 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4209 #define USB_OTGSTAT_BSESSEND_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4210 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4211 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4212 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4213 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4214 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4215 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4216 #define USB_OTGSTAT_ID_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4217 #define USB_OTGSTAT_ID_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4218 /* OTGCTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4219 #define USB_OTGCTL_OTGEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4220 #define USB_OTGCTL_OTGEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4221 #define USB_OTGCTL_DMLOW_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4222 #define USB_OTGCTL_DMLOW_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4223 #define USB_OTGCTL_DPLOW_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4224 #define USB_OTGCTL_DPLOW_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4225 #define USB_OTGCTL_DPHIGH_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4226 #define USB_OTGCTL_DPHIGH_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4227 /* ISTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4228 #define USB_ISTAT_USBRST_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4229 #define USB_ISTAT_USBRST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4230 #define USB_ISTAT_ERROR_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4231 #define USB_ISTAT_ERROR_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4232 #define USB_ISTAT_SOFTOK_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4233 #define USB_ISTAT_SOFTOK_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4234 #define USB_ISTAT_TOKDNE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4235 #define USB_ISTAT_TOKDNE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4236 #define USB_ISTAT_SLEEP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4237 #define USB_ISTAT_SLEEP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4238 #define USB_ISTAT_RESUME_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4239 #define USB_ISTAT_RESUME_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4240 #define USB_ISTAT_ATTACH_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4241 #define USB_ISTAT_ATTACH_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4242 #define USB_ISTAT_STALL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4243 #define USB_ISTAT_STALL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4244 /* INTEN Bit Fields */
sahilmgandhi 18:6a4db94011d3 4245 #define USB_INTEN_USBRSTEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4246 #define USB_INTEN_USBRSTEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4247 #define USB_INTEN_ERROREN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4248 #define USB_INTEN_ERROREN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4249 #define USB_INTEN_SOFTOKEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4250 #define USB_INTEN_SOFTOKEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4251 #define USB_INTEN_TOKDNEEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4252 #define USB_INTEN_TOKDNEEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4253 #define USB_INTEN_SLEEPEN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4254 #define USB_INTEN_SLEEPEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4255 #define USB_INTEN_RESUMEEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4256 #define USB_INTEN_RESUMEEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4257 #define USB_INTEN_ATTACHEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4258 #define USB_INTEN_ATTACHEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4259 #define USB_INTEN_STALLEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4260 #define USB_INTEN_STALLEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4261 /* ERRSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4262 #define USB_ERRSTAT_PIDERR_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4263 #define USB_ERRSTAT_PIDERR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4264 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4265 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4266 #define USB_ERRSTAT_CRC16_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4267 #define USB_ERRSTAT_CRC16_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4268 #define USB_ERRSTAT_DFN8_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4269 #define USB_ERRSTAT_DFN8_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4270 #define USB_ERRSTAT_BTOERR_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4271 #define USB_ERRSTAT_BTOERR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4272 #define USB_ERRSTAT_DMAERR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4273 #define USB_ERRSTAT_DMAERR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4274 #define USB_ERRSTAT_BTSERR_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4275 #define USB_ERRSTAT_BTSERR_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4276 /* ERREN Bit Fields */
sahilmgandhi 18:6a4db94011d3 4277 #define USB_ERREN_PIDERREN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4278 #define USB_ERREN_PIDERREN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4279 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4280 #define USB_ERREN_CRC5EOFEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4281 #define USB_ERREN_CRC16EN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4282 #define USB_ERREN_CRC16EN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4283 #define USB_ERREN_DFN8EN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4284 #define USB_ERREN_DFN8EN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4285 #define USB_ERREN_BTOERREN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4286 #define USB_ERREN_BTOERREN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4287 #define USB_ERREN_DMAERREN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4288 #define USB_ERREN_DMAERREN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4289 #define USB_ERREN_BTSERREN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4290 #define USB_ERREN_BTSERREN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4291 /* STAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4292 #define USB_STAT_ODD_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4293 #define USB_STAT_ODD_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4294 #define USB_STAT_TX_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4295 #define USB_STAT_TX_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4296 #define USB_STAT_ENDP_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 4297 #define USB_STAT_ENDP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4298 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
sahilmgandhi 18:6a4db94011d3 4299 /* CTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4300 #define USB_CTL_USBENSOFEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4301 #define USB_CTL_USBENSOFEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4302 #define USB_CTL_ODDRST_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4303 #define USB_CTL_ODDRST_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4304 #define USB_CTL_RESUME_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4305 #define USB_CTL_RESUME_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4306 #define USB_CTL_HOSTMODEEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4307 #define USB_CTL_HOSTMODEEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4308 #define USB_CTL_RESET_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4309 #define USB_CTL_RESET_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4310 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4311 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4312 #define USB_CTL_SE0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4313 #define USB_CTL_SE0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4314 #define USB_CTL_JSTATE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4315 #define USB_CTL_JSTATE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4316 /* ADDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4317 #define USB_ADDR_ADDR_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 4318 #define USB_ADDR_ADDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4319 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
sahilmgandhi 18:6a4db94011d3 4320 #define USB_ADDR_LSEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4321 #define USB_ADDR_LSEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4322 /* BDTPAGE1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4323 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 4324 #define USB_BDTPAGE1_BDTBA_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4325 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
sahilmgandhi 18:6a4db94011d3 4326 /* FRMNUML Bit Fields */
sahilmgandhi 18:6a4db94011d3 4327 #define USB_FRMNUML_FRM_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4328 #define USB_FRMNUML_FRM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4329 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
sahilmgandhi 18:6a4db94011d3 4330 /* FRMNUMH Bit Fields */
sahilmgandhi 18:6a4db94011d3 4331 #define USB_FRMNUMH_FRM_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 4332 #define USB_FRMNUMH_FRM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4333 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
sahilmgandhi 18:6a4db94011d3 4334 /* TOKEN Bit Fields */
sahilmgandhi 18:6a4db94011d3 4335 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 4336 #define USB_TOKEN_TOKENENDPT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4337 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
sahilmgandhi 18:6a4db94011d3 4338 #define USB_TOKEN_TOKENPID_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 4339 #define USB_TOKEN_TOKENPID_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4340 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
sahilmgandhi 18:6a4db94011d3 4341 /* SOFTHLD Bit Fields */
sahilmgandhi 18:6a4db94011d3 4342 #define USB_SOFTHLD_CNT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4343 #define USB_SOFTHLD_CNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4344 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
sahilmgandhi 18:6a4db94011d3 4345 /* BDTPAGE2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4346 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4347 #define USB_BDTPAGE2_BDTBA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4348 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
sahilmgandhi 18:6a4db94011d3 4349 /* BDTPAGE3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4350 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4351 #define USB_BDTPAGE3_BDTBA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4352 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
sahilmgandhi 18:6a4db94011d3 4353 /* ENDPT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4354 #define USB_ENDPT_EPHSHK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4355 #define USB_ENDPT_EPHSHK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4356 #define USB_ENDPT_EPSTALL_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4357 #define USB_ENDPT_EPSTALL_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4358 #define USB_ENDPT_EPTXEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4359 #define USB_ENDPT_EPTXEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4360 #define USB_ENDPT_EPRXEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4361 #define USB_ENDPT_EPRXEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4362 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4363 #define USB_ENDPT_EPCTLDIS_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4364 #define USB_ENDPT_RETRYDIS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4365 #define USB_ENDPT_RETRYDIS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4366 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4367 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4368 /* USBCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4369 #define USB_USBCTRL_PDE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4370 #define USB_USBCTRL_PDE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4371 #define USB_USBCTRL_SUSP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4372 #define USB_USBCTRL_SUSP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4373 /* OBSERVE Bit Fields */
sahilmgandhi 18:6a4db94011d3 4374 #define USB_OBSERVE_DMPD_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4375 #define USB_OBSERVE_DMPD_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4376 #define USB_OBSERVE_DPPD_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4377 #define USB_OBSERVE_DPPD_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4378 #define USB_OBSERVE_DPPU_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4379 #define USB_OBSERVE_DPPU_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4380 /* CONTROL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4381 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4382 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4383 /* USBTRC0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4384 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4385 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4386 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4387 #define USB_USBTRC0_SYNC_DET_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4388 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4389 #define USB_USBTRC0_USBRESMEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4390 #define USB_USBTRC0_USBRESET_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4391 #define USB_USBTRC0_USBRESET_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4392 /* USBFRMADJUST Bit Fields */
sahilmgandhi 18:6a4db94011d3 4393 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 4394 #define USB_USBFRMADJUST_ADJ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4395 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
sahilmgandhi 18:6a4db94011d3 4396
sahilmgandhi 18:6a4db94011d3 4397 /**
sahilmgandhi 18:6a4db94011d3 4398 * @}
sahilmgandhi 18:6a4db94011d3 4399 */ /* end of group USB_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4400
sahilmgandhi 18:6a4db94011d3 4401
sahilmgandhi 18:6a4db94011d3 4402 /* USB - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4403 /** Peripheral USB0 base address */
sahilmgandhi 18:6a4db94011d3 4404 #define USB0_BASE (0x40072000u)
sahilmgandhi 18:6a4db94011d3 4405 /** Peripheral USB0 base pointer */
sahilmgandhi 18:6a4db94011d3 4406 #define USB0 ((USB_Type *)USB0_BASE)
sahilmgandhi 18:6a4db94011d3 4407 /** Array initializer of USB peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 4408 #define USB_BASES { USB0 }
sahilmgandhi 18:6a4db94011d3 4409
sahilmgandhi 18:6a4db94011d3 4410 /**
sahilmgandhi 18:6a4db94011d3 4411 * @}
sahilmgandhi 18:6a4db94011d3 4412 */ /* end of group USB_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4413
sahilmgandhi 18:6a4db94011d3 4414
sahilmgandhi 18:6a4db94011d3 4415 /*
sahilmgandhi 18:6a4db94011d3 4416 ** End of section using anonymous unions
sahilmgandhi 18:6a4db94011d3 4417 */
sahilmgandhi 18:6a4db94011d3 4418
sahilmgandhi 18:6a4db94011d3 4419 #if defined(__ARMCC_VERSION)
sahilmgandhi 18:6a4db94011d3 4420 #pragma pop
sahilmgandhi 18:6a4db94011d3 4421 #elif defined(__CWCC__)
sahilmgandhi 18:6a4db94011d3 4422 #pragma pop
sahilmgandhi 18:6a4db94011d3 4423 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 4424 /* leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 4425 #elif defined(__IAR_SYSTEMS_ICC__)
sahilmgandhi 18:6a4db94011d3 4426 #pragma language=default
sahilmgandhi 18:6a4db94011d3 4427 #else
sahilmgandhi 18:6a4db94011d3 4428 #error Not supported compiler type
sahilmgandhi 18:6a4db94011d3 4429 #endif
sahilmgandhi 18:6a4db94011d3 4430
sahilmgandhi 18:6a4db94011d3 4431 /**
sahilmgandhi 18:6a4db94011d3 4432 * @}
sahilmgandhi 18:6a4db94011d3 4433 */ /* end of group Peripheral_access_layer */
sahilmgandhi 18:6a4db94011d3 4434
sahilmgandhi 18:6a4db94011d3 4435
sahilmgandhi 18:6a4db94011d3 4436 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4437 -- Backward Compatibility
sahilmgandhi 18:6a4db94011d3 4438 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4439
sahilmgandhi 18:6a4db94011d3 4440 /**
sahilmgandhi 18:6a4db94011d3 4441 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
sahilmgandhi 18:6a4db94011d3 4442 * @{
sahilmgandhi 18:6a4db94011d3 4443 */
sahilmgandhi 18:6a4db94011d3 4444
sahilmgandhi 18:6a4db94011d3 4445 /* No backward compatibility issues. */
sahilmgandhi 18:6a4db94011d3 4446
sahilmgandhi 18:6a4db94011d3 4447 /**
sahilmgandhi 18:6a4db94011d3 4448 * @}
sahilmgandhi 18:6a4db94011d3 4449 */ /* end of group Backward_Compatibility_Symbols */
sahilmgandhi 18:6a4db94011d3 4450
sahilmgandhi 18:6a4db94011d3 4451
sahilmgandhi 18:6a4db94011d3 4452 #endif /* #if !defined(MKL26Z4_H_) */
sahilmgandhi 18:6a4db94011d3 4453
sahilmgandhi 18:6a4db94011d3 4454 /* MKL26Z4.h, eof. */