Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/pll.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief PLL management |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | #ifndef CLK_PLL_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 47 | #define CLK_PLL_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | #include "parts.h" |
sahilmgandhi | 18:6a4db94011d3 | 50 | #include "conf_clock.h" |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | #if SAM3S |
sahilmgandhi | 18:6a4db94011d3 | 53 | # include "sam3s/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 54 | #elif SAM3XA |
sahilmgandhi | 18:6a4db94011d3 | 55 | # include "sam3x/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 56 | #elif SAM3U |
sahilmgandhi | 18:6a4db94011d3 | 57 | # include "sam3u/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 58 | #elif SAM3N |
sahilmgandhi | 18:6a4db94011d3 | 59 | # include "sam3n/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 60 | #elif SAM4S |
sahilmgandhi | 18:6a4db94011d3 | 61 | # include "sam4s/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 62 | #elif SAM4E |
sahilmgandhi | 18:6a4db94011d3 | 63 | # include "sam4e/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 64 | #elif SAM4C |
sahilmgandhi | 18:6a4db94011d3 | 65 | # include "sam4c/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 66 | #elif SAM4CM |
sahilmgandhi | 18:6a4db94011d3 | 67 | # include "sam4cm/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 68 | #elif SAM4CP |
sahilmgandhi | 18:6a4db94011d3 | 69 | # include "sam4cp/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 70 | #elif SAM4L |
sahilmgandhi | 18:6a4db94011d3 | 71 | # include "sam4l/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 72 | #elif SAM4N |
sahilmgandhi | 18:6a4db94011d3 | 73 | # include "sam4n/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 74 | #elif SAMG |
sahilmgandhi | 18:6a4db94011d3 | 75 | # include "samg/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 76 | #elif SAMV71 |
sahilmgandhi | 18:6a4db94011d3 | 77 | # include "samv71/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 78 | #elif SAMV70 |
sahilmgandhi | 18:6a4db94011d3 | 79 | # include "samv70/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 80 | #elif SAME70 |
sahilmgandhi | 18:6a4db94011d3 | 81 | # include "same70/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 82 | #elif SAMS70 |
sahilmgandhi | 18:6a4db94011d3 | 83 | # include "sams70/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 84 | #elif (UC3A0 || UC3A1) |
sahilmgandhi | 18:6a4db94011d3 | 85 | # include "uc3a0_a1/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 86 | #elif UC3A3 |
sahilmgandhi | 18:6a4db94011d3 | 87 | # include "uc3a3_a4/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 88 | #elif UC3B |
sahilmgandhi | 18:6a4db94011d3 | 89 | # include "uc3b0_b1/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 90 | #elif UC3C |
sahilmgandhi | 18:6a4db94011d3 | 91 | # include "uc3c/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 92 | #elif UC3D |
sahilmgandhi | 18:6a4db94011d3 | 93 | # include "uc3d/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 94 | #elif (UC3L0128 || UC3L0256 || UC3L3_L4) |
sahilmgandhi | 18:6a4db94011d3 | 95 | # include "uc3l/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 96 | #elif XMEGA |
sahilmgandhi | 18:6a4db94011d3 | 97 | # include "xmega/pll.h" |
sahilmgandhi | 18:6a4db94011d3 | 98 | #else |
sahilmgandhi | 18:6a4db94011d3 | 99 | # error Unsupported chip type |
sahilmgandhi | 18:6a4db94011d3 | 100 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | /** |
sahilmgandhi | 18:6a4db94011d3 | 103 | * \ingroup clk_group |
sahilmgandhi | 18:6a4db94011d3 | 104 | * \defgroup pll_group PLL Management |
sahilmgandhi | 18:6a4db94011d3 | 105 | * |
sahilmgandhi | 18:6a4db94011d3 | 106 | * This group contains functions and definitions related to configuring |
sahilmgandhi | 18:6a4db94011d3 | 107 | * and enabling/disabling on-chip PLLs. A PLL will take an input signal |
sahilmgandhi | 18:6a4db94011d3 | 108 | * (the \em source), optionally divide the frequency by a configurable |
sahilmgandhi | 18:6a4db94011d3 | 109 | * \em divider, and then multiply the frequency by a configurable \em |
sahilmgandhi | 18:6a4db94011d3 | 110 | * multiplier. |
sahilmgandhi | 18:6a4db94011d3 | 111 | * |
sahilmgandhi | 18:6a4db94011d3 | 112 | * Some devices don't support input dividers; specifying any other |
sahilmgandhi | 18:6a4db94011d3 | 113 | * divisor than 1 on these devices will result in an assertion failure. |
sahilmgandhi | 18:6a4db94011d3 | 114 | * Other devices may have various restrictions to the frequency range of |
sahilmgandhi | 18:6a4db94011d3 | 115 | * the input and output signals. |
sahilmgandhi | 18:6a4db94011d3 | 116 | * |
sahilmgandhi | 18:6a4db94011d3 | 117 | * \par Example: Setting up PLL0 with default parameters |
sahilmgandhi | 18:6a4db94011d3 | 118 | * |
sahilmgandhi | 18:6a4db94011d3 | 119 | * The following example shows how to configure and enable PLL0 using |
sahilmgandhi | 18:6a4db94011d3 | 120 | * the default parameters specified using the configuration symbols |
sahilmgandhi | 18:6a4db94011d3 | 121 | * listed above. |
sahilmgandhi | 18:6a4db94011d3 | 122 | * \code |
sahilmgandhi | 18:6a4db94011d3 | 123 | pll_enable_config_defaults(0); \endcode |
sahilmgandhi | 18:6a4db94011d3 | 124 | * |
sahilmgandhi | 18:6a4db94011d3 | 125 | * To configure, enable PLL0 using the default parameters and to disable |
sahilmgandhi | 18:6a4db94011d3 | 126 | * a specific feature like Wide Bandwidth Mode (a UC3A3-specific |
sahilmgandhi | 18:6a4db94011d3 | 127 | * PLL option.), you can use this initialization process. |
sahilmgandhi | 18:6a4db94011d3 | 128 | * \code |
sahilmgandhi | 18:6a4db94011d3 | 129 | struct pll_config pllcfg; |
sahilmgandhi | 18:6a4db94011d3 | 130 | if (pll_is_locked(pll_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 131 | return; // Pll already running |
sahilmgandhi | 18:6a4db94011d3 | 132 | } |
sahilmgandhi | 18:6a4db94011d3 | 133 | pll_enable_source(CONFIG_PLL0_SOURCE); |
sahilmgandhi | 18:6a4db94011d3 | 134 | pll_config_defaults(&pllcfg, 0); |
sahilmgandhi | 18:6a4db94011d3 | 135 | pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); |
sahilmgandhi | 18:6a4db94011d3 | 136 | pll_enable(&pllcfg, 0); |
sahilmgandhi | 18:6a4db94011d3 | 137 | pll_wait_for_lock(0); \endcode |
sahilmgandhi | 18:6a4db94011d3 | 138 | * |
sahilmgandhi | 18:6a4db94011d3 | 139 | * When the last function call returns, PLL0 is ready to be used as the |
sahilmgandhi | 18:6a4db94011d3 | 140 | * main system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 141 | * |
sahilmgandhi | 18:6a4db94011d3 | 142 | * \section pll_group_config Configuration Symbols |
sahilmgandhi | 18:6a4db94011d3 | 143 | * |
sahilmgandhi | 18:6a4db94011d3 | 144 | * Each PLL has a set of default parameters determined by the following |
sahilmgandhi | 18:6a4db94011d3 | 145 | * configuration symbols in the application's configuration file: |
sahilmgandhi | 18:6a4db94011d3 | 146 | * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the |
sahilmgandhi | 18:6a4db94011d3 | 147 | * input of PLL \a n. Must be one of the values defined by the |
sahilmgandhi | 18:6a4db94011d3 | 148 | * #pll_source enum. |
sahilmgandhi | 18:6a4db94011d3 | 149 | * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL |
sahilmgandhi | 18:6a4db94011d3 | 150 | * \a n. |
sahilmgandhi | 18:6a4db94011d3 | 151 | * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. |
sahilmgandhi | 18:6a4db94011d3 | 152 | * |
sahilmgandhi | 18:6a4db94011d3 | 153 | * These configuration symbols determine the result of calling |
sahilmgandhi | 18:6a4db94011d3 | 154 | * pll_config_defaults() and pll_get_default_rate(). |
sahilmgandhi | 18:6a4db94011d3 | 155 | * |
sahilmgandhi | 18:6a4db94011d3 | 156 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 157 | */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | |
sahilmgandhi | 18:6a4db94011d3 | 159 | //! \name Chip-specific PLL characteristics |
sahilmgandhi | 18:6a4db94011d3 | 160 | //@{ |
sahilmgandhi | 18:6a4db94011d3 | 161 | /** |
sahilmgandhi | 18:6a4db94011d3 | 162 | * \def PLL_MAX_STARTUP_CYCLES |
sahilmgandhi | 18:6a4db94011d3 | 163 | * \brief Maximum PLL startup time in number of slow clock cycles |
sahilmgandhi | 18:6a4db94011d3 | 164 | */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | /** |
sahilmgandhi | 18:6a4db94011d3 | 166 | * \def NR_PLLS |
sahilmgandhi | 18:6a4db94011d3 | 167 | * \brief Number of on-chip PLLs |
sahilmgandhi | 18:6a4db94011d3 | 168 | */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | |
sahilmgandhi | 18:6a4db94011d3 | 170 | /** |
sahilmgandhi | 18:6a4db94011d3 | 171 | * \def PLL_MIN_HZ |
sahilmgandhi | 18:6a4db94011d3 | 172 | * \brief Minimum frequency that the PLL can generate |
sahilmgandhi | 18:6a4db94011d3 | 173 | */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | /** |
sahilmgandhi | 18:6a4db94011d3 | 175 | * \def PLL_MAX_HZ |
sahilmgandhi | 18:6a4db94011d3 | 176 | * \brief Maximum frequency that the PLL can generate |
sahilmgandhi | 18:6a4db94011d3 | 177 | */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | /** |
sahilmgandhi | 18:6a4db94011d3 | 179 | * \def PLL_NR_OPTIONS |
sahilmgandhi | 18:6a4db94011d3 | 180 | * \brief Number of PLL option bits |
sahilmgandhi | 18:6a4db94011d3 | 181 | */ |
sahilmgandhi | 18:6a4db94011d3 | 182 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 183 | |
sahilmgandhi | 18:6a4db94011d3 | 184 | /** |
sahilmgandhi | 18:6a4db94011d3 | 185 | * \enum pll_source |
sahilmgandhi | 18:6a4db94011d3 | 186 | * \brief PLL clock source |
sahilmgandhi | 18:6a4db94011d3 | 187 | */ |
sahilmgandhi | 18:6a4db94011d3 | 188 | |
sahilmgandhi | 18:6a4db94011d3 | 189 | //! \name PLL configuration |
sahilmgandhi | 18:6a4db94011d3 | 190 | //@{ |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | /** |
sahilmgandhi | 18:6a4db94011d3 | 193 | * \struct pll_config |
sahilmgandhi | 18:6a4db94011d3 | 194 | * \brief Hardware-specific representation of PLL configuration. |
sahilmgandhi | 18:6a4db94011d3 | 195 | * |
sahilmgandhi | 18:6a4db94011d3 | 196 | * This structure contains one or more device-specific values |
sahilmgandhi | 18:6a4db94011d3 | 197 | * representing the current PLL configuration. The contents of this |
sahilmgandhi | 18:6a4db94011d3 | 198 | * structure is typically different from platform to platform, and the |
sahilmgandhi | 18:6a4db94011d3 | 199 | * user should not access any fields except through the PLL |
sahilmgandhi | 18:6a4db94011d3 | 200 | * configuration API. |
sahilmgandhi | 18:6a4db94011d3 | 201 | */ |
sahilmgandhi | 18:6a4db94011d3 | 202 | |
sahilmgandhi | 18:6a4db94011d3 | 203 | /** |
sahilmgandhi | 18:6a4db94011d3 | 204 | * \fn void pll_config_init(struct pll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 205 | * enum pll_source src, unsigned int div, unsigned int mul) |
sahilmgandhi | 18:6a4db94011d3 | 206 | * \brief Initialize PLL configuration from standard parameters. |
sahilmgandhi | 18:6a4db94011d3 | 207 | * |
sahilmgandhi | 18:6a4db94011d3 | 208 | * \note This function may be defined inline because it is assumed to be |
sahilmgandhi | 18:6a4db94011d3 | 209 | * called very few times, and usually with constant parameters. Inlining |
sahilmgandhi | 18:6a4db94011d3 | 210 | * it will in such cases reduce the code size significantly. |
sahilmgandhi | 18:6a4db94011d3 | 211 | * |
sahilmgandhi | 18:6a4db94011d3 | 212 | * \param cfg The PLL configuration to be initialized. |
sahilmgandhi | 18:6a4db94011d3 | 213 | * \param src The oscillator to be used as input to the PLL. |
sahilmgandhi | 18:6a4db94011d3 | 214 | * \param div PLL input divider. |
sahilmgandhi | 18:6a4db94011d3 | 215 | * \param mul PLL loop divider (i.e. multiplier). |
sahilmgandhi | 18:6a4db94011d3 | 216 | * |
sahilmgandhi | 18:6a4db94011d3 | 217 | * \return A configuration which will make the PLL run at |
sahilmgandhi | 18:6a4db94011d3 | 218 | * (\a mul / \a div) times the frequency of \a src |
sahilmgandhi | 18:6a4db94011d3 | 219 | */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | /** |
sahilmgandhi | 18:6a4db94011d3 | 221 | * \def pll_config_defaults(cfg, pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 222 | * \brief Initialize PLL configuration using default parameters. |
sahilmgandhi | 18:6a4db94011d3 | 223 | * |
sahilmgandhi | 18:6a4db94011d3 | 224 | * After this function returns, \a cfg will contain a configuration |
sahilmgandhi | 18:6a4db94011d3 | 225 | * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) |
sahilmgandhi | 18:6a4db94011d3 | 226 | * times the frequency of CONFIG_PLLx_SOURCE. |
sahilmgandhi | 18:6a4db94011d3 | 227 | * |
sahilmgandhi | 18:6a4db94011d3 | 228 | * \param cfg The PLL configuration to be initialized. |
sahilmgandhi | 18:6a4db94011d3 | 229 | * \param pll_id Use defaults for this PLL. |
sahilmgandhi | 18:6a4db94011d3 | 230 | */ |
sahilmgandhi | 18:6a4db94011d3 | 231 | /** |
sahilmgandhi | 18:6a4db94011d3 | 232 | * \def pll_get_default_rate(pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 233 | * \brief Get the default rate in Hz of \a pll_id |
sahilmgandhi | 18:6a4db94011d3 | 234 | */ |
sahilmgandhi | 18:6a4db94011d3 | 235 | /** |
sahilmgandhi | 18:6a4db94011d3 | 236 | * \fn void pll_config_set_option(struct pll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 237 | * unsigned int option) |
sahilmgandhi | 18:6a4db94011d3 | 238 | * \brief Set the PLL option bit \a option in the configuration \a cfg. |
sahilmgandhi | 18:6a4db94011d3 | 239 | * |
sahilmgandhi | 18:6a4db94011d3 | 240 | * \param cfg The PLL configuration to be changed. |
sahilmgandhi | 18:6a4db94011d3 | 241 | * \param option The PLL option bit to be set. |
sahilmgandhi | 18:6a4db94011d3 | 242 | */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | /** |
sahilmgandhi | 18:6a4db94011d3 | 244 | * \fn void pll_config_clear_option(struct pll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 245 | * unsigned int option) |
sahilmgandhi | 18:6a4db94011d3 | 246 | * \brief Clear the PLL option bit \a option in the configuration \a cfg. |
sahilmgandhi | 18:6a4db94011d3 | 247 | * |
sahilmgandhi | 18:6a4db94011d3 | 248 | * \param cfg The PLL configuration to be changed. |
sahilmgandhi | 18:6a4db94011d3 | 249 | * \param option The PLL option bit to be cleared. |
sahilmgandhi | 18:6a4db94011d3 | 250 | */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | /** |
sahilmgandhi | 18:6a4db94011d3 | 252 | * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 253 | * \brief Read the currently active configuration of \a pll_id. |
sahilmgandhi | 18:6a4db94011d3 | 254 | * |
sahilmgandhi | 18:6a4db94011d3 | 255 | * \param cfg The configuration object into which to store the currently |
sahilmgandhi | 18:6a4db94011d3 | 256 | * active configuration. |
sahilmgandhi | 18:6a4db94011d3 | 257 | * \param pll_id The ID of the PLL to be accessed. |
sahilmgandhi | 18:6a4db94011d3 | 258 | */ |
sahilmgandhi | 18:6a4db94011d3 | 259 | /** |
sahilmgandhi | 18:6a4db94011d3 | 260 | * \fn void pll_config_write(const struct pll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 261 | * unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 262 | * \brief Activate the configuration \a cfg on \a pll_id |
sahilmgandhi | 18:6a4db94011d3 | 263 | * |
sahilmgandhi | 18:6a4db94011d3 | 264 | * \param cfg The configuration object representing the PLL |
sahilmgandhi | 18:6a4db94011d3 | 265 | * configuration to be activated. |
sahilmgandhi | 18:6a4db94011d3 | 266 | * \param pll_id The ID of the PLL to be updated. |
sahilmgandhi | 18:6a4db94011d3 | 267 | */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | |
sahilmgandhi | 18:6a4db94011d3 | 269 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 270 | |
sahilmgandhi | 18:6a4db94011d3 | 271 | //! \name Interaction with the PLL hardware |
sahilmgandhi | 18:6a4db94011d3 | 272 | //@{ |
sahilmgandhi | 18:6a4db94011d3 | 273 | /** |
sahilmgandhi | 18:6a4db94011d3 | 274 | * \fn void pll_enable(const struct pll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 275 | * unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 276 | * \brief Activate the configuration \a cfg and enable PLL \a pll_id. |
sahilmgandhi | 18:6a4db94011d3 | 277 | * |
sahilmgandhi | 18:6a4db94011d3 | 278 | * \param cfg The PLL configuration to be activated. |
sahilmgandhi | 18:6a4db94011d3 | 279 | * \param pll_id The ID of the PLL to be enabled. |
sahilmgandhi | 18:6a4db94011d3 | 280 | */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | /** |
sahilmgandhi | 18:6a4db94011d3 | 282 | * \fn void pll_disable(unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 283 | * \brief Disable the PLL identified by \a pll_id. |
sahilmgandhi | 18:6a4db94011d3 | 284 | * |
sahilmgandhi | 18:6a4db94011d3 | 285 | * After this function is called, the PLL identified by \a pll_id will |
sahilmgandhi | 18:6a4db94011d3 | 286 | * be disabled. The PLL configuration stored in hardware may be affected |
sahilmgandhi | 18:6a4db94011d3 | 287 | * by this, so if the caller needs to restore the same configuration |
sahilmgandhi | 18:6a4db94011d3 | 288 | * later, it should either do a pll_config_read() before disabling the |
sahilmgandhi | 18:6a4db94011d3 | 289 | * PLL, or remember the last configuration written to the PLL. |
sahilmgandhi | 18:6a4db94011d3 | 290 | * |
sahilmgandhi | 18:6a4db94011d3 | 291 | * \param pll_id The ID of the PLL to be disabled. |
sahilmgandhi | 18:6a4db94011d3 | 292 | */ |
sahilmgandhi | 18:6a4db94011d3 | 293 | /** |
sahilmgandhi | 18:6a4db94011d3 | 294 | * \fn bool pll_is_locked(unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 295 | * \brief Determine whether the PLL is locked or not. |
sahilmgandhi | 18:6a4db94011d3 | 296 | * |
sahilmgandhi | 18:6a4db94011d3 | 297 | * \param pll_id The ID of the PLL to check. |
sahilmgandhi | 18:6a4db94011d3 | 298 | * |
sahilmgandhi | 18:6a4db94011d3 | 299 | * \retval true The PLL is locked and ready to use as a clock source |
sahilmgandhi | 18:6a4db94011d3 | 300 | * \retval false The PLL is not yet locked, or has not been enabled. |
sahilmgandhi | 18:6a4db94011d3 | 301 | */ |
sahilmgandhi | 18:6a4db94011d3 | 302 | /** |
sahilmgandhi | 18:6a4db94011d3 | 303 | * \fn void pll_enable_source(enum pll_source src) |
sahilmgandhi | 18:6a4db94011d3 | 304 | * \brief Enable the source of the pll. |
sahilmgandhi | 18:6a4db94011d3 | 305 | * The source is enabled, if the source is not already running. |
sahilmgandhi | 18:6a4db94011d3 | 306 | * |
sahilmgandhi | 18:6a4db94011d3 | 307 | * \param src The ID of the PLL source to enable. |
sahilmgandhi | 18:6a4db94011d3 | 308 | */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | /** |
sahilmgandhi | 18:6a4db94011d3 | 310 | * \fn void pll_enable_config_defaults(unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 311 | * \brief Enable the pll with the default configuration. |
sahilmgandhi | 18:6a4db94011d3 | 312 | * PLL is enabled, if the PLL is not already locked. |
sahilmgandhi | 18:6a4db94011d3 | 313 | * |
sahilmgandhi | 18:6a4db94011d3 | 314 | * \param pll_id The ID of the PLL to enable. |
sahilmgandhi | 18:6a4db94011d3 | 315 | */ |
sahilmgandhi | 18:6a4db94011d3 | 316 | |
sahilmgandhi | 18:6a4db94011d3 | 317 | /** |
sahilmgandhi | 18:6a4db94011d3 | 318 | * \brief Wait for PLL \a pll_id to become locked |
sahilmgandhi | 18:6a4db94011d3 | 319 | * |
sahilmgandhi | 18:6a4db94011d3 | 320 | * \todo Use a timeout to avoid waiting forever and hanging the system |
sahilmgandhi | 18:6a4db94011d3 | 321 | * |
sahilmgandhi | 18:6a4db94011d3 | 322 | * \param pll_id The ID of the PLL to wait for. |
sahilmgandhi | 18:6a4db94011d3 | 323 | * |
sahilmgandhi | 18:6a4db94011d3 | 324 | * \retval STATUS_OK The PLL is now locked. |
sahilmgandhi | 18:6a4db94011d3 | 325 | * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. |
sahilmgandhi | 18:6a4db94011d3 | 326 | */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | static inline int pll_wait_for_lock(unsigned int pll_id) |
sahilmgandhi | 18:6a4db94011d3 | 328 | { |
sahilmgandhi | 18:6a4db94011d3 | 329 | Assert(pll_id < NR_PLLS); |
sahilmgandhi | 18:6a4db94011d3 | 330 | |
sahilmgandhi | 18:6a4db94011d3 | 331 | while (!pll_is_locked(pll_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 332 | /* Do nothing */ |
sahilmgandhi | 18:6a4db94011d3 | 333 | } |
sahilmgandhi | 18:6a4db94011d3 | 334 | |
sahilmgandhi | 18:6a4db94011d3 | 335 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 336 | } |
sahilmgandhi | 18:6a4db94011d3 | 337 | |
sahilmgandhi | 18:6a4db94011d3 | 338 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 339 | //! @} |
sahilmgandhi | 18:6a4db94011d3 | 340 | |
sahilmgandhi | 18:6a4db94011d3 | 341 | #endif /* CLK_PLL_H_INCLUDED */ |